September 2007 - U-Boot

[U-Boot-Users] Please pull u-boot-mpc83xx.git mpc83xx branch into testing
by Kim Phillips 19 Nov '07

19 Nov '07

Wolfgang, Please pull the mpc83xx branch into your testing tree: git pull git://www.denx.de/git/u-boot-mpc83xx.git mpc83xx to get the following changes (essentially support for the MPC837xEMDS board): Dave Liu (6): mpc83xx: Add the support of MPC837x SoC mpc83xx: Add the support of MPC8315E SoC mpc83xx: Add the support of MPC837xEMDS board mpc83xx: Add the MPC837xEMDS board readme mpc83xx: add MAINTAINER and MAKEALL entries for the mpc837xemds mpc83xx: update the CREDITS and MAINTAINERS CREDITS | 5 + MAINTAINERS | 2 + MAKEALL | 1 + Makefile | 10 + board/freescale/mpc837xemds/Makefile | 50 +++ board/freescale/mpc837xemds/config.mk | 28 ++ board/freescale/mpc837xemds/mpc837xemds.c | 144 +++++++ board/freescale/mpc837xemds/pci.c | 65 +++ cpu/mpc83xx/cpu.c | 36 ++- cpu/mpc83xx/cpu_init.c | 6 +- cpu/mpc83xx/spd_sdram.c | 7 +- cpu/mpc83xx/speed.c | 201 ++++++++-- doc/README.mpc837xemds | 104 +++++ drivers/tsec.c | 10 + include/asm-ppc/global_data.h | 15 +- include/asm-ppc/immap_83xx.h | 145 +++++++- include/configs/MPC837XEMDS.h | 605 +++++++++++++++++++++++++++++ include/mpc83xx.h | 261 +++++++++++-- 18 files changed, 1635 insertions(+), 60 deletions(-) create mode 100644 board/freescale/mpc837xemds/Makefile create mode 100644 board/freescale/mpc837xemds/config.mk create mode 100644 board/freescale/mpc837xemds/mpc837xemds.c create mode 100644 board/freescale/mpc837xemds/pci.c create mode 100644 doc/README.mpc837xemds create mode 100644 include/configs/MPC837XEMDS.h Thanks, Kim

5 16

[U-Boot-Users] [GIT PULL] [ARM] Please pull from git://www.denx.de/git/u-boot-arm.git
by Peter Pearse 07 Nov '07

07 Nov '07

Wolfgang Please pull from git://www.denx.de/git/u-boot-arm.git The changes address your comments:- >> Moved to asm-arm as coloured_led.h > I still would rather have this integrated into the existing status_led driver. Incorporated coloured_led.h into status_led.h >> - ran Lindent on it (drivers/at45.c) > Actually the new version is even worse. It has many lines which are not indented by multiple of 8 chars. Revisited Signed-off-by: Peter Pearse <peter.pearse(a)arm.com> Regards Peter --- The following changes since commit afd477b227c089f2b7ce0aadb20b9ea7dc6ee6f8: Peter Pearse (1): Merge with git://www.denx.de/git/u-boot.git are found in the git repository at: git://www.denx.de/git/u-boot-arm.git Peter Pearse (1): Move coloured led API to status_led.h cpu/arm920t/start.S | 2 +- drivers/at45.c | 180 ++++++++++++++++++++------------------- include/asm-arm/coloured_led.h | 45 ---------- include/status_led.h | 21 +++++ 4 files changed, 114 insertions(+), 134 deletions(-) mode change 100755 => 100644 drivers/at45.c delete mode 100644 include/asm-arm/coloured_led.h ---

3 4

[U-Boot-Users] [PATCH] tsec.c patch for receiver reset
by Dan Wilson 19 Oct '07

19 Oct '07

When we upgraded from u-boot 1.1.6 to 1.2.0, we found that ethernet no longer worked reliably on our 8541-based platforms, although for some reason 8548-based systems seemed to work fine. The problem was traced to a missing assignment in function startup_tsec. We have tried this patch on all of our 8541 and 8548-based boards, and it has resolved the problem for us. Any comments or suggestions are greatly appreciated. Signed-off by: Alain Gravel <agravel(a)fulcrummicro.com> Signed-off by: Dan Wilson <dwilson(a)fulcrummicro.com> ==================================================== --- u-boot.git/drivers/tsec.c +++ fulcrum/drivers/tsec.c @@ -803,6 +803,7 @@ /* Tell the DMA it is clear to go */ regs->dmactrl |= DMACTRL_INIT_SETTINGS; regs->tstat = TSTAT_CLEAR_THALT; + regs->rstat = RSTAT_CLEAR_RHALT; regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); }

3 2

[U-Boot-Users] [PATCH] 86xx: Allow for fewer DDR slots per memory controller.
by Jon Loeliger 16 Oct '07

16 Oct '07

As a direct correlation exists between DDR DIMM slots and SPD EEPROM addresses used to configure them, use the individually defined SPD_EEPROM_ADDRESS* values to determine if a DDR DIMM slot should have its SPD configuration read or not. Effectively, this now allows for 1 or 2 DIMM slots per memory controller. Signed-off-by: Jon Loeliger <jdl(a)freescale.com> --- cpu/mpc86xx/spd_sdram.c | 30 +++++++++++++++++++++--------- 1 files changed, 21 insertions(+), 9 deletions(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index f37ab43..059097f 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -948,19 +948,25 @@ unsigned int enable_ddr(unsigned int ddr_num) * Read both dimm slots and decide whether * or not to enable this controller. */ - memset((void *)&spd1,0,sizeof(spd1)); - memset((void *)&spd2,0,sizeof(spd2)); + memset((void *)&spd1, 0, sizeof(spd1)); + memset((void *)&spd2, 0, sizeof(spd2)); if (ddr_num == 1) { CFG_READ_SPD(SPD_EEPROM_ADDRESS1, 0, 1, (uchar *) &spd1, sizeof(spd1)); +#if defined(SPD_EEPROM_ADDRESS2) CFG_READ_SPD(SPD_EEPROM_ADDRESS2, 0, 1, (uchar *) &spd2, sizeof(spd2)); +#endif } else { +#if defined(SPD_EEPROM_ADDRESS3) CFG_READ_SPD(SPD_EEPROM_ADDRESS3, 0, 1, (uchar *) &spd1, sizeof(spd1)); +#endif +#if defined(SPD_EEPROM_ADDRESS4) CFG_READ_SPD(SPD_EEPROM_ADDRESS4, 0, 1, (uchar *) &spd2, sizeof(spd2)); +#endif } /* @@ -1105,21 +1111,25 @@ spd_sdram(void) { int memsize_ddr1_dimm1 = 0; int memsize_ddr1_dimm2 = 0; + int memsize_ddr1 = 0; + unsigned int law_size_ddr1; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) int memsize_ddr2_dimm1 = 0; int memsize_ddr2_dimm2 = 0; - int memsize_total = 0; - int memsize_ddr1 = 0; int memsize_ddr2 = 0; + unsigned int law_size_ddr2; +#endif + unsigned int ddr1_enabled = 0; unsigned int ddr2_enabled = 0; - unsigned int law_size_ddr1; - unsigned int law_size_ddr2; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + int memsize_total = 0; #ifdef CONFIG_DDR_INTERLEAVE unsigned int law_size_interleaved; - volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2; memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, @@ -1194,9 +1204,11 @@ spd_sdram(void) (unsigned int)memsize_total * 1024*1024); memsize_total += memsize_ddr1_dimm1; +#if defined(SPD_EEPROM_ADDRESS2) memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2, 1, 2, (unsigned int)memsize_total * 1024*1024); +#endif memsize_total += memsize_ddr1_dimm2; /*

2 1

[U-Boot-Users] [PATCH] USB OHCI driver: Add NEC's PCI OHCI module ID
by David Saada 14 Oct '07

14 Oct '07

Description: Add NEC's PCI OHCI module ID to the USB OHCI driver Signed-off-by: David Saada <david.saada(a)ecitele.com> diff -purN usb_ohci.c.orig usb_ohci.c --- usb_ohci.c.orig 2007-09-11 15:59:55.780415000 +0300 +++ usb_ohci.c 2007-09-16 09:52:06.146578000 +0200 @@ -93,6 +93,7 @@ #ifdef CONFIG_PCI_OHCI static struct pci_device_id ohci_pci_ids[] = { {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ + {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ /* Please add supported PCI OHCI controller ids here */ {0, 0} }; -- View this message in context: http://www.nabble.com/-PATCH--USB-OHCI-driver%3A-Add-NEC%27s-PCI-OHCI-modul… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] [PATCH] Added support for TrizepsIV module - PXA270
by stefano babic 14 Oct '07

14 Oct '07

This patch add support for the Trizeps IV module (520Mhz). Signed-off-by: Stefano Babic <sbabic(a)denx.de> -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de ===================================================================== >From c040a64dc4f1b552f445aac47a7144c3cd133883 Mon Sep 17 00:00:00 2001 From: Stefano Babic <sbabic(a)denx.de> Date: Thu, 30 Aug 2007 19:34:56 +0200 Subject: [PATCH] Added support for TrizepsIV module --- Makefile | 3 + board/trizepsiv/Makefile | 51 ++++ board/trizepsiv/config.mk | 3 + board/trizepsiv/conxs.c | 146 +++++++++++ board/trizepsiv/eeprom.c | 85 +++++++ board/trizepsiv/lowlevel_init.S | 503 +++++++++++++++++++++++++++++++++++++++ board/trizepsiv/pxavoltage.S | 31 +++ board/trizepsiv/u-boot.lds | 56 +++++ drivers/dm9000x.c | 16 +- include/configs/trizepsiv.h | 325 +++++++++++++++++++++++++ 10 files changed, 1217 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 2e15cea..8bdb2f0 100644 --- a/Makefile +++ b/Makefile @@ -2332,6 +2332,9 @@ scpu_config: unconfig pxa255_idp_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp +trizepsiv_config : unconfig + @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv + wepep250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile new file mode 100644 index 0000000..115e17d --- /dev/null +++ b/board/trizepsiv/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := conxs.o eeprom.o +SOBJS := lowlevel_init.o pxavoltage.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk new file mode 100644 index 0000000..4486f6b --- /dev/null +++ b/board/trizepsiv/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f00000 +# 0xa1700000 +#TEXT_BASE = 0 diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c new file mode 100644 index 0000000..7c6c855 --- /dev/null +++ b/board/trizepsiv/conxs.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic(a)denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley(a)applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/pxa-regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ + +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +void usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(RH_A_NPS); + UHCRHDA |= RH_A_PSM; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + puts("Called USB STOP\n"); + return; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of ConXS Board */ + gd->bd->bi_arch_number = 776; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa000003c; + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_SERIAL_MULTI) + char *console=getenv("boot_console"); + + if ((strcmp(console,"serial_btuart") == 0) || + (strcmp(console,"serial_stuart") == 0) || + (strcmp(console,"serial_ffuart") == 0)) { + setenv("stdout",console); + setenv("stdin", console); + setenv("stderr",console); + } else { + setenv("stdout", "serial"); + setenv("stdin", "serial"); + setenv("stderr", "serial"); + } +#endif + return 0; +} + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c new file mode 100644 index 0000000..e963213 --- /dev/null +++ b/board/trizepsiv/eeprom.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Software Engineering, sbabic(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +static unsigned char srom[128]; +extern u16 read_srom_word(int); +extern void write_srom_word(int offset, u16 val); + +static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int i; + + for (i=0; i < 0x40; i++) { + if (!(i % 0x10)) + printf("\n%08lx:", i); + printf(" %04x", read_srom_word(i)); + } + printf ("\n"); + return (0); +} + +static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int offset,value; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + offset=simple_strtoul(argv[2],NULL,16); + value=simple_strtoul(argv[3],NULL,16); + if (offset > 0x40) { + printf("Wrong offset : 0x%x\n",offset); + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + write_srom_word(offset, value); + return (0); +} + +int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp (argv[1],"read") == 0) { + return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else if (strcmp (argv[1],"write") == 0) { + return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} + +U_BOOT_CMD( + dm9000ee,4,1,do_dm9000_eeprom, + "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n", + "\ndm9000ee write <word offset> <value> \n" + "\tdm9000ee read \n" + "\tword:\t\t00-02 : MAC Address\n" + "\t\t\t03-07 : DM9000 Configuration\n" + "\t\t\t08-63 : User data\n"); diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S new file mode 100644 index 0000000..d886938 --- /dev/null +++ b/board/trizepsiv/lowlevel_init.S @@ -0,0 +1,503 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + ldr r0, =GRER3 + ldr r1, =CFG_GRER3_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + ldr r0, =GFER3 + ldr r1, =CFG_GFER3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + bic r4, r4, #MDREFR_K2FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CFG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + + +setvoltage: + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +#if 1 + b initirqs +#endif + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S new file mode 100644 index 0000000..5e41132 --- /dev/null +++ b/board/trizepsiv/pxavoltage.S @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic(a)denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/pxa-regs.h> + + + .global initPXAvoltage + +initPXAvoltage: + mov pc, lr + diff --git a/board/trizepsiv/u-boot.lds b/board/trizepsiv/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/trizepsiv/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index e0d531b..6131b5c 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -99,7 +99,7 @@ void eth_halt(void); static int dm9000_probe(void); static u16 phy_read(int); static void phy_write(int, u16); -static u16 read_srom_word(int); +u16 read_srom_word(int); static u8 DM9000_ior(int); static void DM9000_iow(int reg, u8 value); @@ -537,7 +537,7 @@ eth_rx(void) /* Read a word data from SROM */ -static u16 +u16 read_srom_word(int offset) { DM9000_iow(DM9000_EPAR, offset); @@ -547,6 +547,18 @@ read_srom_word(int offset) return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); } +void +write_srom_word(int offset, u16 val) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); + DM9000_iow(DM9000_EPDRL, (val & 0xff)); + DM9000_iow(DM9000_EPCR, 0x12); + udelay(8000); + DM9000_iow(DM9000_EPCR, 0); +} + + /* Read a byte from I/O port */ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h new file mode 100644 index 0000000..69548ec --- /dev/null +++ b/include/configs/trizepsiv.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic(a)denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley(a)applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ + +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define RTC + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_FFUART 1 /* we use FFUART on Conxs */ +#define CONFIG_BTUART 1 /* we use BTUART on Conxs */ +#define CONFIG_STUART 1 /* we use STUART on Conxs */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SERVERIP 192.168.1.99 +#define CONFIG_BOOTCOMMAND "run boot_flash" +#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ + " rw root=/dev/ram initrd=0xa0800000,5m" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "program_boot_mmc=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_mmc=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_mmc=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa0030000 uzImage && " \ + "fatload mmc 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "boot_flash=" \ + "cp.b 0x1c0000 0xa0800000 0x500000; " \ + "bootm 0x40000\0" \ + +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +/* #define CONFIG_INITRD_TAG 1 */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00018000 +#define CFG_GPSR1_VAL 0x00000000 +#define CFG_GPSR2_VAL 0x400dc000 +#define CFG_GPSR3_VAL 0x00000000 +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPCR3_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x00018000 +#define CFG_GPDR1_VAL 0x00028801 +#define CFG_GPDR2_VAL 0x520dc000 +#define CFG_GPDR3_VAL 0x0001E000 +#define CFG_GAFR0_L_VAL 0x801c0000 +#define CFG_GAFR0_U_VAL 0x00000013 +#define CFG_GAFR1_L_VAL 0x6990100A +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x010900F2 +#define CFG_GAFR3_L_VAL 0x54000003 +#define CFG_GAFR3_U_VAL 0x00002401 +#define CFG_GRER0_VAL 0x00000000 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 +#define CFG_GRER3_VAL 0x00000000 +#define CFG_GFER0_VAL 0x00000000 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 +#define CFG_GFER3_VAL 0x00000020 + + +#define CFG_PSSR_VAL 0x20 /* CHECK */ + +/* + * Clock settings + */ +#define CFG_CKEN 0x01FFFFFF /* CHECK */ +#define CFG_CCCR 0x02000290 /* 520Mhz */ + +/* + * Memory settings + */ + +#define CFG_MSC0_VAL 0x4df84df0 +#define CFG_MSC1_VAL 0x7ff87ff4 +#define CFG_MSC2_VAL 0xa26936d4 +#define CFG_MDCNFG_VAL 0x880009C9 +#define CFG_MDREFR_VAL 0x20ca201e +#define CFG_MDMRS_VAL 0x00220022 + +#define CFG_FLYCNFG_VAL 0x00000000 +#define CFG_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000001 +#define CFG_MCMEM0_VAL 0x00004204 +#define CFG_MCMEM1_VAL 0x00010204 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00008407 +#define CFG_MCIO1_VAL 0x0000c108 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) +/* #define CONFIG_DM9000_USE_8BIT */ +/* #define CONFIG_DM9000_USE_16BIT */ +#define CONFIG_DM9000_USE_32BIT + +#define CONFIG_USB_OHCI_NEW 1 +#define CFG_USB_OHCI_BOARD_INIT 1 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 +#define CFG_USB_OHCI_REGS_BASE 0x4C000000 +#define CFG_USB_OHCI_SLOT_NAME "trizepsiv" +#define CONFIG_USB_STORAGE 1 +#define CFG_USB_OHCI_CPU_INIT 1 + +/* + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x40000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* write flash less slowly */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* Flash environment locations */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#endif /* __CONFIG_H */ -- 1.4.3.4

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[U-Boot-Users] Fix warning differ in signedness in cpu/pxa/mmc.c
by Jean-Christophe PLAGNIOL-VILLARD 13 Oct '07

13 Oct '07

Hi, Fix warning differ in signedness in cpu/pxa/mmc.c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c index 0fbaa16..d76e0cd 100644 --- a/cpu/pxa/mmc.c +++ b/cpu/pxa/mmc.c @@ -438,11 +438,11 @@ mmc_init(int verbose) /* FIXME fill in the correct size (is set to 32MByte) */ mmc_dev.blksz = 512; mmc_dev.lba = 0x10000; - sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", + sprintf((char*)mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", cid->id[0], cid->id[1], cid->id[2], cid->sn[0], cid->sn[1], cid->sn[2]); - sprintf(mmc_dev.product,"%s",cid->name); - sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); + sprintf((char*)mmc_dev.product,"%s",cid->name); + sprintf((char*)mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); mmc_dev.removable = 0; mmc_dev.block_read = mmc_bread;

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[U-Boot-Users] Fix warning differ in signedness in board/mpl/vcma9/vcma9.c
by Jean-Christophe PLAGNIOL-VILLARD 13 Oct '07

13 Oct '07

Hi, Fix warning differ in signedness in board/mpl/vcma9/vcma9.c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 45ab654..a4c463a 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -288,7 +288,7 @@ int dram_init(void) int checkboard(void) { - unsigned char s[50]; + char s[50]; int i; backup_t *b = (backup_t *) s; @@ -337,7 +337,7 @@ int overwrite_console(void) ************************************************************************/ void print_vcma9_info(void) { - unsigned char s[50]; + char s[50]; int i; if ((i = getenv_r("serial#", s, 32)) < 0) {

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[U-Boot-Users] Some RFCs about U-Boot's the generic FPGA support
by Matthias Fuchs 09 Oct '07

09 Oct '07

Hi, I am currently setting up a new board that will use U-Boot's generic FPGA support to boot zwi different Xilinx FPGA in slave serial mode. While grep'ing through the U-Boot board config files I noticed that nearly nobody uses this code. I made a couple of changes to the code. Some of them changes the current behavior a little bit, so I like to request for comments before submitting a final patch. Since nobody uses this code I see nothing that speaks against these changes: 1) Make the 'size' parameter obsolete for the 'fpga loadb' command. The actual bitstream size is taken from the bitstream. 2) Do not bit-swap the bytes in the xilinx bitstream. When using the slave serial code the bits may not be swapped. I can imagine that this swapping requirement comes from a special board layout. So is should be done in board specific code. When removing the swapping code, we can get rid of the complete malloc/free stuff in fpga_loadbitstream(). 3) Fix a signed/unsigned issue in slave serial download code. 4) Make post() and pre() callback optional in relocation. So do not relocate NULL-pointers. This has been discussed a short time ago on the list. 5) Add a post() configuration callback for Spartan II devices in slave serial mode. 6) Add some more devices. 7) Minor typo fixes. Any comments? BTW: Are there any boards that use the FPGA stuff and that are not made public ?:-) Matthias diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 3444091..2e1cf26 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -145,13 +145,14 @@ int fpga_loadbitstream(unsigned long dev dataptr+=4; printf(" bytes in bitstream = %d\n", swapsize); - /* check consistency of length obtained */ - if (swapsize >= size) { + /* check consistency of length obtained when length parameter is non-0 */ + if (size && (swapsize >= size)) { printf("%s: Could not find right length of data in bitstream\n", __FUNCTION__); return FPGA_FAIL; } +#if 0 /* mf test-only */ /* allocate memory */ swapdata = (unsigned char *)malloc(swapsize); if (swapdata == NULL) { @@ -178,6 +179,9 @@ int fpga_loadbitstream(unsigned long dev rc = fpga_load(dev, swapdata, swapsize); free(swapdata); +#else + rc = fpga_load(dev, dataptr, swapsize); +#endif return rc; #else printf("Bitstream support only for Xilinx devices\n"); diff --git a/common/fpga.c b/common/fpga.c index 2eff239..2c231c2 100644 --- a/common/fpga.c +++ b/common/fpga.c @@ -112,11 +112,15 @@ static __attribute__((__const__)) fpga_d printf( "%s: Null buffer.\n", fn ); return (fpga_desc * const)NULL; } +#if 0 /* mf test-only + * bsize might be obsolete so do not check it. + * also bsize=3 is not better than 0 :-) + */ if ( !bsize ) { printf( "%s: Null buffer size.\n", fn ); return (fpga_desc * const)NULL; } - +#endif return desc; } diff --git a/common/spartan2.c b/common/spartan2.c index 0fb23b6..bcb67ba 100644 --- a/common/spartan2.c +++ b/common/spartan2.c @@ -516,7 +516,7 @@ static int Spartan2_ss_load (Xilinx_desc (*fn->clk) (FALSE, TRUE, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val < 0), TRUE, cookie); + (*fn->wr) ((val & 0x80), TRUE, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); @@ -561,6 +561,13 @@ static int Spartan2_ss_load (Xilinx_desc } putc ('\n'); /* terminate the dotted line */ + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) { + (*fn->post) (cookie); + } + #ifdef CFG_FPGA_PROG_FEEDBACK if (ret_val == FPGA_SUCCESS) { puts ("Done.\n"); @@ -615,8 +622,10 @@ static int Spartan2_ss_reloc (Xilinx_des PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, desc); - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; + if (fn->pre) { + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + } addr = (ulong) (fn->pgm) + reloc_offset; fn_r->pgm = (Xilinx_pgm_fn) addr; @@ -633,6 +642,11 @@ static int Spartan2_ss_reloc (Xilinx_des addr = (ulong) (fn->wr) + reloc_offset; fn_r->wr = (Xilinx_wr_fn) addr; + if (fn->post) { + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Xilinx_post_fn) addr; + } + fn_r->relocated = TRUE; } else { diff --git a/common/spartan3.c b/common/spartan3.c index c0f2b05..1435d1f 100644 --- a/common/spartan3.c +++ b/common/spartan3.c @@ -446,7 +446,7 @@ static int Spartan3_ss_load (Xilinx_desc int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; int i; - char val; + char val; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -521,7 +521,7 @@ static int Spartan3_ss_load (Xilinx_desc (*fn->clk) (FALSE, TRUE, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val < 0), TRUE, cookie); + (*fn->wr) ((val & 0x80), TRUE, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); @@ -566,6 +566,13 @@ static int Spartan3_ss_load (Xilinx_desc } putc ('\n'); /* terminate the dotted line */ + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) { + (*fn->post) (cookie); + } + #ifdef CFG_FPGA_PROG_FEEDBACK if (ret_val == FPGA_SUCCESS) { puts ("Done.\n"); @@ -620,8 +627,10 @@ static int Spartan3_ss_reloc (Xilinx_des PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, desc); - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; + if (fn->pre) { + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + } addr = (ulong) (fn->pgm) + reloc_offset; fn_r->pgm = (Xilinx_pgm_fn) addr; @@ -638,6 +647,11 @@ static int Spartan3_ss_reloc (Xilinx_des addr = (ulong) (fn->wr) + reloc_offset; fn_r->wr = (Xilinx_wr_fn) addr; + if (fn->post) { + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Xilinx_post_fn) addr; + } + fn_r->relocated = TRUE; } else { diff --git a/include/spartan2.h b/include/spartan2.h index d2e81e3..bd159e1 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -58,6 +58,7 @@ typedef struct { Xilinx_init_fn init; Xilinx_done_fn done; Xilinx_wr_fn wr; + Xilinx_post_fn post; int relocated; } Xilinx_Spartan2_Slave_Serial_fns; @@ -69,6 +70,7 @@ typedef struct { #define XILINX_XC2S50_SIZE 559232/8 #define XILINX_XC2S100_SIZE 781248/8 #define XILINX_XC2S150_SIZE 1040128/8 +#define XILINX_XC2S200_SIZE 1335872/8 /* Spartan-IIE (1.8V) */ #define XILINX_XC2S50E_SIZE 630048/8 @@ -95,6 +97,9 @@ typedef struct { #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } +#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie } + #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } diff --git a/include/spartan3.h b/include/spartan3.h index b14db03..95f62bc 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -58,6 +58,7 @@ typedef struct { Xilinx_init_fn init; Xilinx_done_fn done; Xilinx_wr_fn wr; + Xilinx_post_fn post; int relocated; } Xilinx_Spartan3_Slave_Serial_fns; @@ -73,9 +74,12 @@ typedef struct { #define XILINX_XC3S4000_SIZE 11316864/8 #define XILINX_XC3S5000_SIZE 13271936/8 +/* Spartan-IIIE (1.2V) */ +#define XILINX_XC3S1200E_SIZE 3841184/8 + /* Descriptor Macros *********************************************************************/ -/* Spartan-II devices */ +/* Spartan-III devices */ #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } @@ -100,4 +104,9 @@ typedef struct { #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie } + +/* Spartan-IIIE devices */ +#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } + #endif /* _SPARTAN3_H_ */

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[U-Boot-Users] [PATCH 0/6] updates for the TQM8xx board family
by Martin Krause 05 Oct '07

05 Oct '07

The following series implements some patches and updates for the TQM8xx board family. The patches should be independent from each other, but it is propably a good idea to apply them in the given order, to avoid merge conflicts. -- Martin Krause

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