September 2007 - U-Boot

[U-Boot-Users] minimum bdi config to read flash on 85xx
by robert lazarski 28 May '13

28 May '13

Hi all, On our custom 8548 board, we can't read our flash correctly. We have one 1Gb bank of spansion S29GL01GP flash and we get: atum>mdh 0xf8000000 0_f8000000 : f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 The big problem we have now: is this a hardware issue or a bdi config issue? Aside from the flash we have 1GigaByte of DDR ram. Can anyone help us track our flash issues down to be hardware, config file, or some combination? The hardware guys think the board is fine. We've been deep into the manuals of both the 8548 and the bdi and can't find anything wrong. Here's the config, thanks for any help! ;bdiGDB configuration file for ATUM 8548 ;--------------------------------------------------- ; [INIT] ; ; ; use the following two lines for STARTUP HALT WSPR 63 0xffff0000 ;IVPR to boot core WSPR 415 0x0000f000 ;IVOR15 : Debug exception ; ; ;================= setup for flash programming =============== ; Move CCSRBAR to 0xe0000000 WM32 0xff700000 0x000e0000 ;CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's WM32 0xe0000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0xe0000C10 0x80f0001d ;LAWAR0 : DDR 1GB WM32 0xe0000C28 0xf8000000 ;LAWBAR1 : @0xf8000000 WM32 0xe0000C30 0x8040001a ;LAWAR1 : Local Bus 128MB for S29GL01GP ; ; Setup Flash chip select WM32 0xe0005000 0xf8001001 ;BR0 WM32 0xe0005004 0xf8000E65 ;OR0 ; CS0_BNDS WM32 0xe0002000 0x0000000f ; DDR CS0 ; CS0_CONFIG WM32 0xe0002080 0x80000102 ; TIMING_CFG_0 WM32 0xe0002104 0x00260802 ; TIMING_CFG_1 WM32 0xe0002108 0x38355322 ; TIMING_CFG_2 WM32 0xe000210C 0x039048c7 ; DDR_SDRAM_MODE WM32 0xe0002118 0x00000432 ; DDR_SDRAM_INTERVAL WM32 0xe0002124 0x05150100 ; DDR_SDRAM_CFG2 WM32 0xe0002114 0x24000000 ; DDR_SDRAM_CLK_CNTL WM32 0xe0002130 0x03000000 DELAY 200 ; enable the memory interface ; DDR_SDRAM_CFG ; enable the memory interface WM32 0xe0002110 0xc3000000 ;================= end flash programming ===================== ; [TARGET] CPUTYPE 8548 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock ;STARTUP STOP 5000 ;let U-boot code setup the system STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 500 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms [REGS] FILE $reg8548.def [HOST] IP 10.101.43.10 FILE vmlinux.8548 FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP e500.bin PROMPT atum> [FLASH] CHIPTYPE MIRRORX16 ;S29GL01GP CHIPSIZE 0x8000000 ;The size of one flash chip in bytes - 1Gb BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE u-boot.bin FORMAT BIN 0xF8000000 ERASE 0xF8000000 ;erase sector 0 [REGS] FILE $reg8548.def

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[U-Boot-Users] U boot modification...
by Kiran Jammula 23 May '12

23 May '12

Hi, I am using U boot for my project. I need to configure the console while booting by prompting the user from target board LCD and Keypad. So please let me know which file of the U-boot I have to modify to achieve this. Kiran _________________________________________________________________ Special offer for NRIs! http://creative.mediaturf.net/creatives/citibankrca/rca_msntagofline.htm Get a zero balance account for next 20 years. From Citibank

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[U-Boot-Users] Ethernet loopback command
by Thomas Schäfer 17 Apr '12

17 Apr '12

Hi, The patch attached provides a command called 'ethloop' which allows to perform loopback testing on the current eth device. To achieve this, a new ethernet packet type (PROT_TEST, 0x0808, AFAIK this is not used otherwise) is introduced in net/net.c. The patch is against SF CVS from 20050307. The functions EthLoopStart, EthLoopSend and EthLoopHandler generate a simple ethernet frame with NetOurEther as destination address and packet type PROT_TEST. The looped back package is compared with the original one and a message is displayed. It is necessary to set the ethernet line into loopback mode either by programming the PHY or using a loopback plug. I've tested this on our PPC405 custom board, but it should also work on all other systems because packet generation is independent of the underlying ethernet hardware. Example usage: => mii w 0 0 7100 <-- sets PHY into loopback mode => ethloop Using ppc_405x_eth0 device Got ethernet loopback frame, len=64 loopback test successfully completed => mii w 0 0 8000 <-- PHY reset after test is completed Maybe this is also useful for others.. Best regards, Thomas Schäfer ____________________________________ Kontron Modular Computers GmbH Konrad-Zuse-Str. 9 66115 Saarbrücken Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: thomas.schaefer(a)kontron.com

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[U-Boot-Users] Add a new command to U-Boot
by Carlos Filipe Silva 20 May '09

20 May '09

Hi all! I have one doubt. How can I add a new command to U-Boot? Do I have to use only the macro U_BOOT_CMD() like files .../common/cmd_* or do I have to do more things, like defines, etc.? And after this is compliled with no error, if I type help in U-Boot's shell, do I see this command like the others? Best regards, Carlos Silva

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Re: [U-Boot-Users] NAND boot from file
by Charles Krinke 06 Mar '09

06 Mar '09

Dear Wolfgang: >Um... if this is JFFS2, then why not simply "fsload" + "bootm" ? Although I can format the flash in Linux and run fsinfo, ls or fsload in u-boot, there is a time of several minutes after Scanning JFFS2 FS Before ls can find the directory or fsload can attempt to load the uImage file. I am thinking that the 'flash_eraseall -j' command I am using may not be quite setup correctly with the u-boot environment. It should not take several minutes to pull a directory off a formatted flash. Here is what I do: Linux# flash_eraseall -j /dev/mtd0 Linux# mount -t jffs2 /dev/mtdblock0 /mnt/flash1 Linux# cp /uImage /mnt/flash1 Linux# ls /mnt/flash1 uImage is here, now reboot uboot> ls uImage is here, but it takes several minutes to get the listing. Fsload takes several minutes also. Can you think of what other assumptions I may be making that may be invalid? Charles

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[U-Boot-Users] [PATCH] part 2. Embedded PlanetBoards
by Jeff Mann 29 Nov '08

29 Nov '08

*CHANGELOG Added Support for Embedded Planet Boards EP852 EP866 and EP85xxm. See respective board config file for original author information. Merged from internal company port and QUICCstart kit into the most recent u-boot git by J. Mann, Embedded Planet, 2006-JUL-27. (this is part 2 of 2 split in half for size reasons.) (the first attempt to send this e-mail resulted in a message too big error. Sorry if you get two on acident)

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[U-Boot-Users] how to support usbtty
by zhuzhenhua 31 Aug '08

31 Aug '08

becides set CONFIG_USB_TTY, what other modification need to do for the usbtty support? thanks for any hints

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[U-Boot-Users] [PATCH] M18 flash (Sibley) support (attempt 2)
by Vasiliy Leoenenko 03 Jun '08

03 Jun '08

Hi Wolfgang, > Your patch was corrupted by your mailer which wrapped long lines. It > cannot be applied. Thank you very much for your reply. Gmail wrapped long lines. So I changed mail box. This is the second attempt. The patch was verified on different kinds of NOR using Mainstone II platform - no issues are found on u-boot (versions 1.3.0-rc1 and 1.3.0-rc2). Any comments and suggestions are welcome. Thanks, Signed-off-by: Vasiliy Leonenko <vasiliy.leonenko(a)mail.ru> Signed-off-by: Alexey Korolev <akorolex(a)gmail.com> ==================================================== --- u-boot-1.3.0-rc1.base/drivers/cfi_flash.c 2007-09-07 19:43:36.000000000 +0400 +++ u-boot-1.3.0-rc1/drivers/cfi_flash.c 2007-09-24 16:07:10.000000000 +0400 @@ -74,6 +74,7 @@ #define FLASH_CMD_PROTECT_CLEAR 0xD0 #define FLASH_CMD_CLEAR_STATUS 0x50 #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_TO_BUFFER_EXT 0xE9 #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 #define FLASH_STATUS_DONE 0x80 @@ -136,6 +137,7 @@ #define CFI_CMDSET_MITSU_STANDARD 256 #define CFI_CMDSET_MITSU_EXTENDED 257 #define CFI_CMDSET_SST 258 +#define CFI_CMDSET_INTEL_PROG_REGIONS 512 #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ # undef FLASH_CMD_RESET @@ -184,8 +186,8 @@ flash_info_t flash_info[CFG_MAX_FLASH_BA typedef unsigned long flash_sect_t; static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); -static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf); +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, ulong cmd); static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); @@ -474,6 +476,7 @@ int flash_erase (flash_info_t * info, in for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS); @@ -522,6 +525,9 @@ void flash_print_info (flash_info_t * in info->size >> 20, info->sector_count); printf (" "); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: + printf ("Intel Prog Regions"); + break; case CFI_CMDSET_INTEL_STANDARD: printf ("Intel Standard"); break; @@ -771,6 +777,7 @@ static int flash_is_busy (flash_info_t * int retval; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); @@ -825,6 +832,7 @@ static int flash_full_status_check (flas retcode = flash_status_check (info, sector, tout, prompt); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: if ((retcode == ERR_OK) @@ -903,7 +911,7 @@ static void flash_add_byte (flash_info_t /*----------------------------------------------------------------------- * make a proper sized command based on the port and chip widths */ -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf) { int i; uchar *cp = (uchar *) cmdbuf; @@ -913,13 +921,13 @@ static void flash_make_cmd (flash_info_t #else for (i = 1; i <= info->portwidth; i++) #endif - *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; + *cp++ = (i > info->chipwidth) ? '\0' : *((uchar *)&cmd + info->portwidth - i); } /* * Write a proper sized command to the correct address */ -static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, ulong cmd) { volatile cfiptr_t addr; @@ -1090,6 +1098,7 @@ static void flash_read_jedec_ids (flash_ info->device_id2 = 0; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); @@ -1209,6 +1218,7 @@ ulong flash_get_size (ulong base, int ba flash_printqry (info, 0); #endif switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: default: @@ -1289,6 +1299,7 @@ ulong flash_get_size (ulong base, int ba * Only read protection status from supported devices (intel...) */ switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: info->protect[sect_cnt] = @@ -1377,6 +1388,7 @@ static int flash_write_cfiword (flash_in flag = disable_interrupts (); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); @@ -1422,15 +1434,19 @@ static int flash_write_cfibuffer (flash_ int retcode; volatile cfiptr_t src; volatile cfiptr_t dst; + uchar write_cmd; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: src.cp = cp; dst.cp = (uchar *) dest; sector = find_sector (info, dest); + write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? + FLASH_CMD_WRITE_TO_BUFFER_EXT : FLASH_CMD_WRITE_TO_BUFFER; flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + flash_write_cmd (info, sector, 0, write_cmd); if ((retcode = flash_status_check (info, sector, info->buffer_write_tout, "write to buffer")) == ERR_OK) { /* reduce the number of loops by the width of the port */ @@ -1451,7 +1467,7 @@ static int flash_write_cfibuffer (flash_ return ERR_INVAL; break; } - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + flash_write_cmd (info, sector, 0, cnt - 1); while (cnt-- > 0) { switch (info->portwidth) { case FLASH_CFI_8BIT:

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[U-Boot-Users] bootargs for partitioned nand flash
by Terence Soh 30 Apr '08

30 Apr '08

Hi, I'm trying to get a 64 MByte nand flash to be partitioned in a 32MB cramfs and 32MB jffs2 partition. In case anyone's curious, I would like the cramfs to be root as it would be a faster mount and its read-only feature. I tried to do this in the kernel by static struct mtd_partition partition_info[] = { [0] = { .name = "CRAM", .offset = 0, .size = 32 * 1024 * 1024, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, [1] = { .name = "JFFS2", .offset = 32 * 1024 * 1024, .size = MTDPART_SIZ_FULL, } }; but when I cat/proc/mtd, I get / # cat /proc/mtd dev: size erasesize name mtd0: 04000000 00004000 "rootfs" so I realise that this is affected by the bootargs passed by u-bootloader which is "bootargs=console=ttyS0 mtdparts=a9m9750:0x4000000@0(rootfs) root=mtdblock/0 rootfstype=jffs2" How should I passed the bootargs? Thanks in advance, Terence.

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[U-Boot-Users] [MPC82xx] Fixes for MPC8272
by Wolfgang Denk 26 Apr '08

26 Apr '08

The following changes since commit 14da5f7675bbb427c469e3f45006e027b6e21db9: Wolfgang Denk (1): Cleanup compiler warnings, update CHANGELOG are found in the git repository at: git://www.denx.de/git/u-boot-mpc82xx.git Heiko Schocher (1): [MPC826x] update defines in include/mpc8260.h for the MPC8272 family include/mpc8260.h | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 89 insertions(+), 1 deletions(-) Please help testing this code. If there are no complaints, it will be merged into the master repo in aboutr 3 weeks from now. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk Office: Kirchenstr. 5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de "If God had wanted us to use the metric system, Jesus would have had 10 apostles."

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[U-Boot-Users] PATCH - Fix oob data copied into supplied buffer
by Troy Kisky 21 Apr '08

21 Apr '08

This patch correctly sets the oobavail variable and fixes a bug where the oob data was not valid when there where multiple groups in oobfree. It also defines a new variable so that you can tell which parts of a large page have ecc errors. Signed-off-by: Troy Kisky <troy.kisky(a)boundarydevices.com> diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c index 151f535..45b8fb0 100644 --- a/drivers/nand/nand_base.c +++ b/drivers/nand/nand_base.c @@ -931,7 +931,7 @@ static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int pa for (i = 0; i < eccbytes; i++, eccidx++) oob_buf[oob_config[eccidx]] = ecc_code[i]; /* If the hardware ecc provides syndromes then - * the ecc code must be written immidiately after + * the ecc code must be written immediately after * the data bytes (words) */ if (this->options & NAND_HWECC_SYNDROME) this->write_buf(mtd, ecc_code, eccbytes); @@ -1092,7 +1092,7 @@ static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * re return nand_read_ecc (mtd, from, len, retlen, buf, NULL, NULL); } - +ulong eccReadMask; /* bitmask off ecc err groups*/ /** * nand_read_ecc - [MTD Interface] Read data with ECC * @mtd: MTD device structure @@ -1267,6 +1267,7 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, ecc_code[j] = oob_data[oob_config[j]]; /* correct data, if neccecary */ + eccReadMask = 0; for (i = 0, j = 0, datidx = 0; i < this->eccsteps; i++, datidx += ecc) { ecc_status = this->correct_data(mtd, &data_poi[datidx], &ecc_code[j], &ecc_calc[j]); @@ -1283,6 +1284,7 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, } if (ecc_status == -1) { + eccReadMask |= (1<<i); DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page); ecc_failed++; } @@ -1299,7 +1301,7 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, for (i = 0, j = 0; j < mtd->oobavail; i++) { int from = oobsel->oobfree[i][0]; int num = oobsel->oobfree[i][1]; - memcpy(&oob_buf[oob], &oob_data[from], num); + memcpy(&oob_buf[oob+j], &oob_data[from], num); j+= num; } oob += mtd->oobavail; @@ -1644,8 +1646,10 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, this->select_chip(mtd, chipnr); /* Check, if it is write protected */ - if (nand_check_wp(mtd)) + if (nand_check_wp(mtd)) { + printk (KERN_NOTICE "nand_write_ecc: Device is write protected\n"); goto out; + } /* if oobsel is NULL, use chip defaults */ if (oobsel == NULL) @@ -2486,12 +2490,9 @@ int nand_scan (struct mtd_info *mtd, int maxchips) /* The number of bytes available for the filesystem to place fs dependend * oob data */ - if (this->options & NAND_BUSWIDTH_16) { - mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2); - if (this->autooob->eccbytes & 0x01) - mtd->oobavail--; - } else - mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1); + mtd->oobavail = 0; + for (i=0; this->autooob->oobfree[i][1]; i++) + mtd->oobavail += this->autooob->oobfree[i][1]; /* * check ECC mode, default to software

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[U-Boot-Users] [Patch] Disable icache before call the first line of kernel in do_bootelf().
by Sonic Zhang 14 Apr '08

14 Apr '08

On some architecture, it is not save to call the first line of kernel without disable the instruction cache. For do_bootm() path, architecture specific library code do_bootm_linux() can adress this issue, but do_bootelf() is common code. This patch disables icache before call kernel. Signed-off-by: Sonic Zhang <sonic.zhang(a)gmail.com> Index: common/cmd_elf.c =================================================================== --- common/cmd_elf.c (revision 871) +++ common/cmd_elf.c (working copy) @@ -65,6 +65,8 @@ */ if (dcache_status ()) dcache_disable (); + if (icache_status ()) + icache_disable (); /* pass cmdline to the kernel. */ cmdline = make_command_line();

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[U-Boot-Users] CramFS endianness
by Laurent Pinchart 04 Mar '08

04 Mar '08

Hi everybody, I recently had a problem with cramfs endianness. cramfs tools generates a host-endian file system, which was incompatible with my big-endian MPC8260 system. I patched mkcramfs to reverse the bit order, and was able to read the cramfs image from Linux. However, even though Linux doesn't do any byte swapping, U-Boot assumes little-endian byte order and swap bytes on big-endian architectures. Why is that ? U-Boot and Linux are clearly not compatible on big-endian architectures, and I'd like to fix the problem in the right place. Laurent Pinchart

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[U-Boot-Users] (no subject)
by Yotam Admon 01 Feb '08

01 Feb '08

Hi, I am trying to find EHCI drivers for U-boot, does any one know of a board supporting EHCI in U-boot? Thanks, Yotam

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[U-Boot-Users] [PATCH] Add S3C2410 MMC/SD support
by Harald Welte 28 Jan '08

28 Jan '08

This patch adds MMC/SD support to the S3C2410 SoC code in u-boot Signed-off-by: Harald Welte <laforge(a)openmoko.org> Index: u-boot/cpu/arm920t/s3c24x0/Makefile =================================================================== --- u-boot.orig/cpu/arm920t/s3c24x0/Makefile 2007-02-16 23:42:19.000000000 +0100 +++ u-boot/cpu/arm920t/s3c24x0/Makefile 2007-02-16 23:42:19.000000000 +0100 @@ -26,7 +26,7 @@ LIB = $(obj)lib$(SOC).a COBJS = i2c.o interrupts.o serial.o speed.o \ - usb_ohci.o nand_read.o nand.o cmd_s3c2410.o + usb_ohci.o nand_read.o nand.o mmc.o cmd_s3c2410.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) Index: u-boot/cpu/arm920t/s3c24x0/mmc.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot/cpu/arm920t/s3c24x0/mmc.c 2007-02-16 23:43:28.000000000 +0100 @@ -0,0 +1,504 @@ +/* + * u-boot S3C2410 MMC/SD card driver + * (C) Copyright 2006 by OpenMoko, Inc. + * Author: Harald Welte <laforge(a)openmoko.org> + * + * based on u-boot pxa MMC driver and linux/drivers/mmc/s3c2410mci.c + * (C) 2005-2005 Thomas Kleffel + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <mmc.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <s3c2410.h> +#include <part.h> + +#ifdef CONFIG_MMC + +#define CONFIG_MMC_WIDE + +//#define MMC_DEBUG + +#ifdef MMC_DEBUG +#define DEBUGP printf +#else +#define DEBUGP(x, args ...) do { } while(0) +#endif + +static S3C2410_SDI *sdi; + +extern int +fat_register_device(block_dev_desc_t *dev_desc, int part_no); + +static block_dev_desc_t mmc_dev; + +block_dev_desc_t * mmc_get_dev(int dev) +{ + return ((block_dev_desc_t *)&mmc_dev); +} + +/* + * FIXME needs to read cid and csd info to determine block size + * and other parameters + */ +static uchar mmc_buf[MMC_BLOCK_SIZE]; +static mmc_csd_t mmc_csd; +static int mmc_ready = 0; +static int wide = 0; + + +#define CMD_F_RESP 0x01 +#define CMD_F_RESP_LONG 0x02 + +static u_int32_t * +/****************************************************/ +mmc_cmd(ushort cmd, ulong arg, ushort flags) +/****************************************************/ +{ + static u_int32_t resp[5]; + ulong status; + int i; + + u_int32_t ccon, csta; + u_int32_t csta_rdy_bit = S3C2410_SDICMDSTAT_CMDSENT; + + memset(resp, 0, sizeof(resp)); + + DEBUGP("mmc_cmd CMD%d arg=0x%08x flags=%x\n", cmd, arg, flags); + + sdi->SDICSTA = 0xffffffff; + sdi->SDIDSTA = 0xffffffff; + sdi->SDIFSTA = 0xffffffff; + + sdi->SDICARG = arg; + + ccon = cmd & S3C2410_SDICMDCON_INDEX; + ccon |= S3C2410_SDICMDCON_SENDERHOST|S3C2410_SDICMDCON_CMDSTART; + + if (flags & CMD_F_RESP) { + ccon |= S3C2410_SDICMDCON_WAITRSP; + csta_rdy_bit = S3C2410_SDICMDSTAT_RSPFIN; /* 1 << 9 */ + } + + if (flags & CMD_F_RESP_LONG) + ccon |= S3C2410_SDICMDCON_LONGRSP; + + sdi->SDICCON = ccon; + + while (1) { + csta = sdi->SDICSTA; + if (csta & csta_rdy_bit) + break; + if (csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) { + printf("===============> MMC CMD Timeout\n"); + sdi->SDICSTA |= S3C2410_SDICMDSTAT_CMDTIMEOUT; + break; + } + } + + DEBUGP("final MMC CMD status 0x%x\n", csta); + + sdi->SDICSTA |= csta_rdy_bit; + + if (flags & CMD_F_RESP) { + resp[0] = sdi->SDIRSP0; + resp[1] = sdi->SDIRSP1; + resp[2] = sdi->SDIRSP2; + resp[3] = sdi->SDIRSP3; + } + + return resp; +} + +#define FIFO_FILL(host) ((host->SDIFSTA & S3C2410_SDIFSTA_COUNTMASK) >> 2) + +static int +/****************************************************/ +mmc_block_read(uchar *dst, ulong src, ulong len) +/****************************************************/ +{ + u_int32_t dcon, fifo; + u_int32_t *dst_u32 = (u_int32_t *)dst; + u_int32_t *resp; + + if (len == 0) { + return 0; + } + + DEBUGP("mmc_block_rd dst %lx src %lx len %d\n", (ulong)dst, src, len); + + /* set block len */ + resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, len, CMD_F_RESP); + sdi->SDIBSIZE = len; + + //sdi->SDIPRE = 0xff; + + /* setup data */ + dcon = (len >> 9) & S3C2410_SDIDCON_BLKNUM_MASK; + dcon |= S3C2410_SDIDCON_BLOCKMODE; + dcon |= S3C2410_SDIDCON_RXAFTERCMD|S3C2410_SDIDCON_XFER_RXSTART; + if (wide) + dcon |= S3C2410_SDIDCON_WIDEBUS; + sdi->SDIDCON = dcon; + + /* send read command */ + resp = mmc_cmd(MMC_CMD_READ_BLOCK, src, CMD_F_RESP); + + while (len > 0) { + u_int32_t sdidsta = sdi->SDIDSTA; + fifo = FIFO_FILL(sdi); + if (sdidsta & (S3C2410_SDIDSTA_FIFOFAIL| + S3C2410_SDIDSTA_CRCFAIL| + S3C2410_SDIDSTA_RXCRCFAIL| + S3C2410_SDIDSTA_DATATIMEOUT)) { + printf("mmc_block_read: err SDIDSTA=0x%08x\n", sdidsta); + return -EIO; + } + + while (fifo--) { + //DEBUGP("dst_u32 = 0x%08x\n", dst_u32); + *(dst_u32++) = sdi->SDIDAT; + if (len >= 4) + len -= 4; + else { + len = 0; + break; + } + } + } + + DEBUGP("waiting for SDIDSTA (currently 0x%08x\n", sdi->SDIDSTA); + while (!(sdi->SDIDSTA & (1 << 4))) {} + DEBUGP("done waiting for SDIDSTA (currently 0x%08x\n", sdi->SDIDSTA); + + sdi->SDIDCON = 0; + + if (!(sdi->SDIDSTA & S3C2410_SDIDSTA_XFERFINISH)) + DEBUGP("mmc_block_read; transfer not finished!\n"); + + return 0; +} + +static int +/****************************************************/ +mmc_block_write(ulong dst, uchar *src, int len) +/****************************************************/ +{ + printf("MMC block write not yet supported on S3C2410!\n"); + return -1; +} + + +int +/****************************************************/ +mmc_read(ulong src, uchar *dst, int size) +/****************************************************/ +{ + ulong end, part_start, part_end, part_len, aligned_start, aligned_end; + ulong mmc_block_size, mmc_block_address; + + if (size == 0) { + return 0; + } + + if (!mmc_ready) { + printf("Please initialize the MMC first\n"); + return -1; + } + + mmc_block_size = MMC_BLOCK_SIZE; + mmc_block_address = ~(mmc_block_size - 1); + + src -= CFG_MMC_BASE; + end = src + size; + part_start = ~mmc_block_address & src; + part_end = ~mmc_block_address & end; + aligned_start = mmc_block_address & src; + aligned_end = mmc_block_address & end; + + /* all block aligned accesses */ + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_start) { + part_len = mmc_block_size - part_start; + DEBUGP("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) { + return -1; + } + memcpy(dst, mmc_buf+part_start, part_len); + dst += part_len; + src += part_len; + } + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) { + DEBUGP("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) { + return -1; + } + } + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_end && src < end) { + DEBUGP("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { + return -1; + } + memcpy(dst, mmc_buf, part_end); + } + return 0; +} + +int +/****************************************************/ +mmc_write(uchar *src, ulong dst, int size) +/****************************************************/ +{ + ulong end, part_start, part_end, part_len, aligned_start, aligned_end; + ulong mmc_block_size, mmc_block_address; + + if (size == 0) { + return 0; + } + + if (!mmc_ready) { + printf("Please initialize the MMC first\n"); + return -1; + } + + mmc_block_size = MMC_BLOCK_SIZE; + mmc_block_address = ~(mmc_block_size - 1); + + dst -= CFG_MMC_BASE; + end = dst + size; + part_start = ~mmc_block_address & dst; + part_end = ~mmc_block_address & end; + aligned_start = mmc_block_address & dst; + aligned_end = mmc_block_address & end; + + /* all block aligned accesses */ + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_start) { + part_len = mmc_block_size - part_start; + DEBUGP("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) { + return -1; + } + memcpy(mmc_buf+part_start, src, part_len); + if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) { + return -1; + } + dst += part_len; + src += part_len; + } + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) { + DEBUGP("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) { + return -1; + } + } + DEBUGP("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_end && dst < end) { + DEBUGP("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { + return -1; + } + memcpy(mmc_buf, src, part_end); + if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) { + return -1; + } + } + return 0; +} + +ulong +/****************************************************/ +mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst) +/****************************************************/ +{ + int mmc_block_size = MMC_BLOCK_SIZE; + ulong src = blknr * mmc_block_size + CFG_MMC_BASE; + + mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size); + return blkcnt; +} + +static u_int16_t rca = MMC_DEFAULT_RCA; + +static u_int32_t mmc_size(const struct mmc_csd *csd) +{ + u_int32_t block_len, mult, blocknr; + + block_len = csd->read_bl_len << 12; + mult = csd->c_size_mult1 << 8; + blocknr = (csd->c_size+1) * mult; + + return blocknr * block_len; +} + +int +/****************************************************/ +mmc_init(int verbose) +/****************************************************/ +{ + int retries, rc = -ENODEV; + int is_sd = 0; + u_int32_t *resp; + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + + sdi = S3C2410_GetBase_SDI(); + + DEBUGP("mmc_init(PCLK=%u)\n", get_PCLK()); + + clk_power->CLKCON |= (1 << 9); + + /* S3C2410 has some bug that prevents reliable operation at higher speed */ + //sdi->SDIPRE = 0x3e; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ + sdi->SDIPRE = 0x02; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ + sdi->SDIBSIZE = 512; + sdi->SDIDTIMER = 0xffff; + sdi->SDIIMSK = 0x0; + sdi->SDICON = S3C2410_SDICON_FIFORESET|S3C2440_SDICON_MMCCLOCK; + udelay(125000); /* FIXME: 74 SDCLK cycles */ + + mmc_csd.c_size = 0; + + /* reset */ + retries = 10; + resp = mmc_cmd(MMC_CMD_RESET, 0, 0); + + printf("trying to detect SD Card...\n"); + while (retries--) { + int i; + udelay(100000); + resp = mmc_cmd(55, 0x00000000, CMD_F_RESP); + resp = mmc_cmd(41, 0x00300000, CMD_F_RESP); + + if (resp[0] & (1 << 31)) { + is_sd = 1; + break; + } + } + + if (retries == 0 && !is_sd) { + retries = 10; + printf("failed to detect SD Card, trying MMC\n"); + resp = mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ffc000, CMD_F_RESP); + while (retries-- && resp && !(resp[4] & 0x80)) { + DEBUGP("resp %x %x\n", resp[0], resp[1]); + udelay(50); + resp = mmc_cmd(1, 0x00ffff00, CMD_F_RESP); + } + } + + /* try to get card id */ + resp = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, CMD_F_RESP|CMD_F_RESP_LONG); + if (resp) { + /* TODO configure mmc driver depending on card attributes */ + mmc_cid_t *cid = (mmc_cid_t *)resp; + if (verbose) { + printf("MMC found. Card desciption is:\n"); + printf("Manufacturer ID = %02x%02x%02x\n", + cid->id[0], cid->id[1], cid->id[2]); + printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev); + cid->hwrev = cid->fwrev = 0; /* null terminate string */ + printf("Product Name = %s\n",cid->name); + printf("Serial Number = %02x%02x%02x\n", + cid->sn[0], cid->sn[1], cid->sn[2]); + printf("Month = %d\n",cid->month); + printf("Year = %d\n",1997 + cid->year); + } + /* fill in device description */ + mmc_dev.if_type = IF_TYPE_MMC; + mmc_dev.part_type = PART_TYPE_DOS; + mmc_dev.dev = 0; + mmc_dev.lun = 0; + mmc_dev.type = 0; + /* FIXME fill in the correct size (is set to 32MByte) */ + mmc_dev.blksz = 512; + mmc_dev.lba = 0x10000; + sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", + cid->id[0], cid->id[1], cid->id[2], + cid->sn[0], cid->sn[1], cid->sn[2]); + sprintf(mmc_dev.product,"%s",cid->name); + sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); + mmc_dev.removable = 0; + mmc_dev.block_read = mmc_bread; + + /* MMC exists, get CSD too */ + resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, CMD_F_RESP); + if (is_sd) + rca = resp[0] >> 16; + + resp = mmc_cmd(MMC_CMD_SEND_CSD, rca<<16, CMD_F_RESP|CMD_F_RESP_LONG); + if (resp) { + mmc_csd_t *csd = (mmc_csd_t *)resp; + memcpy(&mmc_csd, csd, sizeof(csd)); + rc = 0; + mmc_ready = 1; + /* FIXME add verbose printout for csd */ + printf("READ_BL_LEN=%u, C_SIZE_MULT=%u, C_SIZE=%u\n", + csd->read_bl_len, csd->c_size_mult1, csd->c_size); + printf("size = %u\n", mmc_size(csd)); + } + } + + resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca<<16, CMD_F_RESP); + +#ifdef CONFIG_MMC_WIDE + if (is_sd) { + resp = mmc_cmd(55, rca<<16, CMD_F_RESP); + resp = mmc_cmd(6, 0x02, CMD_F_RESP); + wide = 1; + } +#endif + + fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ + + return rc; +} + +int +mmc_ident(block_dev_desc_t *dev) +{ + return 0; +} + +int +mmc2info(ulong addr) +{ + /* FIXME hard codes to 32 MB device */ + if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) { + return 1; + } + return 0; +} + +#endif /* CONFIG_MMC */ Index: u-boot/include/asm-arm/arch-s3c24x0/mmc.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot/include/asm-arm/arch-s3c24x0/mmc.h 2007-02-16 23:42:19.000000000 +0100 @@ -0,0 +1,112 @@ +/* + * linux/drivers/mmc/mmc_pxa.h + * + * Author: Vladimir Shebordaev, Igor Oblakov + * Copyright: MontaVista Software Inc. + * + * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __MMC_PXA_P_H__ +#define __MMC_PXA_P_H__ + +#include <asm/arch/regs-sdi.h> + +#define MMC_DEFAULT_RCA (1<<16) + +#define MMC_BLOCK_SIZE 512 +#define MMC_CMD_RESET 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RCA 3 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_BLOCK 17 +#define MMC_CMD_RD_BLK_MULTI 18 +#define MMC_CMD_WRITE_BLOCK 24 + +#define MMC_MAX_BLOCK_SIZE 512 + +#define MMC_R1_IDLE_STATE 0x01 +#define MMC_R1_ERASE_STATE 0x02 +#define MMC_R1_ILLEGAL_CMD 0x04 +#define MMC_R1_COM_CRC_ERR 0x08 +#define MMC_R1_ERASE_SEQ_ERR 0x01 +#define MMC_R1_ADDR_ERR 0x02 +#define MMC_R1_PARAM_ERR 0x04 + +#define MMC_R1B_WP_ERASE_SKIP 0x0002 +#define MMC_R1B_ERR 0x0004 +#define MMC_R1B_CC_ERR 0x0008 +#define MMC_R1B_CARD_ECC_ERR 0x0010 +#define MMC_R1B_WP_VIOLATION 0x0020 +#define MMC_R1B_ERASE_PARAM 0x0040 +#define MMC_R1B_OOR 0x0080 +#define MMC_R1B_IDLE_STATE 0x0100 +#define MMC_R1B_ERASE_RESET 0x0200 +#define MMC_R1B_ILLEGAL_CMD 0x0400 +#define MMC_R1B_COM_CRC_ERR 0x0800 +#define MMC_R1B_ERASE_SEQ_ERR 0x1000 +#define MMC_R1B_ADDR_ERR 0x2000 +#define MMC_R1B_PARAM_ERR 0x4000 + +typedef struct mmc_cid +{ +/* FIXME: BYTE_ORDER */ + uchar year:4, + month:4; + uchar sn[3]; + uchar fwrev:4, + hwrev:4; + uchar name[6]; + uchar id[3]; +} mmc_cid_t; + +typedef struct mmc_csd +{ + uchar ecc:2, + file_format:2, + tmp_write_protect:1, + perm_write_protect:1, + copy:1, + file_format_grp:1; + uint64_t content_prot_app:1, + rsvd3:4, + write_bl_partial:1, + write_bl_len:4, + r2w_factor:3, + default_ecc:2, + wp_grp_enable:1, + wp_grp_size:5, + erase_grp_mult:5, + erase_grp_size:5, + c_size_mult1:3, + vdd_w_curr_max:3, + vdd_w_curr_min:3, + vdd_r_curr_max:3, + vdd_r_curr_min:3, + c_size:12, + rsvd2:2, + dsr_imp:1, + read_blk_misalign:1, + write_blk_misalign:1, + read_bl_partial:1; + + ushort read_bl_len:4, + ccc:12; + uchar tran_speed; + uchar nsac; + uchar taac; + uchar rsvd1:2, + spec_vers:4, + csd_structure:2; +} mmc_csd_t; + + +#endif /* __MMC_PXA_P_H__ */ Index: u-boot/include/asm-arm/arch-s3c24x0/regs-sdi.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot/include/asm-arm/arch-s3c24x0/regs-sdi.h 2007-02-16 23:42:19.000000000 +0100 @@ -0,0 +1,110 @@ +/* linux/include/asm/arch-s3c2410/regs-sdi.h + * + * Copyright (c) 2004 Simtec Electronics <linux(a)simtec.co.uk> + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 MMC/SDIO register definitions + * + * Changelog: + * 18-Aug-2004 Ben Dooks Created initial file + * 29-Nov-2004 Koen Martens Added some missing defines, fixed duplicates + * 29-Nov-2004 Ben Dooks Updated Koen's patch +*/ + +#ifndef __ASM_ARM_REGS_SDI +#define __ASM_ARM_REGS_SDI "regs-sdi.h" + +#define S3C2440_SDICON_SDRESET (1<<8) +#define S3C2440_SDICON_MMCCLOCK (1<<5) +#define S3C2410_SDICON_BYTEORDER (1<<4) +#define S3C2410_SDICON_SDIOIRQ (1<<3) +#define S3C2410_SDICON_RWAITEN (1<<2) +#define S3C2410_SDICON_FIFORESET (1<<1) +#define S3C2410_SDICON_CLOCKTYPE (1<<0) + +#define S3C2410_SDICMDCON_ABORT (1<<12) +#define S3C2410_SDICMDCON_WITHDATA (1<<11) +#define S3C2410_SDICMDCON_LONGRSP (1<<10) +#define S3C2410_SDICMDCON_WAITRSP (1<<9) +#define S3C2410_SDICMDCON_CMDSTART (1<<8) +#define S3C2410_SDICMDCON_SENDERHOST (1<<6) +#define S3C2410_SDICMDCON_INDEX (0x3f) + +#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) +#define S3C2410_SDICMDSTAT_CMDSENT (1<<11) +#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) +#define S3C2410_SDICMDSTAT_RSPFIN (1<<9) +#define S3C2410_SDICMDSTAT_XFERING (1<<8) +#define S3C2410_SDICMDSTAT_INDEX (0xff) + +#define S3C2440_SDIDCON_DS_BYTE (0<<22) +#define S3C2440_SDIDCON_DS_HALFWORD (1<<22) +#define S3C2440_SDIDCON_DS_WORD (2<<22) +#define S3C2410_SDIDCON_IRQPERIOD (1<<21) +#define S3C2410_SDIDCON_TXAFTERRESP (1<<20) +#define S3C2410_SDIDCON_RXAFTERCMD (1<<19) +#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) +#define S3C2410_SDIDCON_BLOCKMODE (1<<17) +#define S3C2410_SDIDCON_WIDEBUS (1<<16) +#define S3C2410_SDIDCON_DMAEN (1<<15) +#define S3C2410_SDIDCON_STOP (1<<14) +#define S3C2440_SDIDCON_DATSTART (1<<14) +#define S3C2410_SDIDCON_DATMODE (3<<12) +#define S3C2410_SDIDCON_BLKNUM (0x7ff) + +/* constants for S3C2410_SDIDCON_DATMODE */ +#define S3C2410_SDIDCON_XFER_READY (0<<12) +#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) +#define S3C2410_SDIDCON_XFER_RXSTART (2<<12) +#define S3C2410_SDIDCON_XFER_TXSTART (3<<12) + +#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) +#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) + +#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) +#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) +#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ +#define S3C2410_SDIDSTA_CRCFAIL (1<<7) +#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) +#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) +#define S3C2410_SDIDSTA_XFERFINISH (1<<4) +#define S3C2410_SDIDSTA_BUSYFINISH (1<<3) +#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ +#define S3C2410_SDIDSTA_TXDATAON (1<<1) +#define S3C2410_SDIDSTA_RXDATAON (1<<0) + +#define S3C2440_SDIFSTA_FIFORESET (1<<16) +#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ +#define S3C2410_SDIFSTA_TFDET (1<<13) +#define S3C2410_SDIFSTA_RFDET (1<<12) +#define S3C2410_SDIFSTA_TFHALF (1<<11) +#define S3C2410_SDIFSTA_TFEMPTY (1<<10) +#define S3C2410_SDIFSTA_RFLAST (1<<9) +#define S3C2410_SDIFSTA_RFFULL (1<<8) +#define S3C2410_SDIFSTA_RFHALF (1<<7) +#define S3C2410_SDIFSTA_COUNTMASK (0x7f) + +#define S3C2410_SDIIMSK_RESPONSECRC (1<<17) +#define S3C2410_SDIIMSK_CMDSENT (1<<16) +#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) +#define S3C2410_SDIIMSK_RESPONSEND (1<<14) +#define S3C2410_SDIIMSK_READWAIT (1<<13) +#define S3C2410_SDIIMSK_SDIOIRQ (1<<12) +#define S3C2410_SDIIMSK_FIFOFAIL (1<<11) +#define S3C2410_SDIIMSK_CRCSTATUS (1<<10) +#define S3C2410_SDIIMSK_DATACRC (1<<9) +#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) +#define S3C2410_SDIIMSK_DATAFINISH (1<<7) +#define S3C2410_SDIIMSK_BUSYFINISH (1<<6) +#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ +#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) +#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) +#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) +#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) +#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) + +#endif /* __ASM_ARM_REGS_SDI */ Index: u-boot/include/s3c24x0.h =================================================================== --- u-boot.orig/include/s3c24x0.h 2007-02-16 23:42:02.000000000 +0100 +++ u-boot/include/s3c24x0.h 2007-02-16 23:42:19.000000000 +0100 @@ -637,13 +637,7 @@ S3C24X0_REG32 SDIDCNT; S3C24X0_REG32 SDIDSTA; S3C24X0_REG32 SDIFSTA; -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res[3]; - S3C24X0_REG8 SDIDAT; -#else - S3C24X0_REG8 SDIDAT; - S3C24X0_REG8 res[3]; -#endif + S3C24X0_REG32 SDIDAT; S3C24X0_REG32 SDIIMSK; } /*__attribute__((__packed__))*/ S3C2410_SDI; @@ -1123,11 +1117,7 @@ #define rSDIDatCnt (*(volatile unsigned *)0x5A000030) #define rSDIDatSta (*(volatile unsigned *)0x5A000034) #define rSDIFSTA (*(volatile unsigned *)0x5A000038) -#ifdef __BIG_ENDIAN -#define rSDIDAT (*(volatile unsigned char *)0x5A00003F) -#else -#define rSDIDAT (*(volatile unsigned char *)0x5A00003C) -#endif +#define rSDIDAT (*(volatile unsigned *)0x5A00003C) #define rSDIIntMsk (*(volatile unsigned *)0x5A000040) #endif -- - Harald Welte <laforge(a)openmoko.org> http://openmoko.org/ ============================================================================ Software for the world's first truly open Free Software mobile phone

6 9

[U-Boot-Users] [PATCH] Add Fujitsu CoralP/Lime video driver
by Anatolij Gustschin 10 Jan '08

10 Jan '08

Add Fujitsu CoralP/Lime video driver and also fix video console newline and carriage return handling. This driver is known to work with Fujitsu CoralP PCI Eval. Board on sequoia board. It also works with lwmon5 board. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- drivers/Makefile | 2 drivers/cfb_console.c | 60 +++++++ drivers/mb862xx.c | 423 +++++++++++++++++++++++++++++++++++++++++++++++++ include/mb862xx.h | 44 +++++ 4 files changed, 526 insertions(+), 3 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index 6bf05cc..74edf2d 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -32,7 +32,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45 cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ e1000.o eepro100.o enc28j60.o \ i8042.o inca-ip_sw.o isp116x-hcd.o keyboard.o \ - lan91c96.o macb.o \ + lan91c96.o macb.o mb862xx.o \ natsemi.o ne2000.o netarm_eth.o netconsole.o \ ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \ omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \ diff --git a/drivers/cfb_console.c b/drivers/cfb_console.c index bcf8771..47fda60 100644 --- a/drivers/cfb_console.c +++ b/drivers/cfb_console.c @@ -141,6 +141,18 @@ #endif #endif /*****************************************************************************/ +/* Defines for the MB862xx driver */ +/*****************************************************************************/ +#ifdef CONFIG_VIDEO_MB862xx + +#ifdef CONFIG_VIDEO_CORALP +#define VIDEO_FB_LITTLE_ENDIAN +#endif +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + +/*****************************************************************************/ /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */ /*****************************************************************************/ #include <video_fb.h> @@ -304,7 +316,11 @@ #define SHORTSWAP32(x) ((((x) & 0x00000 #else #define SWAP16(x) (x) #define SWAP32(x) (x) +#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP) #define SHORTSWAP32(x) (x) +#else +#define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) ) +#endif #endif #if defined(DEBUG) || defined(DEBUG_CFB_CONSOLE) @@ -647,7 +663,13 @@ static void console_back (void) static void console_newline (void) { - CURSOR_OFF console_row++; + /* Check if last character in the line was just drawn. If so, cursor was + overwriten and need not to be cleared. Cursor clearing without this + check causes overwriting the 1st character of the line + */ + if (console_col < CONSOLE_COLS) + CURSOR_OFF + console_row++; console_col = 0; /* Check if we need to scroll the terminal */ @@ -662,10 +684,18 @@ static void console_newline (void) /*****************************************************************************/ +static void console_cr (void) +{ + CURSOR_OFF console_col = 0; +} + +/*****************************************************************************/ + void video_putc (const char c) { switch (c) { - case 13: /* ignore */ + case 13: /* back to first column */ + console_cr (); break; case '\n': /* next line */ @@ -716,10 +746,24 @@ #define FILL_8BIT_332RGB(r,g,b) { \ fb ++; \ } +#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP) #define FILL_15BIT_555RGB(r,g,b) { \ *(unsigned short *)fb = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \ fb += 2; \ } +#else +static int tgl; +static unsigned short p0; +#define FILL_15BIT_555RGB(r,g,b) { \ + if (!tgl++) { \ + p0 = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \ + } else { \ + tgl=0; \ + *(unsigned long *)(fb-2) = (SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3)))<<16) | p0; \ + } \ + fb += 2; \ +} +#endif #define FILL_16BIT_565RGB(r,g,b) { \ *(unsigned short *)fb = SWAP16((unsigned short)((((r)>>3)<<11) | (((g)>>2)<<5) | ((b)>>3))); \ @@ -1061,8 +1105,20 @@ #endif *dest = ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6); break; case GDF_15BIT_555RGB: +#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP) *(unsigned short *) dest = SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3))); +#else + { + if (!tgl++) { + p0 = SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3))); + } else { + *(unsigned long *)(dest-2) = + (SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)))<<16) | p0; + tgl=0; + } + } +#endif break; case GDF_16BIT_565RGB: *(unsigned short *) dest = diff --git a/drivers/mb862xx.c b/drivers/mb862xx.c new file mode 100644 index 0000000..819064e --- /dev/null +++ b/drivers/mb862xx.c @@ -0,0 +1,423 @@ +/* + * (C) Copyright 2007 + * DENX Software Engineering, Anatolij Gustschin, agust(a)denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime + * PCI and video mode code was derived from smiLynxEM driver. + */ + +#include <common.h> + +#if defined(CONFIG_VIDEO_MB862xx) + +#include <asm/io.h> +#include <pci.h> +#include <video_fb.h> +#include "videomodes.h" +#include <mb862xx.h> + +/* + * Graphic Device + */ +GraphicDevice mb862xx; + +/* + * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ; + */ +#define VIDEO_MEM_SIZE 0x01FC0000 + +#if defined(CONFIG_PCI) +#if defined(CONFIG_VIDEO_CORALP) + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P }, + { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA }, + { } +}; + +/* Internal clock frequency divider table, index is mode number */ +unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; +#endif +#endif + +#if defined(CONFIG_VIDEO_CORALP) +#define rd_io in32r +#define wr_io out32r +#else +#define rd_io(addr) in_be32((volatile unsigned*)(addr)) +#define wr_io(addr,val) out_be32((volatile unsigned*)(addr), (val)) +#endif + +#define HOST_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fc0000 + (off))) +#define HOST_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fc0000 + (off)), (val)) +#define DISP_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fd0000 + (off))) +#define DISP_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fd0000 + (off)), (val)) +#define DE_RD_REG(off) rd_io((pGD->dprBase + (off))) +#define DE_WR_REG(off, val) wr_io((pGD->dprBase + (off)), (val)) + +#if defined(CONFIG_VIDEO_CORALP) +#define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x8400)), (val)) +#else +#define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x04a0)), (val)) +#endif + +#define L0PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2))) +#define L0PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)), (val)) +#define L1PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2))) +#define L1PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)), (val)) +#define L2PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2))) +#define L2PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)), (val)) +#define L3PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2))) +#define L3PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)), (val)) + +static void gdc_sw_reset(void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + HOST_WR_REG (0x002c, 0x00000001); + udelay (500); + video_hw_init (); +} + + +static void de_wait(void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + int lc = 0x10000; + + /* Sync with software writes to framebuffer, + try to reset if engine locked */ + while (DE_RD_REG (0x0400) & 0x00000131) + if (lc-- < 0) { + gdc_sw_reset (); + printf ("gdc reset done after drawing engine lock...\n"); + break; + } +} + +static void de_wait_slots(int slots) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + int lc = 0x10000; + + /* Wait for free fifo slots */ + while (DE_RD_REG (0x0408) < slots) + if (lc-- < 0) { + gdc_sw_reset (); + printf ("gdc reset done after drawing engine lock...\n"); + break; + } +} + +#if !defined(CONFIG_VIDEO_CORALP) +static void board_disp_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + const gdc_regs *regs = board_get_regs (); + + while (regs->index) { + DISP_WR_REG (regs->index, regs->value); + regs++; + } +} +#endif + +/* + * Init drawing engine + */ +static void de_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + int cf = (pGD->gdfBytesPP == 1) ? 0x0000 : 0x8000; + + pGD->dprBase = pGD->frameAdrs + 0x01ff0000; + + /* Setup mode and fbbase, xres, fg, bg */ + de_wait_slots (2); + DE_WR_FIFO (0xf1010108); + DE_WR_FIFO (cf | 0x0300); + DE_WR_REG (0x0440, 0x0000); + DE_WR_REG (0x0444, pGD->winSizeX); + DE_WR_REG (0x0480, 0x0000); + DE_WR_REG (0x0484, 0x0000); + /* Reset clipping */ + DE_WR_REG (0x0454, 0x0000); + DE_WR_REG (0x0458, pGD->winSizeX); + DE_WR_REG (0x045c, 0x0000); + DE_WR_REG (0x0460, pGD->winSizeY); + + /* Clear framebuffer using drawing engine */ + de_wait_slots (3); + DE_WR_FIFO (0x09410000); + DE_WR_FIFO (0x00000000); + DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX); +} + +#if defined(CONFIG_VIDEO_CORALP) +unsigned int pci_video_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + pci_dev_t devbusfn; + + if ((devbusfn = pci_find_devices(supported, 0)) < 0) + { + printf ("PCI video controller not found!\n"); + return 0; + } + + /* PCI setup */ + pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs); + pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs); + + if (pGD->frameAdrs == 0) { + printf ("PCI config: failed to get base address\n"); + return 0; + } + + pGD->pciBase = pGD->frameAdrs; + + /* Setup clocks and memory mode for Coral-P Eval. Board */ + HOST_WR_REG (0x0038, 0x00090000); + udelay (200); + HOST_WR_REG (0xfffc, 0x11d7fa13); + udelay (100); + return pGD->frameAdrs; +} + +unsigned int card_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + unsigned int cf, videomode, div = 0; + unsigned long t1, hsync, vsync; + char *penv; + int tmp, i, bpp; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + + memset (pGD, 0, sizeof (GraphicDevice)); + + if (!pci_video_init ()) { + return 0; + } + + printf ("CoralP\n"); + + tmp = 0; + videomode = 0x310; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("\tno VESA Mode found, switching to mode 0x%x \n", videomode); + i = 0; + } + res_mode = + (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; + if (vesa_modes[i].resindex > 2) { + printf ("\tUnsupported resolution, switching to default\n"); + bpp = vesa_modes[1].bits_per_pixel; + div = fr_div[1]; + } + bpp = vesa_modes[i].bits_per_pixel; + div = fr_div[vesa_modes[i].resindex]; + } else { + + res_mode = (struct ctfb_res_modes *) &var_mode; + bpp = video_get_params (res_mode, penv); + } + + /* calculate hsync and vsync freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsync = 1000000000L / t1; + t1 *= (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsync = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bpp, (hsync / 1000), (vsync / 1000)); + printf ("\t%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->memSize = VIDEO_MEM_SIZE; + + switch (bpp) { + case 8: + pGD->gdfIndex = GDF__8BIT_INDEX; + pGD->gdfBytesPP = 1; + break; + case 15: + case 16: + pGD->gdfIndex = GDF_15BIT_555RGB; + pGD->gdfBytesPP = 2; + break; + #if 0 + /* TODO: Could be done but we have to implement rectfill + and bitblt SW fallbacks for this */ + case 24: + case 32: + pGD->gdfIndex = GDF_24BIT_888RGB; + pGD->gdfBytesPP = 4; + break; + #endif + default: + printf ("\t%d bpp configured, but only 8,15 and 16 supported.\n", bpp); + printf ("\tSwitching back to 15bpp\n"); + pGD->gdfIndex = GDF_15BIT_555RGB; + pGD->gdfBytesPP = 2; + } + + /* Setup dot clock (internal pll, division rate) */ + DISP_WR_REG (0x0100, div); + /* L0 init */ + cf = (pGD->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; + DISP_WR_REG (0x0020, ((pGD->winSizeX * pGD->gdfBytesPP)/64)<<16 | + (pGD->winSizeY-1) | + cf); + DISP_WR_REG (0x0024, 0x00000000); + DISP_WR_REG (0x0028, 0x00000000); + DISP_WR_REG (0x002c, 0x00000000); + DISP_WR_REG (0x0110, 0x00000000); + DISP_WR_REG (0x0114, 0x00000000); + DISP_WR_REG (0x0118, (pGD->winSizeY-1)<<16 | pGD->winSizeX); + + /* Display timing init */ + DISP_WR_REG (0x0004, (pGD->winSizeX+res_mode->left_margin+res_mode->right_margin+res_mode->hsync_len-1)<<16); + DISP_WR_REG (0x0008, (pGD->winSizeX-1) << 16 | (pGD->winSizeX-1)); + DISP_WR_REG (0x000c, (res_mode->vsync_len-1)<<24|(res_mode->hsync_len-1)<<16|(pGD->winSizeX+res_mode->right_margin-1)); + DISP_WR_REG (0x0010, (pGD->winSizeY+res_mode->lower_margin+res_mode->upper_margin+res_mode->vsync_len-1)<<16); + DISP_WR_REG (0x0014, (pGD->winSizeY-1) << 16 | (pGD->winSizeY+res_mode->lower_margin-1)); + DISP_WR_REG (0x0018, 0x00000000); + DISP_WR_REG (0x001c, pGD->winSizeY << 16 | pGD->winSizeX); + /* Display enable, L0 layer */ + DISP_WR_REG (0x0100, 0x80010000 | div); + + return pGD->frameAdrs; +} +#endif + +void *video_hw_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + + printf ("Video: Fujitsu "); + + memset (pGD, 0, sizeof (GraphicDevice)); + +#if defined(CONFIG_VIDEO_CORALP) + if (card_init () == 0) { + return (NULL); + } +#else + /* Preliminary init of the onboard graphic controller, + retrieve base address */ + if ((pGD->frameAdrs = board_video_init ()) == 0) { + printf ("Controller not found!\n"); + return (NULL); + } else + printf("Lime\n"); +#endif + + de_init (); + +#if !defined(CONFIG_VIDEO_CORALP) + board_disp_init(); +#endif + +#if defined(CONFIG_LWMON5) + /* Lamp on */ + board_backlight_switch (1); +#endif + + return pGD; +} + +/* + * Set a RGB color in the LUT + */ +void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + + L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); +} + +/* + * Drawing engine Fill and BitBlt screen region + */ +void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, unsigned int dst_y, + unsigned int dim_x, unsigned int dim_y, unsigned int color) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + + de_wait_slots (3); + DE_WR_REG (0x0480, color); + DE_WR_FIFO (0x09410000); + DE_WR_FIFO ((dst_y << 16) | dst_x); + DE_WR_FIFO ((dim_y << 16) | dim_x); + de_wait (); +} + +void video_hw_bitblt (unsigned int bpp, unsigned int src_x, unsigned int src_y, + unsigned int dst_x, unsigned int dst_y, unsigned int width, + unsigned int height) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + unsigned int ctrl = 0x0d000000L; + + if (src_x >= dst_x && src_y >= dst_y) + ctrl |= 0x00440000L; + else if (src_x >= dst_x && src_y <= dst_y) + ctrl |= 0x00460000L; + else if (src_x <= dst_x && src_y >= dst_y) + ctrl |= 0x00450000L; + else + ctrl |= 0x00470000L; + + de_wait_slots (4); + DE_WR_FIFO (ctrl); + DE_WR_FIFO ((src_y << 16) | src_x); + DE_WR_FIFO ((dst_y << 16) | dst_x); + DE_WR_FIFO ((height << 16) | width); + de_wait (); /* sync */ +} +#endif /* CONFIG_VIDEO_MB862xx */ diff --git a/include/mb862xx.h b/include/mb862xx.h new file mode 100644 index 0000000..1af5670 --- /dev/null +++ b/include/mb862xx.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2007 + * DENX Software Engineering, Anatolij Gustschin, agust(a)denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mb862xx.h - Graphic interface for Fujitsu CoralP/Lime + */ + +#ifndef _MB862XX_H_ +#define _MB862XX_H_ + +#define PCI_VENDOR_ID_FUJITSU 0x10CF +#define PCI_DEVICE_ID_CORAL_P 0x2019 +#define PCI_DEVICE_ID_CORAL_PA 0x201E + +typedef struct { + unsigned int index; + unsigned int value; +} gdc_regs; + +const gdc_regs *board_get_regs (void); +unsigned int board_video_init (void); +void board_backlight_switch(int); + +#endif /* _MB862XX_H_ */ -- 1.4.1 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de

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[U-Boot-Users] [PATCH] Removed compiler issue (invalid lvalue) - CPU PXA270
by stefano babic 09 Jan '08

09 Jan '08

Code is broken for PXA270 due to "invalid lvalue in assignment". This patch fix it in pxa-regs.h Signed-off-by: Stefano Babic <sbabic(a)denx.de> -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de ===================================================================== >From c22ab518961157f7558a448e126d1372ba74fa5c Mon Sep 17 00:00:00 2001 From: Stefano Babic <sbabic(a)denx.de> Date: Thu, 30 Aug 2007 19:29:19 +0200 Subject: [PATCH] Removed compiler issue (invalid lvalue) --- include/asm-arm/arch-pxa/pxa-regs.h | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index e8cb299..9b4da3a 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1288,15 +1288,15 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) -#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3) -#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3) -#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3) -#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3) -#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3) -#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3) -#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3) -#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \ - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)) +#define GPLR(x) __REG2(0x40E00000 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GPDR(x) __REG2(0x40E0000C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GPSR(x) __REG2(0x40E00018 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GPCR(x) __REG2(0x40E00024 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GRER(x) __REG2(0x40E00030 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GFER(x) __REG2(0x40E0003C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GEDR(x) __REG2(0x40E00048 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3) +#define GAFR(x) __REG2((((x) & 0x7f) < 96) ? 0x40E00054 : \ + ((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3) #else #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -- 1.4.3.4

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[U-Boot-Users] Linux kernel hang (infinite loop)
by Madhu Saravana Sibi Govindan 02 Jan '08

02 Jan '08

Hello all, I'm using U-boot to bring up a custom 440gp-based board. We are able to transfer the kernel image (uImage) to the target board's memory and jump to it. But, the kernel seems to hang after that. We have verified that the board info struct and the clock frequencies are ok. We also have a BDI2000 hardware debugger with us, but we are unable to set any breakpoints using this (both using telnet or using gdb). However, I can use the telnet interface and single-step the 440gp after it seems to hang. I found that 440gp is infinitely looping through the "DataTLBError" routine. It is unclear to me what might have caused this in the first place. Has anyone seen this behaviour before? We are currently working on getting breakpoints to work using the BDI2000. Any help is greatly appreciated. Regards, G.Sibi

4 11

Re: [U-Boot-Users] boot up u-boot from RAM
by Nghiem, Tien 26 Nov '07

26 Nov '07

Lei, You have to rebuild your code to put your code in the RAM area (other than the FLASH area). Don't use the address 0x00-0x2fff because its reserved for the exception vectors usually. I have a Lite5200 EVB. I use the address 0x20000 to put my u-boot in RAM and it works. I don't know if it could be done for the mpc8270. Tien -----Original Message----- From: u-boot-users-bounces(a)lists.sourceforge.net [mailto:u-boot-users-bounces@lists.sourceforge.net]On Behalf Of Lei Sun Sent: Thursday, October 26, 2006 4:15 PM To: u-boot-users(a)lists.sourceforge.net Subject: [U-Boot-Users] boot up u-boot from RAM Hi all: I am debugging a costomized board based on mpc8270, due to the design flaw, we can't boot up the system using flash, so I was trying to debug u-boot by loading it into the RAM. I used JTAG debugger to initialize the SDRAM and load the u-boot to 0x0, after reset, the PC is at 0x100. the disassembled code looks correct on that location, however, i can't single step start from 0x100. Is that because 0x100 is the reset vector ? I tried to put some breakpoint at some places not far from start point, but it gave me "unknown halt at 0x00000000" error after "run" command. after that the memory seems corrupted. Too bad I was using a bad debugger(Guardian-SE), I have a evaluation copy of the codewarrior plus USB+TAP from freescale. I tried that on our PQ2FADS-VR SDK. After reset, and CPU halt, I can't see any disassembed code on 0x100 (the uboot is already in the flash, and I assume it should read data from CS0 upon reset). Although the code does execute after hitting "run" button. I wonder why can't I see the disassembed code after reset? Thanks lei ------------------------------------------------------------------------- Using Tomcat but need to do more? Need to support web services, security? Get stuff done quickly with pre-integrated technology to make your job easier Download IBM WebSphere Application Server v.1.0.1 based on Apache Geronimo http://sel.as-us.falkag.net/sel?cmd=lnk&kid=120709&bid=263057&dat=121642 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

4 3

[U-Boot-Users] AMCC440SPe & PCI Express
by Patil, Pankaj P. 26 Nov '07

26 Nov '07

Hi, I have been using u-boot-1.1.5 on my custom 440SPe based board. I am able to establish a link on PCIE0. However, I am having trouble accessing outbound Memory on PCIE0. My memory map seetings for Outbound PCIE memory are the default U-boot Settings. I was curious if anybody's tried accessing PCIE Outbound memory with the default settings. I seem to get a bus error when I try to access that region. Thanks Pankaj

3 3

[U-Boot-Users] Please pull u-boot-mpc83xx.git mpc83xx branch into testing
by Kim Phillips 19 Nov '07

19 Nov '07

Wolfgang, Please pull the mpc83xx branch into your testing tree: git pull git://www.denx.de/git/u-boot-mpc83xx.git mpc83xx to get the following changes (essentially support for the MPC837xEMDS board): Dave Liu (6): mpc83xx: Add the support of MPC837x SoC mpc83xx: Add the support of MPC8315E SoC mpc83xx: Add the support of MPC837xEMDS board mpc83xx: Add the MPC837xEMDS board readme mpc83xx: add MAINTAINER and MAKEALL entries for the mpc837xemds mpc83xx: update the CREDITS and MAINTAINERS CREDITS | 5 + MAINTAINERS | 2 + MAKEALL | 1 + Makefile | 10 + board/freescale/mpc837xemds/Makefile | 50 +++ board/freescale/mpc837xemds/config.mk | 28 ++ board/freescale/mpc837xemds/mpc837xemds.c | 144 +++++++ board/freescale/mpc837xemds/pci.c | 65 +++ cpu/mpc83xx/cpu.c | 36 ++- cpu/mpc83xx/cpu_init.c | 6 +- cpu/mpc83xx/spd_sdram.c | 7 +- cpu/mpc83xx/speed.c | 201 ++++++++-- doc/README.mpc837xemds | 104 +++++ drivers/tsec.c | 10 + include/asm-ppc/global_data.h | 15 +- include/asm-ppc/immap_83xx.h | 145 +++++++- include/configs/MPC837XEMDS.h | 605 +++++++++++++++++++++++++++++ include/mpc83xx.h | 261 +++++++++++-- 18 files changed, 1635 insertions(+), 60 deletions(-) create mode 100644 board/freescale/mpc837xemds/Makefile create mode 100644 board/freescale/mpc837xemds/config.mk create mode 100644 board/freescale/mpc837xemds/mpc837xemds.c create mode 100644 board/freescale/mpc837xemds/pci.c create mode 100644 doc/README.mpc837xemds create mode 100644 include/configs/MPC837XEMDS.h Thanks, Kim

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[U-Boot-Users] [GIT PULL] [ARM] Please pull from git://www.denx.de/git/u-boot-arm.git
by Peter Pearse 07 Nov '07

07 Nov '07

Wolfgang Please pull from git://www.denx.de/git/u-boot-arm.git The changes address your comments:- >> Moved to asm-arm as coloured_led.h > I still would rather have this integrated into the existing status_led driver. Incorporated coloured_led.h into status_led.h >> - ran Lindent on it (drivers/at45.c) > Actually the new version is even worse. It has many lines which are not indented by multiple of 8 chars. Revisited Signed-off-by: Peter Pearse <peter.pearse(a)arm.com> Regards Peter --- The following changes since commit afd477b227c089f2b7ce0aadb20b9ea7dc6ee6f8: Peter Pearse (1): Merge with git://www.denx.de/git/u-boot.git are found in the git repository at: git://www.denx.de/git/u-boot-arm.git Peter Pearse (1): Move coloured led API to status_led.h cpu/arm920t/start.S | 2 +- drivers/at45.c | 180 ++++++++++++++++++++------------------- include/asm-arm/coloured_led.h | 45 ---------- include/status_led.h | 21 +++++ 4 files changed, 114 insertions(+), 134 deletions(-) mode change 100755 => 100644 drivers/at45.c delete mode 100644 include/asm-arm/coloured_led.h ---

3 4

[U-Boot-Users] [PATCH] tsec.c patch for receiver reset
by Dan Wilson 19 Oct '07

19 Oct '07

When we upgraded from u-boot 1.1.6 to 1.2.0, we found that ethernet no longer worked reliably on our 8541-based platforms, although for some reason 8548-based systems seemed to work fine. The problem was traced to a missing assignment in function startup_tsec. We have tried this patch on all of our 8541 and 8548-based boards, and it has resolved the problem for us. Any comments or suggestions are greatly appreciated. Signed-off by: Alain Gravel <agravel(a)fulcrummicro.com> Signed-off by: Dan Wilson <dwilson(a)fulcrummicro.com> ==================================================== --- u-boot.git/drivers/tsec.c +++ fulcrum/drivers/tsec.c @@ -803,6 +803,7 @@ /* Tell the DMA it is clear to go */ regs->dmactrl |= DMACTRL_INIT_SETTINGS; regs->tstat = TSTAT_CLEAR_THALT; + regs->rstat = RSTAT_CLEAR_RHALT; regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); }

3 2

[U-Boot-Users] [PATCH] 86xx: Allow for fewer DDR slots per memory controller.
by Jon Loeliger 16 Oct '07

16 Oct '07

As a direct correlation exists between DDR DIMM slots and SPD EEPROM addresses used to configure them, use the individually defined SPD_EEPROM_ADDRESS* values to determine if a DDR DIMM slot should have its SPD configuration read or not. Effectively, this now allows for 1 or 2 DIMM slots per memory controller. Signed-off-by: Jon Loeliger <jdl(a)freescale.com> --- cpu/mpc86xx/spd_sdram.c | 30 +++++++++++++++++++++--------- 1 files changed, 21 insertions(+), 9 deletions(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index f37ab43..059097f 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -948,19 +948,25 @@ unsigned int enable_ddr(unsigned int ddr_num) * Read both dimm slots and decide whether * or not to enable this controller. */ - memset((void *)&spd1,0,sizeof(spd1)); - memset((void *)&spd2,0,sizeof(spd2)); + memset((void *)&spd1, 0, sizeof(spd1)); + memset((void *)&spd2, 0, sizeof(spd2)); if (ddr_num == 1) { CFG_READ_SPD(SPD_EEPROM_ADDRESS1, 0, 1, (uchar *) &spd1, sizeof(spd1)); +#if defined(SPD_EEPROM_ADDRESS2) CFG_READ_SPD(SPD_EEPROM_ADDRESS2, 0, 1, (uchar *) &spd2, sizeof(spd2)); +#endif } else { +#if defined(SPD_EEPROM_ADDRESS3) CFG_READ_SPD(SPD_EEPROM_ADDRESS3, 0, 1, (uchar *) &spd1, sizeof(spd1)); +#endif +#if defined(SPD_EEPROM_ADDRESS4) CFG_READ_SPD(SPD_EEPROM_ADDRESS4, 0, 1, (uchar *) &spd2, sizeof(spd2)); +#endif } /* @@ -1105,21 +1111,25 @@ spd_sdram(void) { int memsize_ddr1_dimm1 = 0; int memsize_ddr1_dimm2 = 0; + int memsize_ddr1 = 0; + unsigned int law_size_ddr1; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) int memsize_ddr2_dimm1 = 0; int memsize_ddr2_dimm2 = 0; - int memsize_total = 0; - int memsize_ddr1 = 0; int memsize_ddr2 = 0; + unsigned int law_size_ddr2; +#endif + unsigned int ddr1_enabled = 0; unsigned int ddr2_enabled = 0; - unsigned int law_size_ddr1; - unsigned int law_size_ddr2; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + int memsize_total = 0; #ifdef CONFIG_DDR_INTERLEAVE unsigned int law_size_interleaved; - volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2; memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, @@ -1194,9 +1204,11 @@ spd_sdram(void) (unsigned int)memsize_total * 1024*1024); memsize_total += memsize_ddr1_dimm1; +#if defined(SPD_EEPROM_ADDRESS2) memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2, 1, 2, (unsigned int)memsize_total * 1024*1024); +#endif memsize_total += memsize_ddr1_dimm2; /*

2 1

[U-Boot-Users] [PATCH] USB OHCI driver: Add NEC's PCI OHCI module ID
by David Saada 14 Oct '07

14 Oct '07

Description: Add NEC's PCI OHCI module ID to the USB OHCI driver Signed-off-by: David Saada <david.saada(a)ecitele.com> diff -purN usb_ohci.c.orig usb_ohci.c --- usb_ohci.c.orig 2007-09-11 15:59:55.780415000 +0300 +++ usb_ohci.c 2007-09-16 09:52:06.146578000 +0200 @@ -93,6 +93,7 @@ #ifdef CONFIG_PCI_OHCI static struct pci_device_id ohci_pci_ids[] = { {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ + {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ /* Please add supported PCI OHCI controller ids here */ {0, 0} }; -- View this message in context: http://www.nabble.com/-PATCH--USB-OHCI-driver%3A-Add-NEC%27s-PCI-OHCI-modul… Sent from the Uboot - Users mailing list archive at Nabble.com.

5 11

[U-Boot-Users] [PATCH] Added support for TrizepsIV module - PXA270
by stefano babic 14 Oct '07

14 Oct '07

This patch add support for the Trizeps IV module (520Mhz). Signed-off-by: Stefano Babic <sbabic(a)denx.de> -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de ===================================================================== >From c040a64dc4f1b552f445aac47a7144c3cd133883 Mon Sep 17 00:00:00 2001 From: Stefano Babic <sbabic(a)denx.de> Date: Thu, 30 Aug 2007 19:34:56 +0200 Subject: [PATCH] Added support for TrizepsIV module --- Makefile | 3 + board/trizepsiv/Makefile | 51 ++++ board/trizepsiv/config.mk | 3 + board/trizepsiv/conxs.c | 146 +++++++++++ board/trizepsiv/eeprom.c | 85 +++++++ board/trizepsiv/lowlevel_init.S | 503 +++++++++++++++++++++++++++++++++++++++ board/trizepsiv/pxavoltage.S | 31 +++ board/trizepsiv/u-boot.lds | 56 +++++ drivers/dm9000x.c | 16 +- include/configs/trizepsiv.h | 325 +++++++++++++++++++++++++ 10 files changed, 1217 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 2e15cea..8bdb2f0 100644 --- a/Makefile +++ b/Makefile @@ -2332,6 +2332,9 @@ scpu_config: unconfig pxa255_idp_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp +trizepsiv_config : unconfig + @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv + wepep250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile new file mode 100644 index 0000000..115e17d --- /dev/null +++ b/board/trizepsiv/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := conxs.o eeprom.o +SOBJS := lowlevel_init.o pxavoltage.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk new file mode 100644 index 0000000..4486f6b --- /dev/null +++ b/board/trizepsiv/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f00000 +# 0xa1700000 +#TEXT_BASE = 0 diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c new file mode 100644 index 0000000..7c6c855 --- /dev/null +++ b/board/trizepsiv/conxs.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic(a)denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley(a)applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/pxa-regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ + +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +void usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(RH_A_NPS); + UHCRHDA |= RH_A_PSM; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + puts("Called USB STOP\n"); + return; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of ConXS Board */ + gd->bd->bi_arch_number = 776; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa000003c; + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_SERIAL_MULTI) + char *console=getenv("boot_console"); + + if ((strcmp(console,"serial_btuart") == 0) || + (strcmp(console,"serial_stuart") == 0) || + (strcmp(console,"serial_ffuart") == 0)) { + setenv("stdout",console); + setenv("stdin", console); + setenv("stderr",console); + } else { + setenv("stdout", "serial"); + setenv("stdin", "serial"); + setenv("stderr", "serial"); + } +#endif + return 0; +} + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c new file mode 100644 index 0000000..e963213 --- /dev/null +++ b/board/trizepsiv/eeprom.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Software Engineering, sbabic(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +static unsigned char srom[128]; +extern u16 read_srom_word(int); +extern void write_srom_word(int offset, u16 val); + +static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int i; + + for (i=0; i < 0x40; i++) { + if (!(i % 0x10)) + printf("\n%08lx:", i); + printf(" %04x", read_srom_word(i)); + } + printf ("\n"); + return (0); +} + +static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int offset,value; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + offset=simple_strtoul(argv[2],NULL,16); + value=simple_strtoul(argv[3],NULL,16); + if (offset > 0x40) { + printf("Wrong offset : 0x%x\n",offset); + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + write_srom_word(offset, value); + return (0); +} + +int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp (argv[1],"read") == 0) { + return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else if (strcmp (argv[1],"write") == 0) { + return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} + +U_BOOT_CMD( + dm9000ee,4,1,do_dm9000_eeprom, + "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n", + "\ndm9000ee write <word offset> <value> \n" + "\tdm9000ee read \n" + "\tword:\t\t00-02 : MAC Address\n" + "\t\t\t03-07 : DM9000 Configuration\n" + "\t\t\t08-63 : User data\n"); diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S new file mode 100644 index 0000000..d886938 --- /dev/null +++ b/board/trizepsiv/lowlevel_init.S @@ -0,0 +1,503 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + ldr r0, =GRER3 + ldr r1, =CFG_GRER3_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + ldr r0, =GFER3 + ldr r1, =CFG_GFER3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + bic r4, r4, #MDREFR_K2FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CFG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + + +setvoltage: + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +#if 1 + b initirqs +#endif + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S new file mode 100644 index 0000000..5e41132 --- /dev/null +++ b/board/trizepsiv/pxavoltage.S @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic(a)denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/pxa-regs.h> + + + .global initPXAvoltage + +initPXAvoltage: + mov pc, lr + diff --git a/board/trizepsiv/u-boot.lds b/board/trizepsiv/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/trizepsiv/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index e0d531b..6131b5c 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -99,7 +99,7 @@ void eth_halt(void); static int dm9000_probe(void); static u16 phy_read(int); static void phy_write(int, u16); -static u16 read_srom_word(int); +u16 read_srom_word(int); static u8 DM9000_ior(int); static void DM9000_iow(int reg, u8 value); @@ -537,7 +537,7 @@ eth_rx(void) /* Read a word data from SROM */ -static u16 +u16 read_srom_word(int offset) { DM9000_iow(DM9000_EPAR, offset); @@ -547,6 +547,18 @@ read_srom_word(int offset) return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); } +void +write_srom_word(int offset, u16 val) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); + DM9000_iow(DM9000_EPDRL, (val & 0xff)); + DM9000_iow(DM9000_EPCR, 0x12); + udelay(8000); + DM9000_iow(DM9000_EPCR, 0); +} + + /* Read a byte from I/O port */ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h new file mode 100644 index 0000000..69548ec --- /dev/null +++ b/include/configs/trizepsiv.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic(a)denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley(a)applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ + +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define RTC + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_FFUART 1 /* we use FFUART on Conxs */ +#define CONFIG_BTUART 1 /* we use BTUART on Conxs */ +#define CONFIG_STUART 1 /* we use STUART on Conxs */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SERVERIP 192.168.1.99 +#define CONFIG_BOOTCOMMAND "run boot_flash" +#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ + " rw root=/dev/ram initrd=0xa0800000,5m" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "program_boot_mmc=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_mmc=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_mmc=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa0030000 uzImage && " \ + "fatload mmc 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "boot_flash=" \ + "cp.b 0x1c0000 0xa0800000 0x500000; " \ + "bootm 0x40000\0" \ + +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +/* #define CONFIG_INITRD_TAG 1 */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00018000 +#define CFG_GPSR1_VAL 0x00000000 +#define CFG_GPSR2_VAL 0x400dc000 +#define CFG_GPSR3_VAL 0x00000000 +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPCR3_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x00018000 +#define CFG_GPDR1_VAL 0x00028801 +#define CFG_GPDR2_VAL 0x520dc000 +#define CFG_GPDR3_VAL 0x0001E000 +#define CFG_GAFR0_L_VAL 0x801c0000 +#define CFG_GAFR0_U_VAL 0x00000013 +#define CFG_GAFR1_L_VAL 0x6990100A +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x010900F2 +#define CFG_GAFR3_L_VAL 0x54000003 +#define CFG_GAFR3_U_VAL 0x00002401 +#define CFG_GRER0_VAL 0x00000000 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 +#define CFG_GRER3_VAL 0x00000000 +#define CFG_GFER0_VAL 0x00000000 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 +#define CFG_GFER3_VAL 0x00000020 + + +#define CFG_PSSR_VAL 0x20 /* CHECK */ + +/* + * Clock settings + */ +#define CFG_CKEN 0x01FFFFFF /* CHECK */ +#define CFG_CCCR 0x02000290 /* 520Mhz */ + +/* + * Memory settings + */ + +#define CFG_MSC0_VAL 0x4df84df0 +#define CFG_MSC1_VAL 0x7ff87ff4 +#define CFG_MSC2_VAL 0xa26936d4 +#define CFG_MDCNFG_VAL 0x880009C9 +#define CFG_MDREFR_VAL 0x20ca201e +#define CFG_MDMRS_VAL 0x00220022 + +#define CFG_FLYCNFG_VAL 0x00000000 +#define CFG_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000001 +#define CFG_MCMEM0_VAL 0x00004204 +#define CFG_MCMEM1_VAL 0x00010204 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00008407 +#define CFG_MCIO1_VAL 0x0000c108 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) +/* #define CONFIG_DM9000_USE_8BIT */ +/* #define CONFIG_DM9000_USE_16BIT */ +#define CONFIG_DM9000_USE_32BIT + +#define CONFIG_USB_OHCI_NEW 1 +#define CFG_USB_OHCI_BOARD_INIT 1 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 +#define CFG_USB_OHCI_REGS_BASE 0x4C000000 +#define CFG_USB_OHCI_SLOT_NAME "trizepsiv" +#define CONFIG_USB_STORAGE 1 +#define CFG_USB_OHCI_CPU_INIT 1 + +/* + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x40000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* write flash less slowly */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* Flash environment locations */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#endif /* __CONFIG_H */ -- 1.4.3.4

2 3

[U-Boot-Users] Fix warning differ in signedness in cpu/pxa/mmc.c
by Jean-Christophe PLAGNIOL-VILLARD 13 Oct '07

13 Oct '07

Hi, Fix warning differ in signedness in cpu/pxa/mmc.c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c index 0fbaa16..d76e0cd 100644 --- a/cpu/pxa/mmc.c +++ b/cpu/pxa/mmc.c @@ -438,11 +438,11 @@ mmc_init(int verbose) /* FIXME fill in the correct size (is set to 32MByte) */ mmc_dev.blksz = 512; mmc_dev.lba = 0x10000; - sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", + sprintf((char*)mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", cid->id[0], cid->id[1], cid->id[2], cid->sn[0], cid->sn[1], cid->sn[2]); - sprintf(mmc_dev.product,"%s",cid->name); - sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); + sprintf((char*)mmc_dev.product,"%s",cid->name); + sprintf((char*)mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); mmc_dev.removable = 0; mmc_dev.block_read = mmc_bread;

2 1

[U-Boot-Users] Fix warning differ in signedness in board/mpl/vcma9/vcma9.c
by Jean-Christophe PLAGNIOL-VILLARD 13 Oct '07

13 Oct '07

Hi, Fix warning differ in signedness in board/mpl/vcma9/vcma9.c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 45ab654..a4c463a 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -288,7 +288,7 @@ int dram_init(void) int checkboard(void) { - unsigned char s[50]; + char s[50]; int i; backup_t *b = (backup_t *) s; @@ -337,7 +337,7 @@ int overwrite_console(void) ************************************************************************/ void print_vcma9_info(void) { - unsigned char s[50]; + char s[50]; int i; if ((i = getenv_r("serial#", s, 32)) < 0) {

2 1

[U-Boot-Users] Some RFCs about U-Boot's the generic FPGA support
by Matthias Fuchs 09 Oct '07

09 Oct '07

Hi, I am currently setting up a new board that will use U-Boot's generic FPGA support to boot zwi different Xilinx FPGA in slave serial mode. While grep'ing through the U-Boot board config files I noticed that nearly nobody uses this code. I made a couple of changes to the code. Some of them changes the current behavior a little bit, so I like to request for comments before submitting a final patch. Since nobody uses this code I see nothing that speaks against these changes: 1) Make the 'size' parameter obsolete for the 'fpga loadb' command. The actual bitstream size is taken from the bitstream. 2) Do not bit-swap the bytes in the xilinx bitstream. When using the slave serial code the bits may not be swapped. I can imagine that this swapping requirement comes from a special board layout. So is should be done in board specific code. When removing the swapping code, we can get rid of the complete malloc/free stuff in fpga_loadbitstream(). 3) Fix a signed/unsigned issue in slave serial download code. 4) Make post() and pre() callback optional in relocation. So do not relocate NULL-pointers. This has been discussed a short time ago on the list. 5) Add a post() configuration callback for Spartan II devices in slave serial mode. 6) Add some more devices. 7) Minor typo fixes. Any comments? BTW: Are there any boards that use the FPGA stuff and that are not made public ?:-) Matthias diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 3444091..2e1cf26 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -145,13 +145,14 @@ int fpga_loadbitstream(unsigned long dev dataptr+=4; printf(" bytes in bitstream = %d\n", swapsize); - /* check consistency of length obtained */ - if (swapsize >= size) { + /* check consistency of length obtained when length parameter is non-0 */ + if (size && (swapsize >= size)) { printf("%s: Could not find right length of data in bitstream\n", __FUNCTION__); return FPGA_FAIL; } +#if 0 /* mf test-only */ /* allocate memory */ swapdata = (unsigned char *)malloc(swapsize); if (swapdata == NULL) { @@ -178,6 +179,9 @@ int fpga_loadbitstream(unsigned long dev rc = fpga_load(dev, swapdata, swapsize); free(swapdata); +#else + rc = fpga_load(dev, dataptr, swapsize); +#endif return rc; #else printf("Bitstream support only for Xilinx devices\n"); diff --git a/common/fpga.c b/common/fpga.c index 2eff239..2c231c2 100644 --- a/common/fpga.c +++ b/common/fpga.c @@ -112,11 +112,15 @@ static __attribute__((__const__)) fpga_d printf( "%s: Null buffer.\n", fn ); return (fpga_desc * const)NULL; } +#if 0 /* mf test-only + * bsize might be obsolete so do not check it. + * also bsize=3 is not better than 0 :-) + */ if ( !bsize ) { printf( "%s: Null buffer size.\n", fn ); return (fpga_desc * const)NULL; } - +#endif return desc; } diff --git a/common/spartan2.c b/common/spartan2.c index 0fb23b6..bcb67ba 100644 --- a/common/spartan2.c +++ b/common/spartan2.c @@ -516,7 +516,7 @@ static int Spartan2_ss_load (Xilinx_desc (*fn->clk) (FALSE, TRUE, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val < 0), TRUE, cookie); + (*fn->wr) ((val & 0x80), TRUE, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); @@ -561,6 +561,13 @@ static int Spartan2_ss_load (Xilinx_desc } putc ('\n'); /* terminate the dotted line */ + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) { + (*fn->post) (cookie); + } + #ifdef CFG_FPGA_PROG_FEEDBACK if (ret_val == FPGA_SUCCESS) { puts ("Done.\n"); @@ -615,8 +622,10 @@ static int Spartan2_ss_reloc (Xilinx_des PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, desc); - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; + if (fn->pre) { + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + } addr = (ulong) (fn->pgm) + reloc_offset; fn_r->pgm = (Xilinx_pgm_fn) addr; @@ -633,6 +642,11 @@ static int Spartan2_ss_reloc (Xilinx_des addr = (ulong) (fn->wr) + reloc_offset; fn_r->wr = (Xilinx_wr_fn) addr; + if (fn->post) { + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Xilinx_post_fn) addr; + } + fn_r->relocated = TRUE; } else { diff --git a/common/spartan3.c b/common/spartan3.c index c0f2b05..1435d1f 100644 --- a/common/spartan3.c +++ b/common/spartan3.c @@ -446,7 +446,7 @@ static int Spartan3_ss_load (Xilinx_desc int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; int i; - char val; + char val; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -521,7 +521,7 @@ static int Spartan3_ss_load (Xilinx_desc (*fn->clk) (FALSE, TRUE, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val < 0), TRUE, cookie); + (*fn->wr) ((val & 0x80), TRUE, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); @@ -566,6 +566,13 @@ static int Spartan3_ss_load (Xilinx_desc } putc ('\n'); /* terminate the dotted line */ + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) { + (*fn->post) (cookie); + } + #ifdef CFG_FPGA_PROG_FEEDBACK if (ret_val == FPGA_SUCCESS) { puts ("Done.\n"); @@ -620,8 +627,10 @@ static int Spartan3_ss_reloc (Xilinx_des PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, desc); - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; + if (fn->pre) { + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + } addr = (ulong) (fn->pgm) + reloc_offset; fn_r->pgm = (Xilinx_pgm_fn) addr; @@ -638,6 +647,11 @@ static int Spartan3_ss_reloc (Xilinx_des addr = (ulong) (fn->wr) + reloc_offset; fn_r->wr = (Xilinx_wr_fn) addr; + if (fn->post) { + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Xilinx_post_fn) addr; + } + fn_r->relocated = TRUE; } else { diff --git a/include/spartan2.h b/include/spartan2.h index d2e81e3..bd159e1 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -58,6 +58,7 @@ typedef struct { Xilinx_init_fn init; Xilinx_done_fn done; Xilinx_wr_fn wr; + Xilinx_post_fn post; int relocated; } Xilinx_Spartan2_Slave_Serial_fns; @@ -69,6 +70,7 @@ typedef struct { #define XILINX_XC2S50_SIZE 559232/8 #define XILINX_XC2S100_SIZE 781248/8 #define XILINX_XC2S150_SIZE 1040128/8 +#define XILINX_XC2S200_SIZE 1335872/8 /* Spartan-IIE (1.8V) */ #define XILINX_XC2S50E_SIZE 630048/8 @@ -95,6 +97,9 @@ typedef struct { #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } +#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie } + #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } diff --git a/include/spartan3.h b/include/spartan3.h index b14db03..95f62bc 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -58,6 +58,7 @@ typedef struct { Xilinx_init_fn init; Xilinx_done_fn done; Xilinx_wr_fn wr; + Xilinx_post_fn post; int relocated; } Xilinx_Spartan3_Slave_Serial_fns; @@ -73,9 +74,12 @@ typedef struct { #define XILINX_XC3S4000_SIZE 11316864/8 #define XILINX_XC3S5000_SIZE 13271936/8 +/* Spartan-IIIE (1.2V) */ +#define XILINX_XC3S1200E_SIZE 3841184/8 + /* Descriptor Macros *********************************************************************/ -/* Spartan-II devices */ +/* Spartan-III devices */ #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } @@ -100,4 +104,9 @@ typedef struct { #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie } + +/* Spartan-IIIE devices */ +#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } + #endif /* _SPARTAN3_H_ */

9 27

[U-Boot-Users] [PATCH 0/6] updates for the TQM8xx board family
by Martin Krause 05 Oct '07

05 Oct '07

The following series implements some patches and updates for the TQM8xx board family. The patches should be independent from each other, but it is propably a good idea to apply them in the given order, to avoid merge conflicts. -- Martin Krause

3 16

[U-Boot-Users] [PATCH 0/4] Some patches for the TQM885D board
by Martin Krause 05 Oct '07

05 Oct '07

The following series implements some patches and updates for the TQM885D board. -- Martin Krause

3 18

[U-Boot-Users] Q) Anyone know how to debug u-boot on AT91SMA9263-EK using J-Link from Segger?
by Jeff Franks 04 Oct '07

04 Oct '07

Does anyone have a recipe for debugging u-boot on AT91SAM9263-EK target? Our proprietary board is very similar, but can't see what goes wrong. Atmel has a bootstrap that inits SDRAM, and loads u-boot image from Flash device into SDRAM. It jumps to the proper address in the SDRAM and dies. All we have to debug is J-Link from Segger along gdbserver from Segger which is an application that runs on Windows and talks via Usb to the J-Link Pod. We can talk to Windows as if it were gdbserver from a Linux host. The bootup sequence provided by Atmel looks different from u-boot in that u-boot does not move itself into SDRAM, this is done by the Atmel bootstrap. Don't know how to init SDRAM from J-Link. Has anyone done that? --jlf

3 3

[U-Boot-Users] [PATCH] Bugfix: Use only one PTD for one endpoint
by Timo Ketola 02 Oct '07

02 Oct '07

Original isp116x-hcd code prepared multiple PTDs for longer than 16 byte transfers for one endpoint. That is unnecessary because the ISP116x is able to split long data from one PTD into multiple transactions based on the buffer size of the endpoint. It also caused serious problems if the endpoint NAKed some of the transactions. In that case ISP116x wouldn't notice that the other PTDs were for the same endpoint and would try the other PTDs possibly out of order. That would break the whole transfer. This patch makes isp116x_submit_job to use one PTD for one transfer. Signed-off-by: Timo Ketola <timo.ketola(a)exertus.fi> --- --- a/drivers/isp116x-hcd.c 2007-09-07 18:43:36.000000000 +0300 +++ b/drivers/isp116x-hcd.c 2007-09-24 13:10:50.000000000 +0300 @@ -113,9 +113,9 @@ static const char hcd_name[] = "isp116x- struct isp116x isp116x_dev; struct isp116x_platform_data isp116x_board; -int got_rhsc = 0; /* root hub status change */ +static int got_rhsc; /* root hub status change */ struct usb_device *devgone; /* device which was disconnected */ -int rh_devnum = 0; /* address of Root Hub endpoint */ +static int rh_devnum; /* address of Root Hub endpoint */ /* ------------------------------------------------------------------------- */ @@ -522,11 +522,13 @@ static int unpack_fifo(struct isp116x *i done += PTD_GET_LEN(&ptd[i]); cc = PTD_GET_CC(&ptd[i]); - if (cc == TD_DATAUNDERRUN) { /* underrun is no error... */ - DBG("allowed data underrun"); - cc = TD_CC_NOERROR; - } - if (cc != TD_CC_NOERROR && ret == TD_CC_NOERROR) + + /* Data underrun means basically that we had more buffer space than + * the function had data. It is perfectly normal but upper levels have + * to know how much we actually transferred. + */ + if (cc == TD_NOTACCESSED || + (cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN))) ret = cc; } @@ -592,11 +594,19 @@ static int isp116x_interrupt(struct isp1 return ret; } -#define PTD_NUM 64 /* it should be enougth... */ -struct ptd ptd[PTD_NUM]; +/* With one PTD we can transfer almost 1K in one go; + * HC does the splitting into endpoint digestible transactions + */ +struct ptd ptd[1]; + static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe) { - return min(PTD_NUM * usb_maxpacket(dev, pipe), PTD_NUM * 16); + unsigned mpck = usb_maxpacket(dev, pipe); + + /* One PTD can transfer 1023 bytes but try to always + * transfer multiples of endpoint buffer size + */ + return 1023 / mpck * mpck; } /* Do an USB transfer @@ -610,13 +620,21 @@ static int isp116x_submit_job(struct usb int max = usb_maxpacket(dev, pipe); int dir_out = usb_pipeout(pipe); int speed_low = usb_pipeslow(pipe); - int i, done, stat, timeout, cc; - int retries = 10; + int i, done = 0, stat, timeout, cc; + + /* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */ + int retries = 500; DBG("------------------------------------------------"); dump_msg(dev, pipe, buffer, len, "SUBMIT"); DBG("------------------------------------------------"); + if (len >= 1024) { + ERR("Too big job"); + dev->status = USB_ST_CRC_ERR; + return -1; + } + if (isp116x->disabled) { ERR("EPIPE"); dev->status = USB_ST_CRC_ERR; @@ -653,29 +671,15 @@ static int isp116x_submit_job(struct usb isp116x_write_reg32(isp116x, HCINTSTAT, 0xff); /* Prepare the PTD data */ - done = 0; - i = 0; - do { - ptd[i].count = PTD_CC_MSK | PTD_ACTIVE_MSK | - PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out)); - ptd[i].mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum); - ptd[i].len = PTD_LEN(max > len - done ? len - done : max) | - PTD_DIR(dir); - ptd[i].faddr = PTD_FA(usb_pipedevice(pipe)); - - usb_dotoggle(dev, epnum, dir_out); - done += PTD_GET_LEN(&ptd[i]); - i++; - if (i >= PTD_NUM) { - ERR("****** Cannot pack buffer! ******"); - dev->status = USB_ST_BUF_ERR; - return -1; - } - } while (done < len); - ptd[i - 1].mps |= PTD_LAST_MSK; + ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK | + PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out)); + ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK; + ptd->len = PTD_LEN(len) | PTD_DIR(dir); + ptd->faddr = PTD_FA(usb_pipedevice(pipe)); +retry_same: /* Pack data into FIFO ram */ - pack_fifo(isp116x, dev, pipe, ptd, i, buffer, len); + pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len); #ifdef EXTRA_DELAY wait_ms(EXTRA_DELAY); #endif @@ -738,17 +742,42 @@ static int isp116x_submit_job(struct usb } /* Unpack data from FIFO ram */ - cc = unpack_fifo(isp116x, dev, pipe, ptd, i, buffer, len); + cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len); + + i = PTD_GET_COUNT(ptd); + done += i; + buffer += i; + len -= i; - /* Mmm... sometime we get 0x0f as cc which is a non sense! - * Just retry the transfer... + /* There was some kind of real problem; Prepare the PTD again + * and retry from the failed transaction on */ - if (cc == 0x0f && retries-- > 0) { - usb_dotoggle(dev, epnum, dir_out); - goto retry; + if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) { + if (retries >= 100) { + retries -= 100; + /* The chip will have toggled the toggle bit for the failed + * transaction too. We have to toggle it back. + */ + usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd)); + goto retry; + } + } + /* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed + * the transactions from the first on for the whole frame. It may be busy and we retry + * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the + * PTD didn't make it because the function was busy or the frame ended before the PTD + * finished. We prepare the rest of the data and try again. + */ + else if (cc == TD_NOTACCESSED || PTD_GET_ACTIVE(ptd) || (cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) { + if (retries) { + --retries; + if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) goto retry_same; + usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd)); + goto retry; + } } - if (cc != TD_CC_NOERROR) { + if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) { DBG("****** completition code error %x ******", cc); switch (cc) { case TD_CC_BITSTUFFING: @@ -766,6 +795,7 @@ static int isp116x_submit_job(struct usb } return -cc; } + else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd)); dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)"); @@ -1369,6 +1399,8 @@ int usb_lowlevel_init(void) DBG(""); + got_rhsc = rh_devnum = 0; + /* Init device registers addr */ isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR; isp116x->data_reg = (u16 *) ISP116X_HCD_DATA;

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[U-Boot-Users] a problem about rtl8139 driver on sandpoint8245 board
by Lucas Jin 01 Oct '07

01 Oct '07

Hi, all I am debuging RTL8139 driver for a board based on Sandpoint8245 and I have a problem. The CPU panic on line 529 in rtl8139.c. (outb(CmdReset, ioaddr + ChipCmd);) Serial port displayed: ( Bad trap at PC: fffffffc, SR: 1000, vector=800 NIP: FFFFFFFC XER: 20000000 LR: 00001288 REGS: 077ceb30 TRAP: 0800 DAR: 077CECC0 MSR: 00001000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 00000010 077CEC20 FFFFFF1F 00000000 0000000A 00000010 FFFFFFFB 00000000 GPR08: 00000040 81000000 00000000 FFFFFFFF 00000020 A7AC5E24 07FFD000 080D1000 GPR16: 31380950 8E109020 05808002 55D84040 00003032 00000001 00000000 00000001 GPR24: 00000000 077CEEA8 077CEFC8 00000005 07FF80C8 077CEF94 07FFD6D8 00000000 Call backtrace: Exception in kernel pc fffffffc signal 0 ) The value of ioaddr is 0x80000000 The value of _IO_BASE outb uses is defined as 0 Thank you all Jinlu

3 3

[U-Boot-Users] litekit mx31 u-boot port successly.
by Andy 01 Oct '07

01 Oct '07

Hi, I have successly ported u-boot to litekit mx31 board. It run at 532MHz and include LAN driver. The u-boot version is 1.2.0. If anyone is interested in this. e-mail to ting0609(a)yahoo.com.tw for detail. Best Regards. ____________________________________________________________________________________ 設定安全圖章，保護您的 Yahoo!奇摩帳號不被駭客盜用！ http://tw.info.yahoo.com/seal/index.html

4 3

[U-Boot-Users] This yacht is in every magazine out there
by eki11＠enersur.com.pe 30 Sep '07

30 Sep '07

FRLE Facility Hits 75% Capacity Of production On Orders Fearless International FRLE.OB Current: $0.32 Fearless International released the Porsche Designed "Fearless 28" as the feature yacht this year in Miami. Since the release, fearless has nearly maxed their production line to fill orders. Media coverage has been extensive, including GQ, Bloomberg Markets, Time, and many more. Go to fearlessyachts dot com to watch the video and see all the media coverage. It will blow you away. This will be one of the top trades this year, get on it first thing Monday.

1 0

[U-Boot-Users] Need help understanding cpu/mpc85xx/start.S
by robert lazarski 29 Sep '07

29 Sep '07

Hi all, My custom 85xx board code off of the latest u-boot git repo is dying - or locking up the bdi somehow - and I've spent the last few days trying to understand the code and how the bdi can tell me what the registers are doing. Starting with the basics: R1 has a 4K stack from 0xfffff000-0xffffffff and the stack grows down? Here's the part of the code I'm crashing in and which I trying to understand, shown here from vim with lines enabled: 158 bl tlb1_entry 159 mr r5,r0 160 lwzu r4,0(r5) /* how many TLB1 entries we actually use */ 161 mtctr r4 162 163 0: lwzu r6,4(r5) 164 lwzu r7,4(r5) 165 lwzu r8,4(r5) 166 lwzu r9,4(r5) 167 mtspr MAS0,r6 168 mtspr MAS1,r7 169 mtspr MAS2,r8 170 mtspr MAS3,r9 171 isync 172 msync 173 tlbwe 174 isync 175 bdnz 0b 176 177 1: Are lines 158-171 setting up the TLB's as defined by 'bl tlb1_entry' ? Line 160 is disassembled to be address fffff0b8 , which I can set a breakpoint to and analyze as follows: ATUM>bi 0xfffff0b8 Breakpoint identification is 0 ATUM>go - TARGET: stopped ATUM>info Target CPU : MPC85xx (e500v2 rev.2) Target state : halted Debug entry cause : instruction breakpoint Current PC : 0xfffff0b8 Current CR : 0x00000000 Current MSR : 0x00000200 Current LR : 0xfffff0b4 Current CCSRBAR : 0x0_e0000000 ATUM>rd GPR00: fffff210 fffff0b4 00010001 00000000 GPR04: 00000000 fffff210 00000000 00000000 GPR08: 00000000 00000000 00000000 00000000 GPR12: 00000000 00000000 00000000 00000000 GPR16: 00000000 00000000 00000000 00000000 GPR20: 00000000 00000000 00000000 00000000 GPR24: 00000000 00000000 00000000 00000000 GPR28: 00000000 00000000 00000000 00000000 CR : 00000000 MSR: 00000200 ATUM>mdh 0xfffff210 2 0_fffff210 : 0x0000 0 .. 0_fffff212 : 0x000b 11 .. I read the above to say that the 'rd' command shows all Rx registers as zero based, and R5 is fffff210. Line 160's 'lwzu r4,0(r5)' will read a 16bit word of a value of 'b' and assign it to R4, confirmed by the next 'ti' : ATUM>ti Target CPU : MPC85xx (e500v2 rev.2) Target state : halted Debug entry cause : single step Current PC : 0xfffff0bc Current CR : 0x00000000 Current MSR : 0x00000200 Current LR : 0xfffff0b4 Current CCSRBAR : 0x0_e0000000 ATUM>rd GPR00: fffff210 fffff0b4 00010001 00000000 GPR04: 0000000b fffff210 00000000 00000000 GPR08: 00000000 00000000 00000000 00000000 GPR12: 00000000 00000000 00000000 00000000 GPR16: 00000000 00000000 00000000 00000000 GPR20: 00000000 00000000 00000000 00000000 GPR24: 00000000 00000000 00000000 00000000 GPR28: 00000000 00000000 00000000 00000000 CR : 00000000 MSR: 00000200 Here's the part where my code or the bdi is crashing, line 163 which is mapped as fffff0c0 : 163 0: lwzu r6,4(r5) I can single step or set a breakpoint as shown below: ATUM>info Target CPU : MPC85xx (e500v2 rev.2) Target state : halted Debug entry cause : instruction breakpoint Current PC : 0xfffff0c0 Current CR : 0x00000000 Current MSR : 0x00000200 Current LR : 0xfffff0b4 Current CCSRBAR : 0x0_e0000000 ATUM>rd GPR00: fffff210 fffff0b4 00010001 00000000 GPR04: 0000000b fffff210 00000000 00000000 GPR08: 00000000 00000000 00000000 00000000 GPR12: 00000000 00000000 00000000 00000000 GPR16: 00000000 00000000 00000000 00000000 GPR20: 00000000 00000000 00000000 00000000 GPR24: 00000000 00000000 00000000 00000000 GPR28: 00000000 00000000 00000000 00000000 CR : 00000000 MSR: 00000200 'lwzu r6,4(r5)' as I read it says: load a word from R5 + 4 bytes, ie, address fffff214: ATUM>mdh 0xfffff214 2 0_fffff214 : 0x0000 0 .. 0_fffff216 : 0x0000 0 .. Disassembled u-boot in both my code _and_ current MPC8548CDS shows: fffff214: 00 00 00 00 .long 0x0 Is my problem is that I am assigning zero here? I'm confused since the CDS code seems to work the same way. The result of single stepping consistently results in: ATUM>info Target CPU : MPC85xx (e500v2 rev.2) Target state : halted Debug entry cause : instruction breakpoint Current PC : 0xfffff0c0 Current CR : 0x00000000 Current MSR : 0x00000200 Current LR : 0xfffff0b4 Current CCSRBAR : 0x0_e0000000 ATUM>ti - Core status is 0x0041 *** Core is stopped, no debugging possible # PPC: timeout while waiting for halt ATUM> Target CPU : MPC85xx (e500v2 rev.2) Target state : running # Step timeout detected I sent a question to Abatron technical support about this in the case its a bdi issue - still waiting to see what they say. Any clues please? Robert

3 7

[U-Boot-Users] Missing File ssi.h
by Jean-Christophe PLAGNIOL-VILLARD 29 Sep '07

29 Sep '07

Hi, I've a missing file "ssh.h" needs by board/sc520_spunk/sc520_spunk.c cpu/i386/sc520.c drivers/eeprom/mw_eeprom.c drivers/hwmon/ds1722.c If someone know why? Best Regards

1 0

[U-Boot-Users] BUG on board adsvix
by Jean-Christophe PLAGNIOL-VILLARD 29 Sep '07

29 Sep '07

Hi, I've the following bug on adsvix common/libcommon.a(cmd_ide.o): dans la fonction « __ide_inb »: /home/git/repos/u-boot-build/common/cmd_ide.c:821: référence indéfinie vers « inb » common/libcommon.a(cmd_ide.o): dans la fonction « __ide_outb »: /home/git/repos/u-boot-build/common/cmd_ide.c:812: référence indéfinie vers « outb » make: *** [u-boot] Erreur 1 I'm currently investigating on It.

1 0

[U-Boot-Users] [MIPS] Make mips_io_port_base more generic
by Shinya Kuribayashi 29 Sep '07

29 Sep '07

From: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> Although mips_io_port_base is currently a part of IDE command, but it is quite fundamental for MIPS memory mapped I/O port access such as in[bwl] and out[bwl]. So let's move it to MIPS generic part. This patch adds a helper routine for mips_io_port_base from Linux, and fixes two multiple definition of this variable, tb0229 and gth2. This change is triggered by gth2 build error: board/gth2/libgth2.a(gth2.o): In function `log_serial_char': /home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base' common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here make: *** [u-boot] Error 1 Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- board/gth2/gth2.c | 4 ++-- board/tb0229/tb0229.c | 6 ++---- common/cmd_ide.c | 4 ---- include/asm-mips/io.h | 16 +++++++++++++++- lib_mips/board.c | 5 +++++ 5 files changed, 24 insertions(+), 11 deletions(-) diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c index ffeaf58..3c5563e 100644 --- a/board/gth2/gth2.c +++ b/board/gth2/gth2.c @@ -26,14 +26,13 @@ #include <asm/au1x00.h> #include <asm/addrspace.h> #include <asm/mipsregs.h> +#include <asm/io.h> #include <watchdog.h> #include "ee_access.h" static int wdi_status = 0; -unsigned long mips_io_port_base = 0; - #define SDRAM_SIZE ((64*1024*1024)-(12*4096)) @@ -90,6 +89,7 @@ long int initdram(int board_type) /* If memory could be changed, we should return the true value here */ WATCHDOG_RESET(); + set_io_port_base(0); return (SDRAM_SIZE); } diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c index e7914bd..c80db56 100644 --- a/board/tb0229/tb0229.c +++ b/board/tb0229/tb0229.c @@ -13,10 +13,9 @@ #include <command.h> #include <asm/addrspace.h> #include <asm/inca-ip.h> +#include <asm/io.h> #include <pci.h> -unsigned long mips_io_port_base = 0; - #if defined(CONFIG_PCI) static struct pci_controller hose; @@ -26,17 +25,16 @@ void pci_init_board (void) } #endif - long int initdram(int board_type) { return get_ram_size (CFG_SDRAM_BASE, 0x8000000); } - int checkboard (void) { printf("Board: TANBAC TB0229 "); printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000); + set_io_port_base(0); return 0; } diff --git a/common/cmd_ide.c b/common/cmd_ide.c index bb064ea..feb89d6 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -54,10 +54,6 @@ #ifndef __PPC__ #include <asm/io.h> -#ifdef __MIPS__ -/* Macros depend on this variable */ -unsigned long mips_io_port_base = 0; -#endif #endif #ifdef CONFIG_IDE_8xx_DIRECT diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index cd4d5dc..1e060f7 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -71,7 +71,21 @@ * instruction, so the lower 16 bits must be zero. Should be true on * on any sane architecture; generic code does not use this assumption. */ -extern unsigned long mips_io_port_base; +extern const unsigned long mips_io_port_base; + +/* + * Gcc will generate code to load the value of mips_io_port_base after each + * function call which may be fairly wasteful in some cases. So we don't + * play quite by the book. We tell gcc mips_io_port_base is a long variable + * which solves the code generation issue. Now we need to violate the + * aliasing rules a little to make initialization possible and finally we + * will need the barrier() to fight side effects of the aliasing chat. + * This trickery will eventually collapse under gcc's optimizer. Oh well. + */ +static inline void set_io_port_base(unsigned long base) +{ + * (unsigned long *) &mips_io_port_base = base; +} /* * Thanks to James van Artsdalen for a better timing-fix than diff --git a/lib_mips/board.c b/lib_mips/board.c index 91ccec0..c1a0acf 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -62,6 +62,11 @@ static ulong mem_malloc_start; static ulong mem_malloc_end; static ulong mem_malloc_brk; +/* + * mips_io_port_base is the begin of the address space to which x86 style + * I/O ports are mapped. + */ +unsigned long mips_io_port_base = -1; /* * The Malloc area is immediately below the monitor copy in DRAM

2 2

[U-Boot-Users] u-boot init problem on ml403 (virtex-4) board
by Miroslaw Dach 28 Sep '07

28 Sep '07

Dear All, I am trying to use u-boot 1.2.0 on my avnet evaluation board (ml403 like with virtex-4 chip with built-in ppc405). My observation is as following: I am able to run linux v2.6.21 v2.6.22 v2.6.23 (zImage.elf) on my board. Linux always boots correctly. My board has 32 MB of RAM and 8 MB of Flash. Right now I run all of the software straight from RAM (by means of jtag). For couple of weeks I am dealing with u-boot with UART lite serial console. My observation is as following that u-boot does not always run properly. The u-boot crashes (or has some initialization problems) in most cases when I go through following steps: 1. I load Linux zImage.elf via jtag: XMD% dow zImage.elf section, .text: 0x00400000-0x004036c4 section, .data: 0x00404000-0x00505000 section, .bss: 0x00505000-0x0050719c Downloaded Program zImage.elf Setting PC with program start addr = 0x00400000 PC reset to 0x00400000, Clearing MSR Register XMD% run 2. Linux loads and boot always without any problems 3. Next I stop Linux and load u-boot via jtag XMD% dow u-bootXil section, .text: 0x00800000-0x0080e85c section, .resetvec: 0x00815050-0x00815054 section, .rodata: 0x0080e85c-0x00811027 section, .reloc: 0x00811100-0x00811770 section, .data: 0x00811770-0x00811c60 section, .data.rel: 0x00811c60-0x00811c8c section, .data.rel.local: 0x00811c8c-0x008120c4 section, .u_boot_cmd: 0x008120c4-0x00812364 section, .bss: 0x00812400-0x00815050 Downloaded Program u-bootXil Setting PC with program start addr = 0x00800100 PC reset to 0x00800100, Clearing MSR Register XMD% run ----------------------------------------------------------------- The output on the console is as following: ----------------------------------------------------------------- U-Boot 1.2.0 (Sep 25 2007 - 09:24:54) ### No HW ID - assuming ML403 DRAM: 32 MB Top of RAM usable for U-Boot at: 02000000 Reserving 84k for U-Boot at: 01fea000 Reserving 129k for malloc() at: 01fc9c00 Reserving 120 Bytes for Board Info at: 01fc9b88 Reserving 48 Bytes for Global Data at: 01fc9b58 Stack Pointer at: 01fc9b38 New Stack Pointer is: 01fc9b38 Now running in RAM - U-Boot at: 01fea000 Using default environment Bus Fault @ 0x01ff34dc, fixup 0x00000000 Machine check in kernel mode. Caused by (from msr): regs 01fc98f8 Data parity signal NIP: 01FF34DC XER: 00000000 LR: 01FF2F40 REGS: 01fc98f8 TRAP: 0200 DAR: 00000000 MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 00000000 01FC99E8 C01F3950 01AEA000 00000120 00000000 00000001 00000021 -------------------------------------------------------------------------- Sometimes u-boot dos not crash but it seems to be something wrong with board info: -------------------------------------------------------------------------- U-Boot 1.2.0 (Sep 24 2007 - 12:48:09) ### No HW ID - assuming ML403 DRAM: 32 MB Top of RAM usable for U-Boot at: 02000000 Reserving 83k for U-Boot at: 01feb000 Reserving 129k for malloc() at: 01fcac00 Reserving 120 Bytes for Board Info at: 01fcab88 Reserving 48 Bytes for Global Data at: 01fcab58 Stack Pointer at: 01fcab38 New Stack Pointer is: 01fcab38 Now running in RAM - U-Boot at: 01feb000 ˙ţď\In: ˙ţď\Err: U-Boot relocated to 01feb000 ### main_loop entered: bootdelay=3 ### main_loop: bootcmd="tftp 0x500000 uImage; bootm 0x500000" Hit any key to stop autoboot: 3 2 1 0 => bdinfo bd address = 0x0memstart = 0x00000000 memsize = 0x0flashstart = 0x00000000 flashsize = 0x00000000 flashoffset = 0x00000000 sramstart = 0x00000000 sramsize = 0x00000000 bootflags = 0xCprocfreq = 100 MHz plb_busfreq = 100 MHz ethaddr = 00:ţ:C:˙ď:D:0 IP addr = 129.129.144.83 baudrate = 9600 bps => md 01fcab88 100 01fcab88: ................ 01fcab98: ............. . 01fcaba8: ...S.P.F........ 01fcabb8: ......%.1.2.U-Bo 01fcabc8: ot 1.2.0........ 01fcabd8: ................ 01fcabe8: ................ 01fcabf8: ................ 01fcac08: ..r|bootargs=con 01fcac18: sole=ttyUL0,9600 01fcac28: root=/dev/nfs r 01fcac38: w nfsroot=129.12 01fcac48: 9.144.113:/opt/e 01fcac58: ldk41/ppc_4xx,tc 01fcac68: p ip=::::virtex 01fcac78: 4-mirek:eth0:dhc 01fcac88: p panic=1.bootcm 01fcac98: d=tftp 0x500000 01fcaca8: uImage; bootm 0x 01fcacb8: 500000.bootdelay 01fcacc8: =3.baudrate=9600 01fcacd8: .loads_echo=1.et 01fcace8: haddr=00:50:C2:4 01fcacf8: 6:D8:01.ipaddr=1 01fcad08: 29.129.144.83.se 01fcad18: rverip=129.129.1 01fcad28: 44.113.hostname= 01fcad38: virtex4-mirek.lo 01fcad48: adaddr=0x500000. 01fcad58: stdin=.stdout=.s 01fcad68: tderr=.......... 01fcad78: ................ ------------------------------------------------------------------------- When u-boot starts properly the output looks like below: ------------------------------------------------------------------------- U-Boot 1.2.0 (Sep 24 2007 - 12:48:09) ### No HW ID - assuming ML403 DRAM: 32 MB Top of RAM usable for U-Boot at: 02000000 Reserving 83k for U-Boot at: 01feb000 Reserving 129k for malloc() at: 01fcac00 Reserving 120 Bytes for Board Info at: 01fcab88 Reserving 48 Bytes for Global Data at: 01fcab58 Stack Pointer at: 01fcab38 New Stack Pointer is: 01fcab38 Now running in RAM - U-Boot at: 01feb000 Using default environment In: serial Out: serial Err: serial U-Boot relocated to 01feb000 ### main_loop entered: bootdelay=3 ### main_loop: bootcmd="tftp 0x500000 uImage; bootm 0x500000" Hit any key to stop autoboot: 3 2 1 0 => bdinfo bd address = 0x01FCAB88 memstart = 0x00000000 memsize = 0x02000000 flashstart = 0x00000000 flashsize = 0x00000000 flashoffset = 0x00000000 sramstart = 0x00000000 sramsize = 0x00000000 bootflags = 0xC1CB7D60 procfreq = 100 MHz plb_busfreq = 100 MHz ethaddr = 00:50:C2:46:D8:01 IP addr = 129.129.144.83 baudrate = 9600 bps ------------------------------------------------------------------------ I was trying to play with various u-boot parameters (CFG_ or CONFIG_ ) but I have never got it running reliably. My observation is also as following ACTION (jtag side): STATUS: load zImage.elf run runs properly (always) stop load u-boot run crashes (in most cases) stop load u-boot run runs properly (in most cases) stop load u-boot run runs properly (in most cases) stop Does somebody have some hints what could be wrong? Best Regards Mirek p.s. I attache to this e-mail my config file include/configs/ml403.h

3 3

[U-Boot-Users] TEXT_BASE question
by robert lazarski 28 Sep '07

28 Sep '07

Hi all, I see that many boards use, and that TEXT_BASE is often defined in config.mk . In my 85xx case, I have: TEXT_BASE = 0xfff80000 However, some of my registers are using TEXT_BASE + DATA that don't seem right. In the bdi I get: ATUM>rd ivor15 ivor15 : 0x00000f00 3840 That seems out of range of my 4K stack before relocation, could that be a problem or am I simply reading this wrong? Thanks, Robert

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[U-Boot-Users] gaon
by Jeegar blamey 28 Sep '07

28 Sep '07

Mining Sector --- Delta Mining UPDATE HOT SECTOR: Additional information on (O_T_C: D M X C) D M X C is expected to arrive soon. For those of you who currently own this company this will be great news. For those that don't currently own this company, you need to get in on this now. The company recently traded as high as .13 and with any significant news should be able to see (if not exceed) those prices again. Contact your broker now, don't miss this opportunity in D M X C!

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[U-Boot-Users] make entry for creating new folder in standalone board
by nivas 28 Sep '07

28 Sep '07

Hi All, lam using u-boot-1.1.6 source(cpu-arm926ejs board-mcs8140(our standalone board). I want to create a new folder under my board(mcs8140) for some validation code. how to make entry for new folder and how to create a makefile in new folder? Please give me a solution for above problem. Srinivas Rao.Ch -- View this message in context: http://www.nabble.com/make-entry-for-creating-new-folder-in-standalone-boar… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] Please help me!
by zxl 28 Sep '07

28 Sep '07

Hi: My u-boot can not start. DRAM: 64 MB Flash: 1 MB NAND: 64 MB *** Warning - bad CRC or NAND, using default environment It stop here. Please help me, thanks! Note: u-boot-1.1.6 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.

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[U-Boot-Users] Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial
by Jean-Christophe PLAGNIOL-VILLARD 28 Sep '07

28 Sep '07

Hi, Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index 27eb73a..1b0e147 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -125,6 +125,8 @@ serial_puts (const char *s) #elif defined(CONFIG_LPC2292) +DECLARE_GLOBAL_DATA_PTR; + #include <asm/arch/hardware.h> void serial_setbrg (void) Best Regards Jean-Christophe PLAGNIOL-VILLARD

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[U-Boot-Users] FPGA loading question
by E Robertson 27 Sep '07

27 Sep '07

Hi All, I've got a Spartan3E fpga I'm trying to program serially with a bin file. Is there any similar driver available to so this? I'm not sure if this is better done as a driver with embedded binary or as part of a hust script but the bin file embedded in the u-boot source. (I'm not sure if the latter is possible). Thanks.

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[U-Boot-Users] Looking for Help booting Kernel
by Nick Droogh 27 Sep '07

27 Sep '07

Hi, I am trying to boot the latest kernel for a MPC5200B based board from DENX. I built the latest UBoot which seems to run fine on my board. With the new uboot, my same environment variables, I can still boot my old kernel. U-Boot 1.3.0-rc2-dirty (Sep 24 2007 - 08:08:49) CPU: MPC5200 v1.2, Core v1.1 at 462 MHz Bus 132 MHz, IPB 132 MHz, PCI 33 MHz Board: MyBoard MPC5200 Controller I2C: 343 kHz, ready DRAM: 128 MB FLASH: 64 MB In: serial Out: serial Err: serial Net: FEC ETHERNET IDE: Bus 0: not available Type "run net_nfs" to mount root filesystem over NFS Hit any key to stop autoboot: 0 Using FEC ETHERNET device TFTP from server 192.168.100.102; our IP address is 192.168.100.11 Filename 'uImage'. Load address: 0x200000 Loading: ################################################################# ############################################# done Bytes transferred = 1612360 (189a48 hex) ## Booting image at 00200000 ... Image Name: Linux-2.6.19.2 Created: 2007-09-21 8:11:59 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 1612296 Bytes = 1.5 MB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK id mach(): done MMU:enter MMU:hw init MMU:mapin MMU:setio MMU:exit setup_arch: enter setup_arch: bootmem arch: exit Linux version 2.6.19.2 (nick@nick_lnx) (gcc version 4.0.0 (DENX ELDK 4.1 4.0.0)) \ #5 Fri Sep 21 04:11:50 EDT 2007 Zone PFN ranges: DMA 0 -> 32768 Normal 32768 -> 32768 early_node_map[1] active PFN ranges 0: 0 -> 32768 Built 1 zonelists. Total pages: 32512 Kernel command line: root=/dev/nfs rw nfsroot=192.168.100.102:/opt/eldk/ppc_6xx \ ip=192.168.100.11:192.168.100.102:192.168.100.102:255.255.255.0:\ MyBoard:eth0:off console=ttyPSC0,115200 panic=1 PID hash table entries: 512 (order: 9, 2048 bytes) I-pipe 1.5-00: pipeline enabled. Console: colour dummy device 80x25 ... and the kernel runs fine. With the latest kernel from Denx, I get the following: U-Boot 1.3.0-rc2-dirty (Sep 24 2007 - 08:08:49) CPU: MPC5200 v1.2, Core v1.1 at 462 MHz Bus 132 MHz, IPB 132 MHz, PCI 33 MHz Board: MyBoard MPC5200 Controller I2C: 343 kHz, ready DRAM: 128 MB FLASH: 64 MB In: serial Out: serial Err: serial Net: FEC ETHERNET IDE: Bus 0: not available Type "run net_nfs" to mount root filesystem over NFS Hit any key to stop autoboot: 0 => boot Using FEC ETHERNET device TFTP from server 192.168.100.102; our IP address is 192.168.100.11 Filename 'uImage'. Load address: 0x200000 Loading: ################################################################# ################## done Bytes transferred = 1212323 (127fa3 hex) ## Booting image at 00200000 ... Image Name: Linux-2.6.23-rc6-gea60adb5-dirty Created: 2007-09-26 9:53:02 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 1212259 Bytes = 1.2 MB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK Is there anything special I need to pass to the kernel for setting up the console on the MPC5200B? I had to change ttyS0 to ttyPSC0 for the old console to work. Is there anything I need to enable inside the kernel? The kernel command line is: root=/dev/nfs rw nfsroot=192.168.100.102:/opt/eldk/ppc_6xx \ ip=192.168.100.11:192.168.100.102:192.168.100.102:255.255.255.0:\ MyBoard:eth0:off console=ttyPSC0,115200 panic=1 Many thanks, Nick

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Re: [U-Boot-Users] Problem with Lite5200 DDR configuration
by Txema Lopez 27 Sep '07

27 Sep '07

Prakash Palanisamy, TLS-Chennai wrote: > Hi, > > We are using u-Boot in Lite5200B with DDR. We compiled the u-Boot with > “ icecube_5200_DDR_LOWBOOT_config” option and flashed the image in to > flash at * 0xFF800000 * . > > The problem we are facing is, > > The image is *booting* only if we flash the image in *both (0xFF800000 > and 0xFF000000) places*. The reset vector for the two configurations > (icecube_5200_LOWBOOT & icecube_5200_DDR_LOWBOOT) are same. > > We have tried by writing different images in these locations and found > that the booted image is the one which is flashed in 0xFF800000. But > if erase the image at 0xFF000000, it is not booting. > The Lite5200B has two banks of 16Mbtes flash, so if you flashed U-Boot in the 0xFF800000 you are putting it in the meddle of the flash, nor in theLOWBOOT location, nor in the HIGH boot location. When you flash a new U-Boot in the 0xFF000000 the system starts from this location but I think there is a jump to the U-Boot flashed in the 0xFF800000 because your TEXT_BASE ( the address reference for the linker) in U-Boot is 0xFF800000. The correct address for the LOWBOOT in the Lite5200B is 0xFF000000. Best Regards, Txema.

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[U-Boot-Users] Problem with Lite5200 DDR configuration
by Prakash Palanisamy, TLS-Chennai 27 Sep '07

27 Sep '07

Hi, We are using u-Boot in Lite5200B with DDR. We compiled the u-Boot with "icecube_5200_DDR_LOWBOOT_config" option and flashed the image in to flash at 0xFF800000. The problem we are facing is, The image is booting only if we flash the image in both (0xFF800000 and 0xFF000000) places. The reset vector for the two configurations (icecube_5200_LOWBOOT & icecube_5200_DDR_LOWBOOT) are same. We have tried by writing different images in these locations and found that the booted image is the one which is flashed in 0xFF800000. But if erase the image at 0xFF000000, it is not booting. In the README for Icecube is as follows ------------------------------------------------------------------------ --- Build target Flash address | BDI "go" command | Reset Vector ------------------------------------------------------------------------ --- Lite5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100 Lite5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100 Lite5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 icecube_5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100 icecube_5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100 icecube_5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 icecube_5200_DDR 0xFFF00000 | 0xFFF00100 | 0xFFF00100 icecube_5200_DDR_LOWBOOT 0xFF800000 | 0xFF800100 | 0x00000100 icecube_5200_DDR_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 ------------------------------------------------------------------------ --- Can any one help me to find out the issue? Thanks & Regards, P.Prakash DISCLAIMER: ----------------------------------------------------------------------------------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. It shall not attach any liability on the originator or HCL or its affiliates. Any views or opinions presented in this email are solely those of the author and may not necessarily reflect the opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of the author of this e-mail is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any mail and attachments please check them for viruses and defect. -----------------------------------------------------------------------------------------------------------------------

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