September 2007 - U-Boot

[U-Boot-Users] [PATCH] 85xx io out functions need sync after write.
by Ed Swarthout 27 Sep '07

27 Sep '07

This fixes the mc146818 rtc_read/write functions for 85xx. Signed-off-by: Ed Swarthout <Ed.Swarthout(a)freescale.com> --- cpu/mpc85xx/start.S | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 2c98c2a..5d65190 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -701,6 +701,7 @@ in8: .globl out8 out8: stb r4,0x0000(r3) + sync blr /*------------------------------------------------------------------------------- */ @@ -710,6 +711,7 @@ out8: .globl out16 out16: sth r4,0x0000(r3) + sync blr /*------------------------------------------------------------------------------- */ @@ -719,6 +721,7 @@ out16: .globl out16r out16r: sthbrx r4,r0,r3 + sync blr /*------------------------------------------------------------------------------- */ @@ -728,6 +731,7 @@ out16r: .globl out32 out32: stw r4,0x0000(r3) + sync blr /*------------------------------------------------------------------------------- */ @@ -737,6 +741,7 @@ out32: .globl out32r out32r: stwbrx r4,r0,r3 + sync blr /*------------------------------------------------------------------------------- */ -- 1.5.3.1.65.g47184

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[U-Boot-Users] need help to bringup LCD via SPI interface
by Dharmosoth Seetharam 27 Sep '07

27 Sep '07

Hi, I am using the atmel board (AT91sam9263ek) and cpu type is at91sam926x. working on u-boot-1.3.0 source code. my board is up now and booting the kernel ... i need help to configure (activate) LCD via SPI interface. Can you please help me how do i enable the LCD using the SPI bus ?? As per my board specification, it has to work with SPI interface. What i am not able to find is how do i setup SPI interface for some registers to write?? Thanks in advance Seetharam --------------------------------- Luggage? GPS? Comic books? Check out fitting gifts for grads at Yahoo! Search.

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[U-Boot-Users] RFC on davinci Nand support changes
by Troy Kisky 27 Sep '07

27 Sep '07

This patch fixes Nand largepage support for Davinci Changes the ecc values stored in the spare bytes so that an erased block does not contain ecc errors. The ecc correction function is much easier to read. Chip select other than CS2 should also work now but not tested. The bus width now comes from the EM_WIDTH pin. Normal gpio may be used for EM_WAIT function. What I mainly want commented on is whether we should emulate software ECC for the hardware ecc as the hardware is flexible. I think it would be nice to use 8 - 256 byte eccs instead of 4 - 512 byte eccs. But I haven't changed that yet. I sent this to the davinci mailing list, but didn't get much interest. Linux must be modified to match the ecc if it will read blocks that u-boot writes diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c index 127be9f..2fecaed 100644 --- a/cpu/arm926ejs/davinci/nand.c +++ b/cpu/arm926ejs/davinci/nand.c @@ -52,32 +52,35 @@ extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; -static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd) -{ - struct nand_chip *this = mtd->priv; - u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); +unsigned char nandCtlSetClr[] = { + 0x00, /*1 - NAND_CTL_SETNCE, 2 - NAND_CTL_CLRNCE, Select/Deselect Chip Select (nCE) */ + MASK_CLE, /*3 - NAND_CTL_SETCLE, 4 - NAND_CTL_CLRCLE, Select/Deselect the command latch (CLE) */ + MASK_ALE, /*5 - NAND_CTL_SETALE, 6 - NAND_CTL_CLRALE, Select/Deselect the address latch (ALE) */ + 0x00, /*7 - NAND_CTL_SETWP, 8 - NAND_CTL_CLRWP, Set/Clear write protection (WP) Not used! */ +}; - switch (cmd) { - case NAND_CTL_SETCLE: - IO_ADDR_W |= MASK_CLE; - break; - case NAND_CTL_SETALE: - IO_ADDR_W |= MASK_ALE; - break; +static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd) +{ + cmd--; + if ((cmd>=0)&&(cmd<8)) { + struct nand_chip *nand = mtd->priv; + u_int32_t addr = (u_int32_t)nand->IO_ADDR_W; + if (cmd&1) addr &= ~nandCtlSetClr[cmd>>1]; + else addr |= nandCtlSetClr[cmd>>1]; + nand->IO_ADDR_W = (void *)addr; + } else { + DEBUG (MTD_DEBUG_LEVEL0, "Invalid command 0x%x\n",cmd+1); } - - this->IO_ADDR_W = (void *)IO_ADDR_W; } /* Set WP on deselect, write enable on select */ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) { +#ifdef SONATA_BOARD_GPIOWP #define GPIO_SET_DATA01 0x01c67018 #define GPIO_CLR_DATA01 0x01c6701c #define GPIO_NAND_WP (1 << 4) -#ifdef SONATA_BOARD_GPIOWP if (chip < 0) { REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; } else { @@ -91,232 +94,217 @@ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) static struct nand_oobinfo davinci_nand_oobinfo = { .useecc = MTD_NANDECC_AUTOPLACE, .eccbytes = 12, +#if 1 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, - .oobfree = { {2, 6}, {12, 12}, {28, 12}, {44, 12}, {60, 4} } + /* The 1st two bytes of spare are reserved for factory bad block markers */ + .oobfree = { {2, 6}, {11, 13}, {27, 13}, {43, 13}, {59, 5} } +#else + /* I would prefer this format, or the software format with 8 eccs in 256 byte groups (nand_oob_64 in nand_base), what do you think? */ + .eccpos = {2,3,4, 5,6,7, 8,9,10, 11,12,13}, + /* The 1st two bytes of spare are reserved for factory bad block markers */ + .oobfree = { {14, 50} } +#endif }; #elif defined(CFG_NAND_SMALLPAGE) static struct nand_oobinfo davinci_nand_oobinfo = { .useecc = MTD_NANDECC_AUTOPLACE, .eccbytes = 3, .eccpos = {0, 1, 2}, - .oobfree = { {6, 2}, {8, 8} } + .oobfree = { {6, 10} } }; #else #error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" #endif -static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) -{ - emifregs emif_addr; - int dummy; - - emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - dummy = emif_addr->NANDF1ECC; - dummy = emif_addr->NANDF2ECC; - dummy = emif_addr->NANDF3ECC; - dummy = emif_addr->NANDF4ECC; - emif_addr->NANDFCR |= (1 << 8); -} - -static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) +static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t chipNum) { u_int32_t ecc = 0; emifregs emif_base_addr; emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - if (region == 1) - ecc = emif_base_addr->NANDF1ECC; - else if (region == 2) - ecc = emif_base_addr->NANDF2ECC; - else if (region == 3) - ecc = emif_base_addr->NANDF3ECC; - else if (region == 4) - ecc = emif_base_addr->NANDF4ECC; - + ecc = emif_base_addr->NANDF_ECC[chipNum]; return(ecc); } - -static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) -{ - u_int32_t tmp; - int region, n; - struct nand_chip *this = mtd->priv; - - n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; - - region = 1; - while (n--) { - tmp = nand_davinci_readecc(mtd, region); - *ecc_code++ = tmp; - *ecc_code++ = tmp >> 16; - *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0); - region++; - } - return(0); -} - -static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf) +static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { - u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8); + struct nand_chip *nand = mtd->priv; + u_int32_t addr = (u_int32_t)nand->IO_ADDR_R; + u_int32_t chipNum=(addr-CFG_NAND_BASE)>>25; /* 0 - cs2, 1 - cs3, 2 - cs4, 3 - cs5 */ + emifregs emif_addr; + int dummy; + if (chipNum>=4) return; - ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); - ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); - ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); + emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + dummy = nand_davinci_readecc(mtd, chipNum); /* reset ecc to 0 */ + emif_addr->NANDFCR |= (1 << (8+chipNum)); /* start ECC on chip select region+2 */ } -static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data) +static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { - u_int32_t i; - u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; - u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8]; - u_int8_t ecc_bit[24]; - u_int8_t ecc_sum = 0; - u_int8_t find_bit = 0; - u_int32_t find_byte = 0; - int is_ecc_ff; - - is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff)); - - nand_davinci_gen_true_ecc(ecc_nand); - nand_davinci_gen_true_ecc(ecc_calc); - - for (i = 0; i <= 2; i++) { - *(ecc_nand + i) = ~(*(ecc_nand + i)); - *(ecc_calc + i) = ~(*(ecc_calc + i)); + struct nand_chip *nand = mtd->priv; + u_int32_t addr = (u_int32_t)nand->IO_ADDR_R; + u_int32_t chipNum=(addr-CFG_NAND_BASE)>>25; /* 0 - cs2, 1 - cs3, 2 - cs4, 3 - cs5 */ + if (chipNum>=4) return -1; + u_int32_t tmp = nand_davinci_readecc(mtd, chipNum); +#ifdef CONFIG_MTD_DEBUG +/* calculate it ourself and compare */ +/* FORCE_ECC_ERROR is undefined for normal operation */ +/* #define FORCE_ECC_ERROR */ +#ifdef FORCE_ECC_ERROR + { + /* force single bit ecc error to test ecc correction code */ + u_char* p = (u_char*)dat; + unsigned int i = p[0] | (p[1]<<8); /* 1st word of block determines which bit is made in error */ + i &= 0xfff; + p[i>>3] ^= 1<<(i&7); + printf("Forcing ecc error, byte:%d, bit:%d\n",i>>3,i&7); } - - for (i = 0; i < 8; i++) { - tmp0_bit[i] = *ecc_nand % 2; - *ecc_nand = *ecc_nand / 2; - } - - for (i = 0; i < 8; i++) { - tmp1_bit[i] = *(ecc_nand + 1) % 2; - *(ecc_nand + 1) = *(ecc_nand + 1) / 2; - } - - for (i = 0; i < 8; i++) { - tmp2_bit[i] = *(ecc_nand + 2) % 2; - *(ecc_nand + 2) = *(ecc_nand + 2) / 2; - } - - for (i = 0; i < 8; i++) { - comp0_bit[i] = *ecc_calc % 2; - *ecc_calc = *ecc_calc / 2; - } - - for (i = 0; i < 8; i++) { - comp1_bit[i] = *(ecc_calc + 1) % 2; - *(ecc_calc + 1) = *(ecc_calc + 1) / 2; - } - - for (i = 0; i < 8; i++) { - comp2_bit[i] = *(ecc_calc + 2) % 2; - *(ecc_calc + 2) = *(ecc_calc + 2) / 2; - } - - for (i = 0; i< 6; i++) - ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; - - for (i = 0; i < 8; i++) - ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; - - for (i = 0; i < 8; i++) - ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; - - ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; - ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; - - for (i = 0; i < 24; i++) - ecc_sum += ecc_bit[i]; - - switch (ecc_sum) { - case 0: - /* Not reached because this function is not called if - ECC values are equal */ - return 0; - case 1: - /* Uncorrectable error */ - DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); - return(-1); - case 12: - /* Correctable error */ - find_byte = (ecc_bit[23] << 8) + - (ecc_bit[21] << 7) + - (ecc_bit[19] << 6) + - (ecc_bit[17] << 5) + - (ecc_bit[15] << 4) + - (ecc_bit[13] << 3) + - (ecc_bit[11] << 2) + - (ecc_bit[9] << 1) + - ecc_bit[7]; - - find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; - - DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit); - - page_data[find_byte] ^= (1 << find_bit); - - return(0); - default: - if (is_ecc_ff) { - if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0) - return(0); - } - DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); - return(-1); +#endif + { + unsigned int i = 0x00000fff; /* 2**12 bits/ecc MAX */ + unsigned int j = mtd->eccsize; /* 256 or 512 bytes/ecc */ + unsigned int ecc = 0; + do { + unsigned int k=i; + unsigned int v = *dat++; + do { + if (v&1) ecc ^= k; + k += (1<<16); + k--; + v >>= 1; + } while (v); + i += 8<<16; + i -= 8; + j--; + } while (j); + if (tmp!=ecc) { +#ifndef FORCE_ECC_ERROR + printf("Hardware Ecc: %x, Calculated: %x\n",tmp,ecc); +#endif + tmp=ecc; + } } +#endif + tmp = (tmp&0x0fff)|((tmp&0x0fff0000)>>4); /* squeeze 0 middle bits out so that it fits in 3 bytes */ + tmp = ~tmp; /* invert so that erased block ecc is correct */ + *ecc_code++ = (u_char)(tmp); + *ecc_code++ = (u_char)(tmp >> 8); + *ecc_code++ = (u_char)(tmp >> 16); + return(0); } + static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { - struct nand_chip *this; - int block_count = 0, i, rc; - - this = mtd->priv; - block_count = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; - for (i = 0; i < block_count; i++) { - if (memcmp(read_ecc, calc_ecc, 3) != 0) { - rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat); - if (rc < 0) { - return(rc); + u_int32_t eccNand = read_ecc[0] | (read_ecc[1]<<8) | (read_ecc[2]<< 16); + u_int32_t eccCalc = calc_ecc[0] | (calc_ecc[1]<<8) | (calc_ecc[2]<< 16); + u_int32_t diff = eccCalc ^ eccNand; + if (diff) { + if ((((diff>>12)^diff)&0xfff)==0xfff) { + /* Correctable error */ + if ( (diff>>(12+3)) < mtd->eccsize ) { + DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", diff>>(12+3), ((diff>>12)&7)); + dat[diff>>(12+3)] ^= (1 << ((diff>>12)&7)); + } else { + DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR, illegal byte # %d\n",diff>>(12+3)); + return(-1); } + } else if ((diff & (-diff))==diff) { + DEBUG (MTD_DEBUG_LEVEL0, "Single bit ECC error in the ECC itself, nothing to fix\n"); + } else { + /* Uncorrectable error */ + u_int32_t hwCalc = (~eccCalc)&0xffffff; + hwCalc = (hwCalc&0xfff)|((hwCalc&0xfff000)<<4); + DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR diff:%x nandBlock:%x calc:%x hwCalc:%08x\n",diff,eccNand,eccCalc,hwCalc); + return(-1); } - read_ecc += 3; - calc_ecc += 3; - dat += 512; } return(0); } #endif +#ifdef NAND_GPIO_READY_LIST +static unsigned char nandGpioReadyList[] = {NAND_GPIO_READY_LIST}; +#endif + static int nand_davinci_dev_ready(struct mtd_info *mtd) { - emifregs emif_addr; - - emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - return(emif_addr->NANDFSR & 0x1); +#ifdef NAND_GPIO_READY_LIST +#define GP_BANK0_OFFSET 0x10 +#define GP_BANK_LENGTH 0x28 +#define GP_DIR 0x00 +#define GP_OUT 0x04 +#define GP_SET 0x08 +#define GP_CLR 0x0C +#define GP_IN 0x10 + + struct nand_chip *nand = mtd->priv; + u_int32_t addr = (u_int32_t)nand->IO_ADDR_R; + u_int32_t chipNum=(addr-CFG_NAND_BASE)>>25; /* 0 - cs2, 1 - cs3, 2 - cs4, 3 - cs5 */ + if (chipNum<4) { + unsigned int gp = nandGpioReadyList[chipNum]; + if (gp) { + unsigned int bank = (gp>>5); + volatile unsigned int* p = (unsigned int*)(DAVINCI_GPIO_BASE+GP_BANK0_OFFSET+(bank*GP_BANK_LENGTH)); + int ret = (p[GP_IN>>2] >> (gp&0x1f))&1; + DEBUG (MTD_DEBUG_LEVEL3, "Ready: %d\n", ret); + return ret; + } + } +#endif + emifregs emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + return (emif_addr->NANDFSR & 0x1); } +/** + * nand_davinci_waitfunc - [DEFAULT] wait until the command is done + * @mtd: MTD device structure + * @this: NAND chip structure + * @state: state to select the max. timeout value + * + * Wait for command done. This applies to erase and program only + * Erase can take up to 400ms and program up to 20ms according to + * general NAND and SmartMedia specs + * +*/ static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state) { - while(!nand_davinci_dev_ready(mtd)) {;} - *NAND_CE0CLE = NAND_STATUS; - return(*NAND_CE0DATA); + ulong start = get_timer(0); + volatile u_int8_t * p = (volatile u_int8_t *)((unsigned int)this->IO_ADDR_R); + unsigned long timeout = (state == FL_ERASING)? ((CFG_HZ * 400) / 1000) : ((CFG_HZ * 20) / 1000); +#if 0 /* enable this if you don't trust your ready pin. */ + unsigned long mwait = (state == FL_ERASING)? 400 : 20; + udelay(mwait*1000); +#endif + + p[MASK_CLE] = NAND_CMD_STATUS; + + while (1) { + if (get_timer(start) > timeout) { + printf("!!!Nand wait Timeout!!!\n"); + return 1; + } + if (nand_davinci_dev_ready(mtd)) break; + } + return (*p); } -static void nand_flash_init(void) +#define BOOTCFG 0x01C40014 +int board_nand_init(struct nand_chip *nand) { - u_int32_t acfg1 = 0x3ffffffc; - u_int32_t acfg2 = 0x3ffffffc; - u_int32_t acfg3 = 0x3ffffffc; - u_int32_t acfg4 = 0x3ffffffc; - emifregs emif_regs; - + u_int32_t acfg = 0 + | (0<<31) /* selectStrobe */ + | (0<<30) /* extWait */ + | (1<<26) /* writeSetup 10 ns */ + | (3<<20) /* writeStrobe 40 ns */ + | (1<<17) /* writeHold 10 ns */ + | (1<<13) /* readSetup 10 ns */ + | (5<<7) /* readStrobe 60 ns */ + | (1<<4) /* readHold 10 ns */ + | (3<<2) /* turnAround ?? ns */ + ; + acfg |= (*((unsigned int*)BOOTCFG)>>5)&1; /* grab default width from EM_WIDTH */ /*------------------------------------------------------------------* * NAND FLASH CHIP TIMEOUT @ 459 MHz * * * @@ -324,46 +312,39 @@ static void nand_flash_init(void) * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * * * *------------------------------------------------------------------*/ - acfg1 = 0 - | (0 << 31 ) /* selectStrobe */ - | (0 << 30 ) /* extWait */ - | (1 << 26 ) /* writeSetup 10 ns */ - | (3 << 20 ) /* writeStrobe 40 ns */ - | (1 << 17 ) /* writeHold 10 ns */ - | (1 << 13 ) /* readSetup 10 ns */ - | (5 << 7 ) /* readStrobe 60 ns */ - | (1 << 4 ) /* readHold 10 ns */ - | (3 << 2 ) /* turnAround ?? ns */ - | (0 << 0 ) /* asyncSize 8-bit bus */ - ; - - emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - emif_regs->AWCCR |= 0x10000000; - emif_regs->AB1CR = acfg1; /* 0x08244128 */; - emif_regs->AB2CR = acfg2; - emif_regs->AB3CR = acfg3; - emif_regs->AB4CR = acfg4; - emif_regs->NANDFCR = 0x00000101; -} + emifregs emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + u_int32_t addr = (u_int32_t)nand->IO_ADDR_R; + u_int32_t chipNum=(addr-CFG_NAND_BASE)>>25; /* 0 - cs2, 1 - cs3, 2 - cs4, 3 - cs5 */ + if (chipNum>=4) return -1; + + emif_regs->AB_CR[chipNum] = acfg; /* 0x08244128 */ + emif_regs->NANDFCR |= 1<<chipNum; + +#ifdef NAND_GPIO_READY_LIST + { + unsigned int gp = nandGpioReadyList[chipNum]; + if (gp) { + unsigned int bank = (gp>>5); + volatile unsigned int* p = (unsigned int*)(DAVINCI_GPIO_BASE+GP_BANK0_OFFSET+(bank*GP_BANK_LENGTH)); + int val; + int bitNum = (gp&0x1f); + p[GP_DIR>>2] |= 1<<bitNum; /* make sure it's an input */ + val = (p[GP_IN>>2] >> bitNum)&1; + DEBUG (MTD_DEBUG_LEVEL3, "Bank: %x curVal:%x inReg:%p=%x\n", bank,val,&p[GP_IN>>2],p[GP_IN>>2]); + } + } +#endif -int board_nand_init(struct nand_chip *nand) -{ - nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA; - nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA; + DEBUG (MTD_DEBUG_LEVEL3, "Nand base read:%p write:%p\n",nand->IO_ADDR_R,nand->IO_ADDR_W); nand->chip_delay = 0; nand->select_chip = nand_davinci_select_chip; + nand->options = (acfg&1)? NAND_BUSWIDTH_16 : 0; #ifdef CFG_NAND_USE_FLASH_BBT - nand->options = NAND_USE_FLASH_BBT; + nand->options |= NAND_USE_FLASH_BBT; #endif #ifdef CFG_NAND_HW_ECC -#ifdef CFG_NAND_LARGEPAGE - nand->eccmode = NAND_ECC_HW12_2048; -#elif defined(CFG_NAND_SMALLPAGE) nand->eccmode = NAND_ECC_HW3_512; -#else -#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" -#endif nand->autooob = &davinci_nand_oobinfo; nand->calculate_ecc = nand_davinci_calculate_ecc; nand->correct_data = nand_davinci_correct_data; @@ -377,9 +358,6 @@ int board_nand_init(struct nand_chip *nand) nand->dev_ready = nand_davinci_dev_ready; nand->waitfunc = nand_davinci_waitfunc; - - nand_flash_init(); - return(0); } diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h index 646fc77..d6b36da 100644 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -29,10 +29,7 @@ typedef struct { dv_reg AWCCR; dv_reg SDBCR; dv_reg SDRCR; - dv_reg AB1CR; - dv_reg AB2CR; - dv_reg AB3CR; - dv_reg AB4CR; + dv_reg AB_CR[4]; dv_reg SDTIMR; dv_reg DDRSR; dv_reg DDRPHYCR; @@ -51,10 +48,7 @@ typedef struct { dv_reg NANDFCR; dv_reg NANDFSR; u_int8_t RSVD1[8]; - dv_reg NANDF1ECC; - dv_reg NANDF2ECC; - dv_reg NANDF3ECC; - dv_reg NANDF4ECC; + dv_reg NANDF_ECC[4]; } emif_registers; typedef emif_registers *emifregs; diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h index 619bd47..9c324c9 100644 --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -26,136 +26,11 @@ #ifndef _NAND_DEFS_H_ #define _NAND_DEFS_H_ -#include <asm/arch/hardware.h> - #define MASK_CLE 0x10 -#define MASK_ALE 0x0a - -#define NAND_CE0CLE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x10)) -#define NAND_CE0ALE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a)) -#define NAND_CE0DATA ((volatile u_int8_t *)CFG_NAND_BASE) - -typedef struct { - u_int32_t NRCSR; - u_int32_t AWCCR; - u_int8_t RSVD0[8]; - u_int32_t AB1CR; - u_int32_t AB2CR; - u_int32_t AB3CR; - u_int32_t AB4CR; - u_int8_t RSVD1[32]; - u_int32_t NIRR; - u_int32_t NIMR; - u_int32_t NIMSR; - u_int32_t NIMCR; - u_int8_t RSVD2[16]; - u_int32_t NANDFCR; - u_int32_t NANDFSR; - u_int8_t RSVD3[8]; - u_int32_t NANDF1ECC; - u_int32_t NANDF2ECC; - u_int32_t NANDF3ECC; - u_int32_t NANDF4ECC; - u_int8_t RSVD4[4]; - u_int32_t IODFTECR; - u_int32_t IODFTGCR; - u_int8_t RSVD5[4]; - u_int32_t IODFTMRLR; - u_int32_t IODFTMRMR; - u_int32_t IODFTMRMSBR; - u_int8_t RSVD6[20]; - u_int32_t MODRNR; - u_int8_t RSVD7[76]; - u_int32_t CE0DATA; - u_int32_t CE0ALE; - u_int32_t CE0CLE; - u_int8_t RSVD8[4]; - u_int32_t CE1DATA; - u_int32_t CE1ALE; - u_int32_t CE1CLE; - u_int8_t RSVD9[4]; - u_int32_t CE2DATA; - u_int32_t CE2ALE; - u_int32_t CE2CLE; - u_int8_t RSVD10[4]; - u_int32_t CE3DATA; - u_int32_t CE3ALE; - u_int32_t CE3CLE; -} nand_registers; - -typedef volatile nand_registers *nandregs; +#define MASK_ALE 0x08 #define NAND_READ_START 0x00 #define NAND_READ_END 0x30 #define NAND_STATUS 0x70 -#ifdef CFG_NAND_HW_ECC -#define NAND_Ecc_P1e (1 << 0) -#define NAND_Ecc_P2e (1 << 1) -#define NAND_Ecc_P4e (1 << 2) -#define NAND_Ecc_P8e (1 << 3) -#define NAND_Ecc_P16e (1 << 4) -#define NAND_Ecc_P32e (1 << 5) -#define NAND_Ecc_P64e (1 << 6) -#define NAND_Ecc_P128e (1 << 7) -#define NAND_Ecc_P256e (1 << 8) -#define NAND_Ecc_P512e (1 << 9) -#define NAND_Ecc_P1024e (1 << 10) -#define NAND_Ecc_P2048e (1 << 11) - -#define NAND_Ecc_P1o (1 << 16) -#define NAND_Ecc_P2o (1 << 17) -#define NAND_Ecc_P4o (1 << 18) -#define NAND_Ecc_P8o (1 << 19) -#define NAND_Ecc_P16o (1 << 20) -#define NAND_Ecc_P32o (1 << 21) -#define NAND_Ecc_P64o (1 << 22) -#define NAND_Ecc_P128o (1 << 23) -#define NAND_Ecc_P256o (1 << 24) -#define NAND_Ecc_P512o (1 << 25) -#define NAND_Ecc_P1024o (1 << 26) -#define NAND_Ecc_P2048o (1 << 27) - -#define TF(v) (v ? 1 : 0) - -#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) -#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) -#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) -#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) -#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) -#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) -#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) -#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) - -#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) -#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) -#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) -#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) -#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) -#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) -#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) -#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) - -#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) -#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) -#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) -#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) -#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) -#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) -#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) -#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) - -#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) -#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) -#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) -#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) -#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) -#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) -#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) -#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) - -#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) -#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) -#endif - #endif

3 7

[U-Boot-Users] U-BOOT and UART TX with interrupts (need help please)
by veter 26 Sep '07

26 Sep '07

Hello friends! We have troubles, need you help, please We usage Linux for develop and GCC. Our program based on U-BOOT and we need transmit data at UART-TX with interrupts. But, as we understand, U-BOOT do not have "API" for correct realization Interrupts, we fount in cpu/bf532/serial.c each initialization with as-be usage Interrupts, but not used it, because only doing looping ISR register on FLAG IRQ_UART_TX_BIT. It is not correct usage Interrupts. We need full usage interrupts. In /examples/ each examples with realization but for other CPU, not under BlackFin. May be you know or have examples? May be correct write our programs as standalone and run her from workspace U-BOOT? Help please do victory at this our troubles...! . ---------------------------------------------------------------------- Stanislav G. Prihodko ( ICQ #83332014 ) [www.projects.org.ua] + [www.klug.org.ua] -- View this message in context: http://www.nabble.com/U-BOOT-and-UART-TX-with-interrupts-%28need-help-pleas… Sent from the Uboot - Users mailing list archive at Nabble.com.

5 10

[U-Boot-Users] [PATCH 0/9] First wave of config changes
by Grant Likely 26 Sep '07

26 Sep '07

Here's my first set of config changes. It allows the Makefiles to conditionally compile *.o files based on the board configuration. Only CONFIG_* macros may be used in the build system. Future patches will rename many of the CFG_ macros to something prefixed with CONFIG_ I've heavily build-tested these changes for PPC, MIPS and ARM targets using MAKEALL. The build results in binaries of identical size. I've also pushed these changes to the 'kconfig-for-1.3.1' branch of the u-boot-mpc5xxx.git repository. Please review and comment. Thanks, g. -- Grant Likely, B.Sc. P.Eng. Secret Lab Technologies Ltd.

4 14

[U-Boot-Users] Environment and fonction getenv_r()
by fabien 26 Sep '07

26 Sep '07

Hello, What is the purpose of the environment ? How is it set up ? at compile time ? I don't really know how that work. Could someone give me some informations about how that work ? Thank a lot Fab

2 1

[U-Boot-Users] [PATCH] M18 flash (Sibley) support
by Vasiliy Leonenko 26 Sep '07

26 Sep '07

Hi, The following patch adds support of M18 flash in u-boot. This flash has new command set (0x200) - so most changes in code are related to dealing with it. The patch is verified on different kinds of NOR using Mainstone II platform - no issues are found. Hope to see this patch included (since M18 is widely used in embedded). Any comments and suggestions are welcome. Thanks, Vasiliy Signed-off-by: Vasiliy Leonenko <vasiliy.leonenko(a)gmail.com> Signed-off-by: Alexey Korolev <akorolex(a)gmail.com> ==================================================== --- u-boot-1.3.0-rc1.base/drivers/cfi_flash.c 2007-09-07 19:43:36.000000000 +0400 +++ u-boot-1.3.0-rc1/drivers/cfi_flash.c 2007-09-24 16:07:10.000000000 +0400 @@ -74,6 +74,7 @@ #define FLASH_CMD_PROTECT_CLEAR 0xD0 #define FLASH_CMD_CLEAR_STATUS 0x50 #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_TO_BUFFER_EXT 0xE9 #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 #define FLASH_STATUS_DONE 0x80 @@ -136,6 +137,7 @@ #define CFI_CMDSET_MITSU_STANDARD 256 #define CFI_CMDSET_MITSU_EXTENDED 257 #define CFI_CMDSET_SST 258 +#define CFI_CMDSET_INTEL_PROG_REGIONS 512 #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ # undef FLASH_CMD_RESET @@ -184,8 +186,8 @@ flash_info_t flash_info[CFG_MAX_FLASH_BA typedef unsigned long flash_sect_t; static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); -static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf); +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, ulong cmd); static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); @@ -474,6 +476,7 @@ int flash_erase (flash_info_t * info, in for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS); @@ -522,6 +525,9 @@ void flash_print_info (flash_info_t * in info->size >> 20, info->sector_count); printf (" "); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: + printf ("Intel Prog Regions"); + break; case CFI_CMDSET_INTEL_STANDARD: printf ("Intel Standard"); break; @@ -771,6 +777,7 @@ static int flash_is_busy (flash_info_t * int retval; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); @@ -825,6 +832,7 @@ static int flash_full_status_check (flas retcode = flash_status_check (info, sector, tout, prompt); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: if ((retcode == ERR_OK) @@ -903,7 +911,7 @@ static void flash_add_byte (flash_info_t /*----------------------------------------------------------------------- * make a proper sized command based on the port and chip widths */ -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf) { int i; uchar *cp = (uchar *) cmdbuf; @@ -913,13 +921,13 @@ static void flash_make_cmd (flash_info_t #else for (i = 1; i <= info->portwidth; i++) #endif - *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; + *cp++ = (i > info->chipwidth) ? '\0' : *((uchar *)&cmd + info->portwidth - i); } /* * Write a proper sized command to the correct address */ -static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, ulong cmd) { volatile cfiptr_t addr; @@ -1090,6 +1098,7 @@ static void flash_read_jedec_ids (flash_ info->device_id2 = 0; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); @@ -1209,6 +1218,7 @@ ulong flash_get_size (ulong base, int ba flash_printqry (info, 0); #endif switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: default: @@ -1289,6 +1299,7 @@ ulong flash_get_size (ulong base, int ba * Only read protection status from supported devices (intel...) */ switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: info->protect[sect_cnt] = @@ -1377,6 +1388,7 @@ static int flash_write_cfiword (flash_in flag = disable_interrupts (); switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); @@ -1422,15 +1434,19 @@ static int flash_write_cfibuffer (flash_ int retcode; volatile cfiptr_t src; volatile cfiptr_t dst; + uchar write_cmd; switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: src.cp = cp; dst.cp = (uchar *) dest; sector = find_sector (info, dest); + write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? + FLASH_CMD_WRITE_TO_BUFFER_EXT : FLASH_CMD_WRITE_TO_BUFFER; flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + flash_write_cmd (info, sector, 0, write_cmd); if ((retcode = flash_status_check (info, sector, info->buffer_write_tout, "write to buffer")) == ERR_OK) { /* reduce the number of loops by the width of the port */ @@ -1451,7 +1467,7 @@ static int flash_write_cfibuffer (flash_ return ERR_INVAL; break; } - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + flash_write_cmd (info, sector, 0, cnt - 1); while (cnt-- > 0) { switch (info->portwidth) { case FLASH_CFI_8BIT:

2 1

Re: [U-Boot-Users] adding support to new board
by Jeff Mann 26 Sep '07

26 Sep '07

See http://www.freescale.com/files/32bit/doc/app_note/AN3220.pdf -JM -----Original Message----- From: u-boot-users-bounces(a)lists.sourceforge.net [mailto:u-boot-users-bounces@lists.sourceforge.net] On Behalf Of Maximus Sent: Saturday, July 15, 2006 5:31 AM To: U-Boot-Users(a)lists.sourceforge.net Subject: [U-Boot-Users] adding support to new board Hi, Is there any document (step by step) approach on how to add u-boot support to a new board? any advices, Regards, jo ------------------------------------------------------------------------ - Using Tomcat but need to do more? Need to support web services, security? Get stuff done quickly with pre-integrated technology to make your job easier Download IBM WebSphere Application Server v.1.0.1 based on Apache Geronimo http://sel.as-us.falkag.net/sel?cmd=lnk&kid=120709&bid=263057&dat=121642 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

4 3

Re: [U-Boot-Users] (no subject)
by briano manoj 26 Sep '07

26 Sep '07

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1 0

[U-Boot-Users] 49-55811
by gokce paolini 26 Sep '07

26 Sep '07

http://goolyl.com/ greeting u-boot-users All i want for christmas is a big phat pe@nis to please my girl gokce paolini

1 0

[U-Boot-Users] Unable to write to flash..
by rags 26 Sep '07

26 Sep '07

Hi, We've been having a strange problem during our board bringup. I have given a brief description about our board, the problem we are facing and investigation done so far. Would appreciate any comments/pointers for further investigations.. I apologize in advance for the long post that follows..:-) Regards Vijay Board description: This is a MPC8360E based board with a S29GL01GP12T (16 bit) flash (size=128MB) and 256 MB DDRRam + other peripherals. We have a BDI2000 JTAG debugger connected to the board. Relevant sections of our BDI config file are given below, [INIT] ; init core register WREG MSR 0x00001002 ;MSR : ME,RI ; Move MBAR to 0xe0000000 WM32 0xff400000 0xe0000000 ;MBAR to 0xe0000000 ; Initialize LAWBAR's WM32 0xe0000020 0xf8000000 ;LBLAWBAR0 : Flash WM32 0xe0000024 0x8000001a ;LBLAWAR0 : * WM32 0xe00000A0 0x00000000 ;DDRLAWBAR0: DDR Main SODIMM WM32 0xe00000A4 0x8000001b ;DDRLAWAR0 : 256M ... WM32 0xe0005000 0xf8001001 ;BR0 : Flash WM32 0xe0005004 0xf80069f7 ;OR0 : Flash 32M ... [TARGET] BOOTADDR 0xfff00100 ;boot address used for start-up break RCW 0x84600000 0x04030006 ;override reset configuration words ... [FLASH] CHIPTYPE MIRRORX16 ;Flash type: Spansion S29GL01GP CHIPSIZE 0x08000000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) ;WORKSPACE 0x00200000 ;workspace in DDR RAM With this the processor halts at 0xFFF00100 on reset. We are able to read the system configuration registers at the relocated IMMR address and able to access the DDR Ram (starting at 0x00000000) and Flash starting at (0xF8000000). The flash contains some data that was pre-programmed (First sector contains HRCW and a U-boot image is also burned at another location). Problem description: We are able to read the contents of the flash, but unable to erase or program it (we have tried several combinations of sectors). We can confirm the read because of the pre-programmed content (HRCW + U-boot image). Is it possible to isolate this to a HW/SW(config file) issue?? Investigation done so far: We have done the following so far, 1. We have probed the address and data lines along with other control signals (Chip select etc..). Also we have made sure that the write protect remains high for the flash. All the address lines are toggling and data lines seem to be ok (since we are able to read stuff ok from the flash). Also chip select is getting issued properly at the correct time. (All these, as per our hw guys). 2. We have tried mapping the flash at different addresses with the same result 3. We used the same flash on a Freescale MDS reference board (with the same configuration for Flash) and are able to read and write successfully. Also the U-boot image burned in the flash comes up. 4. We tried using the protocol defined in the datasheet to read the 'manufacturer id' using BDI MM/MD commands. But this seems to fail in both our board and the MDS board. -- View this message in context: http://www.nabble.com/Unable-to-write-to-flash..-tf4451149.html#a12699172 Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] Protected sectors
by Frank Prepelica 26 Sep '07

26 Sep '07

Hi all, I got a question regarding protected sectors. When I build the u-boot image and program the image into the flash I can see that the area of u-boot is protected. My u-boot image needs about 3 sectors but 4 sectors are protected. Could someone please tell me in which file I can change the amount of protected sectors? Thank you very much! Best regards, Frank

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[U-Boot-Users] flash file system on flash chip
by raj reddy 26 Sep '07

26 Sep '07

Hi, My flash chip size is 1MB. U-boot takes 256k, rest is free. what's the size it takes when I create flash file system on the flash chip? I want to place small size file in the flash file system. How can i do that? If so how can I access that file from flash file system. Raj. Forgot the famous last words? Access your message archive online at http://in.messenger.yahoo.com/webmessengerpromo.php

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[U-Boot-Users] autoscr can't execute script in u-boot 1.2.0
by frisky_linux 26 Sep '07

26 Sep '07

Hi all, I have tested the autoscr command and found that autoscr can't execute script in u-boot 1.2.0. The steps follow here: 1. Generate autos.img 1) echo "printenv serverip" >>test.txt 2) mkimage [frisky@FC6 test]$ mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n "auto script example" -d test.txt autos.img && rm -rf /tftpboot/coreblade/autos.img && cp autos.img /tftpboot/coreblade/ Image Name: auto script example Created: Wed Sep 26 10:17:46 2007 Image Type: PowerPC Linux Script (uncompressed) Data Size: 27 Bytes = 0.03 kB = 0.00 MB Load Address: 0x00000000 Entry Point: 0x00000000 Contents: Image 0: 19 Bytes = 0 kB = 0 MB 2. In u-boot command shell, download autos.img,check it and run. 1) tftp 200000 coreblade/autos.img coreblade => tftp 200000 coreblade/autos.img Waiting for PHY auto negotiation to complete.. done ENET Speed is 100 Mbps - FULL duplex connection (EMAC1) Using ppc_4xx_eth1 device TFTP from server 10.3.8.66; our IP address is 10.4.40.1; sending through gateway 10.4.0.254 Filename 'coreblade/autos.img'. Load address: 0x200000 Loading: # done Bytes transferred = 91 (5b hex) 2) Check this image coreblade => iminfo 200000 ## Checking Image at 00200000 ... Image Name: auto script example Image Type: PowerPC Linux Script (uncompressed) Data Size: 27 Bytes = 0 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK 3) Run it!! coreblade => autoscr 200000 ## Executing script at 00200000 " not definedrverip 4) But I can see the serverip defined. coreblade => printe serverip serverip=10.3.8.66 I don't know what's the problem. Could you please help me? Thank you very much! Frisky

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[U-Boot-Users] What's the Difference between u-boot-1.3.0-rc2 and u-boot-1.2.0?
by Haifeng.Wu＠infineon.com 26 Sep '07

26 Sep '07

Dear All, Would some one please explain the main difference between u-boot-1.3.0-rc2 and u-boot-1.2.0? I'm confused by the CHANGELOG, for it gives too detailed information. I'm lost in too much discussions and I think an explanation on the bone change would be more helpful. B.R Dinny

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[U-Boot-Users] [PATCH] Fpga: fix incorrect test of CFG_FPGA_XILINX macro
by Grant Likely 26 Sep '07

26 Sep '07

From: Grant Likely <grant.likely(a)secretlab.ca> CFG_FPGA_XILINX is a bit value used to test against the value in CONFIG_FPGA. Testing for a value will always return TRUE. I don't think that is the intention in this code. Signed-off-by: Grant Likely <grant.likely(a)secretlab.ca> --- Wolfgang, this is a bug-fix only. It might be a good idea to go into 1.3.0, but all I've done is compile tested it. I don't have any hardware which is affected by this. Cheers, g. common/cmd_fpga.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 000406e..377a692 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -58,6 +58,7 @@ static int fpga_get_op (char *opstr); /* Convert bitstream data and load into the fpga */ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) { +#if (CONFIG_FPGA & CFG_FPGA_XILINX) unsigned int length; unsigned char* swapdata; unsigned int swapsize; @@ -70,7 +71,6 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) dataptr = (unsigned char *)fpgadata; -#if CFG_FPGA_XILINX /* skip the first bytes of the bitsteam, their meaning is unknown */ length = (*dataptr << 8) + *(dataptr+1); dataptr+=2;

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[U-Boot-Users] Bolsa de trabajo en internet
by Norris Hyde 25 Sep '07

25 Sep '07

Ingresos adicionales ó principales en compañías de confianza. Nuestra organización fue creada por la petición de La Unión Europea para reducir el desempleo en los países europeos. La página Web de nuestra compañía proporciona la información a los ciudadanos de La UE sobre nuevas vacantes. En nuestras páginas procuramos de publicar las ofertas más interesantes y que merecen su atención. Por ejemplo, la última vacante no precisa formación ni experiencia particular, por lo que acceder al puesto puede prácticamente cualquiera: Puesto: Responsable de reservas (41 puestos): - Ingresos 511-820 EUR semanales - Posibilidad de trabajar sólo un par de horas diarias (ocupación plena o parcial) - No se precisa formación particular (se realiza formación en la empresa) - Ninguna contribución por su parte, Usted puede empezar a trabajar sin ningún centavo. Si Usted esta interesado y requiere más información, por favor rellene la solicitud en la página www.eubiz.org/apply.php Alice Manferd El redactor en jefe del portal EuBiz.org Todos los solicitantes recibirán respuesta sin falta, por eso por favor, no dude en intentar a cambiar su bienestar hacia lo mejor. ATENCION! This message (including attachment if any) is confidential and may be privileged. Before opening attachments please check them for viruses and defects. EU Business will not be responsible for any viruses or defects or any forwarded attachments emanating either from within EU Business or outside. If you have received this message by mistake please notify the sender by return e-mail and delete this message from your system. Any unauthorized use or dissemination of this message in whole or in part is strictly prohibited. Please note that e-mails are susceptible to change and EU Business shall not be liable for any improper, untimely or incomplete transmission.

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[U-Boot-Users] [PATCH 0/6] mpc83xx patchset
by Dave Liu 25 Sep '07

25 Sep '07

Hello, The patch set is based on the commit id: 67c31036acaaaa992fc346cc89db0909a7e733c4 of the 'master' branch of http://www.denx.de/git/u-boot.git Thanks, Dave

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[U-Boot-Users] watchdog api support
by Mike Frysinger 25 Sep '07

25 Sep '07

the documentation for the watchdog seems to be on the non-existant side ... the toplevel mentions CONFIG_WATCHDOG, but there doesnt seem to be any internal documentation on what exactly this entails for people who want to implement a watchdog (the Blackfin processor has an on-chip watchdog) looking at include/watchdog.h shows that there is also the (undocumented) CONFIG_HW_WATCHDOG option which implies CONFIG_WATCHDOG is only for software watchdogs (which the toplevel README doesnt mention) sadly, the watchdog.h seems to have PPC-specific warts here (using the "bl" instruction in assembly), inconsistent defines for the reset function (trailing "()"), and the common API only covers a reset function ... there is no init function usage wise, there seems to be a requirement that there be a periodic timer to reset the watchdog as well as the random sprinkling of calls to "WATCHDOG_RESET ()" through some core pieces of code. there also doesnt seem to be information on what the standard expected timeout for the watchdog is ... 1 second ? 5 seconds ? a minute ? and is it just me, or is doing something like: void hw_watchdog_reset(void) { } seem kind of stupid ? -mike

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[U-Boot-Users] [RFC] u-boot migration to kconfig
by Jean-Christophe PLAGNIOL-VILLARD 24 Sep '07

24 Sep '07

Hi, I'd like to be involved in the migration to Kconfig. How could it be possible? Best regards

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[U-Boot-Users] [MIPS] Fix toolchain restriction for little endian build
by Shinya Kuribayashi 24 Sep '07

24 Sep '07

Fix ENDIANNESS condition to allow gcc toolchains other than ELDK. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- cpu/mips/config.mk | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk index b29986e..1a4e800 100644 --- a/cpu/mips/config.mk +++ b/cpu/mips/config.mk @@ -29,7 +29,7 @@ else \ echo "-march=4kc -mtune=4kc"; \ fi) -ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) +ifneq (,$(shell $(CC) -dumpmachine |grep 'mips.*el-.*')) ENDIANNESS = -EL else ENDIANNESS = -EB

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[U-Boot-Users] how to use 'eeprom read' command
by Sachin Rane, Alphion Communications 24 Sep '07

24 Sep '07

Hi, I want to read boot eeprom using u-boot. Can you tell me which 'addr' I need to pass to the 'eeprom read' command? -------------------------------------------------------------------------- => help eeprom eeprom read devaddr addr off cnt eeprom write devaddr addr off cnt - read/write `cnt' bytes from `devaddr` EEPROM at offset `off' -------------------------------------------------------------------------- I want to access boot eprom which is at 'devaddr' 0x54 and offset '0' to '10'. But I am not clear what ro pass for the 'addr' argument. Regards, Sachin Rane

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[U-Boot-Users] [PATCH]: MSR overwrite fix
by urwithsughosh＠gmail.com 24 Sep '07

24 Sep '07

Hello, This patch fixes the MSR overwrite in the start.S when moving out of the last 4K page. Signed-off-by: Sughosh Ganu <urwithsughosh(a)gmail.com> --- cpu/mpc85xx/start.S | 11 +++-------- 1 files changed, 3 insertions(+), 8 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 2c98c2a..74aa823 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -218,6 +218,8 @@ _start_e500: bdnz 0b /* Clear and set up some registers. */ + li r0,0 + mtmsr r0 li r0,0x0000 lis r1,0xffff mtspr DEC,r0 /* prevent dec exceptions */ @@ -277,7 +279,6 @@ _start_e500: /* Jump out the last 4K page and continue to 'normal' start */ #ifdef CFG_RAMBOOT - bl 3f b _start_cont #else /* Calculate absolute address in FLASH and jump there */ @@ -286,15 +287,9 @@ _start_e500: ori r3,r3,CFG_MONITOR_BASE@l addi r3,r3,_start_cont - _start + _START_OFFSET mtlr r3 + blr #endif -3: li r0,0 - mtspr SRR1,r0 /* Keep things disabled for now */ - mflr r1 - mtspr SRR0,r1 - rfi - isync - .text .globl _start _start: -- 1.4.4.4

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[U-Boot-Users] [PATCH]: Setting MSR[DE] in do_reset
by urwithsughosh＠gmail.com 24 Sep '07

24 Sep '07

Hello, This patch ensures the soft reset of the board for the 85xx boards by setting the MSR[DE] in the do_reset function. Signed-off-by: Sughosh Ganu <urwithsughosh(a)gmail.com> --- cpu/mpc85xx/cpu.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 08e0468..bbc5444 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -163,7 +163,12 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ - unsigned long val; + unsigned long val, msr; + + msr = mfmsr (); + msr |= MSR_DE; + mtmsr (msr); + val = mfspr(DBCR0); val |= 0x70000000; mtspr(DBCR0,val); -- 1.4.4.4

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[U-Boot-Users] Debugging u-boot on a custom 8548 board
by robert lazarski 24 Sep '07

24 Sep '07

Hi all, been spending a few days with my board and I see no signs of life from u-boot. I'm running my code in u-boot pulled from sept 18th's git repo - rc1 I think. I've tried: /home/iksrazal/eldk2/usr/bin> ./ppc_85xx-gdb /home/iksrazal/u-boot/u-boot GNU gdb Red Hat Linux (6.3.0.0-1.21_3rh) Copyright 2004 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type "show copying" to see the conditions. There is absolutely no warranty for GDB. Type "show warranty" for details. This GDB was configured as "--host=i386-redhat-linux --target=ppc-linux". The target architecture is set automatically (currently powerpc:e500) .. (gdb) set verbose on (gdb) target remote 10.101.43.42:2001 Remote debugging using 10.101.43.42:2001 0x00000000 in ?? () (gdb) mon break hard (gdb) b board_init_f Reading in symbols for board.c...done. Breakpoint 1 at 0xfff896e8: file board.c, line 365. (gdb) c Continuing. Where it just hangs. I've tried 'go' in the bdi to no avail. I see no life on the serial port. While I have 128MB of flash positioned at 0xf8000000 , I've loaded u-boot to 0xff8000000 - the default boot rom location for the 8548. I suppose one of the things to try is booting from low memory - but I haven't figured out how to do that via the boot sequencer or another register just yet. I also tried loading uboot to 0xf8000000 but it didn't work either. The first culprit is probably our memory - 1GB of DDR2 ram. The hardware guys tell me our DDR2 is exactly like the MPC8548CDS reference board. I have the memory mapped to 0x00000000 , and I can do this: ATUM>mmh 0x00000000 0xcafe ATUM>mdh 0x00000000 1 0_00000000 : 0xcafe -13570 .. ATUM> I get the feeling that somehow that u-boot isn't being executed yet - how can I verify that? Maybe setting a breakpoint in start.S ? Pins on the 8548 ? Googling has turned up a few posts saying that perhaps my bdi config could be the culprit. Since I can erase the flash and load u-boot into it, and seemingly read and write the memory, I'm going to post my latest bdi config version but its most definetly a work in progress! Any help appreciated. ; - BDI2000 - Atum ;--------------------------------------------------- ; ; ; 3 TLBs: 1 para CCSBAR - 1 para DDR (1GB) - 1 para Flash (1GB) ; [INIT] DELAY 5000 ; ;####################################################################### ; Errata PCI-Ex 26 workaround WM32 0xFF70A000 0x0000005C ;Clear bit 1 & 0 in Link Control & Status Register WM32 0xFF70A004 0x00000000 ;(PCIconfiguration space register at offset 0x5C) WM32 0xFF7E0F08 0x00000008 ;Clear bit 30 in the engineering only register ;(CCSR space register at offset 0xe0f08) ;####################################################################### ;####################################################################### ; use the following two lines for STARTUP HALT ;WSPR 63 0xffff0000 ;IVPR to boot core ;WSPR 415 0x0000f000 ;IVOR15 : Debug exception ; ;####################################################################### ;####################################################################### ; Move the L2SRAM to the initial MMU page WM32 0xFF720E44 0x0000001C ;L2ERRDIS: disable parity error WM32 0xFF720000 0x60010000 ;L2CTL - 0110 0000 0000 0001 0000 0000 0000 0000 WM32 0xFF720100 0x0FFF8000 ;L2SRBAR0: map to 0x0_FFF80000 WM32 0xFF720000 0xA0010000 ;L2CTL ; load and execute some boot code WM32 0xfffffffc 0x48000000 ;loop EXEC 0xfffffffc ; ;####################################################################### ;################################################################################## ;# MMU initialization ;# ;# MAS0: MMU read/write and replacement control ;# MAS1: descriptor context and configuration control ;# MAS2: EPN and page attributes ;# MAS3: RPN and access control ;# MAS4: Hardware replacement assist configuration ;---------------------------------------------------------------------------------- ;# define 1MB TLB1 entry 1: 0x40000000 - 0x400FFFFF ;# for CCSR WSPR 624 0x10010000 ;# MAS0 WSPR 625 0x80000500 ;# MAS1 WSPR 626 0x40000008 ;# MAS2 WSPR 627 0x4000003f ;# MAS3 WSPR 628 0x00000000 ;# MAS4 ;# write tlb entry WM32 0xFFFFF000 0x7C0007A4 ;# tlbwe WM32 0xFFFFF004 0x4C00012C ;# isync WM32 0xFFFFF008 0x7C0004AC ;# msync WM32 0xFFFFF00C 0x38600055 ;# li r3, 0x55 to confirm the running WM32 0xFFFFF010 0x48000000 ;# infinite loop WM32 0xfffffffc 0xfffff000 EXEC 0xfffff000 ;---------------------------------------------------------------------------------- ; ;---------------------------------------------------------------------------------- ;# define 1GB TLB1 entry 2: 0x00000000 - 0x3FFFFFFF ;# for DDR WSPR 624 0x10020000 ;# MAS0 WSPR 625 0x80000A00 ;# MAS1 - 1000 0000 0000 0000 0000 1010 0000 0000 WSPR 626 0x00000000 ;# MAS2 WSPR 627 0x0000003f ;# MAS3 ;# write tlb entry WM32 0xfffffffc 0xfffff000 EXEC 0xfffff000 ;---------------------------------------------------------------------------------- ;---------------------------------------------------------------------------------- ;# define 64MBytes TLB entry 3: 0xF8000000 - 0xFFFFFFFF ;# for FLASH bank #0 and bank #1 WSPR 624 0x10030000 ;# MAS0 WSPR 625 0x80000800 ;# MAS1 WSPR 626 0xF8000008 ;# MAS2 WSPR 627 0xF800003f ;# MAS3 ;# write tlb entry WM32 0xfffffffc 0xfffff000 EXEC 0xfffff000 ;---------------------------------------------------------------------------------- ;################################################################################## ;# move CCSR at 0xE0000000 ;# CCSRBAR ;# bit 12 - 23 - BASE_ADDR WM32 0xFF700000 0x000E0000 ; ;################################################################################## ;################################################################################## ;# config BPTR register (Boot Page Translation Register) ;# remove the 4k boot page from 0xFFFFF000 address ;WM32 0xE0000020 0x00000000 ;# Invalidate again BR0 to prevent flash data damage in case ;# the boot sequencer re-enables CS0 access ;WM32 0xE0005000 0x00001000 ;################################################################################## ;################################################################################## ;# configure internal SRAM at 0x40100000 ;# L2CTL ;# bit 0 = 0 - L2E: L2 SRAM disabled ;# bit 4-5 = 01 - L2BLKSZ: = 512KB ;# bit 13-15 = 001 - L2SRAM: Block 0 = SRAM 0 WM32 0xE0020000 0x00010000 ;# L2SRBAR0 ;# bit 0-17 = BASE addr: 0x40100000 WM32 0xE0020100 0x40100000 ;# L2CTL ;# bit 0 = 1 - L2E: L2 SRAM enable ;# bit 4-5 = 01 - L2BLKSZ: = 512KB ;# bit 13-15 = 001 - L2SRAM: Block 0 = SRAM 0 WM32 0xE0020000 0x80010000 ;################################################################################## ; Setup flash programming workspace in L2SRAM WM32 0xE0020000 0x68010000 ;L2CTL WM32 0xE0020100 0xf0000000 ;L2SRBAR0 WM32 0xE0020000 0xA8010000 ;L2CTL WSPR 63 0xf0000000 ;IVPR to workspace WSPR 415 0x0001500 ;IVOR15 : Debug exception WM32 0xf0001500 0x48000000 ;write valid instruction ;################################################################################## ;# ;# Memory Windows ;# ;# 0x00000000 0x3ffffff LAW0 DDR ;# 0xc0000000 0xfffffff LAW1 Local Bus ;# ;################################################################################## ;################################################################################## ;# configure local access windows ;# ;# window 0: DDR = F ;# window 1: Local Bus = 4 ;---------------------------------------------------------------------------------- ;# LAWBAR0 ;# bit 12 - 31 = 0x00000000 - base addr WM32 0xE0000c08 0x00000000 ;# LAWAR0 ;# bit 1 = 1 - enable window ;# bit 8-11 = F - DDR ;# bit 26 - 31 = 1GB - size WM32 0xE0000c10 0x80f0001D ;---------------------------------------------------------------------------------- ;---------------------------------------------------------------------------------- ;# LAWBAR1 ;# bit 12 - 31 = 0xF8000000 - base addr WM32 0xE0000c28 0x000F8000 ;# LAWAR1 ;# bit 1 = 1 - enable window ;# bit 8-11 = 4 - local bus ;# bit 26 - 31 = 256MB - size WM32 0xE0000c30 0x8040001A ;- 1D ;---------------------------------------------------------------------------------- ;################################################################################### ;################################################################################### ;# ;# DDR initalization ;# ;### Clocks: CPU: 990 MHz, CCB: 396 MHz, DDR: 198 MHz ;# DDR_SDRAM_CFG 0100 0011 0000 0000 0000 0000 0000 0000 ;# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled ;# bit 1 = 1 - SREN enable self refresh during sleep ;# bit 2 = 0 - ECC_EN disable ECC interrupt generation ;# bit 3 = 0 - RD_EN unbuffered DIMMs ;# bit 6 - 7 = 2 - SDRAM_TYPE DDR2 SDRAM ;# bit 10 = 0 - DYN_PWR power management disabled WM32 0xE0002110 0x43000000 ;# configure the appropriate DDR controller registers ;# CS0_BNDS ;# bit 8-15 - starting address ;# bit 24-31 - ending address WM32 0xE0002000 0x0000000f ; DDR CS0 ;# CS0_CONFIG WM32 0xE0002080 0x80000102 ;# TIMING_CFG_0 WM32 0xE0002104 0x00260802 ;# TIMING_CFG_1 WM32 0xE0002108 0x38355322 ;# TIMING_CFG_2 WM32 0xE000210C 0x039048c7 ;# DDR_SDRAM_MODE WM32 0xE0002118 0x00000432 ;# DDR_SDRAM_INTERVAL WM32 0xE0002124 0x05150100 ;# DDR_SDRAM_CFG2 WM32 0xE0002114 0x24000000 ;# DDR_SDRAM_CLK_CNTL WM32 0xE0002130 0x03000000 DELAY 200 ;# enable the memory interface ;# DDR_SDRAM_CFG ;# enable the memory interface WM32 0xE0002110 0xc3000000 ;################################################################################## ;################################################################################## ;# configure local bus memory controller ;# CS0 - Flash Bank #0 WM32 0xE0005000 0xf8001001 ;# BR0 base address at 0xF8000000, port size 16 bit, GPCM, valid WM32 0xE0005004 0xf8006e65 ;# OR1 64MBytes flash size ;################################################################################## ;WM16 0xf8000AAA 0x5500 ; ;WM16 0xf8000554 0xAA00 ; ;WM16 0xf8000AAA 0x0100 ; ;WM16 0xf8000AAA 0x5500 ; ;WM16 0xf8000554 0xAA00 ; ;WM16 0xf8000AAA 0x0800 ; ;;WM16 0xfbffffff 0x0010 ;WM16 0xf8000000 0x0010 ; ;WM32 0xf8000AAA 0x00AA ; ;WM32 0xf8000554 0x0055 ; ;WM32 0xf8000AAA 0x00A0 ; ;DELAY 2000 ;WM32 0xf8000F00 0x5555 ; [TARGET] CPUTYPE 8548 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses a hardware breakpointeraserase WAKEUP 2000 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms [HOST] IP 10.101.42.16 FILE uboot.bin FORMAT BIN LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP dump.bin PROMPT ATUM> [FLASH] CHIPTYPE MIRRORX16 ;S29GL01GP CHIPSIZE 0x8000000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) ;WORKSPACE 0xf0000000 ;workspace in L2SRAM ERASE 0xf8000000 CHIP; erase chip [REGS] FILE $reg8548.def Thanks! Robert

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