September 2007 - U-Boot

[U-Boot-Users] [MIPS] Fix toolchain restriction for little endian build
by Shinya Kuribayashi 24 Sep '07

24 Sep '07

Fix ENDIANNESS condition to allow gcc toolchains other than ELDK. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- cpu/mips/config.mk | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk index b29986e..1a4e800 100644 --- a/cpu/mips/config.mk +++ b/cpu/mips/config.mk @@ -29,7 +29,7 @@ else \ echo "-march=4kc -mtune=4kc"; \ fi) -ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) +ifneq (,$(shell $(CC) -dumpmachine |grep 'mips.*el-.*')) ENDIANNESS = -EL else ENDIANNESS = -EB

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[U-Boot-Users] how to use 'eeprom read' command
by Sachin Rane, Alphion Communications 24 Sep '07

24 Sep '07

Hi, I want to read boot eeprom using u-boot. Can you tell me which 'addr' I need to pass to the 'eeprom read' command? -------------------------------------------------------------------------- => help eeprom eeprom read devaddr addr off cnt eeprom write devaddr addr off cnt - read/write `cnt' bytes from `devaddr` EEPROM at offset `off' -------------------------------------------------------------------------- I want to access boot eprom which is at 'devaddr' 0x54 and offset '0' to '10'. But I am not clear what ro pass for the 'addr' argument. Regards, Sachin Rane

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[U-Boot-Users] [PATCH]: MSR overwrite fix
by urwithsughosh＠gmail.com 24 Sep '07

24 Sep '07

Hello, This patch fixes the MSR overwrite in the start.S when moving out of the last 4K page. Signed-off-by: Sughosh Ganu <urwithsughosh(a)gmail.com> --- cpu/mpc85xx/start.S | 11 +++-------- 1 files changed, 3 insertions(+), 8 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 2c98c2a..74aa823 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -218,6 +218,8 @@ _start_e500: bdnz 0b /* Clear and set up some registers. */ + li r0,0 + mtmsr r0 li r0,0x0000 lis r1,0xffff mtspr DEC,r0 /* prevent dec exceptions */ @@ -277,7 +279,6 @@ _start_e500: /* Jump out the last 4K page and continue to 'normal' start */ #ifdef CFG_RAMBOOT - bl 3f b _start_cont #else /* Calculate absolute address in FLASH and jump there */ @@ -286,15 +287,9 @@ _start_e500: ori r3,r3,CFG_MONITOR_BASE@l addi r3,r3,_start_cont - _start + _START_OFFSET mtlr r3 + blr #endif -3: li r0,0 - mtspr SRR1,r0 /* Keep things disabled for now */ - mflr r1 - mtspr SRR0,r1 - rfi - isync - .text .globl _start _start: -- 1.4.4.4

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[U-Boot-Users] [PATCH]: Setting MSR[DE] in do_reset
by urwithsughosh＠gmail.com 24 Sep '07

24 Sep '07

Hello, This patch ensures the soft reset of the board for the 85xx boards by setting the MSR[DE] in the do_reset function. Signed-off-by: Sughosh Ganu <urwithsughosh(a)gmail.com> --- cpu/mpc85xx/cpu.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 08e0468..bbc5444 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -163,7 +163,12 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ - unsigned long val; + unsigned long val, msr; + + msr = mfmsr (); + msr |= MSR_DE; + mtmsr (msr); + val = mfspr(DBCR0); val |= 0x70000000; mtspr(DBCR0,val); -- 1.4.4.4

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[U-Boot-Users] Debugging u-boot on a custom 8548 board
by robert lazarski 24 Sep '07

24 Sep '07

Hi all, been spending a few days with my board and I see no signs of life from u-boot. I'm running my code in u-boot pulled from sept 18th's git repo - rc1 I think. I've tried: /home/iksrazal/eldk2/usr/bin> ./ppc_85xx-gdb /home/iksrazal/u-boot/u-boot GNU gdb Red Hat Linux (6.3.0.0-1.21_3rh) Copyright 2004 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type "show copying" to see the conditions. There is absolutely no warranty for GDB. Type "show warranty" for details. This GDB was configured as "--host=i386-redhat-linux --target=ppc-linux". The target architecture is set automatically (currently powerpc:e500) .. (gdb) set verbose on (gdb) target remote 10.101.43.42:2001 Remote debugging using 10.101.43.42:2001 0x00000000 in ?? () (gdb) mon break hard (gdb) b board_init_f Reading in symbols for board.c...done. Breakpoint 1 at 0xfff896e8: file board.c, line 365. (gdb) c Continuing. Where it just hangs. I've tried 'go' in the bdi to no avail. I see no life on the serial port. While I have 128MB of flash positioned at 0xf8000000 , I've loaded u-boot to 0xff8000000 - the default boot rom location for the 8548. I suppose one of the things to try is booting from low memory - but I haven't figured out how to do that via the boot sequencer or another register just yet. I also tried loading uboot to 0xf8000000 but it didn't work either. The first culprit is probably our memory - 1GB of DDR2 ram. The hardware guys tell me our DDR2 is exactly like the MPC8548CDS reference board. I have the memory mapped to 0x00000000 , and I can do this: ATUM>mmh 0x00000000 0xcafe ATUM>mdh 0x00000000 1 0_00000000 : 0xcafe -13570 .. ATUM> I get the feeling that somehow that u-boot isn't being executed yet - how can I verify that? Maybe setting a breakpoint in start.S ? Pins on the 8548 ? Googling has turned up a few posts saying that perhaps my bdi config could be the culprit. Since I can erase the flash and load u-boot into it, and seemingly read and write the memory, I'm going to post my latest bdi config version but its most definetly a work in progress! Any help appreciated. ; - BDI2000 - Atum ;--------------------------------------------------- ; ; ; 3 TLBs: 1 para CCSBAR - 1 para DDR (1GB) - 1 para Flash (1GB) ; [INIT] DELAY 5000 ; ;####################################################################### ; Errata PCI-Ex 26 workaround WM32 0xFF70A000 0x0000005C ;Clear bit 1 & 0 in Link Control & Status Register WM32 0xFF70A004 0x00000000 ;(PCIconfiguration space register at offset 0x5C) WM32 0xFF7E0F08 0x00000008 ;Clear bit 30 in the engineering only register ;(CCSR space register at offset 0xe0f08) ;####################################################################### ;####################################################################### ; use the following two lines for STARTUP HALT ;WSPR 63 0xffff0000 ;IVPR to boot core ;WSPR 415 0x0000f000 ;IVOR15 : Debug exception ; ;####################################################################### ;####################################################################### ; Move the L2SRAM to the initial MMU page WM32 0xFF720E44 0x0000001C ;L2ERRDIS: disable parity error WM32 0xFF720000 0x60010000 ;L2CTL - 0110 0000 0000 0001 0000 0000 0000 0000 WM32 0xFF720100 0x0FFF8000 ;L2SRBAR0: map to 0x0_FFF80000 WM32 0xFF720000 0xA0010000 ;L2CTL ; load and execute some boot code WM32 0xfffffffc 0x48000000 ;loop EXEC 0xfffffffc ; ;####################################################################### ;################################################################################## ;# MMU initialization ;# ;# MAS0: MMU read/write and replacement control ;# MAS1: descriptor context and configuration control ;# MAS2: EPN and page attributes ;# MAS3: RPN and access control ;# MAS4: Hardware replacement assist configuration ;---------------------------------------------------------------------------------- ;# define 1MB TLB1 entry 1: 0x40000000 - 0x400FFFFF ;# for CCSR WSPR 624 0x10010000 ;# MAS0 WSPR 625 0x80000500 ;# MAS1 WSPR 626 0x40000008 ;# MAS2 WSPR 627 0x4000003f ;# MAS3 WSPR 628 0x00000000 ;# MAS4 ;# write tlb entry WM32 0xFFFFF000 0x7C0007A4 ;# tlbwe WM32 0xFFFFF004 0x4C00012C ;# isync WM32 0xFFFFF008 0x7C0004AC ;# msync WM32 0xFFFFF00C 0x38600055 ;# li r3, 0x55 to confirm the running WM32 0xFFFFF010 0x48000000 ;# infinite loop WM32 0xfffffffc 0xfffff000 EXEC 0xfffff000 ;---------------------------------------------------------------------------------- ; ;---------------------------------------------------------------------------------- ;# define 1GB TLB1 entry 2: 0x00000000 - 0x3FFFFFFF ;# for DDR WSPR 624 0x10020000 ;# MAS0 WSPR 625 0x80000A00 ;# MAS1 - 1000 0000 0000 0000 0000 1010 0000 0000 WSPR 626 0x00000000 ;# MAS2 WSPR 627 0x0000003f ;# MAS3 ;# write tlb entry WM32 0xfffffffc 0xfffff000 EXEC 0xfffff000 ;---------------------------------------------------------------------------------- ;---------------------------------------------------------------------------------- ;# define 64MBytes TLB entry 3: 0xF8000000 - 0xFFFFFFFF ;# for FLASH bank #0 and bank #1 WSPR 624 0x10030000 ;# MAS0 WSPR 625 0x80000800 ;# MAS1 WSPR 626 0xF8000008 ;# MAS2 WSPR 627 0xF800003f ;# MAS3 ;# write tlb entry WM32 0xfffffffc 0xfffff000 EXEC 0xfffff000 ;---------------------------------------------------------------------------------- ;################################################################################## ;# move CCSR at 0xE0000000 ;# CCSRBAR ;# bit 12 - 23 - BASE_ADDR WM32 0xFF700000 0x000E0000 ; ;################################################################################## ;################################################################################## ;# config BPTR register (Boot Page Translation Register) ;# remove the 4k boot page from 0xFFFFF000 address ;WM32 0xE0000020 0x00000000 ;# Invalidate again BR0 to prevent flash data damage in case ;# the boot sequencer re-enables CS0 access ;WM32 0xE0005000 0x00001000 ;################################################################################## ;################################################################################## ;# configure internal SRAM at 0x40100000 ;# L2CTL ;# bit 0 = 0 - L2E: L2 SRAM disabled ;# bit 4-5 = 01 - L2BLKSZ: = 512KB ;# bit 13-15 = 001 - L2SRAM: Block 0 = SRAM 0 WM32 0xE0020000 0x00010000 ;# L2SRBAR0 ;# bit 0-17 = BASE addr: 0x40100000 WM32 0xE0020100 0x40100000 ;# L2CTL ;# bit 0 = 1 - L2E: L2 SRAM enable ;# bit 4-5 = 01 - L2BLKSZ: = 512KB ;# bit 13-15 = 001 - L2SRAM: Block 0 = SRAM 0 WM32 0xE0020000 0x80010000 ;################################################################################## ; Setup flash programming workspace in L2SRAM WM32 0xE0020000 0x68010000 ;L2CTL WM32 0xE0020100 0xf0000000 ;L2SRBAR0 WM32 0xE0020000 0xA8010000 ;L2CTL WSPR 63 0xf0000000 ;IVPR to workspace WSPR 415 0x0001500 ;IVOR15 : Debug exception WM32 0xf0001500 0x48000000 ;write valid instruction ;################################################################################## ;# ;# Memory Windows ;# ;# 0x00000000 0x3ffffff LAW0 DDR ;# 0xc0000000 0xfffffff LAW1 Local Bus ;# ;################################################################################## ;################################################################################## ;# configure local access windows ;# ;# window 0: DDR = F ;# window 1: Local Bus = 4 ;---------------------------------------------------------------------------------- ;# LAWBAR0 ;# bit 12 - 31 = 0x00000000 - base addr WM32 0xE0000c08 0x00000000 ;# LAWAR0 ;# bit 1 = 1 - enable window ;# bit 8-11 = F - DDR ;# bit 26 - 31 = 1GB - size WM32 0xE0000c10 0x80f0001D ;---------------------------------------------------------------------------------- ;---------------------------------------------------------------------------------- ;# LAWBAR1 ;# bit 12 - 31 = 0xF8000000 - base addr WM32 0xE0000c28 0x000F8000 ;# LAWAR1 ;# bit 1 = 1 - enable window ;# bit 8-11 = 4 - local bus ;# bit 26 - 31 = 256MB - size WM32 0xE0000c30 0x8040001A ;- 1D ;---------------------------------------------------------------------------------- ;################################################################################### ;################################################################################### ;# ;# DDR initalization ;# ;### Clocks: CPU: 990 MHz, CCB: 396 MHz, DDR: 198 MHz ;# DDR_SDRAM_CFG 0100 0011 0000 0000 0000 0000 0000 0000 ;# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled ;# bit 1 = 1 - SREN enable self refresh during sleep ;# bit 2 = 0 - ECC_EN disable ECC interrupt generation ;# bit 3 = 0 - RD_EN unbuffered DIMMs ;# bit 6 - 7 = 2 - SDRAM_TYPE DDR2 SDRAM ;# bit 10 = 0 - DYN_PWR power management disabled WM32 0xE0002110 0x43000000 ;# configure the appropriate DDR controller registers ;# CS0_BNDS ;# bit 8-15 - starting address ;# bit 24-31 - ending address WM32 0xE0002000 0x0000000f ; DDR CS0 ;# CS0_CONFIG WM32 0xE0002080 0x80000102 ;# TIMING_CFG_0 WM32 0xE0002104 0x00260802 ;# TIMING_CFG_1 WM32 0xE0002108 0x38355322 ;# TIMING_CFG_2 WM32 0xE000210C 0x039048c7 ;# DDR_SDRAM_MODE WM32 0xE0002118 0x00000432 ;# DDR_SDRAM_INTERVAL WM32 0xE0002124 0x05150100 ;# DDR_SDRAM_CFG2 WM32 0xE0002114 0x24000000 ;# DDR_SDRAM_CLK_CNTL WM32 0xE0002130 0x03000000 DELAY 200 ;# enable the memory interface ;# DDR_SDRAM_CFG ;# enable the memory interface WM32 0xE0002110 0xc3000000 ;################################################################################## ;################################################################################## ;# configure local bus memory controller ;# CS0 - Flash Bank #0 WM32 0xE0005000 0xf8001001 ;# BR0 base address at 0xF8000000, port size 16 bit, GPCM, valid WM32 0xE0005004 0xf8006e65 ;# OR1 64MBytes flash size ;################################################################################## ;WM16 0xf8000AAA 0x5500 ; ;WM16 0xf8000554 0xAA00 ; ;WM16 0xf8000AAA 0x0100 ; ;WM16 0xf8000AAA 0x5500 ; ;WM16 0xf8000554 0xAA00 ; ;WM16 0xf8000AAA 0x0800 ; ;;WM16 0xfbffffff 0x0010 ;WM16 0xf8000000 0x0010 ; ;WM32 0xf8000AAA 0x00AA ; ;WM32 0xf8000554 0x0055 ; ;WM32 0xf8000AAA 0x00A0 ; ;DELAY 2000 ;WM32 0xf8000F00 0x5555 ; [TARGET] CPUTYPE 8548 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses a hardware breakpointeraserase WAKEUP 2000 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms [HOST] IP 10.101.42.16 FILE uboot.bin FORMAT BIN LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP dump.bin PROMPT ATUM> [FLASH] CHIPTYPE MIRRORX16 ;S29GL01GP CHIPSIZE 0x8000000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) ;WORKSPACE 0xf0000000 ;workspace in L2SRAM ERASE 0xf8000000 CHIP; erase chip [REGS] FILE $reg8548.def Thanks! Robert

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[U-Boot-Users] isp116x-hcd and usb_storage
by tike64 24 Sep '07

24 Sep '07

Dear List, I'm trying to set usb host up on our board (LH7A400 + ISP1160). It already works to some extend; it detects my Kingston 1GB stick. But then it (usb reset) fails with "Request Sense returned 00 00 00". Funny thing is that it starts to work if I enable debugging messages in usb_storage.c and isp116x-hcd.c. If I enable them in usb_storage.c only, it doesn't work. Here is the debug message log with debugging enabled in usb_storage.c only till the first difference I can see: ================================ USB Mass Storage device detected Transport: Bulk/Bulk/Bulk Endpoints In 1 Out 2 Int 0 BBB_reset BBB_reset result 0: status 0 reset BBB_reset result 0: status 0 clearing IN endpoint BBB_reset result 0: status 0 clearing OUT endpoint BBB_reset done address 2 COMMAND phase dir 1 lun 0 cmdlen 12 cmd c1ff9514 datalen 36 pdata c1ff9314 cmd[0] 0x12 cmd[1] 0x0 cmd[2] 0x0 cmd[3] 0x0 cmd[4] 0x24 cmd[5] 0x0 cmd[6] 0x0 cmd[7] 0x0 cmd[8] 0x0 cmd[9] 0x0 cmd[10] 0x0 cmd[11] 0x0 DATA phase pdata[0] 0x0 pdata[1] 0x80 pdata[2] 0x0 pdata[3] 0x1 pdata[4] 0x1f pdata[5] 0x0 pdata[6] 0x0 pdata[7] 0x0 pdata[8] 0x4b pdata[9] 0x69 pdata[10] 0x6e pdata[11] 0x67 pdata[12] 0x73 pdata[13] 0x74 pdata[14] 0x6f pdata[15] 0x6e pdata[16] 0x44 pdata[17] 0x61 pdata[18] 0x74 pdata[19] 0x61 pdata[20] 0x54 pdata[21] 0x72 pdata[22] 0x61 pdata[23] 0x76 pdata[24] 0x65 pdata[25] 0x6c pdata[26] 0x65 pdata[27] 0x72 pdata[28] 0x20 pdata[29] 0x49 pdata[30] 0x49 pdata[31] 0x20 pdata[32] 0x31 pdata[33] 0x2e pdata[34] 0x31 pdata[35] 0x33 STATUS phase ptr[0] 0x55 ptr[1] 0x53 ptr[2] 0x42 ptr[3] 0x53 ptr[4] 0x17 ptr[5] 0x0 ptr[6] 0x0 ptr[7] 0x0 ptr[8] 0x0 ptr[9] 0x0 ptr[10] 0x0 ptr[11] 0x0 ptr[12] 0x0 inquiry returns 0 ================================ ptr[4] is different when I have debugging enabled in both files: ================================ - - isp116x-hcd.c: data(13): 55 53 42 53 00 00 00 00 00 00 00 00 00 ptr[0] 0x55 ptr[1] 0x53 ptr[2] 0x42 ptr[3] 0x53 ptr[4] 0x0 ptr[5] 0x0 ptr[6] 0x0 ptr[7] 0x0 ptr[8] 0x0 ptr[9] 0x0 ptr[10] 0x0 ptr[11] 0x0 ptr[12] 0x0 inquiry returns 0 ================================ Could someone please help in debugging this? -- Timo ____________________________________________________________________________________ Moody friends. Drama queens. Your life? Nope! - their life, your story. Play Sims Stories at Yahoo! Games. http://sims.yahoo.com/

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[U-Boot-Users] Compilation of U-Boot 1.1.6 with CFI
by Binay Kumar 24 Sep '07

24 Sep '07

Hi, I want to compile U-Boot 1.1.6 with CFI,So I'm following below steps.Pls. correct me if I'm wrong. 1.Edit u-boot-1.1.6/include/configs/BMW.h Insert the following 2 lines: #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1 2.# make

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[U-Boot-Users] how to boot uImage from flash
by sun 24 Sep '07

24 Sep '07

hi: Now i have downloaded the linux uImage to flash at address 0xf8000000,and i want to boot uImage from flash,and how can i do? a lots of thanks! wish U good luck! --------------------------------- @yahoo.cn 新域名、无限量，快来抢注！

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[U-Boot-Users] Get one this
by anandat420＠petsrest.com 23 Sep '07

23 Sep '07

Keep Your Eyes Open Monday For News From SREA SCORE ONE (S R E A) Price: $0.10 This one always climbs after big news. Beat the news to the market, grab SREA at open on Monday.

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[U-Boot-Users] isoklina
by Josh Norwig 22 Sep '07

22 Sep '07

R-umor N e+w+s-: O-nco*logy M-e'd.. I*n-c'. (OTC': O_NCO) a C+ancer Treatme+'nt Solut+i_ons G'roup is s,a'i+d to h,a,v+e exper*ien ced o.v_e-r a 1000_% inc*reas_e in reve.n,ues f.o r t*h'e fisc,al 3_r+d qua,rter end_ing J-u*l-y,, 2*0.0*7 comp,'ared w*i+t.h t.h-e pr'ior y'e_a r wh.ile fi-scal fourt*h quarte.r resul*ts f,o'r 2-0_0-7 a-r e on trac*k to exc*eed t h-i+s year_s th*ird quart*er result.s. O,N C.O a .dditionally p+lans to in+cre*ase ser+vice o ff,erings wh+ich a+r_e cu rren*tly un+derway-. Do.nt w.a.i.t f,o-r t*h,e n+e w s to c'o m*e o+u+t a+n+d l*o+s'e t h+e opport.*unity to g+e t in fron_t of the gen+eral i *nvesting publi,c. On- cology M,e+d is in a mu,ltibill-ion do'llar i+ndust,ry w'h,e r.e t_h-e y a*r_e gainin_g marke_t shar_e rapidl*y. C a-l.l y,o.u*r broke.r n*o'w f'o*r O N.C+O-.

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