September 2007 - U-Boot

[U-Boot-Users] [PATCH 3/3] Apollon BSP support (take #2)
by Kyungmin Park 17 Sep '07

17 Sep '07

Apollon BSP support (take #2) The Apollon based on OMAP2420 is designed for OneNAND development. It's similar with OMAP2420 H4 except some peripherals. Now this board is maintained at mainline kernel. Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/board/apollon/mem.c b/board/apollon/mem.c new file mode 100644 index 0000000..c0edca5 --- /dev/null +++ b/board/apollon/mem.c @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2005-2007 + * Samsung Electronics, + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * Derived from omap2420 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/omap2420.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mux.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> + +#include "mem.h" + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in 12MHz bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/******************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * (config II default). + * -- called from SRAM, or Flash (using temp SRAM stack). + ********************************************************************/ +void prcm_init(void) { } + +/************************************************************************** + * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow + * command line mem=xyz use all memory with out discontigious support + * compiled in. Could do it at the ATAG, but there really is two banks... + * Called as part of 2nd phase DDR init. + **************************************************************************/ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(SDRC_CS0_OSET); + size /= SZ_32M; /* find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG); + +} + +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in gussing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(void) +{ + u32 val1, val2; + u32 pattern = 0x12345678; + + /* clear pos A */ + __raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400); + /* pattern to pos B */ + __raw_writel(pattern, OMAP2420_SDRC_CS0); + /* remove pattern off the bus */ + __raw_writel(0x0, OMAP2420_SDRC_CS0 + 4); + /* get pos A value */ + val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400); + val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ + + /* see if pos A value changed */ + if ((val1 != 0) || (val2 != pattern)) + return (0); + else + return (1); +} + +/******************************************************** + * sdrc_init() - init the sdrc chip selects CS0 and CS1 + * - early init routines, called from flash or + * SRAM. + *******************************************************/ +void sdrc_init(void) +{ +#define EARLY_INIT 1 + /* only init up first bank here */ + do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); +} + +/************************************************************************* + * do_sdrc_init(): initialize the SDRAM for use. + * -called from low level code with stack only. + * -code sets up SDRAM timing and muxing for 2422 or 2420. + * -optimal settings can be placed here, or redone after i2c + * inspection of board info + * + * This is a bit ugly, but should handle all memory moduels + * used with the APOLLON. The first time though this code from s_init() + * we configure the first chip select. Later on we come back and + * will configure the 2nd chip select if it exists. + * + **************************************************************************/ +void do_sdrc_init(u32 offset, u32 early) +{ +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ + u32 mux = 0, mtype, mwidth, rev, tval; + + rev = get_cpu_rev(); + if (rev == CPU_2420_2422_ES1) + tval = 1; + else + tval = 0; /* disable bit switched meaning */ + + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */ +#ifdef CFG_NAND_BOOT + /* set nWP, disable limited addr */ + __raw_writel(0x001, GPMC_CONFIG); +#else + /* set nWP, disable limited addr */ + __raw_writel(0x111, GPMC_CONFIG); +#endif + + /* discover bus connection from sysboot */ + if (is_gpmc_muxed() == GPMC_MUXED) + mux = BIT9; + mtype = get_gpmc0_type(); + mwidth = get_gpmc0_width(); + + /* setup cs0 */ + __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ + sdelay(1000); + +#ifdef CFG_NOR_BOOT + __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0); +#else + __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth, + GPMC_CONFIG1_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0); + __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0); +#endif + sdelay(2000); + + /* setup cs1 */ + __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */ + sdelay(1000); + + __raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1); + __raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1); + __raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1); + __raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1); + __raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1); + __raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1); + __raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); + sdelay(2000); + + /* setup cs2 */ + __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth, + GPMC_CONFIG1_2); + /* It's same as cs 0 */ + __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2); + __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2); + __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2); + __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2); + __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2); +#ifdef CFG_NOR_BOOT + __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2); +#else + __raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2); +#endif + +#ifndef CFG_NOR_BOOT + /* setup cs3 */ + __raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */ + sdelay(1000); + + __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3); + __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3); + __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3); + __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3); + __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3); + __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3); + __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3); +#endif + +#ifndef ASYNC_NOR + __raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa)); + __raw_writew(0x55, (APOLLON_CS3_BASE + 0x554)); + __raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE)); +#endif + sdelay(2000); +} diff --git a/board/apollon/mem.h b/board/apollon/mem.h new file mode 100644 index 0000000..5bc96fa --- /dev/null +++ b/board/apollon/mem.h @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2005-2007 + * Samsung Electronics, + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _APOLLON_OMAP24XX_MEM_H_ +#define _APOLLON_OMAP24XX_MEM_H_ + +/* Slower full frequency range default timings for x32 operation*/ +#define APOLLON_2420_SDRC_SHARING 0x00000100 +#define APOLLON_2420_SDRC_MDCFG_0_DDR 0x00d04011 +#define APOLLON_2420_SDRC_MR_0_DDR 0x00000032 + +/* optimized timings good for current shipping parts */ +#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x4A59B485 +#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000C + +#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz 0x7BA35907 +#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz 0x00000013 + +#define APOLLON_242X_SDRC_RFR_CTRL_100MHz 0x00030001 +#define APOLLON_242X_SDRC_RFR_CTRL_166MHz 0x00044C01 + +#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz 0x00007306 +#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz 0x00000506 + +#ifdef PRCM_CONFIG_I +#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz +#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz +#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_166MHz +#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_166MHz +#elif PRCM_CONFIG_II +#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz +#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz +#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_100MHz +#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_100MHz +#endif + +/* GPMC settings */ +#ifdef PRCM_CONFIG_I /* L3 at 165MHz */ +/* CS0: OneNAND */ +# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001 +# define APOLLON_24XX_GPMC_CONFIG2_0 0x000c1000 +# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030400 +# define APOLLON_24XX_GPMC_CONFIG4_0 0x0b841006 +# define APOLLON_24XX_GPMC_CONFIG5_0 0x020f0c11 +# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000 +# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24)) + +/* CS1: Ethernet */ +# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011200 +# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01 +# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803 +# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a +# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F +# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4 +# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24)) + +/* CS2: OneNAND */ +/* It's same as CS0 */ +# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24)) + +/* CS3: NOR */ +#ifdef ASYNC_NOR +# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201 +# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601 +# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401 +# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605 +# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317 +#else +# define SYNC_NOR_VALUE 0x24aaa +# define APOLLON_24XX_GPMC_CONFIG1_3 0xe5011211 +# define APOLLON_24XX_GPMC_CONFIG2_3 0x00090b01 +# define APOLLON_24XX_GPMC_CONFIG3_3 0x00020201 +# define APOLLON_24XX_GPMC_CONFIG4_3 0x09030b03 +# define APOLLON_24XX_GPMC_CONFIG5_3 0x010a0a0c +#endif /* ASYNC_NOR */ +# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000 +# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000e40|(APOLLON_CS3_BASE >> 24)) +#endif /* endif PRCM_CONFIG_I */ + +#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ +/* CS0: OneNAND */ +# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001 +# define APOLLON_24XX_GPMC_CONFIG2_0 0x00081080 +# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030300 +# define APOLLON_24XX_GPMC_CONFIG4_0 0x08041004 +# define APOLLON_24XX_GPMC_CONFIG5_0 0x020b0910 +# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000 +# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24)) + +/* CS1: ethernet */ +# define APOLLON_24XX_GPMC_CONFIG1_1 0x00401203 +# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01 +# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803 +# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09 +# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F +# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4 +# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24)) + +/* CS2: OneNAND */ +/* It's same as CS0 */ +# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24)) + +/* CS3: NOR */ +#define ASYNC_NOR +#ifdef ASYNC_NOR +# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201 +# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601 +# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401 +# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605 +# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317 +#else +# define SYNC_NOR_VALUE 0x24aaa +# define APOLLON_24XX_GPMC_CONFIG1_3 0xe1001202 +# define APOLLON_24XX_GPMC_CONFIG2_3 0x00151501 +# define APOLLON_24XX_GPMC_CONFIG3_3 0x00050501 +# define APOLLON_24XX_GPMC_CONFIG4_3 0x0e070e07 +# define APOLLON_24XX_GPMC_CONFIG5_3 0x01131F1F +#endif /* ASYNC_NOR */ +# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000 +# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000C40|(APOLLON_CS3_BASE >> 24)) +#endif /* endif PRCM_CONFIG_II */ + +#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ +# ifdef CFG_NAND_BOOT +# define APOLLON_24XX_GPMC_CONFIG1_0 0x0 +# define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400 +# define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400 +# define APOLLON_24XX_GPMC_CONFIG4_0 0x0F010F01 +# define APOLLON_24XX_GPMC_CONFIG5_0 0x010C1414 +# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000A80 +# else /* NOR boot */ +# define APOLLON_24XX_GPMC_CONFIG1_0 0x3 +# define APOLLON_24XX_GPMC_CONFIG2_0 0x00151501 +# define APOLLON_24XX_GPMC_CONFIG3_0 0x00060602 +# define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008 +# define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F +# define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4 +# endif /* endif CFG_NAND_BOOT */ +# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24)) +# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000 +# define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01 +# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803 +# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09 +# define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F +# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4 +# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24)) +#endif /* endif CFG_PRCM_III */ + +#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */ diff --git a/include/asm-arm/arch-arm1136/mux.h b/include/asm-arm/arch-arm1136/mux.h index 67c8419..4fdb9c6 100644 --- a/include/asm-arm/arch-arm1136/mux.h +++ b/include/asm-arm/arch-arm1136/mux.h @@ -28,6 +28,7 @@ typedef unsigned int uint32; void muxSetupSDRC(void); void muxSetupGPMC(void); void muxSetupUsb0(void); +void muxSetupUsbHost(void); void muxSetupUart3(void); void muxSetupI2C1(void); void muxSetupUART1(void); @@ -53,6 +54,10 @@ void muxSetupHDQ(void); #define CONTROL_PADCONF_GPMC_NCS0_BYTE1 ((volatile unsigned char *)0x4800008D) #define CONTROL_PADCONF_GPMC_NCS0_BYTE2 ((volatile unsigned char *)0x4800008E) #define CONTROL_PADCONF_GPMC_NCS0_BYTE3 ((volatile unsigned char *)0x4800008F) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE4 (0x48000090) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE5 (0x48000091) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE6 (0x48000092) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE7 (0x48000093) /* Pin Muxing registers used for SDRC */ #define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0) @@ -70,6 +75,7 @@ void muxSetupHDQ(void); #define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100) #define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101) #define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102) +#define CONTROL_PADCONF_SPI1_NCS1 (0x48000103) #define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B) @@ -151,8 +157,20 @@ void muxSetupHDQ(void); #define CONTROL_PADCONF_USB0_SE0 ((volatile uint8 *)0x48000122) #define CONTROL_PADCONF_USB0_DAT ((volatile uint8 *)0x48000123) +/* Pin Muxing registres used for USB1. */ +#define CONTROL_PADCONF_USB1_RCV (0x480000EB) +#define CONTROL_PADCONF_USB1_TXEN (0x480000EC) + /* Pin Muxing registers used for UART3/IRDA */ #define CONTROL_PADCONF_UART3_TX_IRTX ((volatile uint8 *)0x48000118) #define CONTROL_PADCONF_UART3_RX_IRRX ((volatile uint8 *)0x48000119) +/* Pin Muxing registers used for GPIO */ +#define CONTROL_PADCONF_GPIO69 (0x480000ED) +#define CONTROL_PADCONF_GPIO70 (0x480000EE) +#define CONTROL_PADCONF_GPIO102 (0x48000116) +#define CONTROL_PADCONF_GPIO103 (0x48000117) +#define CONTROL_PADCONF_GPIO104 (0x48000118) +#define CONTROL_PADCONF_GPIO105 (0x48000119) + #endif diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h index d833035..0c11bec 100644 --- a/include/asm-arm/arch-arm1136/omap2420.h +++ b/include/asm-arm/arch-arm1136/omap2420.h @@ -77,6 +77,20 @@ #define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) #define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) #define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) +#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) +#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) +#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) +#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) +#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) +#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) +#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) +#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) +#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) +#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) +#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) +#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) +#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) +#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) /* SMS */ #define OMAP2420_SMS_BASE 0x68008000 @@ -209,13 +223,24 @@ #define SRAM_OFFSET2 0x0000F800 #define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - /* FPGA on Debug board.*/ #define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) #define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) #endif /* endif CONFIG_2420H4 */ +#if defined(CONFIG_APOLLON) +#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */ +#define APOLLON_CS1_BASE 0x08000000 /* ethernet */ +#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */ +#define APOLLON_CS3_BASE 0x18000000 /* NOR */ + +#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b) +#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c) +#endif /* endif CONFIG_APOLLON */ + +/* Common */ +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + #endif diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index f6a5b4f..ab19047 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -737,6 +737,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 #define MACH_TYPE_AT91SAM9261EK 848 +#define MACH_TYPE_OMAP_APOLLON 919 #define MACH_TYPE_PDNB3 1002 #define MACH_TYPE_AT91SAM9260EK 1099 #define MACH_TYPE_AT91RM9200DF 1119 @@ -6826,6 +6827,18 @@ extern unsigned int __machine_arch_type; # define machine_is_omap_h4() (0) #endif +#ifdef CONFIG_MACH_OMAP_APOLLON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_APOLLON +# endif +# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON) +#else +# define machine_is_omap_apollon() (0) +#endif + #ifdef CONFIG_MACH_N10 # ifdef machine_arch_type # undef machine_arch_type diff --git a/include/configs/apollon.h b/include/configs/apollon.h new file mode 100644 index 0000000..49fd234 --- /dev/null +++ b/include/configs/apollon.h @@ -0,0 +1,250 @@ +/* + * (C) Copyright 2005-2007 + * Samsung Electronics, + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * Configuration settings for the 2420 Samsung Apollon board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP2420 1 /* which is in a 2420 */ +#define CONFIG_OMAP2420_APOLLON 1 +#define CONFIG_APOLLON 1 +#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */ + +/* Clock config to target*/ +#define PRCM_CONFIG_I 1 +/* #define PRCM_CONFIG_II 1 */ + +/* Boot method */ +/* uncomment if you use NOR boot */ +/* #define CFG_NOR_BOOT 1 */ + +/* uncommnet if you use NOR on CS3 */ +/* #define CFG_USE_NOR 1 */ + +#ifdef CFG_NOR_BOOT +#undef CFG_USE_NOR +#define CFG_USE_NOR 1 +#endif + +#include <asm/arch/omap2420.h> /* get chip and board defs */ + +#define V_SCLK 12000000 + +/* input clock of PLL */ +/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ +#define CONFIG_SYS_CLK_FREQ V_SCLK + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +/* Total Size of Environment Sector */ +#define CFG_ENV_SIZE SZ_128K +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ + +/* + * SMC91c96 Etherent + */ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300) +#define CONFIG_LAN91C96_EXT_PHY + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ +#define CFG_NS16550_COM1 OMAP2420_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on H4 */ + + /* + * I2C configuration + */ +#define CONFIG_HARD_I2C +#define CFG_I2C_SPEED 100000 +#define CFG_I2C_SLAVE 1 +#define CONFIG_DRIVER_OMAP24XX_I2C + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ONENAND + +#undef CONFIG_CMD_AUTOSCRIPT + +#ifndef CFG_USE_NOR +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#endif + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.116.25 +#define CONFIG_SERVERIP 192.168.116.1 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_ETHADDR 00:0E:99:00:24:20 +#ifdef CONFIG_APOLLON_PLUS +#define CONFIG_MEMSIZE "64M" +#else +#define CONFIG_MEMSIZE "128M" +#endif + +#define CONFIG_BOOTARGS "root=/dev/nfs rw" \ + " mem=" CONFIG_MEMSIZE " console=ttyS0,115200n8" \ + " ip=192.168.116.25:192.168.116.1::255.255.255.0:" \ + "apollon:eth0:off nfsroot=/tftpboot/nfsroot" \ + " profile=2" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "Image=tftp 0x80008000 Image; go 0x80008000\0" \ + "zImage=tftp 0x80180000 zImage; go 0x80180000\0" \ + "uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \ + "uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \ + "xloader=tftp 0x80180000 x-load.bin;" \ + "cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \ + "syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \ + "syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \ + "norboot=cp32 0x18040000 0x80008000 0x200000; " \ + "go 0x80008000\0" \ + "oneboot=onenand read 0x80008000 0x40000 0x200000; " \ + "go 0x80008000\0" \ + "onesyncboot=run syncmode oneboot\0" \ + "rootpath=/tftpboot/nfsroot\0" \ + "bootcmd=run uboot\0" + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "Apollon # " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ + +/* The 2420 has 12 GP timers, + * they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 /* use with 12MHz/128 */ + +#define CFG_TIMERBASE OMAP2420_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +/* CS1 may or may not be populated */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_128M +#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#ifdef CFG_USE_NOR +/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */ +#define CFG_FLASH_BASE 0x18000000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 1024 +/*----------------------------------------------------------------------- + + * CFI FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +#else /* !CFG_USE_NOR */ + +#define CFG_NO_FLASH 1 +#endif /* CFG_USE_NOR */ + +/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */ +#define CFG_ONENAND_BASE 0x00000000 +#define CFG_ENV_IS_IN_ONENAND 1 +#define CFG_ENV_ADDR 0x00020000 + +#endif /* __CONFIG_H */

1 0

[U-Boot-Users] [PATCH 2/3] Apollon BSP support (take #2)
by Kyungmin Park 17 Sep '07

17 Sep '07

Apollon BSP support (take #2) The Apollon based on OMAP2420 is designed for OneNAND development. It's similar with OMAP2420 H4 except some peripherals. Now this board is maintained at mainline kernel. Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S new file mode 100644 index 0000000..fbc6df2 --- /dev/null +++ b/board/apollon/lowlevel_init.S @@ -0,0 +1,340 @@ +/* + * Board specific setup info + * + * (C) Copyright 2005-2007 + * Samsung Electronics, + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/omap2420.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> +#include "mem.h" + +#define APOLLON_CS0_BASE 0x00000000 + +#ifdef PRCM_CONFIG_I +#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907 +#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013 +#define SDRC_RFR_CTRL_0_VAL 0x00044C01 +#elif defined(PRCM_CONFIG_II) +#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485 +#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C +#define SDRC_RFR_CTRL_0_VAL 0x00030001 +#endif + +#define SDRAM_BASE_ADDRESS 0x80008000 + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +.globl lowlevel_init +lowlevel_init: + +#ifdef CFG_NOR_BOOT + /* Check running in SDRAM */ + mov r0, pc, lsr #28 + cmp r0, #8 + beq prcm_setup + +flash_setup: + /* In Flash */ + ldr r0, =WD2_BASE + ldr r1, =WD_UNLOCK1 + str r1, [r0, #WSPR] + + ldr r1, =WD_UNLOCK2 + str r1, [r0, #WSPR] + + /* Pin muxing for SDRC */ + mov r1, #0x00 + ldr r0, =0x480000A1 /* ball C12, mode 0 */ + strb r1, [r0] + + ldr r0, =0x48000032 /* ball D11, mode 0 */ + strb r1, [r0] + + ldr r0, =0x480000A3 /* ball B13, mode 0 */ + strb r1, [r0] + + /* SDRC setting */ + ldr r0, =OMAP2420_SDRC_BASE + ldr r1, =0x00000010 + str r1, [r0, #0x10] + + ldr r1, =0x00000100 + str r1, [r0, #0x44] + + /* SDRC CS0 configuration */ + ldr r1, =0x00d04011 + str r1, [r0, #0x80] + + ldr r1, =SDRC_ACTIM_CTRLA_0_VAL + str r1, [r0, #0x9C] + + ldr r1, =SDRC_ACTIM_CTRLB_0_VAL + str r1, [r0, #0xA0] + + ldr r1, =SDRC_RFR_CTRL_0_VAL + str r1, [r0, #0xA4] + + ldr r1, =0x00000041 + str r1, [r0, #0x70] + + /* Manual command sequence */ + ldr r1, =0x00000007 + str r1, [r0, #0xA8] + + ldr r1, =0x00000000 + str r1, [r0, #0xA8] + + ldr r1, =0x00000001 + str r1, [r0, #0xA8] + + ldr r1, =0x00000002 + str r1, [r0, #0xA8] + str r1, [r0, #0xA8] + + /* + * CS0 SDRC Mode register + * Burst length = 4 - DDR memory + * Serial mode + * CAS latency = 3 + */ + ldr r1, =0x00000032 + str r1, [r0, #0x84] + + /* Note: You MUST set EMR values */ + /* EMR1 & EMR2 */ + ldr r1, =0x00000000 + str r1, [r0, #0x88] + str r1, [r0, #0x8C] + +#ifdef OLD_SDRC_DLLA_CTRL + /* SDRC_DLLA_CTRL */ + ldr r1, =0x00007306 + str r1, [r0, #0x60] + + ldr r1, =0x00007303 + str r1, [r0, #0x60] +#else + /* SDRC_DLLA_CTRL */ + ldr r1, =0x00000506 + str r1, [r0, #0x60] + + ldr r1, =0x00000503 + str r1, [r0, #0x60] +#endif + +#ifdef __BROKEN_FEATURE__ + /* SDRC_DLLB_CTRL */ + ldr r1, =0x00000506 + str r1, [r0, #0x68] + + ldr r1, =0x00000503 + str r1, [r0, #0x68] +#endif + + /* little delay after init */ + mov r2, #0x1800 +1: + subs r2, r2, #0x1 + bne 1b + + /* Setup base address */ + ldr r0, =0x00000000 /* NOR address */ + ldr r1, =SDRAM_BASE_ADDRESS /* SDRAM address */ + ldr r2, =0x20000 /* Size: 128KB */ + +copy_loop: + ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + ble copy_loop + + ldr r1, =SDRAM_BASE_ADDRESS + mov lr, pc + mov pc, r1 +#endif + +prcm_setup: + ldr r0, =OMAP2420_CM_BASE + ldr r1, [r0, #0x544] /* CLKSEL2_PLL */ + bic r1, r1, #0x03 + orr r1, r1, #0x02 + str r1, [r0, #0x544] + + ldr r1, [r0, #0x500] + bic r1, r1, #0x03 + orr r1, r1, #0x01 + str r1, [r0, #0x500] + + ldr r1, [r0, #0x140] + bic r1, r1, #0x1f + orr r1, r1, #0x02 + str r1, [r0, #0x140] + +#ifdef PRCM_CONFIG_I + ldr r1, =0x000003C3 +#else + ldr r1, =0x00000343 +#endif + str r1, [r0, #0x840] + + ldr r1, =0x00000002 + str r1, [r0, #0x340] + + ldr r1, =CM_CLKSEL1_CORE +#ifdef PRCM_CONFIG_I + ldr r2, =0x08300C44 +#else + ldr r2, =0x04600C26 +#endif + str r2, [r1] + + ldr r0, =OMAP2420_CM_BASE + ldr r1, [r0, #0x084] + and r1, r1, #0x01 + cmp r1, #0x01 + bne clkvalid + + b . + +clkvalid: + mov r1, #0x01 + str r1, [r0, #0x080] + +waitvalid: + ldr r1, [r0, #0x084] + and r1, r1, #0x01 + cmp r1, #0x00 + bne waitvalid + + ldr r0, =CM_CLKSEL1_PLL +#ifdef PRCM_CONFIG_I + ldr r1, =0x01837100 +#else + ldr r1, =0x01832100 +#endif + str r1, [r0] + + ldr r0, =PRCM_CLKCFG_CTRL + mov r1, #0x01 + str r1, [r0] + mov r6, #0x50 +loop1: + subs r6, r6, #0x01 + cmp r6, #0x01 + bne loop1 + + ldr r0, =CM_CLKEN_PLL + mov r1, #0x0f + str r1, [r0] + + mov r6, #0x100 +loop2: + subs r6, r6, #0x01 + cmp r6, #0x01 + bne loop2 + + ldr r0, =0x48008200 + ldr r1, =0xbfffffff + str r1, [r0] + + ldr r0, =0x48008210 + ldr r1, =0xfffffff9 + str r1, [r0] + +#if 1 + ldr r0, =0x4806a004 + ldr r1, =0x00 + strb r1, [r0] + + ldr r0, =0x4806a020 + ldr r1, =0x07 + strb r1, [r0] + + ldr r0, =0x4806a00c + ldr r1, =0x83 + strb r1, [r0] + + ldr r0, =0x4806a000 + ldr r1, =0x1a + strb r1, [r0] + + ldr r0, =0x4806a004 + ldr r1, =0x00 + strb r1, [r0] + + ldr r0, =0x4806a00c + ldr r1, =0x03 + strb r1, [r0] + + ldr r0, =0x4806a010 + ldr r1, =0x03 + strb r1, [r0] + + ldr r0, =0x4806a008 + ldr r1, =0x04 + strb r1, [r0] + + ldr r0, =0x4806a020 + ldr r1, =0x00 + strb r1, [r0] + +#if 0 + ldr r0, =0x4806a000 + mov r1, #'u' + strb r1, [r0] +#endif + +#if 0 + /* LED0 OFF */ + ldr r3, =0x480000E5 + mov r4, #0x0b + strb r4, [r3] +#endif + +#endif + + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* map interrupt controller */ + ldr r0, VAL_INTH_SETUP + mcr p15, 0, r0, c15, c2, 4 + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +VAL_INTH_SETUP: + .word PERIFERAL_PORT_BASE +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK diff --git a/board/apollon/sys_info.c b/board/apollon/sys_info.c new file mode 100644 index 0000000..26ac9a2 --- /dev/null +++ b/board/apollon/sys_info.c @@ -0,0 +1,403 @@ +/* + * (C) Copyright 2005-2007 + * Samsung Electronics, + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * Derived from omap2420 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/omap2420.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mem.h> /* get mem tables */ +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <i2c.h> + +/************************************************************************** + * get_prod_id() - get id info from chips + ***************************************************************************/ +static u32 get_prod_id(void) +{ + u32 p; + p = __raw_readl(PRODUCTION_ID); /* get production ID */ + return ((p & CPU_242X_PID_MASK) >> 16); +} + +/************************************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + * - just looking to say if this is a 2422 or 2420 or ... + * - to start with we will look at switch settings.. + * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics + * (mux for 2420, non-mux for 2422). + ***************************************************************************/ +u32 get_cpu_type(void) +{ + u32 v; + + switch (get_prod_id()) { + case 1:; /* 2420 */ + case 2: + return (CPU_2420); + break; /* 2420 pop */ + case 4: + return (CPU_2422); + break; + case 8: + return (CPU_2423); + break; + default: + break; /* early 2420/2422's unmarked */ + } + + v = __raw_readl(TAP_IDCODE_REG); + v &= CPU_24XX_ID_MASK; + /* currently 2420 and 2422 have same id */ + if (v == CPU_2420_CHIPID) { + if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */ + return (CPU_2420); + else + return (CPU_2422); + } else + return (CPU_2420); /* don't know, say 2420 */ +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 v; + v = __raw_readl(TAP_IDCODE_REG); + v = v >> 28; + return (v + 1); /* currently 2422 and 2420 match up */ +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == H4_2420_SDRC_MR_0_SDR) + return (1); + return (0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + * 2422 uses stacked DDR, 2 parts CS0/CS1. + * 2420 may have 1 or 2, no good way to know...only init 1... + * when eeprom data is up we can select 1 more. + *************************************************************/ +u32 get_mem_type(void) +{ + u32 cpu, sdr = is_mem_sdr(); + + cpu = get_cpu_type(); + if (cpu == CPU_2422 || cpu == CPU_2423) + return (DDR_STACKED); + + if (get_prod_id() == 0x2) + return (XDR_POP); + + if (get_board_type() == BOARD_H4_MENELAUS) + if (sdr) + return (SDR_DISCRETE); + else + return (DDR_COMBO); + else if (sdr) /* SDP + SDR kit */ + return (SDR_DISCRETE); + else + return (DDR_DISCRETE); /* origional SDP */ +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; /* get ram size field */ + size &= 0x2FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/*********************************************************************** + * get_board_type() - get board type based on current production stats. + * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + ************************************************************************/ +u32 get_board_type(void) +{ + return (BOARD_H4_SDP); +} + +/****************************************************************** + * get_sysboot_value() - get init word settings (dip switch on h4) + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return (0x00000FFF & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG7_0); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/***************************************************************** + * is_gpmc_muxed() - tells if address/data lines are multiplexed + *****************************************************************/ +u32 is_gpmc_muxed(void) +{ + u32 mux; + mux = get_sysboot_value(); + if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3)) + return (GPMC_MUXED); /* NAND Boot mode */ + if (mux & BIT1) /* if mux'ed */ + return (GPMC_MUXED); + else + return (GPMC_NONMUXED); +} + +/************************************************************************ + * get_gpmc0_type() - read sysboot lines to see type of memory attached + ************************************************************************/ +u32 get_gpmc0_type(void) +{ + u32 type; + type = get_sysboot_value(); + if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2)) + return (TYPE_NAND); + else + return (TYPE_NOR); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + u32 width; + width = get_sysboot_value(); + if ((width & 0xF) == (BIT3 | BIT2)) + return (WIDTH_8BIT); + else + return (WIDTH_16BIT); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char cpu_2420[] = "2420"; /* cpu type */ + char cpu_2422[] = "2422"; + char cpu_2423[] = "2423"; + char db_men[] = "Menelaus"; /* board type */ + char db_ip[] = "IP"; + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; + + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + if (cpu == CPU_2423) + cpu_s = cpu_2423; + else if (cpu == CPU_2422) + cpu_s = cpu_2422; + else + cpu_s = cpu_2420; + + if (btype == BOARD_H4_MENELAUS) + db_s = db_men; + else + db_s = db_ip; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1); + printf("Samsung Apollon SDP Base Board + %s \n", mem_s); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = 242x IP platform (first 2xx boards) + * 1 = 242x Menelaus platfrom. + *************************************************************************/ +u32 get_board_rev(void) +{ + u32 rev = 0; + u32 btype = get_board_type(); + + if (btype == BOARD_H4_MENELAUS) + rev = 1; + return (rev); +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/******************************************************** + * get_base2(); get 2upper addr of current execution + *******************************************************/ +u32 get_base2(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xFF000000; + val >>= 24; + return (val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} + +/************************************************************* + * running_from_internal_boot() - am I a signed NOR image. + *************************************************************/ +u32 running_from_internal_boot(void) +{ + u32 v, base; + + v = get_sysboot_value() & BIT3; + base = get_base2(); + /* if running at mask rom flash address and + * sysboot3 says this was an internal boot + */ + if ((base == 0x08) && v) + return (1); + else + return (0); +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8); + return (mode >>= 8); +} diff --git a/board/apollon/u-boot.lds b/board/apollon/u-boot.lds new file mode 100644 index 0000000..5f2b5cd --- /dev/null +++ b/board/apollon/u-boot.lds @@ -0,0 +1,63 @@ +/* + * + * Copyright (C) 2005-2007 Samsung Elecronics + * Kyungin Park <kyugnmin.park(a)samsung.com> + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +}

1 0

[U-Boot-Users] [PATCH 1/3] Apollon BSP support (take #2)
by Kyungmin Park 17 Sep '07

17 Sep '07

Apollon BSP support (take #2) The Apollon based on OMAP2420 is designed for OneNAND development. It's similar with OMAP2420 H4 except some peripherals. Now this board is maintained at mainline kernel. Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/Makefile b/Makefile index c35f022..d680ad0 100644 --- a/Makefile +++ b/Makefile @@ -2356,9 +2356,12 @@ zylonite_config : ######################################################################### ## ARM1136 Systems ######################################################################### -omap2420h4_config : unconfig +omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 +apollon_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 apollon + #======================================================================== # i386 #======================================================================== diff --git a/board/apollon/Makefile b/board/apollon/Makefile new file mode 100644 index 0000000..91605ca --- /dev/null +++ b/board/apollon/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := apollon.o mem.o sys_info.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c new file mode 100644 index 0000000..064d143 --- /dev/null +++ b/board/apollon/apollon.c @@ -0,0 +1,472 @@ +/* + * (C) Copyright 2005-2007 + * Samsung Electronics. + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * Derived from omap2420 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/omap2420.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <asm/arch/mem.h> +#include <asm/mach-types.h> + +void wait_for_command_complete(unsigned int wd_base); + +DECLARE_GLOBAL_DATA_PTR; + +#define write_config_reg(reg, value) \ +do { \ + writeb(value, reg); \ +} while (0) + +#define mask_config_reg(reg, mask) \ +do { \ + char value = readb(reg) & ~(mask); \ + writeb(value, reg); \ +} while (0) + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRM, finish GPMC */ + + gd->bd->bi_arch_number = 919; + /* adress of boot parameters */ + gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100); + + return 0; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with sram stack. + **********************************************************/ +void s_init(void) +{ + watchdog_init(); + set_muxconf_regs(); + delay(100); + + peripheral_enable(); + icache_enable(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ + ether_init(); /* better done here so timers are init'ed */ + return (0); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 4 watch dogs. 1 secure, and 3 general purpose. + * The ROM takes care of the secure one. Of the 3 GP ones, + * 1 can reset us directly, the other 2 only generate MPU interrupts. + */ + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); + +#define MPU_WD_CLOCKED 1 +#if MPU_WD_CLOCKED + /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */ + __raw_writel(WD_UNLOCK1, WD3_BASE + WSPR); + wait_for_command_complete(WD3_BASE); + __raw_writel(WD_UNLOCK2, WD3_BASE + WSPR); + + __raw_writel(WD_UNLOCK1, WD4_BASE + WSPR); + wait_for_command_complete(WD4_BASE); + __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR); +#endif +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */ + + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) { + printf("1. eth reset err\n"); + goto eth_reset_err_out; + } + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) { + printf("2. eth reset err\n"); + goto eth_reset_err_out; + } + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + mask_config_reg(ETH_CONTROL_REG, 0x01); + udelay(1000); + +eth_reset_err_out: + return; +#endif +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype, rev = 0, cpu = 0; +#define NOT_EARLY 0 + + btype = get_board_type(); + mtype = get_mem_type(); + rev = get_cpu_rev(); + cpu = get_cpu_type(); + + display_board_info(btype); + + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + /* init other chip select */ + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + } + + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0; + gd->bd->bi_dram[1].size = size1; +#endif + + return 0; +} + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware + *********************************************************/ +void set_muxconf_regs(void) +{ + muxSetupSDRC(); + muxSetupGPMC(); + muxSetupUsb0(); /* USB Device */ + muxSetupUsbHost(); /* USB Host */ + muxSetupUART1(); + muxSetupLCD(); + muxSetupMMCSD(); + muxSetupTouchScreen(); +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void peripheral_enable(void) +{ + unsigned int v, if_clks = 0, func_clks = 0; + + /* Enable GP2 timer. */ + if_clks |= BIT4 | BIT3; + func_clks |= BIT4 | BIT3; + /* Sys_clk input OMAP2420_GPT2 */ + v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2; + __raw_writel(v, CM_CLKSEL2_CORE); + __raw_writel(0x1, CM_CLKSEL_WKUP); + +#ifdef CFG_NS16550 + /* Enable UART1 clock */ + func_clks |= BIT21; + if_clks |= BIT21; +#endif + /* Interface clocks on */ + v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; + __raw_writel(v, CM_ICLKEN1_CORE); + /* Functional Clocks on */ + v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; + __raw_writel(v, CM_FCLKEN1_CORE); + delay(1000); + +#ifndef KERNEL_UPDATED + { +#define V1 0xffffffff +#define V2 0x00000007 + + __raw_writel(V1, CM_FCLKEN1_CORE); + __raw_writel(V2, CM_FCLKEN2_CORE); + __raw_writel(V1, CM_ICLKEN1_CORE); + __raw_writel(V1, CM_ICLKEN2_CORE); + } +#endif +} + +/**************************************** + * Routine: muxSetupUsb0 (ostboot) + * Description: Setup usb muxing + *****************************************/ +void muxSetupUsb0(void) +{ + mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f); + mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f); + mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f); + mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f); + mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f); + mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f); + mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f); +} + +/**************************************** + * Routine: muxSetupUSBHost (ostboot) + * Description: Setup USB Host muxing + *****************************************/ +void muxSetupUsbHost(void) +{ + /* V19 */ + write_config_reg(CONTROL_PADCONF_USB1_RCV, 1); + /* W20 */ + write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1); + /* N14 */ + write_config_reg(CONTROL_PADCONF_GPIO69, 3); + /* P15 */ + write_config_reg(CONTROL_PADCONF_GPIO70, 3); + /* L18 */ + write_config_reg(CONTROL_PADCONF_GPIO102, 3); + /* L19 */ + write_config_reg(CONTROL_PADCONF_GPIO103, 3); + /* K15 */ + write_config_reg(CONTROL_PADCONF_GPIO104, 3); + /* K14 */ + write_config_reg(CONTROL_PADCONF_GPIO105, 3); +} + +/**************************************** + * Routine: muxSetupUART1 (ostboot) + * Description: Set up uart1 muxing + *****************************************/ +void muxSetupUART1(void) +{ + /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_CTS, 0); + /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_RTS, 0); + /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_TX, 0); + /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_RX, 0); +} + +/**************************************** + * Routine: muxSetupLCD (ostboot) + * Description: Setup lcd muxing + *****************************************/ +void muxSetupLCD(void) +{ + /* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D0, 0); + /* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D1, 0); + /* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D2, 0); + /* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D3, 0); + /* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D4, 0); + /* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D5, 0); + /* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D6, 0); + /* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D7, 0); + /* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D8, 0); + /* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D9, 0); + /* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D10, 0); + /* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D11, 0); + /* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D12, 0); + /* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D13, 0); + /* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D14, 0); + /* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D15, 0); + /* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D16, 0); + /* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_D17, 0); + /* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0); + /* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0); + /* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0); + /* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0); +} + +/**************************************** + * Routine: muxSetupMMCSD (ostboot) + * Description: set up MMC muxing + *****************************************/ +void muxSetupMMCSD(void) +{ + /* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0); + /* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0); + /* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_CMD, 0); + /* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0); + /* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0); + /* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0); + /* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0); + /* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0); + /* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0); + /* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0); + /* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0); + /* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0); +} + +/****************************************** + * Routine: muxSetupTouchScreen (ostboot) + * Description: Set up touch screen muxing + *******************************************/ +void muxSetupTouchScreen(void) +{ + /* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0); + /* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0); + /* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0); + /* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0); +#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1 + /* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_GPIO85, 3); +} + +/*************************************************************** + * Routine: muxSetupGPMC (ostboot) + * Description: Configures balls which cam up in protected mode + ***************************************************************/ +void muxSetupGPMC(void) +{ + /* gpmc_io_dir, MCR */ + writel(0x4800008C, 0x19000000); + + /* NOR FLASH CS0 */ + /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */ + write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0); + /* MPDB(Multi Port Debug Port) CS1 */ + /* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */ + write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0); + /* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */ + write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0); + /* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */ + write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0); + /* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */ + write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0); + /* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */ + write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0); + /* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */ + write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0); + /* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */ + write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0); +} + +/**************************************************************** + * Routine: muxSetupSDRC (ostboot) + * Description: Configures balls which come up in protected mode + ****************************************************************/ +void muxSetupSDRC(void) +{ + /* It's set by IPL */ +} diff --git a/board/apollon/config.mk b/board/apollon/config.mk new file mode 100644 index 0000000..45529c8 --- /dev/null +++ b/board/apollon/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2005-2007 +# Samsung Electronics +# +# Samsung December board with OMAP2420 (ARM1136) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# December has 1 bank of 128MB mDDR-SDRAM on CS0 +# December has 1 bank of 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) ES2 will be configurable +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + +# Used with full SRAM boot. +# This is either with a GP system or a signed boot image. +# easiest, and safest way to go if you can. +#TEXT_BASE = 0x40270000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000

1 0

[U-Boot-Users] [PATCH] Typo fix in tsec.c
by urwithsughosh＠gmail.com 15 Sep '07

15 Sep '07

Hello, Fixup for the break statement in wrong place. -- sughosh diff --git a/drivers/tsec.c b/drivers/tsec.c index 6bca4dc..4ff3339 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1262,10 +1262,10 @@ uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) case MIIM_LXT971_SR2_100HDX: priv->speed = 100; priv->duplexity = 0; + break; default: priv->speed = 100; priv->duplexity = 1; - break; } } else { priv->speed = 0;

3 2

[U-Boot-Users] [PATCH][NAND] Fix do_div() usage in nand process output
by Matthias Fuchs 15 Sep '07

15 Sep '07

Fix usage of do_div() in nand erase|read|write process output. The last patch to nand_util.c introduced do_div() instead of libgcc's implementation. But do_div() returns the quotient in its first macro parameter and not as result. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- commit 72ce73aff517363e9fc9fe3ce8c1b21e47ab8fe0 tree 4b241a66240bf37f48cf72c0dc0b19ec3d0d4803 parent 1d9e31e04911a6bb7cc66dd91132c699101c32e2 author Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> Tue, 11 Sep 2007 16:52:29 +0200 committer Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> Tue, 11 Sep 2007 16:52:29 +0200 common/cmd_nand.c | 2 +- drivers/nand/nand_util.c | 21 ++++++++++++++++----- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 254a775..34b522b 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -452,7 +452,7 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" "nand read[.jffs2] - addr off|partition size\n" - "nand write[.jffs2] - addr off|partiton size - read/write `size' bytes starting\n" + "nand write[.jffs2] - addr off|partition size - read/write `size' bytes starting\n" " at offset `off' to/from memory address `addr'\n" "nand erase [clean] [off size] - erase `size' bytes from\n" " offset `off' (entire device if not specified)\n" diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c index cf05043..4fd4e16 100644 --- a/drivers/nand/nand_util.c +++ b/drivers/nand/nand_util.c @@ -210,9 +210,12 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) if (!opts->quiet) { unsigned long long n =(unsigned long long) - (erase.addr+meminfo->erasesize-opts->offset) - * 100; - int percent = (int)do_div(n, erase_length); + (erase.addr + meminfo->erasesize - opts->offset) + * 100; + int percent; + + do_div(n, erase_length); + percent = (int)n; /* output progress message only at whole percent * steps to reduce the number of messages printed @@ -478,7 +481,11 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts) if (!opts->quiet) { unsigned long long n = (unsigned long long) (opts->length-imglen) * 100; - int percent = (int)do_div(n, opts->length); + int percent; + + do_div(n, opts->length); + percent = (int)n; + /* output progress message only at whole percent * steps to reduce the number of messages printed * on (slow) serial consoles @@ -653,7 +660,11 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts) if (!opts->quiet) { unsigned long long n = (unsigned long long) (opts->length-imglen) * 100; - int percent = (int)do_div(n ,opts->length); + int percent; + + do_div(n, opts->length); + percent = (int)n; + /* output progress message only at whole percent * steps to reduce the number of messages printed * on (slow) serial consoles

2 1

[U-Boot-Users] [GIT PULL] [ARM] Please pull from git://denx.de/git/u-boot-arm.git
by Peter Pearse 15 Sep '07

15 Sep '07

Wolfgang Please pull from git://denx.de/git/u-boot-arm.git The changes address your comments:- > The following issues need to be addressed: > include/led.h => seems specific to the at91rm9200dk board only, > please move to board directory. Also, the calls to > these functions should be handled without #ifdef's > in common code. Either use existing functions hooks, > or weak references. Moved to asm-arm as coloured_led.h - I want to play with the coloured leds on other ARM boards sometime. > drivers/at45.c => has coding style issues - indentation of long, > wrapped around lines is broken. - ran Lindent on it > cpu/arm920t/start.S => I'm surprised to see a lot of intialization > code has now been added to the "reset" entry point. > Is this by accident, or am I missing something? Ulf and I missed that CONFIG_BOOTBINFUNC has been deprecated and split into CONFIG_SKIP_RELOCATE_UBOOT CONFIG_SKIP_LOWLEVEL_INIT as described in the README. Since the CONFIG_BOOTBINFUNC code has not been tested e.g. there was no lowlevelinit(), I have removed it for now. I want to take this opportunity to remind ARM developers that any intialization - of the cpu should take place in cpu/<armcpu> /<file>::cpu_init_crit() - of the board should take place in board/<armboard>/<file>::lowlevel_init(). There are currently various misplaced initializations which I hope to sort out with the board maintainers. Anyone submitting at91rm9200 code should be aware that currently - the define CONFIG_AT91RM9200 is used by at91rm9200dk cmc_pu2 mp2usb - the define CONFIG_AT91RM9200DK is used by at91rm9200dk mp2usb please make sure not to break the other boards. > include/config_cmd_all.h: "CONFIG_CMD_MUX" is a pretty generic name, > while here it is used for a board or CPU specific > feature only. I suggest you rename this into > something which has a "AT91" in the name, like > "CONFIG_CMD_AT91_SPIMUX" or so. - done Signed-off-by: Peter Pearse <peter.pearse(a)arm.com> Signed-off-by: Ulf Samuelsson <ulf(a)atmel.com> --- The following changes since commit 38ad82da0c1180ecdeb212a8f4245e945bcc546e: Grzegorz Bernacki (1): [GP3SSA] Add define CONFIG_MPC85XX_PCI2 in config file to allow u-boot to are found in the git repository at: git://www.denx.de/git/u-boot-arm.git Peter Pearse (10): Rename CONFIG_CMD_MUX to CONFIG_CMD_AT91_SPIMUX Ran Lindent on drivers/at45.c Move include/led.h to board/at91rm9200dk Add coloured led interface for ARM boards. Changed API name to coloured_led.h Merge with git://www.denx.de/git/u-boot.git Merge with git://www.denx.de/git/u-boot.git Merge with git://www.denx.de/git/u-boot.git Merge with git://www.denx.de/git/u-boot.git Final tidy board/at91rm9200dk/led.c | 2 +- cpu/arm920t/start.S | 128 ++--------- drivers/at45.c | 334 ++++++++++++++--------------- include/{led.h => asm-arm/coloured_led.h} | 2 +- include/config_cmd_all.h | 2 +- lib_arm/board.c | 24 ++ 6 files changed, 210 insertions(+), 282 deletions(-) rename include/{led.h => asm-arm/coloured_led.h} (97%) ---

2 1

[U-Boot-Users] [PATCH][NAND] add CFG_NAND_QUIET option
by Matthias Fuchs 15 Sep '07

15 Sep '07

Add CFG_NAND_QUIET option This config option sets the default for the progress information output behavior that can also be configured through the 'quiet' environment variable. The legacy NAND code does not print the current progress info on the console. So this option is for backward compatibility for units that are in the field and where setting the quiet variable is not an option. With CFG_NAND_QUIET set to '1' the console progress info is turned off. This can still be overwritten through the environment variable. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- commit 3c84e878d4c38cda79646f540517cdcc9997ac07 tree 1c8e1fdb9f06710219bbe3abf758fb33a4d361d8 parent 72ce73aff517363e9fc9fe3ce8c1b21e47ab8fe0 author Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> Wed, 12 Sep 2007 12:27:51 +0200 committer Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> Wed, 12 Sep 2007 12:27:51 +0200 common/cmd_nand.c | 4 ++++ include/configs/ASH405.h | 3 ++- include/configs/CMS700.h | 3 ++- include/configs/HH405.h | 3 ++- include/configs/HUB405.h | 3 ++- include/configs/PLU405.h | 3 ++- include/configs/VOH405.h | 3 ++- 7 files changed, 16 insertions(+), 6 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 34b522b..1fdd7a6 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -161,7 +161,11 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, ulong addr, off, size; char *cmd, *s; nand_info_t *nand; +#ifdef CFG_NAND_QUIET + int quiet = CFG_NAND_QUIET; +#else int quiet = 0; +#endif const char *quiet_str = getenv("quiet"); /* at least two arguments please */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 0718c85..9adbba9 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -158,7 +158,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 1fd2b53..21cd9c1 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -165,7 +165,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/HH405.h b/include/configs/HH405.h index ea8e61a..8967b3f 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -217,7 +217,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index ed669c5..1ff7108 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -157,7 +157,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 4acbcd5..652210c 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -177,7 +177,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 3880ec7..14848ab 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -163,7 +163,8 @@ #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff

2 1

[U-Boot-Users] ColdFire: Another build error - mii_init() update
by Liew Tsi Chung-r5aahp 15 Sep '07

15 Sep '07

Another update. Thanks! Regards, TsiChung >From 5182f24c723d61cbce237d4e35216ad1a2a5bdc4 Mon Sep 17 00:00:00 2001 From: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> Date: Thu, 13 Sep 2007 10:28:06 -0500 Subject: [PATCH] ColdFire: Update mii function Signed-off-by: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> --- board/freescale/m5235evb/mii.c | 2 +- board/freescale/m5329evb/mii.c | 2 +- board/freescale/m54455evb/mii.c | 2 +- board/m5271evb/mii.c | 2 +- board/m5272c3/mii.c | 2 +- board/m5282evb/mii.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c index 58fabdf..1fd4d99 100644 --- a/board/freescale/m5235evb/mii.c +++ b/board/freescale/m5235evb/mii.c @@ -204,7 +204,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c index 31f1510..8f6abf3 100644 --- a/board/freescale/m5329evb/mii.c +++ b/board/freescale/m5329evb/mii.c @@ -203,7 +203,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c index c067183..7a59aa0 100644 --- a/board/freescale/m54455evb/mii.c +++ b/board/freescale/m54455evb/mii.c @@ -221,7 +221,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/m5271evb/mii.c b/board/m5271evb/mii.c index f6c63c3..3830ce7 100644 --- a/board/m5271evb/mii.c +++ b/board/m5271evb/mii.c @@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/m5272c3/mii.c b/board/m5272c3/mii.c index fadcbb3..0ecc44a 100644 --- a/board/m5272c3/mii.c +++ b/board/m5272c3/mii.c @@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/m5282evb/mii.c b/board/m5282evb/mii.c index ebd3ed9..d7c6d1f 100644 --- a/board/m5282evb/mii.c +++ b/board/m5282evb/mii.c @@ -201,7 +201,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { -- 1.5.2

2 1

[U-Boot-Users] ColdFire: Build error caused by pixis.c
by Liew Tsi Chung-r5aahp 15 Sep '07

15 Sep '07

I moved the #include <asm/cache.h> inside the #ifdef CONFIG_FSL_PIXIS. Thanks, TsiChung >From 0b78f71a029228dbe5c54ee0abdd2accd453cfe8 Mon Sep 17 00:00:00 2001 From: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> Date: Thu, 13 Sep 2007 10:23:58 -0500 Subject: [PATCH] ColdFire: Update build error Signed-off-by: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> --- board/freescale/common/pixis.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index ae4bef1..fd99a93 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -25,10 +25,9 @@ #include <common.h> #include <command.h> #include <watchdog.h> -#include <asm/cache.h> #ifdef CONFIG_FSL_PIXIS - +#include <asm/cache.h> #include "pixis.h" -- 1.5.2

2 1

[U-Boot-Users] [PATCH 1/3] Apollon BSP support
by Kyungmin Park 15 Sep '07

15 Sep '07

Apollon BSP support The Apollon based on OMAP2420 is designed for OneNAND development. It's similar with OMAP2420 H4 except some peripherals. Now this board is maintained at mainline kernel. Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/Makefile b/Makefile index 09bbf4f..78910e2 100644 --- a/Makefile +++ b/Makefile @@ -2356,9 +2356,12 @@ zylonite_config : ######################################################################### ## ARM1136 Systems ######################################################################### -omap2420h4_config : unconfig +omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 +apollon_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 apollon + #======================================================================== # i386 #======================================================================== diff --git a/board/apollon/Makefile b/board/apollon/Makefile new file mode 100644 index 0000000..91605ca --- /dev/null +++ b/board/apollon/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := apollon.o mem.o sys_info.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c new file mode 100644 index 0000000..0a48c64 --- /dev/null +++ b/board/apollon/apollon.c @@ -0,0 +1,607 @@ +/* + * (C) Copyright 2005-2007 + * Samsung Electronics. + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * Derived from omap2420 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/omap2420.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <asm/arch/mem.h> +#include <i2c.h> +#include <asm/mach-types.h> + +void wait_for_command_complete(unsigned int wd_base); + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRM, finish GPMC */ + + gd->bd->bi_arch_number = 919; + /* adress of boot parameters */ + gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100); + + return 0; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with sram stack. + **********************************************************/ +void s_init(void) +{ + + watchdog_init(); + set_muxconf_regs(); + delay(100); + + peripheral_enable(); + icache_enable(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ + ether_init(); /* better done here so timers are init'ed */ + return (0); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 4 watch dogs. 1 secure, and 3 general purpose. + * The ROM takes care of the secure one. Of the 3 GP ones, + * 1 can reset us directly, the other 2 only generate MPU interrupts. + */ + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); + +#define MPU_WD_CLOCKED 1 +#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */ + __raw_writel(WD_UNLOCK1, WD3_BASE + WSPR); + wait_for_command_complete(WD3_BASE); + __raw_writel(WD_UNLOCK2, WD3_BASE + WSPR); + + __raw_writel(WD_UNLOCK1, WD4_BASE + WSPR); + wait_for_command_complete(WD4_BASE); + __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR); +#endif +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */ + + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) { + printf("1. eth reset err\n"); + goto eth_reset_err_out; + } + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) { + printf("2. eth reset err\n"); + goto eth_reset_err_out; + } + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01; + udelay(1000); + +eth_reset_err_out: + return; +#endif +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype, rev = 0, cpu = 0; +#define NOT_EARLY 0 + + btype = get_board_type(); + mtype = get_mem_type(); + rev = get_cpu_rev(); + cpu = get_cpu_type(); + + display_board_info(btype); + + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + printf("ddr combo\n"); + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */ + } + + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0; + gd->bd->bi_dram[1].size = size1; +#endif + + return 0; +} + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware + *********************************************************/ +void set_muxconf_regs(void) +{ + muxSetupSDRC(); + muxSetupGPMC(); + muxSetupUsb0(); /* USB Device */ + muxSetupUsbHost(); /* USB Host */ + muxSetupUART1(); + muxSetupLCD(); + muxSetupMMCSD(); + muxSetupTouchScreen(); +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void peripheral_enable(void) +{ + unsigned int v, if_clks = 0, func_clks = 0; + + /* Enable GP2 timer. */ + if_clks |= BIT4 | BIT3; + func_clks |= BIT4 | BIT3; + v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2; /* Sys_clk input OMAP2420_GPT2 */ + __raw_writel(v, CM_CLKSEL2_CORE); + __raw_writel(0x1, CM_CLKSEL_WKUP); + +#ifdef CFG_NS16550 + /* Enable UART1 clock */ + func_clks |= BIT21; + if_clks |= BIT21; +#endif + v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ + __raw_writel(v, CM_ICLKEN1_CORE); + v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN1_CORE); + delay(1000); + +#ifndef KERNEL_UPDATED + { +#define V1 0xffffffff +#define V2 0x00000007 + + __raw_writel(V1, CM_FCLKEN1_CORE); + __raw_writel(V2, CM_FCLKEN2_CORE); + __raw_writel(V1, CM_ICLKEN1_CORE); + __raw_writel(V1, CM_ICLKEN2_CORE); + } +#endif +} + +/**************************************** + * Routine: muxSetupUsb0 (ostboot) + * Description: Setup usb muxing + *****************************************/ +void muxSetupUsb0(void) +{ + volatile uint8 *MuxConfigReg; + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN; + *MuxConfigReg &= (uint8) (~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP; + *MuxConfigReg &= (uint8) (~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM; + *MuxConfigReg &= (uint8) (~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV; + *MuxConfigReg &= (uint8) (~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN; + *MuxConfigReg &= (uint8) (~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0; + *MuxConfigReg &= (uint8) (~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT; + *MuxConfigReg &= (uint8) (~0x1F); +} + +#define CONTROL_PADCONF_USB1_RCV ((volatile uint8 *)0x480000EB) +#define CONTROL_PADCONF_USB1_TXEN ((volatile uint8 *)0x480000EC) +#define CONTROL_PADCONF_GPIO69 ((volatile uint8 *)0x480000ED) +#define CONTROL_PADCONF_GPIO70 ((volatile uint8 *)0x480000EE) + +#define CONTROL_PADCONF_GPIO102 ((volatile uint8 *)0x48000116) +#define CONTROL_PADCONF_GPIO103 ((volatile uint8 *)0x48000117) +#define CONTROL_PADCONF_GPIO104 ((volatile uint8 *)0x48000118) +#define CONTROL_PADCONF_GPIO105 ((volatile uint8 *)0x48000119) +/**************************************** + * Routine: muxSetupUSBHost (ostboot) + * Description: Setup USB Host muxing + *****************************************/ +void muxSetupUsbHost(void) +{ + volatile uint8 *MuxConfigReg; + + /* V19 */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_RCV; + *MuxConfigReg = 1; + /* W20 */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_TXEN; + *MuxConfigReg = 1; + /* N14 */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO69; + *MuxConfigReg = 3; + /* P15 */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO70; + *MuxConfigReg = 3; + + /* L18 */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO102; + *MuxConfigReg = 3; + /* L19 */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO103; + *MuxConfigReg = 3; + /* K15 */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO104; + *MuxConfigReg = 3; + /* K14 */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO105; + *MuxConfigReg = 3; +} + +/**************************************** + * Routine: muxSetupUART1 (ostboot) + * Description: Set up uart1 muxing + *****************************************/ +void muxSetupUART1(void) +{ + volatile unsigned char *MuxConfigReg; + + /* UART1_CTS pin configuration, PIN = D21 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* UART1_RTS pin configuration, PIN = H21 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* UART1_TX pin configuration, PIN = L20 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* UART1_RX pin configuration, PIN = T21 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ +} + +/**************************************** + * Routine: muxSetupLCD (ostboot) + * Description: Setup lcd muxing + *****************************************/ +void muxSetupLCD(void) +{ + volatile unsigned char *MuxConfigReg; + + /* LCD_D0 pin configuration, PIN = Y7 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D1 pin configuration, PIN = P10 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D2 pin configuration, PIN = V8 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D3 pin configuration, PIN = Y8 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D4 pin configuration, PIN = W8 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D5 pin configuration, PIN = R10 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D6 pin configuration, PIN = Y9 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D7 pin configuration, PIN = V9 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D8 pin configuration, PIN = W9 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D9 pin configuration, PIN = P11 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D10 pin configuration, PIN = V10 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D11 pin configuration, PIN = Y10 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D12 pin configuration, PIN = W10 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D13 pin configuration, PIN = R11 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D14 pin configuration, PIN = V11 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D15 pin configuration, PIN = W11 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D16 pin configuration, PIN = P12 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D17 pin configuration, PIN = R12 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_PCLK pin configuration, PIN = W6 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_VSYNC pin configuration, PIN = V7 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_HSYNC pin configuration, PIN = Y6 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* LCD_ACBIAS pin configuration, PIN = W7 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ +} + +/**************************************** + * Routine: muxSetupMMCSD (ostboot) + * Description: set up MMC muxing + *****************************************/ +void muxSetupMMCSD(void) +{ + volatile unsigned char *MuxConfigReg; + + /* SDMMC_CLKI pin configuration, PIN = H15 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_CLKO pin configuration, PIN = G19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_CMD pin configuration, PIN = H18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + /* External pull-ups are present. */ + /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ + + /* SDMMC_DAT0 pin configuration, PIN = F20 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + /* External pull-ups are present. */ + /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ + + /* SDMMC_DAT1 pin configuration, PIN = H14 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + /* External pull-ups are present. */ + /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ + + /* SDMMC_DAT2 pin configuration, PIN = E19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + /* External pull-ups are present. */ + /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ + + /* SDMMC_DAT3 pin configuration, PIN = D19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + /* External pull-ups are present. */ + /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ + + /* SDMMC_DDIR0 pin configuration, PIN = F19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_DDIR1 pin configuration, PIN = E20 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_DDIR2 pin configuration, PIN = F18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_DDIR3 pin configuration, PIN = E18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_CDIR pin configuration, PIN = G18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ +} + +/****************************************** + * Routine: muxSetupTouchScreen (ostboot) + * Description: Set up touch screen muxing + *******************************************/ +void muxSetupTouchScreen(void) +{ + volatile unsigned char *MuxConfigReg; + + /* SPI1_CLK pin configuration, PIN = U18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* SPI1_MOSI pin configuration, PIN = V20 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* SPI1_MISO pin configuration, PIN = T18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + + /* SPI1_nCS0 pin configuration, PIN = U19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0; + *MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ + +#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1 + + /* PEN_IRQ pin configuration, PIN = N15 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_GPIO85; + *MuxConfigReg = 0x03; /* Mode = 3, PUPD=Disabled */ +} + +/*************************************************************** + * Routine: muxSetupGPMC (ostboot) + * Description: Configures balls which cam up in protected mode + ***************************************************************/ +void muxSetupGPMC(void) +{ + volatile uint8 *MuxConfigReg; + volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C; + + /* gpmc_io_dir */ + *MCR = 0x19000000; + + /* NOR FLASH CS0 */ + /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3; + *MuxConfigReg = 0x00; + + /* MPDB(Multi Port Debug Port) CS1 */ + /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1; + *MuxConfigReg = 0x00; + + /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2; + *MuxConfigReg = 0x00; + + /* signal - Gpmc_ncs3; pin - N2; offset - 0x008C; mode - 0; Byte-3 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3; + *MuxConfigReg = 0x00; + + MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000090); + *MuxConfigReg = 0x00; + MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000091); + *MuxConfigReg = 0x00; + MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000092); + *MuxConfigReg = 0x00; + MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000093); + *MuxConfigReg = 0x00; +} + +/**************************************************************** + * Routine: muxSetupSDRC (ostboot) + * Description: Configures balls which come up in protected mode + ****************************************************************/ +void muxSetupSDRC(void) +{ + /* It's set by IPL */ +} diff --git a/board/apollon/config.mk b/board/apollon/config.mk new file mode 100644 index 0000000..45529c8 --- /dev/null +++ b/board/apollon/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2005-2007 +# Samsung Electronics +# +# Samsung December board with OMAP2420 (ARM1136) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# December has 1 bank of 128MB mDDR-SDRAM on CS0 +# December has 1 bank of 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) ES2 will be configurable +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + +# Used with full SRAM boot. +# This is either with a GP system or a signed boot image. +# easiest, and safest way to go if you can. +#TEXT_BASE = 0x40270000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000

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