August 2007 - U-Boot

[U-Boot-Users] [PATCH] mpc83xx: Correct the burst length for DDR2 with 32 bits
by Dave Liu 04 Aug '07

04 Aug '07

The burst length should be 4 for DDR2 with 32 bits bus Signed-off-by: Dave Liu<daveliu(a)freescale.com> --- cpu/mpc83xx/spd_sdram.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 647813f..5e89add 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -730,8 +730,12 @@ long int spd_sdram() sdram_cfg |= 0x10000000; /* The DIMM is 32bit width */ - if (spd.dataw_lsb == 0x20) - sdram_cfg |= 0x000C0000; + if (spd.dataw_lsb == 0x20) { + if (spd.mem_type == SPD_MEMTYPE_DDR) + sdram_cfg |= 0x000C0000; + if (spd.mem_type == SPD_MEMTYPE_DDR2) + sdram_cfg |= 0x00080000; + } ddrc_ecc_enable = 0; -- 1.5.3.rc2.29.gc4640f

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[U-Boot-Users] Problem w/ GDB and u-boot
by Bruce_Leonard＠selinc.com 04 Aug '07

04 Aug '07

Hi, I'm working on trying to debug my u-boot port to custom HW (mpc8347) using GDB talking to a BDI2K, and I've run into a problem with using GDB to do this. Every time GDB enters or leaves a function, it trys to get a new stack frame from the stack via the stack pointer (GPR1). However, very early on in u-boot there is of course no stack and therefore GPR1 isn't valid as a stack pointer. So when GDB tries to get the new stack frame it complains about being uable to access memory at address blah. That in and of itself is not a big deal to me, but because GDB relies so heavily on the stack frame nothing else will work. I can't display registers or variable, do listings or disassemblies, etc. It doesn't "break" the code, I can still single step and set breakpoints, but I can see anything. Which pretty much makes GDB worthless to me as a tool for debugging early u-boot. Has anyone else experianced this? If so, how did you get around it? Thanks. Bruce

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Re: [U-Boot-Users] uboot custodian question
by Peter Pearse 03 Aug '07

03 Aug '07

I bottom post > -----Original Message----- > From: Nishanth Menon [mailto:menon.nishanth@gmail.com] > Sent: 01 August 2007 03:53 > To: Peter Pearse > Subject: uboot custodian question > > Hi Peter, > am wondering if OMAP patches are expected to be pushed to u or not.. > thought i'd do a bit of devel as i get time.. > Regards, > Nishanth Menon > Until such time as we get a volunteer for arm/OMAP custodian I will be checking them. But patches should be pushed to the list, not direct to me...... Peter

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[U-Boot-Users] UART test in the Uboot
by Yasothabalan Ramaswamy-TLS,Chennai 03 Aug '07

03 Aug '07

Hi all, Can anyone explain me what is done in POST for UART (in the file uart.c in post directory of uboot). Or how the testing is done in that code? I am using PSC (Programmable Serial Controller) as UART, so how can I modify the code for that. Please help me. Regards, Yasotha Balan R DISCLAIMER: ----------------------------------------------------------------------------------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. It shall not attach any liability on the originator or HCL or its affiliates. Any views or opinions presented in this email are solely those of the author and may not necessarily reflect the opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of the author of this e-mail is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any mail and attachments please check them for viruses and defect. -----------------------------------------------------------------------------------------------------------------------

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[U-Boot-Users] [PATCH] changes for support of IDS8247 board
by Sergej Stepanov 03 Aug '07

03 Aug '07

Hello, first of all thanks for your comments and sorry. To get the IDS8247 board we did following changes: - FCC2 is deactivated - FCC1 is activated - I2C is activated - OF Device tree is used - coding style is corrected Regards Sergej Stepanov. diff -rpuN u-boot-1.2.0_orig/board/ids8247/ids8247.c u-boot-1.2.0_IDS8247/board/ids8247/ids8247.c --- u-boot-1.2.0_orig/board/ids8247/ids8247.c 2007-08-03 13:33:52.000000000 +0200 +++ u-boot-1.2.0_IDS8247/board/ids8247/ids8247.c 2007-08-02 12:24:49.000000000 +0200 @@ -19,12 +19,20 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * FCC1 was activated and FCC2 was deactivated for IDS8247 platform + * Sergej Stepanov, IDS GmbH, Germany, <Sergej.Stepanov(a)ids.de> + * */ #include <common.h> #include <ioports.h> #include <mpc8260.h> +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> +#endif + DECLARE_GLOBAL_DATA_PTR; /* @@ -38,12 +46,12 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port A configuration */ { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ #if defined(CONFIG_SOFT_I2C) /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ @@ -53,14 +61,14 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ #endif /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ @@ -79,20 +87,20 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port B configuration */ { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ @@ -123,8 +131,8 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ @@ -180,7 +188,7 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */ + /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ @@ -224,7 +232,7 @@ static long int try_init (volatile memct * mapped by the controller. That means, that the initial mapping has * to be (at least) twice as large as the maximum expected size. */ - maxsize = (1 + (~orx | 0x7fff)) / 2; + maxsize = (1 + (~orx | 0x7fff))/* / 2*/; sdmr_ptr = &memctl->memc_psdmr; orx_ptr = &memctl->memc_or2; @@ -316,3 +324,28 @@ nand_init (void) } #endif /* CFG_CMD_NAND */ + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + ulong clock; + /* do what ft_cpu_setup does */ + + clock = bd->bi_busfreq; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/console@0000/clock-frequency", &len); + memcpy(p, bd->bi_enetaddr, 6); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff -rpuN u-boot-1.2.0_orig/include/configs/IDS8247.h u-boot-1.2.0_IDS8247/include/configs/IDS8247.h --- u-boot-1.2.0_orig/include/configs/IDS8247.h 2007-08-03 13:33:57.000000000 +0200 +++ u-boot-1.2.0_IDS8247/include/configs/IDS8247.h 2007-08-03 13:42:41.000000000 +0200 @@ -19,6 +19,13 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * for IDS8247 platform + * - FCC1 is activated + * - FCC2 is deactivated + * - I2C is activated + * - OF device tree is used + * Sergej Stepanov, IDS GmbH, Germany, <Sergej.Stepanov(a)ids.de> */ /* @@ -120,6 +127,16 @@ #define CFG_NS16550_COM1 (CFG_UART_BASE + 0x8000) + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,8247@0" +#define OF_SOC "soc@e0008000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@e0008000/console@0000" + /* * select ethernet configuration * @@ -135,20 +152,21 @@ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ #undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ +#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ +#define CONFIG_ETHER_ON_FCC1 +#define FCC_ENET /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 + * - Rx-CLK is CLK10 + * - Tx-CLK is CLK9 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) * - Enable Full Duplex in FSMR */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) # define CFG_CPMFCR_RAMTYPE 0 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ #define CONFIG_8260_CLKIN 66666666 /* in Hz */ @@ -161,7 +179,12 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_NFS | \ CFG_CMD_NAND | \ @@ -203,7 +226,10 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_BANKS_LIST { 0xFF800000 } +#define CFG_MAX_FLASH_BANKS_DETECT 1 /* What should the base address of the main FLASH be and how big is * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk * The main FLASH is whichever is connected to *CS0. @@ -219,7 +245,7 @@ * FLASH organization */ #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ @@ -496,19 +522,20 @@ BRx_MS_SDRAM_P |\ BRx_V) -#define CFG_OR2_PRELIM CFG_OR2 /* SDRAM initialization values */ #define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A10 |\ + ORxS_ROWST_PBI0_A9 |\ ORxS_NUMR_12) -#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\ +#define CFG_OR2_PRELIM CFG_OR2 + +#define CFG_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI0_A11 |\ + PSDMR_SDA10_PBI0_A10 |\ PSDMR_RFRC_5_CLK |\ PSDMR_PRETOACT_2W |\ PSDMR_ACTTORW_2W |\ -- Sergej I. Stepanov IDS GmbH Nobelstr. 18, Zim. 2.1.05 D-76275 Ettlingen T +49 (0) 72 43/2 18-615 F +49 (0) 72 43/2 18-400 http://www.ids.de Email: Sergej.Stepanov(a)ids.de

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[U-Boot-Users] U-boot support for M5 Full System MIPS
by Mr. R 03 Aug '07

03 Aug '07

I am interested in using u-boot as a boot-loader and console setup tool for the simulator M5 while running the MIPS ISA. The M5 environment is able to load the linux kernel (and any other application). This means that all u-boot would need to do is setup any state that the linux kernel expects, make necessary connections with the serial console for input/output, and then jump into kernel entry. Which board would be a good choice as a starting point for porting to M5 for the MIPS ISA? I am currently looking at the incaip and attempting a port, but any help would be appreciated. Questions that need answering are as follows: 1) A good board to start from for the MIPS ISA? 2) A location to find the state that the linux kernel expects for the MIPS ISA. 3) Helpful information about the MIPS console (or perhaps consoles in general). Thanks. -- View this message in context: http://www.nabble.com/U-boot-support-for-M5-Full-System-MIPS-tf4213480.html… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] U-boot support for MIPS24KE with writeback cache mode
by sathesh babu 03 Aug '07

03 Aug '07

Hi, I would like to know, does u-boot-1.1.4 support MIPS24KE with writeback cache mode. I am able to run u-boot-1.1.4 on MIPS24KE processor with writethrough mode and working fine. Could you please tell me what are the additional changes required in the u-boot-1.1.4 code to support write back cache mode. Could you plz share if this implementation is avaliable. Thanks in advance. Regards, Sathesh --------------------------------- Get the freedom to save as many mails as you wish. Click here to know how.

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[U-Boot-Users] U-boot hangs on manual Reset...
by Nethra 03 Aug '07

03 Aug '07

Hello, We are using U-boot-1.1.2. In our board CPU(MPC8248) used to prog FPGA. But the concern is when FPGA is programmed and baord is reset using manual reset button. Board doesnt boot at all. It hangs and no u boot mssgs is printed on the console. I don't have any idea where and why u -boot hangs. But if we Power cycle the baord u-boot comes up properly. And this condition never occures when FPGA is not programmed. Can anybody please suggest why it is happening?? As FPGA program memory will not erase by giving reset.It just stop working So i m thinking that at every Poweron Reset i will make the PROG pin (which is an IO for CPU) low for few cycles so that FPGA prog memory will get erased. But with this situation i m not having idea where in U-boot i should do the above changes. Kindly please suggest.. Also in this scenario we connected BDI-2000 and observed the message when Manual reset is pressed. Following is the mssg printed on BDI promt:: BDI asserts HRESET - Reset JTAG controller passed - Bypass check: 0x00000001 => 0xFFFFFFFF - JTAG exists check failed - Remove HRESET and try again - Bypass check: 0x00000001 => 0x00000001 - JTAG exists check passed - COP status is 0x01 - Check running state passed - BDI scans COP freeze command - BDI removes HRESET - Target PVR is 0x80822014 - Target SVR is 0x00000000 - COP status is 0x05 - Check stopped state passed - Check LSRL length passed - BDI resumes program execution - COP status is 0x01 - Waiting for target stop failed - TARGET: Break at boot vector failed, freeze forced - TARGET: Target PVR is 0x80822014 - TARGET: resetting target passed - TARGET: processing target startup .... - TARGET: Writing vector table failed, vector catch disabled - TARGET: processing target startup passed And if we compare with Power on Reset Follwing messages is printed:: BDI asserts HRESET - Reset JTAG controller passed - Bypass check: 0x00000001 => 0x00000001 - JTAG exists check passed - COP status is 0x01 - Check running state passed - BDI scans COP freeze command - BDI removes HRESET - Target PVR is 0x80822014 - Target SVR is 0x00000000 - COP status is 0x05 - Check stopped state passed - Check LSRL length passed - BDI sets breakpoint at 0xFFF00100 - BDI resumes program execution - Waiting for target stop passed - TARGET: Target PVR is 0x80822014 - TARGET: resetting target passed - TARGET: processing target startup .... - TARGET: processing target startup passed Kindly comment.... -- View this message in context: http://www.nabble.com/U-boot-hangs-on-manual-Reset...-tf4211172.html#a11979… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] diagnosis Test
by Yasothabalan Ramaswamy-TLS,Chennai 03 Aug '07

03 Aug '07

Hello, I want to know how POST have been implemented in UBoot code. How the diagnosis test are done for UART,USB, I2C, CPU, ETHERNET and MEMORY. Regards, Yaso. DISCLAIMER: ----------------------------------------------------------------------------------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. It shall not attach any liability on the originator or HCL or its affiliates. Any views or opinions presented in this email are solely those of the author and may not necessarily reflect the opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of the author of this e-mail is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any mail and attachments please check them for viruses and defect. -----------------------------------------------------------------------------------------------------------------------

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[U-Boot-Users] i2c (fram read write) command
by Nethra 03 Aug '07

03 Aug '07

hi... I m using custom board similar to MPC8272ADS board. Here i2c commands to read write from fram have been added. When i writing any data to zeroth location it is writing same data from 00 to FFh. what is the problem...? thnks in advance... nethra -- View this message in context: http://www.nabble.com/i2c-%28fram-read-write%29-command-tf4210579.html#a119… Sent from the Uboot - Users mailing list archive at Nabble.com.

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