August 2007 - U-Boot

[U-Boot-Users] [PATCH 1/2] make MAKEALL more immune to merge conflicts
by Kim Phillips 10 Aug '07

10 Aug '07

..by placing board entries one per line, as suggested by jdl. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- rebased version. This patch expires quickly after it goes out, so please apply asap. MAKEALL | 583 +++++++++++++++++++++++++++++++++++++++++++++++---------------- 1 files changed, 436 insertions(+), 147 deletions(-) diff --git a/MAKEALL b/MAKEALL index 3e186cc..26f1419 100755 --- a/MAKEALL +++ b/MAKEALL @@ -26,124 +26,281 @@ LIST="" ## MPC5xx Systems ######################################################################### -LIST_5xx=" \ - cmi_mpc5xx \ +LIST_5xx=" \ + cmi_mpc5xx \ " ######################################################################### ## MPC5xxx Systems ######################################################################### -LIST_5xxx=" \ - BC3450 cm5200 cpci5200 EVAL5200 \ - fo300 icecube_5100 icecube_5200 lite5200b \ - mcc200 mecp5200 motionpro o2dnt \ - pf5200 PM520 TB5200 Total5100 \ - Total5200 Total5200_Rev2 TQM5200 TQM5200_B \ - TQM5200S v38b \ +LIST_5xxx=" \ + BC3450 \ + cm5200 \ + cpci5200 \ + EVAL5200 \ + fo300 \ + icecube_5100 \ + icecube_5200 \ + lite5200b \ + mcc200 \ + mecp5200 \ + motionpro \ + o2dnt \ + pf5200 \ + PM520 \ + TB5200 \ + Total5100 \ + Total5200 \ + Total5200_Rev2 \ + TQM5200 \ + TQM5200_B \ + TQM5200S \ + v38b \ " ######################################################################### ## MPC512x Systems ######################################################################### -LIST_512x=" \ - ads5121 \ +LIST_512x=" \ + ads5121 \ " ######################################################################### ## MPC8xx Systems ######################################################################### -LIST_8xx=" \ - Adder87x GENIETV MBX860T R360MPI \ - AdderII GTH MHPC RBC823 \ - ADS860 hermes MPC86xADS rmu \ - AMX860 IAD210 MPC885ADS RPXClassic \ - c2mon ICU862_100MHz MVS1 RPXlite \ - CCM IP860 NETPHONE RPXlite_DW \ - cogent_mpc8xx IVML24 NETTA RRvision \ - ELPT860 IVML24_128 NETTA2 SM850 \ - EP88x IVML24_256 NETTA_ISDN spc1920 \ - ESTEEM192E IVMS8 NETVIA SPD823TS \ - ETX094 IVMS8_128 NETVIA_V2 svm_sc8xx \ - FADS823 IVMS8_256 NX823 SXNI855T \ - FADS850SAR KUP4K pcu_e TOP860 \ - FADS860T KUP4X QS823 TQM823L \ - FLAGADM LANTEC QS850 TQM823L_LCD \ - FPS850L lwmon QS860T TQM850L \ - GEN860T MBX quantum TQM855L \ - GEN860T_SC TQM860L \ - TQM885D \ - uc100 \ - v37 \ +LIST_8xx=" \ + Adder87x \ + AdderII \ + ADS860 \ + AMX860 \ + c2mon \ + CCM \ + cogent_mpc8xx \ + ELPT860 \ + EP88x \ + ESTEEM192E \ + ETX094 \ + FADS823 \ + FADS850SAR \ + FADS860T \ + FLAGADM \ + FPS850L \ + GEN860T \ + GEN860T_SC \ + GENIETV \ + GTH \ + hermes \ + IAD210 \ + ICU862_100MHz \ + IP860 \ + IVML24 \ + IVML24_128 \ + IVML24_256 \ + IVMS8 \ + IVMS8_128 \ + IVMS8_256 \ + KUP4K \ + KUP4X \ + LANTEC \ + lwmon \ + MBX \ + MBX860T \ + MHPC \ + MPC86xADS \ + MPC885ADS \ + MVS1 \ + NETPHONE \ + NETTA \ + NETTA2 \ + NETTA_ISDN \ + NETVIA \ + NETVIA_V2 \ + NX823 \ + pcu_e \ + QS823 \ + QS850 \ + QS860T \ + quantum \ + R360MPI \ + RBC823 \ + rmu \ + RPXClassic \ + RPXlite \ + RPXlite_DW \ + RRvision \ + SM850 \ + spc1920 \ + SPD823TS \ + svm_sc8xx \ + SXNI855T \ + TOP860 \ + TQM823L \ + TQM823L_LCD \ + TQM850L \ + TQM855L \ + TQM860L \ + TQM885D \ + uc100 \ + v37 \ " ######################################################################### ## PPC4xx Systems ######################################################################### -LIST_4xx=" \ - acadia acadia_nand ADCIOP alpr \ - AP1000 AR405 ASH405 bamboo \ - bamboo_nand bubinga CANBT CMS700 \ - CPCI2DP CPCI405 CPCI4052 CPCI405AB \ - CPCI405DT CPCI440 CPCIISER4 CRAYL1 \ - csb272 csb472 DASA_SIM DP405 \ - DU405 ebony ERIC EXBITGEN \ - G2000 HH405 HUB405 JSE \ - KAREF katmai luan lwmon5 \ - METROBOX MIP405 MIP405T ML2 \ - ml300 ocotea OCRTC ORSG \ - p3p440 PCI405 pcs440ep PIP405 \ - PLU405 PMC405 PPChameleonEVB sbc405 \ - sc3 sequoia sequoia_nand taishan \ - VOH405 VOM405 W7OLMC W7OLMG \ - walnut WUH405 XPEDITE1K yellowstone \ - yosemite yucca \ +LIST_4xx=" \ + acadia \ + acadia_nand \ + ADCIOP \ + alpr \ + AP1000 \ + AR405 \ + ASH405 \ + bamboo \ + bamboo_nand \ + bubinga \ + CANBT \ + CMS700 \ + CPCI2DP \ + CPCI405 \ + CPCI4052 \ + CPCI405AB \ + CPCI405DT \ + CPCI440 \ + CPCIISER4 \ + CRAYL1 \ + csb272 \ + csb472 \ + DASA_SIM \ + DP405 \ + DU405 \ + ebony \ + ERIC \ + EXBITGEN \ + G2000 \ + HH405 \ + HUB405 \ + JSE \ + KAREF \ + katmai \ + luan \ + lwmon5 \ + METROBOX \ + MIP405 \ + MIP405T \ + ML2 \ + ml300 \ + ocotea \ + OCRTC \ + ORSG \ + p3p440 \ + PCI405 \ + pcs440ep \ + PIP405 \ + PLU405 \ + PMC405 \ + PPChameleonEVB \ + sbc405 \ + sc3 \ + sequoia \ + sequoia_nand \ + taishan \ + VOH405 \ + VOM405 \ + W7OLMC \ + W7OLMG \ + walnut \ + WUH405 \ + XPEDITE1K \ + yellowstone \ + yosemite \ + yucca \ " ######################################################################### ## MPC8220 Systems ######################################################################### -LIST_8220=" \ - Alaska8220 Yukon8220 \ +LIST_8220=" \ + Alaska8220 \ + Yukon8220 \ " ######################################################################### ## MPC824x Systems ######################################################################### -LIST_824x=" \ - A3000 barco BMW CPC45 \ - CU824 debris eXalion HIDDEN_DRAGON \ - MOUSSE MUSENKI MVBLUE \ - OXC PN62 Sandpoint8240 Sandpoint8245 \ - sbc8240 SL8245 utx8245 \ +LIST_824x=" \ + A3000 \ + barco \ + BMW \ + CPC45 \ + CU824 \ + debris \ + eXalion \ + HIDDEN_DRAGON \ + MOUSSE \ + MUSENKI \ + MVBLUE \ + OXC \ + PN62 \ + Sandpoint8240 \ + Sandpoint8245 \ + sbc8240 \ + SL8245 \ + utx8245 \ " ######################################################################### ## MPC8260 Systems (includes 8250, 8255 etc.) ######################################################################### -LIST_8260=" \ - atc cogent_mpc8260 CPU86 CPU87 \ - ep8248 ep8260 ep82xxm gw8260 \ - hymod IPHASE4539 ISPAN MPC8260ADS \ - MPC8266ADS MPC8272ADS PM826 PM828 \ - ppmc8260 Rattler8248 RPXsuper rsdproto \ - sacsng sbc8260 SCM TQM8260_AC \ - TQM8260_AD TQM8260_AE ZPC1900 \ +LIST_8260=" \ + atc \ + cogent_mpc8260 \ + CPU86 \ + CPU87 \ + ep8248 \ + ep8260 \ + ep82xxm \ + gw8260 \ + hymod \ + IPHASE4539 \ + ISPAN \ + MPC8260ADS \ + MPC8266ADS \ + MPC8272ADS \ + PM826 \ + PM828 \ + ppmc8260 \ + Rattler8248 \ + RPXsuper \ + rsdproto \ + sacsng \ + sbc8260 \ + SCM \ + TQM8260_AC \ + TQM8260_AD \ + TQM8260_AE \ + ZPC1900 \ " ######################################################################### ## MPC83xx Systems (includes 8349, etc.) ######################################################################### -LIST_83xx=" \ - MPC8313ERDB_33 MPC8313ERDB_66 MPC832XEMDS MPC8349EMDS \ - MPC8349ITX MPC8349ITXGP MPC8360EMDS sbc8349 \ - TQM834x \ +LIST_83xx=" \ + MPC8313ERDB_33 \ + MPC8313ERDB_66 \ + MPC832XEMDS \ + MPC8349EMDS \ + MPC8349ITX \ + MPC8349ITXGP \ + MPC8360EMDS \ + sbc8349 \ + TQM834x \ " @@ -151,123 +308,223 @@ LIST_83xx=" \ ## MPC85xx Systems (includes 8540, 8560 etc.) ######################################################################### -LIST_85xx=" \ - MPC8540ADS MPC8540EVAL MPC8541CDS MPC8544DS \ - MPC8548CDS MPC8555CDS MPC8560ADS MPC8568MDS \ - PM854 PM856 sbc8540 sbc8560 \ - stxgp3 stxssa TQM8540 TQM8541 \ - TQM8555 TQM8560 \ +LIST_85xx=" \ + MPC8540ADS \ + MPC8540EVAL \ + MPC8541CDS \ + MPC8544DS \ + MPC8548CDS \ + MPC8555CDS \ + MPC8560ADS \ + MPC8568MDS \ + PM854 \ + PM856 \ + sbc8540 \ + sbc8560 \ + stxgp3 \ + stxssa \ + TQM8540 \ + TQM8541 \ + TQM8555 \ + TQM8560 \ " ######################################################################### ## MPC86xx Systems ######################################################################### -LIST_86xx=" \ - MPC8641HPCN \ +LIST_86xx=" \ + MPC8641HPCN \ " ######################################################################### ## 74xx/7xx Systems ######################################################################### -LIST_74xx=" \ - DB64360 DB64460 EVB64260 P3G4 \ - p3m7448 PCIPPC2 PCIPPC6 ZUMA \ - mpc7448hpc2 +LIST_74xx=" \ + DB64360 \ + DB64460 \ + EVB64260 \ + mpc7448hpc2 \ + P3G4 \ + p3m7448 \ + PCIPPC2 \ + PCIPPC6 \ + ZUMA \ " -LIST_7xx=" \ - BAB7xx CPCI750 ELPPC p3m750 \ - ppmc7xx \ +LIST_7xx=" \ + BAB7xx \ + CPCI750 \ + ELPPC \ + p3m750 \ + ppmc7xx \ " -LIST_ppc="${LIST_5xx} ${LIST_5xxx} \ - ${LIST_8xx} \ - ${LIST_8220} ${LIST_824x} ${LIST_8260} \ - ${LIST_83xx} \ - ${LIST_85xx} \ - ${LIST_86xx} \ - ${LIST_4xx} \ - ${LIST_74xx} ${LIST_7xx}" +LIST_ppc=" \ + ${LIST_5xx} \ + ${LIST_5xxx} \ + ${LIST_8xx} \ + ${LIST_8220} \ + ${LIST_824x} \ + ${LIST_8260} \ + ${LIST_83xx} \ + ${LIST_85xx} \ + ${LIST_86xx} \ + ${LIST_4xx} \ + ${LIST_74xx} \ + ${LIST_7xx} \ +" ######################################################################### ## StrongARM Systems ######################################################################### -LIST_SA="assabet dnp1110 gcplus lart shannon" +LIST_SA=" \ + assabet \ + dnp1110 \ + gcplus \ + lart \ + shannon \ +" ######################################################################### ## ARM7 Systems ######################################################################### -LIST_ARM7=" \ - armadillo B2 ep7312 evb4510 \ - impa7 integratorap ap7 ap720t \ - lpc2292sodimm modnet50 SMN42 \ +LIST_ARM7=" \ + ap7 \ + ap720t \ + armadillo \ + B2 \ + ep7312 \ + evb4510 \ + impa7 \ + integratorap \ + lpc2292sodimm \ + modnet50 \ + SMN42 \ " ######################################################################### ## ARM9 Systems ######################################################################### -LIST_ARM9=" \ - at91rm9200dk cmc_pu2 \ - ap920t ap922_XA10 ap926ejs ap946es \ - ap966 cp920t cp922_XA10 cp926ejs \ - cp946es cp966 lpd7a400 mp2usb \ - mx1ads mx1fs2 netstar omap1510inn \ - omap1610h2 omap1610inn omap730p2 sbc2410x \ - scb9328 smdk2400 smdk2410 trab \ - VCMA9 versatile versatileab versatilepb \ - voiceblue \ +LIST_ARM9=" \ + at91rm9200dk \ + cmc_pu2 \ + ap920t \ + ap922_XA10 \ + ap926ejs \ + ap946es \ + ap966 \ + cp920t \ + cp922_XA10 \ + cp926ejs \ + cp946es \ + cp966 \ + lpd7a400 \ + mp2usb \ + mx1ads \ + mx1fs2 \ + netstar \ + omap1510inn \ + omap1610h2 \ + omap1610inn \ + omap730p2 \ + sbc2410x \ + scb9328 \ + smdk2400 \ + smdk2410 \ + trab \ + VCMA9 \ + versatile \ + versatileab \ + versatilepb \ + voiceblue \ " ######################################################################### ## ARM10 Systems ######################################################################### -LIST_ARM10=" \ - integratorcp cp1026 \ +LIST_ARM10=" \ + integratorcp \ + cp1026 \ " ######################################################################### ## ARM11 Systems ######################################################################### -LIST_ARM11=" \ - cp1136 omap2420h4 \ +LIST_ARM11=" \ + cp1136 \ + omap2420h4 \ " ######################################################################### ## Xscale Systems ######################################################################### -LIST_pxa=" \ - adsvix cerf250 cradle csb226 \ - delta innokom lubbock pleb2 \ - pxa255_idp wepep250 xaeniax xm250 \ - xsengine zylonite \ +LIST_pxa=" \ + adsvix \ + cerf250 \ + cradle \ + csb226 \ + delta \ + innokom \ + lubbock \ + pleb2 \ + pxa255_idp \ + wepep250 \ + xaeniax \ + xm250 \ + xsengine \ + zylonite \ " -LIST_ixp="ixdp425 ixdpg425 pdnb3 scpu" +LIST_ixp=" \ + ixdp425 \ + ixdpg425 \ + pdnb3 \ + scpu \ +" -LIST_arm=" \ - ${LIST_SA} \ - ${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11} \ - ${LIST_pxa} ${LIST_ixp} \ +LIST_arm=" \ + ${LIST_SA} \ + ${LIST_ARM7} \ + ${LIST_ARM9} \ + ${LIST_ARM10} \ + ${LIST_ARM11} \ + ${LIST_pxa} \ + ${LIST_ixp} \ " ######################################################################### ## MIPS Systems (default = big endian) ######################################################################### -LIST_mips4kc="incaip" +LIST_mips4kc=" \ + incaip \ +" -LIST_mips5kc="purple" +LIST_mips5kc=" \ + purple \ +" -LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el gth2" +LIST_au1xx0=" \ + dbau1000 \ + dbau1100 \ + dbau1500 \ + dbau1550 \ + dbau1550_el \ + gth2 \ +" -LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}" +LIST_mips=" \ + ${LIST_mips4kc} \ + ${LIST_mips5kc} \ + ${LIST_au1xx0} \ +" ######################################################################### ## MIPS Systems (little endian) @@ -277,36 +534,55 @@ LIST_mips4kc_el="" LIST_mips5kc_el="" -LIST_au1xx0_el="dbau1550_el" +LIST_au1xx0_el=" \ + dbau1550_el \ +" -LIST_mips_el="${LIST_mips4kc_el} ${LIST_mips5kc_el} ${LIST_au1xx0_el}" +LIST_mips_el=" \ + ${LIST_mips4kc_el} \ + ${LIST_mips5kc_el} \ + ${LIST_au1xx0_el} \ +" ######################################################################### ## i386 Systems ######################################################################### -LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel" +LIST_I486=" \ + sc520_cdp \ + sc520_spunk \ + sc520_spunk_rel \ +" -LIST_x86="${LIST_I486}" +LIST_x86=" \ + ${LIST_I486} \ +" ######################################################################### ## NIOS Systems ######################################################################### -LIST_nios=" \ - ADNPESC1 ADNPESC1_base_32 \ - ADNPESC1_DNPEVA2_base_32 \ - DK1C20 DK1C20_standard_32 \ - DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \ +LIST_nios=" \ + ADNPESC1 \ + ADNPESC1_base_32 \ + ADNPESC1_DNPEVA2_base_32\ + DK1C20 \ + DK1C20_standard_32 \ + DK1S10 \ + DK1S10_standard_32 \ + DK1S10_mtx_ldk_20 \ " ######################################################################### ## Nios-II Systems ######################################################################### -LIST_nios2=" \ - EP1C20 EP1S10 EP1S40 \ - PCI5441 PK1C20 \ +LIST_nios2=" \ + EP1C20 \ + EP1S10 \ + EP1S40 \ + PCI5441 \ + PK1C20 \ " ######################################################################### @@ -314,31 +590,44 @@ LIST_nios2=" \ ######################################################################### LIST_microblaze=" \ - suzaku ml401 xupv2p + suzaku \ + ml401 \ + xupv2p \ " ######################################################################### ## ColdFire Systems ######################################################################### -LIST_coldfire=" \ - cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \ - idmr M5271EVB M5272C3 M5282EVB \ - TASREG r5200 M5271EVB \ +LIST_coldfire=" \ + cobra5272 \ + EB+MCF-EV123 \ + EB+MCF-EV123_internal \ + idmr \ + M5271EVB \ + M5272C3 \ + M5282EVB \ + TASREG \ + r5200 \ " ######################################################################### ## AVR32 Systems ######################################################################### -LIST_avr32="atstk1002" +LIST_avr32=" \ + atstk1002 \ +" ######################################################################### ## Blackfin Systems ######################################################################### -LIST_blackfin=" \ - bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit \ +LIST_blackfin=" \ + bf533-ezkit \ + bf533-stamp \ + bf537-stamp \ + bf561-ezkit \ " #----------------------------------------------------------------------- -- 1.5.2.2

2 1

[U-Boot-Users] [PATCH 2/2] Add support for SBC8641D
by Joe Hamman 10 Aug '07

10 Aug '07

Add support for Wind River's SBC8641D reference board. Signed-off by: Joe Hamman <joe.hamman(a)embeddedspecialties.com> diff -uprN -X ../dontdiff a/doc/README.sbc8641d b/doc/README.sbc8641d --- a/doc/README.sbc8641d 1969-12-31 18:00:00.000000000 -0600 +++ b/doc/README.sbc8641d 2007-08-09 09:22:35.000000000 -0500 @@ -0,0 +1,28 @@ +Wind River SBC8641D reference board +=========================== + +Created 06/14/2007 Joe Hamman +Copyright 2007, Embedded Specialties, Inc. +Copyright 2007 Wind River Systemes, Inc. +----------------------------- + +1. Building U-Boot +------------------ +The SBC8641D code is known to build using ELDK 4.1. + + $ make sbc8641d_config + Configuring for sbc8641d board... + + $ make + + +2. Switch and Jumper Settings +----------------------------- +All Jumpers & Switches are in their default positions. Please refer to +the board documentation for details. Some settings control CPU voltages +and settings may change with board revisions. + +3. Known limitations +-------------------- +PCI: + The PCI command may hang if no boards are present in either slot. diff -uprN -X ../dontdiff a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h --- a/include/configs/sbc8641d.h 1969-12-31 18:00:00.000000000 -0600 +++ b/include/configs/sbc8641d.h 2007-08-09 10:32:43.000000000 -0500 @@ -0,0 +1,599 @@ +/* + * Copyright 2007 Wind River Systems <www.windriver.com> + * Copyright 2007 Embedded Specialties, Inc. + * Joe Hamman <joe.hamman(a)embeddedspecialties.com> + * + * Copyright 2006 Freescale Semiconductor. + * + * Srikanth Srinivasan (srikanth.srinivasan(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * SBC8641D board configuration file + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_SBC8641D 1 /* SBC8641D board specific */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ + +#ifdef RUN_DIAG +#define CFG_DIAG_ADDR 0xff800000 +#endif + +#define CFG_RESET_ADDRESS 0xfff00100 + +#define CONFIG_PCI 1 +#define CONFIG_FSL_PCI_INIT 1 + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CACHE_LINE_INTERLEAVING 0x20000000 +#define PAGE_INTERLEAVING 0x21000000 +#define BANK_INTERLEAVING 0x22000000 +#define SUPER_BANK_INTERLEAVING 0x23000000 + + +#define CONFIG_ALTIVEC 1 + +/* + * L2CR setup -- make sure this is right for your board! + */ +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CFG_SDRAM_BASE2 CFG_DDR_SDRAM_BASE2 +#define CONFIG_VERY_BIG_RAM + +#define MPC86xx_DDR_SDRAM_CLK_CNTL + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ + +#else + /* + * Manually set up DDR1 & DDR2 parameters + */ + + #define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ + + #define CFG_DDR_CS0_BNDS 0x0000000F + #define CFG_DDR_CS1_BNDS 0x00000000 + #define CFG_DDR_CS2_BNDS 0x00000000 + #define CFG_DDR_CS3_BNDS 0x00000000 + #define CFG_DDR_CS0_CONFIG 0x80010102 + #define CFG_DDR_CS1_CONFIG 0x00000000 + #define CFG_DDR_CS2_CONFIG 0x00000000 + #define CFG_DDR_CS3_CONFIG 0x00000000 + #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_0 0x00220802 + #define CFG_DDR_TIMING_1 0x38377322 + #define CFG_DDR_TIMING_2 0x002040c7 + #define CFG_DDR_CFG_1A 0x43008008 + #define CFG_DDR_CFG_2 0x24401000 + #define CFG_DDR_MODE_1 0x23c00542 + #define CFG_DDR_MODE_2 0x00000000 + #define CFG_DDR_MODE_CTL 0x00000000 + #define CFG_DDR_INTERVAL 0x05080100 + #define CFG_DDR_DATA_INIT 0x00000000 + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_CFG_1B 0xC3008008 + + #define CFG_DDR2_CS0_BNDS 0x0010001F + #define CFG_DDR2_CS1_BNDS 0x00000000 + #define CFG_DDR2_CS2_BNDS 0x00000000 + #define CFG_DDR2_CS3_BNDS 0x00000000 + #define CFG_DDR2_CS0_CONFIG 0x80010102 + #define CFG_DDR2_CS1_CONFIG 0x00000000 + #define CFG_DDR2_CS2_CONFIG 0x00000000 + #define CFG_DDR2_CS3_CONFIG 0x00000000 + #define CFG_DDR2_EXT_REFRESH 0x00000000 + #define CFG_DDR2_TIMING_0 0x00220802 + #define CFG_DDR2_TIMING_1 0x38377322 + #define CFG_DDR2_TIMING_2 0x002040c7 + #define CFG_DDR2_CFG_1A 0x43008008 + #define CFG_DDR2_CFG_2 0x24401000 + #define CFG_DDR2_MODE_1 0x23c00542 + #define CFG_DDR2_MODE_2 0x00000000 + #define CFG_DDR2_MODE_CTL 0x00000000 + #define CFG_DDR2_INTERVAL 0x05080100 + #define CFG_DDR2_DATA_INIT 0x00000000 + #define CFG_DDR2_CLK_CTRL 0x03800000 + #define CFG_DDR2_CFG_1B 0xC3008008 + + +#endif + +/* #define CFG_ID_EEPROM 1 +#define ID_EEPROM_ADDR 0x57 */ + +/* + * The SBC8641D contains 16MB flash space at ff000000. + */ +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ + +/* Flash */ +#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ + +/* 64KB EEPROM */ +#define CFG_BR1_PRELIM 0xf0000801 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ + +/* EPLD - User switches, board id, LEDs */ +#define CFG_BR2_PRELIM 0xf1000801 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ + +/* Local bus SDRAM 128MB */ +#define CFG_BR3_PRELIM 0xe0001861 /* port size ?bit */ +#define CFG_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ +#define CFG_BR4_PRELIM 0xe4001861 /* port size ?bit */ +#define CFG_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ + +/* Disk on Chip (DOC) 128MB */ +#define CFG_BR5_PRELIM 0xe8001001 /* port size ?bit */ +#define CFG_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ + +/* LCD */ +#define CFG_BR6_PRELIM 0xf4000801 /* port size ?bit */ +#define CFG_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ + +/* Control logic & misc peripherals */ +#define CFG_BR7_PRELIM 0xf2000801 /* port size ?bit */ +#define CFG_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 131 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_WRITE_SWAPPED_DATA +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_PROTECTION + +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#ifndef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ +#else +#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ +#endif +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree to kernel + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@f8000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3100 + +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#undef CFG_SCSI_SCAN_BUS_REVERSE + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CONFIG_DOS_PARTITION +#undef CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* #define CONFIG_MII 1 */ /* MII PHY management */ + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" + +#define TSEC1_PHY_ADDR 0x1F +#define TSEC2_PHY_ADDR 0x00 +#define TSEC3_PHY_ADDR 0x01 +#define TSEC4_PHY_ADDR 0x02 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ + +#define CONFIG_ETHPRIME "eTSEC1" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) +#define CFG_IBAT0U CFG_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory + * Changed it for operating from 0xd0000000 + */ +#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U CFG_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory + */ +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U CFG_DBAT2U + +/* + * BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR + */ +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + * Note that this is at 0xe0000000 + */ +#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U CFG_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U + +/* + * BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH + */ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U + +#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#include <config_cmd_default.h> + #define CONFIG_CMD_PING + #define CONFIG_CMD_I2C + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 02:E0:0C:00:00:01 +#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD +#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD +#endif + +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 + +#define CONFIG_IPADDR 192.168.0.50 + +#define CONFIG_HOSTNAME sbc8641d +#define CONFIG_ROOTPATH /opt/eldk/ppc_74xx +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=uRamdisk\0" \ + "dtbaddr=400000\0" \ + "dtbfile=sbc8641d.dtb\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=1" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" + +#define CONFIG_FLASHBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "bootm ffd00000 ffb00000 ffa00000" + +#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND + +#endif /* __CONFIG_H */ diff -uprN -X ../dontdiff a/MAINTAINERS b/MAINTAINERS --- a/MAINTAINERS 2007-08-09 08:35:01.000000000 -0500 +++ b/MAINTAINERS 2007-08-09 09:22:35.000000000 -0500 @@ -179,6 +179,10 @@ Howard Gray <mvsensor(a)matrix-vision.de> MVS1 MPC823 +Joe Hamman <joe.hamman(a)embeddedspecialties.com> + + sbc8641d MPC8641D + Klaus Heydeck <heydeck(a)kieback-peter.de> KUP4K MPC855 diff -uprN -X ../dontdiff a/MAKEALL b/MAKEALL --- a/MAKEALL 2007-08-09 08:35:01.000000000 -0500 +++ b/MAKEALL 2007-08-09 13:25:23.000000000 -0500 @@ -156,7 +156,7 @@ LIST_85xx=" \ ######################################################################### LIST_86xx=" \ - MPC8641HPCN \ + MPC8641HPCN SBC8641D \ " ######################################################################### diff -uprN -X ../dontdiff a/Makefile b/Makefile --- a/Makefile 2007-08-09 08:35:01.000000000 -0500 +++ b/Makefile 2007-08-09 09:22:35.000000000 -0500 @@ -1849,6 +1849,8 @@ TQM8560_config: unconfig MPC8641HPCN_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn +sbc8641d_config: unconfig + @./mkconfig $(@:_config=) ppc mpc86xx sbc8641d ######################################################################### ## 74xx/7xx Systems

3 3

[U-Boot-Users] [PATCH 2/2] README: Remove outdated cpu type, board type, and NAME_config lists
by Kim Phillips 10 Aug '07

10 Aug '07

Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- per WD's request. README | 140 ++-------------------------------------------------------------- 1 files changed, 4 insertions(+), 136 deletions(-) diff --git a/README b/README index 0df024f..398ea7e 100644 --- a/README +++ b/README @@ -228,114 +228,9 @@ build a config tool - later. The following options need to be configured: -- CPU Type: Define exactly one of - - PowerPC based CPUs: - ------------------- - CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860 - or CONFIG_MPC5xx - or CONFIG_MPC8220 - or CONFIG_MPC824X, CONFIG_MPC8260 - or CONFIG_MPC85xx - or CONFIG_IOP480 - or CONFIG_405GP - or CONFIG_405EP - or CONFIG_440 - or CONFIG_MPC74xx - or CONFIG_750FX - - ARM based CPUs: - --------------- - CONFIG_SA1110 - CONFIG_ARM7 - CONFIG_PXA250 - CONFIG_PXA27X - CONFIG_CPU_MONAHANS - - MicroBlaze based CPUs: - ---------------------- - CONFIG_MICROBLAZE - - Nios-2 based CPUs: - ---------------------- - CONFIG_NIOS2 - - AVR32 based CPUs: - ---------------------- - CONFIG_AT32AP - -- Board Type: Define exactly one of - - PowerPC based boards: - --------------------- - - CONFIG_ADCIOP CONFIG_FPS860L CONFIG_OXC - CONFIG_ADS860 CONFIG_GEN860T CONFIG_PCI405 - CONFIG_AMX860 CONFIG_GENIETV CONFIG_PCIPPC2 - CONFIG_AP1000 CONFIG_GTH CONFIG_PCIPPC6 - CONFIG_AR405 CONFIG_gw8260 CONFIG_pcu_e - CONFIG_BAB7xx CONFIG_hermes CONFIG_PIP405 - CONFIG_BC3450 CONFIG_hymod CONFIG_PM826 - CONFIG_c2mon CONFIG_IAD210 CONFIG_ppmc8260 - CONFIG_CANBT CONFIG_ICU862 CONFIG_QS823 - CONFIG_CCM CONFIG_IP860 CONFIG_QS850 - CONFIG_CMI CONFIG_IPHASE4539 CONFIG_QS860T - CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RBC823 - CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXClassic - CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXlite - CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_RPXsuper - CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_rsdproto - CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_sacsng - CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8240 - CONFIG_CSB272 CONFIG_LANTEC CONFIG_Sandpoint8245 - CONFIG_CU824 CONFIG_LITE5200B CONFIG_sbc8260 - CONFIG_DASA_SIM CONFIG_lwmon CONFIG_sbc8560 - CONFIG_DB64360 CONFIG_MBX CONFIG_SM850 - CONFIG_DB64460 CONFIG_MBX860T CONFIG_SPD823TS - CONFIG_DU405 CONFIG_MHPC CONFIG_STXGP3 - CONFIG_DUET_ADS CONFIG_MIP405 CONFIG_SXNI855T - CONFIG_EBONY CONFIG_MOUSSE CONFIG_TQM823L - CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM8260 - CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM850L - CONFIG_ep8260 CONFIG_MPC8540EVAL CONFIG_TQM855L - CONFIG_ERIC CONFIG_MPC8560ADS CONFIG_TQM860L - CONFIG_ESTEEM192E CONFIG_MUSENKI CONFIG_TTTech - CONFIG_ETX094 CONFIG_MVS1 CONFIG_UTX8245 - CONFIG_EVB64260 CONFIG_NETPHONE CONFIG_V37 - CONFIG_FADS823 CONFIG_NETTA CONFIG_W7OLMC - CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMG - CONFIG_FADS860T CONFIG_NX823 CONFIG_WALNUT - CONFIG_FLAGADM CONFIG_OCRTC CONFIG_ZPC1900 - CONFIG_FPS850L CONFIG_ORSG CONFIG_ZUMA - - ARM based boards: - ----------------- - - CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250, - CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110, - CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, - CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, - CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400, - CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, - CONFIG_PLEB2, CONFIG_SHANNON, CONFIG_P2_OMAP730, - CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB, - CONFIG_VCMA9 - - MicroBlaze based boards: - ------------------------ - - CONFIG_SUZAKU - - Nios-2 based boards: - ------------------------ - - CONFIG_PCI5441 CONFIG_PK1C20 - CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40 - - AVR32 based boards: - ------------------- - - CONFIG_ATSTK1000 +- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX. + +- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS. - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined) Define exactly one of @@ -2492,34 +2387,7 @@ is done by typing: make NAME_config where "NAME_config" is the name of one of the existing -configurations; the following names are supported: - - ADCIOP_config FPS860L_config omap730p2_config - ADS860_config GEN860T_config pcu_e_config - Alaska8220_config - AR405_config GENIETV_config PIP405_config - at91rm9200dk_config GTH_config QS823_config - CANBT_config hermes_config QS850_config - cmi_mpc5xx_config hymod_config QS860T_config - cogent_common_config IP860_config RPXlite_config - cogent_mpc8260_config IVML24_config RPXlite_DW_config - cogent_mpc8xx_config IVMS8_config RPXsuper_config - CPCI405_config JSE_config rsdproto_config - CPCIISER4_config LANTEC_config Sandpoint8240_config - csb272_config lwmon_config sbc8260_config - CU824_config MBX860T_config sbc8560_33_config - DUET_ADS_config MBX_config sbc8560_66_config - EBONY_config mpc7448hpc2_config SM850_config - ELPT860_config MPC8260ADS_config SPD823TS_config - ESTEEM192E_config MPC8540ADS_config stxgp3_config - ETX094_config MPC8540EVAL_config SXNI855T_config - FADS823_config NMPC8560ADS_config TQM823L_config - FADS850SAR_config NETVIA_config TQM850L_config - FADS860T_config omap1510inn_config TQM855L_config - FPS850L_config omap1610h2_config TQM860L_config - omap1610inn_config walnut_config - omap5912osk_config Yukon8220_config - omap2420h4_config ZPC1900_config +configurations; see the main Makefile for supported names. Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for -- 1.5.2.2

2 1

[U-Boot-Users] [ARM] TI DaVinci support, hopefully final [2/5]
by ksi＠koi8.net 10 Aug '07

10 Aug '07

Signed-off-by: Sergey Kubushyn <ksi(a)koi8.net> diff -purN u-boot.git.orig/common/cmd_nvedit.c u-boot.git/common/cmd_nvedit.c --- u-boot.git.orig/common/cmd_nvedit.c 2007-08-06 18:05:59.000000000 -0700 +++ u-boot.git/common/cmd_nvedit.c 2007-08-07 10:15:34.000000000 -0700 @@ -193,7 +193,12 @@ int _do_setenv (int flag, int argc, char * Ethernet Address and serial# can be set only once, * ver is readonly. */ +#ifdef CONFIG_HAS_UID + /* Allow serial# forced overwrite with 0xdeaf4add flag */ + if ( ((strcmp (name, "serial#") == 0) && (flag != 0xdeaf4add)) || +#else if ( (strcmp (name, "serial#") == 0) || +#endif ((strcmp (name, "ethaddr") == 0) #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0) @@ -397,7 +402,15 @@ void setenv (char *varname, char *varval _do_setenv (0, 3, argv); } -int do_setenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +#ifdef CONFIG_HAS_UID +void forceenv (char *varname, char *varvalue) +{ + char *argv[4] = { "forceenv", varname, varvalue, NULL }; + _do_setenv (0xdeaf4add, 3, argv); +} +#endif + +int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { printf ("Usage:\n%s\n", cmdtp->usage); diff -purN u-boot.git.orig/cpu/arm926ejs/davinci/dp83848.c u-boot.git/cpu/arm926ejs/davinci/dp83848.c --- u-boot.git.orig/cpu/arm926ejs/davinci/dp83848.c 1969-12-31 16:00:00.000000000 -0800 +++ u-boot.git/cpu/arm926ejs/davinci/dp83848.c 2007-08-07 10:22:28.000000000 -0700 @@ -0,0 +1,156 @@ +/* + * National Semiconductor DP83848 PHY Driver for TI DaVinci + * (TMS320DM644x) based boards. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <net.h> +#include <dp83848.h> +#include <asm/arch/emac_defs.h> + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +int dp83848_is_phy_connected(int phy_addr) +{ + u_int16_t id1, id2; + + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1)) + return(0); + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2)) + return(0); + + if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI)) + return(1); + + return(0); +} + +int dp83848_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; + + if (!dm644x_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) + return(0); + + if (!(tmp & DP83848_LINK_STATUS)) /* link up? */ + return(0); + + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp)) + return(0); + + /* Speed doesn't matter, there is no setting for it in EMAC... */ + if (tmp & DP83848_SPEED) { + if (tmp & DP83848_DUPLEX) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } else { + if (tmp & DP83848_DUPLEX) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } + + return(0); +} + + +int dp83848_init_phy(int phy_addr) +{ + int ret = 1; + + if (!dp83848_get_link_speed(phy_addr)) { + /* Try another time */ + udelay(100000); + ret = dp83848_get_link_speed(phy_addr); + } + + /* Disable PHY Interrupts */ + dm644x_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0); + + return(ret); +} + + +int dp83848_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + + if (!dm644x_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */ + tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */ + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /* Set the Auto_negotiation Advertisement Register + * MII advertising for Next page, 100BaseTxFD and HD, + * 10BaseTFD and HD, IEEE 802.3 + */ + tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX | + DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3; + dm644x_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp); + + + /* Read Control Register */ + if (!dm644x_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) + return(0); + + tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE; + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /* Restart Auto_negotiation */ + tmp |= DP83848_RESTART_AUTONEG; + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /*check AutoNegotiate complete */ + udelay(10000); + if (!dm644x_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) + return(0); + + if (!(tmp & DP83848_AUTONEG_COMP)) + return(0); + + return (dp83848_get_link_speed(phy_addr)); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff -purN u-boot.git.orig/cpu/arm926ejs/davinci/ether.c u-boot.git/cpu/arm926ejs/davinci/ether.c --- u-boot.git.orig/cpu/arm926ejs/davinci/ether.c 1969-12-31 16:00:00.000000000 -0800 +++ u-boot.git/cpu/arm926ejs/davinci/ether.c 2007-08-07 10:23:13.000000000 -0700 @@ -0,0 +1,652 @@ +/* + * Ethernet driver for TI TMS320DM644x (DaVinci) chips. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright + * follows: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.c + * + * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. + * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors + * + */ +#include <common.h> +#include <command.h> +#include <net.h> +#include <miiphy.h> +#include <asm/arch/emac_defs.h> + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +unsigned int emac_dbg = 0; +#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) + +/* Internal static functions */ +static int dm644x_eth_hw_init (void); +static int dm644x_eth_open (void); +static int dm644x_eth_close (void); +static int dm644x_eth_send_packet (volatile void *packet, int length); +static int dm644x_eth_rcv_packet (void); +static void dm644x_eth_mdio_enable(void); + +static int gen_init_phy(int phy_addr); +static int gen_is_phy_connected(int phy_addr); +static int gen_get_link_speed(int phy_addr); +static int gen_auto_negotiate(int phy_addr); + +/* Wrappers exported to the U-Boot proper */ +int eth_hw_init(void) +{ + return(dm644x_eth_hw_init()); +} + +int eth_init(bd_t * bd) +{ + return(dm644x_eth_open()); +} + +void eth_halt(void) +{ + dm644x_eth_close(); +} + +int eth_send(volatile void *packet, int length) +{ + return(dm644x_eth_send_packet(packet, length)); +} + +int eth_rx(void) +{ + return(dm644x_eth_rcv_packet()); +} + +void eth_mdio_enable(void) +{ + dm644x_eth_mdio_enable(); +} +/* End of wrappers */ + + +static u_int8_t dm644x_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + +/* + * This function must be called before emac_open() if you want to override + * the default mac address. + */ +void dm644x_eth_set_mac_addr(const u_int8_t *addr) +{ + int i; + + for (i = 0; i < sizeof (dm644x_eth_mac_addr); i++) { + dm644x_eth_mac_addr[i] = addr[i]; + } +} + +/* EMAC Addresses */ +static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; +static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; +static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; + +/* EMAC descriptors */ +static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); +static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +static volatile emac_desc *emac_rx_active_head = 0; +static volatile emac_desc *emac_rx_active_tail = 0; +static int emac_rx_queue_active = 0; + +/* Receive packet buffers */ +static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + +/* PHY address for a discovered PHY (0xff - not found) */ +static volatile u_int8_t active_phy_addr = 0xff; + +phy_t phy; + +static void dm644x_eth_mdio_enable(void) +{ + u_int32_t clkdiv; + + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + + adap_mdio->CONTROL = (clkdiv & 0xff) | + MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | + MDIO_CONTROL_FAULT_ENABLE; + + while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;} +} + +/* + * Tries to find an active connected PHY. Returns 1 if address if found. + * If no active PHY (or more than one PHY) found returns 0. + * Sets active_phy_addr variable. + */ +static int dm644x_eth_phy_detect(void) +{ + u_int32_t phy_act_state; + int i; + + active_phy_addr = 0xff; + + if ((phy_act_state = adap_mdio->ALIVE) == 0) + return(0); /* No active PHYs */ + + debug_emac("dm644x_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); + + for (i = 0; i < 32; i++) { + if (phy_act_state & (1 << i)) { + if (phy_act_state & ~(1 << i)) + return(0); /* More than one PHY */ + else { + active_phy_addr = i; + return(1); + } + } + } + + return(0); /* Just to make GCC happy */ +} + + +/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ +int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) +{ + int tmp; + + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16); + + /* Wait for command to complete */ + while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;} + + if (tmp & MDIO_USERACCESS0_ACK) { + *data = tmp & 0xffff; + return(1); + } + + *data = -1; + return(0); +} + +/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ +int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) +{ + + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16) | + (data & 0xffff); + + /* Wait for command to complete */ + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + return(1); +} + +/* PHY functions for a generic PHY */ +static int gen_init_phy(int phy_addr) +{ + int ret = 1; + + if (gen_get_link_speed(phy_addr)) { + /* Try another time */ + ret = gen_get_link_speed(phy_addr); + } + + return(ret); +} + +static int gen_is_phy_connected(int phy_addr) +{ + u_int16_t dummy; + + return(dm644x_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy)); +} + +static int gen_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + + if (dm644x_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04)) + return(1); + + return(0); +} + +static int gen_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + + if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp |= PHY_BMCR_AUTON; + dm644x_eth_phy_write(phy_addr, PHY_BMCR, tmp); + + /*check AutoNegotiate complete */ + udelay (10000); + if (!dm644x_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) + return(0); + + if (!(tmp & PHY_BMSR_AUTN_COMP)) + return(0); + + return(gen_get_link_speed(phy_addr)); +} +/* End of generic PHY functions */ + + + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +static int dm644x_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value) +{ + return(dm644x_eth_phy_read(addr, reg, value) ? 0 : 1); +} + +static int dm644x_mii_phy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value) +{ + return(dm644x_eth_phy_write(addr, reg, value) ? 0 : 1); +} + +int dm644x_eth_miiphy_initialize(bd_t *bis) +{ + miiphy_register(phy.name, dm644x_mii_phy_read, dm644x_mii_phy_write); + + return(1); +} +#endif + +/* + * This function initializes the emac hardware. It does NOT initialize + * EMAC modules power or pin multiplexors, that is done by board_init() + * much earlier in bootup process. Returns 1 on success, 0 otherwise. + */ +static int dm644x_eth_hw_init(void) +{ + u_int32_t phy_id; + u_int16_t tmp; + int i; + + dm644x_eth_mdio_enable(); + + for (i = 0; i < 256; i++) { + if (adap_mdio->ALIVE) + break; + udelay(10); + } + + if (i >= 256) { + printf("No ETH PHY detected!!!\n"); + return(0); + } + + /* Find if a PHY is connected and get it's address */ + if (!dm644x_eth_phy_detect()) + return(0); + + /* Get PHY ID and initialize phy_ops for a detected PHY */ + if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id = (tmp << 16) & 0xffff0000; + + if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id |= tmp & 0x0000ffff; + + switch (phy_id) { + case PHY_LXT972: + sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); + phy.init = lxt972_init_phy; + phy.is_phy_connected = lxt972_is_phy_connected; + phy.get_link_speed = lxt972_get_link_speed; + phy.auto_negotiate = lxt972_auto_negotiate; + break; + case PHY_DP83848: + sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); + phy.init = dp83848_init_phy; + phy.is_phy_connected = dp83848_is_phy_connected; + phy.get_link_speed = dp83848_get_link_speed; + phy.auto_negotiate = dp83848_auto_negotiate; + break; + default: + sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); + phy.init = gen_init_phy; + phy.is_phy_connected = gen_is_phy_connected; + phy.get_link_speed = gen_get_link_speed; + phy.auto_negotiate = gen_auto_negotiate; + } + + return(1); +} + + +/* Eth device open */ +static int dm644x_eth_open(void) +{ + dv_reg_p addr; + u_int32_t clkdiv, cnt; + volatile emac_desc *rx_desc; + + debug_emac("+ emac_open\n"); + + /* Reset EMAC module and disable interrupts in wrapper */ + adap_emac->SOFTRESET = 1; + while (adap_emac->SOFTRESET != 0) {;} + adap_ewrap->EWCTL = 0; + for (cnt = 0; cnt < 5; cnt++) { + clkdiv = adap_ewrap->EWCTL; + } + + rx_desc = emac_rx_desc; + + adap_emac->TXCONTROL = 0x01; + adap_emac->RXCONTROL = 0x01; + + /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ + /* Using channel 0 only - other channels are disabled */ + adap_emac->MACINDEX = 0; + adap_emac->MACADDRHI = + (dm644x_eth_mac_addr[3] << 24) | + (dm644x_eth_mac_addr[2] << 16) | + (dm644x_eth_mac_addr[1] << 8) | + (dm644x_eth_mac_addr[0]); + adap_emac->MACADDRLO = + (dm644x_eth_mac_addr[5] << 8) | + (dm644x_eth_mac_addr[4]); + + adap_emac->MACHASH1 = 0; + adap_emac->MACHASH2 = 0; + + /* Set source MAC address - REQUIRED */ + adap_emac->MACSRCADDRHI = + (dm644x_eth_mac_addr[3] << 24) | + (dm644x_eth_mac_addr[2] << 16) | + (dm644x_eth_mac_addr[1] << 8) | + (dm644x_eth_mac_addr[0]); + adap_emac->MACSRCADDRLO = + (dm644x_eth_mac_addr[4] << 8) | + (dm644x_eth_mac_addr[5]); + + /* Set DMA 8 TX / 8 RX Head pointers to 0 */ + addr = &adap_emac->TX0HDP; + for(cnt = 0; cnt < 16; cnt++) + *addr++ = 0; + + addr = &adap_emac->RX0HDP; + for(cnt = 0; cnt < 16; cnt++) + *addr++ = 0; + + /* Clear Statistics (do this before setting MacControl register) */ + addr = &adap_emac->RXGOODFRAMES; + for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) + *addr++ = 0; + + /* No multicast addressing */ + adap_emac->MACHASH1 = 0; + adap_emac->MACHASH2 = 0; + + /* Create RX queue and set receive process in place */ + emac_rx_active_head = emac_rx_desc; + for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { + rx_desc->next = (u_int32_t)(rx_desc + 1); + rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_desc++; + } + + /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */ + rx_desc--; + rx_desc->next = 0; + emac_rx_active_tail = rx_desc; + emac_rx_queue_active = 1; + + /* Enable TX/RX */ + adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE; + adap_emac->RXBUFFEROFFSET = 0; + + /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */ + adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN; + + /* Enable ch 0 only */ + adap_emac->RXUNICASTSET = 0x01; + + /* Enable MII interface and Full duplex mode */ + adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE); + + /* Init MDIO & get link state */ + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT); + + if (!phy.get_link_speed(active_phy_addr)) + return(0); + + /* Start receive process */ + adap_emac->RX0HDP = (u_int32_t)emac_rx_desc; + + debug_emac("- emac_open\n"); + + return(1); +} + +/* EMAC Channel Teardown */ +static void dm644x_eth_ch_teardown(int ch) +{ + dv_reg dly = 0xff; + dv_reg cnt; + + debug_emac("+ emac_ch_teardown\n"); + + if (ch == EMAC_CH_TX) { + /* Init TX channel teardown */ + adap_emac->TXTEARDOWN = 1; + for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) { + /* Wait here for Tx teardown completion interrupt to occur + * Note: A task delay can be called here to pend rather than + * occupying CPU cycles - anyway it has been found that teardown + * takes very few cpu cycles and does not affect functionality */ + dly--; + udelay(1); + if (dly == 0) + break; + } + adap_emac->TX0CP = cnt; + adap_emac->TX0HDP = 0; + } else { + /* Init RX channel teardown */ + adap_emac->RXTEARDOWN = 1; + for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) { + /* Wait here for Rx teardown completion interrupt to occur + * Note: A task delay can be called here to pend rather than + * occupying CPU cycles - anyway it has been found that teardown + * takes very few cpu cycles and does not affect functionality */ + dly--; + udelay(1); + if (dly == 0) + break; + } + adap_emac->RX0CP = cnt; + adap_emac->RX0HDP = 0; + } + + debug_emac("- emac_ch_teardown\n"); +} + +/* Eth device close */ +static int dm644x_eth_close(void) +{ + debug_emac("+ emac_close\n"); + + dm644x_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ + dm644x_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ + + /* Reset EMAC module and disable interrupts in wrapper */ + adap_emac->SOFTRESET = 1; + adap_ewrap->EWCTL = 0; + + debug_emac("- emac_close\n"); + return(1); +} + +static int tx_send_loop = 0; + +/* + * This function sends a single packet on the network and returns + * positive number (number of bytes transmitted) or negative for error + */ +static int dm644x_eth_send_packet(volatile void *packet, int length) +{ + int ret_status = -1; + tx_send_loop = 0; + + /* Return error if no link */ + if (!phy.get_link_speed(active_phy_addr)) + { + printf("WARN: emac_send_packet: No link\n"); + return (ret_status); + } + + /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ + if (length < EMAC_MIN_ETHERNET_PKT_SIZE) + { + length = EMAC_MIN_ETHERNET_PKT_SIZE; + } + + /* Populate the TX descriptor */ + emac_tx_desc->next = 0; + emac_tx_desc->buffer = (u_int8_t *)packet; + emac_tx_desc->buff_off_len = (length & 0xffff); + emac_tx_desc->pkt_flag_len = ((length & 0xffff) | + EMAC_CPPI_SOP_BIT | + EMAC_CPPI_OWNERSHIP_BIT | + EMAC_CPPI_EOP_BIT); + /* Send the packet */ + adap_emac->TX0HDP = (unsigned int)emac_tx_desc; + + /* Wait for packet to complete or link down */ + while (1) { + if (!phy.get_link_speed(active_phy_addr)) { + dm644x_eth_ch_teardown(EMAC_CH_TX); + return (ret_status); + } + if (adap_emac->TXINTSTATRAW & 0x01) { + ret_status = length; + break; + } + tx_send_loop++; + } + + return(ret_status); +} + +/* + * This function handles receipt of a packet from the network + */ +static int dm644x_eth_rcv_packet(void) +{ + volatile emac_desc *rx_curr_desc; + volatile emac_desc *curr_desc; + volatile emac_desc *tail_desc; + int status, ret = -1; + + rx_curr_desc = emac_rx_active_head; + status = rx_curr_desc->pkt_flag_len; + if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { + if (status & EMAC_CPPI_RX_ERROR_FRAME) { + /* Error in packet - discard it and requeue desc */ + printf("WARN: emac_rcv_pkt: Error in packet\n"); + } else { + NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff)); + ret = rx_curr_desc->buff_off_len & 0xffff; + } + + /* Ack received packet descriptor */ + adap_emac->RX0CP = (unsigned int)rx_curr_desc; + curr_desc = rx_curr_desc; + emac_rx_active_head = (volatile emac_desc *)rx_curr_desc->next; + + if (status & EMAC_CPPI_EOQ_BIT) { + if (emac_rx_active_head) { + adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + } else { + emac_rx_queue_active = 0; + printf("INFO:emac_rcv_packet: RX Queue not active\n"); + } + } + + /* Recycle RX descriptor */ + rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_curr_desc->next = 0; + + if (emac_rx_active_head == 0) { + printf("INFO: emac_rcv_pkt: active queue head = 0\n"); + emac_rx_active_head = curr_desc; + emac_rx_active_tail = curr_desc; + if (emac_rx_queue_active != 0) { + adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); + emac_rx_queue_active = 1; + } + } else { + tail_desc = emac_rx_active_tail; + emac_rx_active_tail = curr_desc; + tail_desc->next = (unsigned int)curr_desc; + status = tail_desc->pkt_flag_len; + if (status & EMAC_CPPI_EOQ_BIT) { + adap_emac->RX0HDP = (unsigned int)curr_desc; + status &= ~EMAC_CPPI_EOQ_BIT; + tail_desc->pkt_flag_len = status; + } + } + return(ret); + } + return(0); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_TI_EMAC */ diff -purN u-boot.git.orig/cpu/arm926ejs/davinci/i2c.c u-boot.git/cpu/arm926ejs/davinci/i2c.c --- u-boot.git.orig/cpu/arm926ejs/davinci/i2c.c 1969-12-31 16:00:00.000000000 -0800 +++ u-boot.git/cpu/arm926ejs/davinci/i2c.c 2007-08-07 10:15:34.000000000 -0700 @@ -0,0 +1,351 @@ +/* + * TI DaVinci (TMS320DM644x) I2C driver. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#ifdef CONFIG_DRIVER_DAVINCI_I2C + +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/i2c_defs.h> + +#define CHECK_NACK() \ + do {\ + if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ + REG(I2C_CON) = 0;\ + return(1);\ + }\ + } while (0) + + +static int wait_for_bus(void) +{ + int stat, timeout; + + REG(I2C_STAT) = 0xffff; + + for (timeout = 0; timeout < 10; timeout++) { + if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { + REG(I2C_STAT) = 0xffff; + return(0); + } + + REG(I2C_STAT) = stat; + udelay(50000); + } + + REG(I2C_STAT) = 0xffff; + return(1); +} + + +static int poll_i2c_irq(int mask) +{ + int stat, timeout; + + for (timeout = 0; timeout < 10; timeout++) { + udelay(1000); + stat = REG(I2C_STAT); + if (stat & mask) { + return(stat); + } + } + + REG(I2C_STAT) = 0xffff; + return(stat | I2C_TIMEOUT); +} + + +void flush_rx(void) +{ + int dummy; + + while (1) { + if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) + break; + + dummy = REG(I2C_DRR); + REG(I2C_STAT) = I2C_STAT_RRDY; + udelay(1000); + } +} + + +void i2c_init(int speed, int slaveadd) +{ + u_int32_t div, psc; + + if (REG(I2C_CON) & I2C_CON_EN) { + REG(I2C_CON) = 0; + udelay (50000); + } + + psc = 2; + div = (CFG_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ + REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ + REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ + REG(I2C_SCLH) = div - REG(I2C_SCLL); + + REG(I2C_OA) = slaveadd; + REG(I2C_CNT) = 0; + + /* Interrupts must be enabled or I2C module won't work */ + REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | + I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; + + /* Now enable I2C controller (get it out of reset) */ + REG(I2C_CON) = I2C_CON_EN; + + udelay(1000); +} + + +int i2c_probe(u_int8_t chip) +{ + int rc = 1; + + if (chip == REG(I2C_OA)) { + return(rc); + } + + REG(I2C_CON) = 0; + if (wait_for_bus()) {return(1);} + + /* try to read one byte from current (or only) address */ + REG(I2C_CNT) = 1; + REG(I2C_SA) = chip; + REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP); + udelay (50000); + + if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { + rc = 0; + flush_rx(); + REG(I2C_STAT) = 0xffff; + } else { + REG(I2C_STAT) = 0xffff; + REG(I2C_CON) |= I2C_CON_STP; + udelay(20000); + if (wait_for_bus()) {return(1);} + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + return(rc); +} + + +int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +{ + u_int32_t tmp; + int i; + + if ((alen < 0) || (alen > 2)) { + printf("%s(): bogus address length %x\n", __FUNCTION__, alen); + return(1); + } + + if (wait_for_bus()) {return(1);} + + if (alen != 0) { + /* Start address phase */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; + REG(I2C_CNT) = alen; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + switch (alen) { + case 2: + /* Send address MSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = (addr >> 8) & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + /* No break, fall through */ + case 1: + /* Send address LSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = addr & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_ARDY)) { + REG(I2C_CON) = 0; + return(1); + } + } + } + + /* Address phase is over, now read 'len' bytes and stop */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; + REG(I2C_CNT) = len & 0xffff; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + for (i = 0; i < len; i++) { + tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); + + CHECK_NACK(); + + if (tmp & I2C_STAT_RRDY) { + buf[i] = REG(I2C_DRR); + } else { + REG(I2C_CON) = 0; + return(1); + } + } + + tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_SCD)) { + REG(I2C_CON) = 0; + return(1); + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + REG(I2C_CON) = 0; + + return(0); +} + + +int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +{ + u_int32_t tmp; + int i; + + if ((alen < 0) || (alen > 2)) { + printf("%s(): bogus address length %x\n", __FUNCTION__, alen); + return(1); + } + if (len < 0) { + printf("%s(): bogus length %x\n", __FUNCTION__, len); + return(1); + } + + if (wait_for_bus()) {return(1);} + + /* Start address phase */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; + REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + switch (alen) { + case 2: + /* Send address MSByte */ + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = (addr >> 8) & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + /* No break, fall through */ + case 1: + /* Send address LSByte */ + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = addr & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + } + + for (i = 0; i < len; i++) { + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = buf[i]; + } else { + return(1); + } + } + + tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_SCD)) { + REG(I2C_CON) = 0; + return(1); + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + REG(I2C_CON) = 0; + + return(0); +} + + +u_int8_t i2c_reg_read(u_int8_t chip, u_int8_t reg) +{ + u_int8_t tmp; + + i2c_read(chip, reg, 1, &tmp, 1); + return(tmp); +} + + +void i2c_reg_write(u_int8_t chip, u_int8_t reg, u_int8_t val) +{ + u_int8_t tmp; + + i2c_write(chip, reg, 1, &tmp, 1); +} + +#endif /* CONFIG_DRIVER_DAVINCI_I2C */ diff -purN u-boot.git.orig/cpu/arm926ejs/davinci/Makefile u-boot.git/cpu/arm926ejs/davinci/Makefile --- u-boot.git.orig/cpu/arm926ejs/davinci/Makefile 1969-12-31 16:00:00.000000000 -0800 +++ u-boot.git/cpu/arm926ejs/davinci/Makefile 2007-08-07 10:15:34.000000000 -0700 @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o ether.o lxt972.o dp83848.o i2c.o nand.o +SOBJS = lowlevel_init.o reset.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -purN u-boot.git.orig/CREDITS u-boot.git/CREDITS --- u-boot.git.orig/CREDITS 2007-04-04 12:28:34.000000000 -0700 +++ u-boot.git/CREDITS 2007-08-07 10:15:34.000000000 -0700 @@ -252,6 +252,10 @@ E: Raghu.Krishnaprasad(a)fci.com D: Support for Adder-II MPC852T evaluation board W: http://www.forcecomputers.com +N: Sergey Kubushyn +E: ksi(a)koi8.net +D: Support for various TI DaVinci based boards. + N: Bernhard Kuhn E: bkuhn(a)metrowerks.com D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards diff -purN u-boot.git.orig/lib_arm/board.c u-boot.git/lib_arm/board.c --- u-boot.git.orig/lib_arm/board.c 2007-08-06 18:05:59.000000000 -0700 +++ u-boot.git/lib_arm/board.c 2007-08-07 10:15:34.000000000 -0700 @@ -364,6 +364,13 @@ void start_armboot (void) enable_interrupts (); /* Perform network card initialisation if necessary */ +#ifdef CONFIG_DRIVER_TI_EMAC +extern void dm644x_eth_set_mac_addr (const u_int8_t *addr); + if (getenv ("ethaddr")) { + dm644x_eth_set_mac_addr(gd->bd->bi_enetaddr); + } +#endif + #ifdef CONFIG_DRIVER_CS8900 cs8900_get_enetaddr (gd->bd->bi_enetaddr); #endif diff -purN u-boot.git.orig/MAINTAINERS u-boot.git/MAINTAINERS --- u-boot.git.orig/MAINTAINERS 2007-08-04 22:07:13.000000000 -0700 +++ u-boot.git/MAINTAINERS 2007-08-07 10:15:34.000000000 -0700 @@ -444,6 +444,12 @@ Nishant Kamat <nskamat(a)ti.com> omap1610h2 ARM926EJS +Sergey Kubushyn <ksi(a)koi8.net> + + DV-EVM ARM926EJS + SONATA ARM926EJS + SCHMOOGIE ARM926EJS + Prakash Kumar <prakash(a)embedx.com> cerf250 xscale diff -purN u-boot.git.orig/MAKEALL u-boot.git/MAKEALL --- u-boot.git.orig/MAKEALL 2007-08-06 18:05:59.000000000 -0700 +++ u-boot.git/MAKEALL 2007-08-07 10:15:34.000000000 -0700 @@ -220,7 +220,8 @@ LIST_ARM9=" \ omap1610h2 omap1610inn omap730p2 sbc2410x \ scb9328 smdk2400 smdk2410 trab \ VCMA9 versatile versatileab versatilepb \ - voiceblue \ + voiceblue davinci_dvevm davinci_schmoogie \ + davinci_sonata " ######################################################################### diff -purN u-boot.git.orig/Makefile u-boot.git/Makefile --- u-boot.git.orig/Makefile 2007-08-06 18:05:59.000000000 -0700 +++ u-boot.git/Makefile 2007-08-07 10:15:34.000000000 -0700 @@ -2019,6 +2019,15 @@ omap1510inn_config : unconfig omap5912osk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap +davinci_dvevm_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs dv-evm davinci davinci + +davinci_schmoogie_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci + +davinci_sonata_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci + omap1610inn_config \ omap1610inn_cs0boot_config \ omap1610inn_cs3boot_config \ diff -purN u-boot.git.orig/net/eth.c u-boot.git/net/eth.c --- u-boot.git.orig/net/eth.c 2007-08-06 18:05:59.000000000 -0700 +++ u-boot.git/net/eth.c 2007-08-07 10:15:34.000000000 -0700 @@ -464,6 +464,8 @@ extern int at91rm9200_miiphy_initialize( extern int emac4xx_miiphy_initialize(bd_t *bis); extern int mcf52x2_miiphy_initialize(bd_t *bis); extern int ns7520_miiphy_initialize(bd_t *bis); +extern int dm644x_eth_miiphy_initialize(bd_t *bis); + int eth_initialize(bd_t *bis) { @@ -484,6 +486,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_NETARM) ns7520_miiphy_initialize(bis); #endif +#if defined(CONFIG_DRIVER_TI_EMAC) + dm644x_eth_miiphy_initialize(bis); +#endif return 0; } #endif

5 9

[U-Boot-Users] [ARM] TI DaVinci support, hopefully final [0/5]
by ksi＠koi8.net 10 Aug '07

10 Aug '07

Here it is. Changes: - Fixed CONFIG_CMD_NET in net files. - Fixed CONFIG_CMD_EEPROM for schmoogie. - Made sure it compiles and works (forceenv() link problem) on SCHMOOGIE and DV_EVM. Can't check if it works on SONATA, don't have a board any more, but it at least compiles. I'm sending patches in two forms -- inline (set of 5 patches) _AND_ as a set of 2 GZIP files. Those should survive _ANY_ reformatting by various MUAs. Hopefully it is the final attempt... Here is an excerpt from session log on SCHMOOGIE... === Cut === U-Boot 1.2.0-g6c33c785-dirty (Aug 7 2007 - 13:07:17) DRAM: 128 MB NAND: 128 MiB In: serial Out: serial Err: serial ARM Clock : 297MHz DDR Clock : 162MHz ETH PHY : DP83848 @ 0x01 U-Boot > iprobe Valid chip addresses: 1B 38 3A 3D 3F 50 5D 6F U-Boot > ping 192.168.253.10 host 192.168.253.10 is alive U-Boot > === Cut === --- ****************************************************************** * KSI@home KOI8 Net < > The impossible we do immediately. * * Las Vegas NV, USA < > Miracles require 24-hour notice. * ******************************************************************

6 8

[U-Boot-Users] [PATCH] 8641hpcn: Do correct sized pointer math.
by Jon Loeliger 10 Aug '07

10 Aug '07

When I rebased Ed's patch and cleaned up a few compilation problems, I apparently rebased my brain on crack first. Fix that by doing (char *) sized pointer math as needed. Signed-off-by: Jon Loeliger <jdl(a)freescale.com> --- board/mpc8641hpcn/mpc8641hpcn.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index d2182ab..bdb834b 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -268,8 +268,8 @@ void pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((unsigned *) CFG_PCI1_MEM_BASE - + CFG_PCI1_MEM_SIZE - 0x1000000); + in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE + + CFG_PCI1_MEM_SIZE - 0x1000000)); } else { puts("PCI-EXPRESS 1: Disabled\n"); -- 1.5.0.3

2 2

[U-Boot-Users] CONFIG_OF_FLAT_TREE in MPC8548CDS.h
by robert lazarski 10 Aug '07

10 Aug '07

Hi all, Since CONFIG_OF_FLAT_TREE "is The Old Way" and CONFIG_OF_LIBFDT is "The New Way" - what's going to be the planned Way for MPC8548CDS in the upcoming release? Mainline currently shows CONFIG_OF_FLAT_TREE - is that ok ? Thanks, Robert

2 1

[U-Boot-Users] USB custodian repo updates
by Markus Klotzbücher 10 Aug '07

10 Aug '07

Dear List, The following changes since commit 09444143670c9c2243cb7aba9f70b3713d33bed1: Markus Klotzbuecher (1): Change duplicate usb_cpu_init_fail to usb_board_init_fail are found in the git repository at: git://www.denx.de/git/u-boot-usb.git Markus Klotzbuecher (4): USB/OHCI: endianness cleanup in the generic ohci driver USB: ohci fixes and cleanup for mpc5xxx and IceCube board config USB: ohci fixes and cleanup for ppc4xx and yosemite board. TRAB, USB: update trab board configuration for use of generic ohci driver Rodolfo Giometti (2): ISP116x: delay for crappy USB keys Files include/linux/byteorder/{big,little}_endian.h define Zhang Wei (3): USB event poll support USB PCI-OHCI, interrupt pipe and usb event poll support Add USB PCI-OHCI, USB keyboard and event poll support to the README | 3 + common/usb_kbd.c | 6 +- cpu/mpc5xxx/usb.c | 54 ++++++ cpu/ppc4xx/Makefile | 2 +- cpu/ppc4xx/usb.c | 50 ++++++ doc/README.generic_usb_ohci | 49 ++++-- drivers/isp116x-hcd.c | 1 + drivers/usb_ohci.c | 386 ++++++++++++++++++++++++++++++----------- drivers/usb_ohci.h | 12 +- drivers/usbtty.c | 6 +- include/configs/IceCube.h | 9 +- include/configs/MPC8641HPCN.h | 13 ++ include/configs/trab.h | 3 +- include/configs/yosemite.h | 1 + include/usb.h | 1 + 15 files changed, 462 insertions(+), 134 deletions(-) create mode 100644 cpu/mpc5xxx/usb.c create mode 100644 cpu/ppc4xx/usb.c This also contains a big endianness cleanup which introduces two new config options: CFG_OHCI_BE_CONTROLLER: The ohci controller is big endian CFG_OHCI_SWAP_REG_ACCESS: For PCI, do byte swapping for register accesses. I successfully tested these changes on arm (trab board), ppc4xx (yosemite) and mpc5xxx (lite5200b). If no problems show up, i'll ask Wolfgang to pull in about two weeks (this time really). Viele Grüße / Best regards Markus Klotzbücher -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de

4 5

[U-Boot-Users] [PATCH] m68k fix for Ethernet Buffers at address 0
by Wilson Callan 10 Aug '07

10 Aug '07

Hi, Attached is a patch that fixes a problem i saw with a coldfire 5235 port. i'll include the patch here in the email as well since it describes the problem: diff -purN u-boot-1.1.6/lib_m68k/board.c u-boot-1.1.6-pktfix/lib_m68k/ board.c --- u-boot-1.1.6/lib_m68k/board.c 2006-11-02 09:15:01.000000000 -0500 +++ u-boot-1.1.6-pktfix/lib_m68k/board.c 2007-06-28 11:07:19.000000000 -0400 @@ -642,6 +642,22 @@ void board_init_r (gd_t *id, ulong dest_ #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) WATCHDOG_RESET(); + + /* init NetRxPackets here otherwise eth_init() will cause + * buffer descriptors to use 0 as their buffer and overwrite lower memory. + * NetLoop() does this properly later. + * Cannot remove eth_init() call because linux driver assumes this + * happened, for MAC Address to be loaded into microcontroller + */ + { + int i; + static uchar pkt[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN]; + uchar *tx = pkt + (PKTALIGN - 1); + tx -= (ulong) tx % PKTALIGN; + for (i = 0; i < PKTBUFSRX; i++) { + NetRxPackets[i] = tx + (i+1)*PKTSIZE_ALIGN; + } + } eth_init(bd); #endif

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[U-Boot-Users] [PATCH] fsl_pci_init cleanup.
by Jon Loeliger 10 Aug '07

10 Aug '07

From: Ed Swarthout <Ed.Swarthout(a)freescale.com> Do not enable normal errors created during probe (master abort, perr, and pcie Invalid Configuration access). Add CONFIG_PCI_NOSCAN board option to prevent bus scan. Signed-off-by: Ed Swarthout <Ed.Swarthout(a)freescale.com> Acked-by: Andy Fleming <afleming(a)freescale.com> --- drivers/fsl_pci_init.c | 46 ++++++++++++++----------------------------- include/asm-ppc/processor.h | 2 +- 2 files changed, 16 insertions(+), 32 deletions(-) diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1d1f6df..1084dc6 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -15,7 +15,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#define DEBUG + #include <common.h> #ifdef CONFIG_FSL_PCI_INIT @@ -93,7 +93,11 @@ fsl_pci_init(struct pci_controller *hose) hose->current_busno = hose->first_busno; pci->pedr = 0xffffffff; /* Clear any errors */ - pci->peer = 0xffffffff; /* Enable Error Interupts */ + pci->peer = ~0x20140; /* Enable All Error Interupts except + * - Master abort (pci) + * - Master PERR (pci) + * - ICCA (PCIe) + */ pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); @@ -108,7 +112,7 @@ fsl_pci_init(struct pci_controller *hose) if (!enabled) { debug("....PCIE link error. Skipping scan." - "LTSSM=0x%02x\n", temp16); + "LTSSM=0x%02x\n", ltssm); hose->last_busno = hose->first_busno; return; } @@ -118,61 +122,41 @@ fsl_pci_init(struct pci_controller *hose) #ifdef DEBUG pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); neg_link_w = (temp16 & 0x3f0 ) >> 4; - debug("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", + printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", ltssm, neg_link_w); #endif hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); - } else { -#if 0 -/* done in pci_hose_config_device() */ - pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); - temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, temp16); - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); -#endif } /* Call setup to allocate PCSRBAR window */ pciauto_setup_device(hose, dev, 1, hose->pci_mem, hose->pci_prefetch, hose->pci_io); - +#ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); if ( bridge ) { /* update limit regs and subordinate busno */ pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); } +#else + hose->last_busno = hose->current_busno; +#endif /* Clear all error indications */ - if (pci->pme_msg_det && pci->pme_msg_det != 0xffffffff) { - debug("pci_fsl_init: pme_msg_det@%x=%x. Clearing\n", - &pci->pme_msg_det, pci->pme_msg_det); - pci->pme_msg_det = 0xffffffff; - } - - if (pci->pedr) { - debug("pci_fsl_init: pedr@%x=%x. Clearing\n", - &pci->pedr, pci->pedr); - pci->pedr = 0xffffffff; - } + pci->pme_msg_det = 0xffffffff; + pci->pedr = 0xffffffff; pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); if (temp16) { - debug("pci_fsl_init: PCI_DSR@%x=%x. Clearing\n", - PCI_DSR, temp16); pci_hose_write_config_word(hose, dev, - PCI_DSR, 0xffff); + PCI_DSR, 0xffff); } pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); if (temp16) { - debug("pci_fsl_init: PCI_SEC_STATUS@%x=%x. Clearing\n", - PCI_SEC_STATUS, temp16); pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); } } diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index b806cc0..9be5a27 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -532,7 +532,7 @@ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCRO +#define MSSCR0 SPRN_MSSCR0 #endif #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR -- 1.5.0.3

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