July 2007 - U-Boot

[U-Boot-Users] [PATCH] suppress const casting warning in common/fpga.c
by eran.liberty＠gmail.com 03 Jul '07

03 Jul '07

suppress some compiler warnings regarding const implicit conversion removed dead code Signed-off-by: Eran Liberty <eran.liberty(a)gmail.com> Index: common/fpga.c =================================================================== --- common/fpga.c (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 69) +++ common/fpga.c (.../branches/exsw6000) (revision 69) @@ -64,7 +64,7 @@ /* fpga_no_sup * 'no support' message function */ -static void fpga_no_sup( char *fn, char *msg ) +static void fpga_no_sup (const char *fn, const char *msg) { if ( fn && msg ) { printf( "%s: No support for %s. CONFIG_FPGA defined as 0x%x.\n", @@ -207,10 +207,6 @@ memset( desc_table, 0, sizeof(desc_table)); PRINTF( "%s: CONFIG_FPGA = 0x%x\n", __FUNCTION__, CONFIG_FPGA ); -#if 0 - PRINTF( "%s: CFG_FPGA_XILINX = 0x%x\n", __FUNCTION__, CFG_FPGA_XILINX ); - PRINTF( "%s: CFG_FPGA_ALTERA = 0x%x\n", __FUNCTION__, CFG_FPGA_ALTERA ); -#endif } /* fpga_count

2 1

[U-Boot-Users] [PATCH 2/2] Adds Extricom EXSW6000 board
by eran.liberty＠gmail.com 03 Jul '07

03 Jul '07

Signed-off-by: Eran Liberty <eran.liberty(a)gmail.com> Index: board/extricom/exsw6000/fpga.c =================================================================== --- board/extricom/exsw6000/fpga.c (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/fpga.c (.../branches/exsw6000) (revision 69) @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom, eran.liberty(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/global_data.h> +#include "fpga.h" +#include <fpga.h> +#include <altera.h> +#include <stratixII.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CONF_MASK 0x0040 +#define DCLK_MASK 0x0080 + +int Exsw6000_stratixII_fpp_pre_fn (int cookie); +int Exsw6000_stratixII_fpp_config_fn (int assert_config, int flush, int cookie); +int Exsw6000_stratixII_fpp_status_fn (int cookie); +int Exsw6000_stratixII_fpp_done_fn (int cookie); +int Exsw6000_stratixII_fpp_clk_fn (int assert_clk, int flush, int cookie); +int Exsw6000_stratixII_fpp_data_fn (int assert_data, int flush, int cookie); +int Exsw6000_stratixII_fpp_abort_fn (int cookie); +int Exsw6000_stratixII_fpp_post_fn (int cookie); + +altera_board_specific_func fpp_func = { + Exsw6000_stratixII_fpp_pre_fn, + Exsw6000_stratixII_fpp_config_fn, + Exsw6000_stratixII_fpp_status_fn, + Exsw6000_stratixII_fpp_done_fn, + Exsw6000_stratixII_fpp_clk_fn, + Exsw6000_stratixII_fpp_data_fn, + Exsw6000_stratixII_fpp_abort_fn, + Exsw6000_stratixII_fpp_post_fn, +}; + +Altera_desc altera_desc_tab[] = { + { + Altera_StratixII, /* part type */ + fast_passive_parallel_security, /* interface type */ + 1, /* bytes of data part can accept */ + (void *)(&fpp_func), /* interface function table */ + 0L, /* base interface address */ + 0 /* implementation specific cookie */ + } +}; + +u16 data; + +static inline void setbit (int *addr, int bit, int val) +{ + *addr = ((*addr & ~(1 << (31 - bit))) | (val << (31 - bit))); +} + +static inline int getbit (int val, int bit) +{ + return ((val >> (31 - bit)) & 1); +} + +void exsw6000_fpga_init () +{ + /* 1. init fpga generic module */ + fpga_init (gd->reloc_off); + + /* 2. Create and add our FPGA modules */ + fpga_add (fpga_altera, &altera_desc_tab[0]); +} + +static void update (void); + +static void update () +{ + u16 *fpga_base = (u16 *) (CONFIG_FPGA_BASE); + *fpga_base = data; +} + +int Exsw6000_stratixII_fpp_pre_fn (int cookie) +{ + /* Enables TSEC2_RX[7:0] for use as general-purpose input */ + setbit (&(((immap_t *) CFG_IMMR)->im_gur.gpiocr), 7, 1); + + /* Disable Tsec2 */ + setbit (&(((immap_t *) CFG_IMMR)->im_gur.devdisr), 25, 1); + + data = 0; + + return FPGA_SUCCESS; +} + +int Exsw6000_stratixII_fpp_config_fn (int assert_config, int flush, int cookie) +{ + + if (assert_config) { + data |= CONF_MASK; + } else { + data &= ~CONF_MASK; + } + if (flush) { + update (); + } + return FPGA_SUCCESS; +} + +int Exsw6000_stratixII_fpp_status_fn (int cookie) +{ + return getbit (((immap_t *) CFG_IMMR)->im_gur.gpindr, 1); +} + +int Exsw6000_stratixII_fpp_done_fn (int cookie) +{ + return getbit (((immap_t *) CFG_IMMR)->im_gur.gpindr, 0); +} + +int Exsw6000_stratixII_fpp_clk_fn (int assert_clk, int flush, int cookie) +{ + if (assert_clk) { + data |= DCLK_MASK; + } else { + data &= ~DCLK_MASK; + } + if (flush) { + update (); + } + + return FPGA_SUCCESS; +} + +int Exsw6000_stratixII_fpp_data_fn (int new_data, int flush, int cookie) +{ + new_data = + ((new_data & 0x80) >> 7) | + ((new_data & 0x40) >> 5) | + ((new_data & 0x20) >> 3) | + ((new_data & 0x10) >> 1) | + ((new_data & 0x08) << 1) | + ((new_data & 0x04) << 3) | + ((new_data & 0x02) << 5) | + ((new_data & 0x01) << 7); + + data = (data & 0x00FF) | (new_data << 8 & 0xFF00); + + if (flush) { + update (); + } + + return FPGA_SUCCESS; +} + +int Exsw6000_stratixII_fpp_abort_fn (int cookie) +{ + return Exsw6000_stratixII_fpp_post_fn (cookie); +} + +int Exsw6000_stratixII_fpp_post_fn (int cookie) +{ + setbit (&(((immap_t *) CFG_IMMR)->im_gur.devdisr), 25, 0); + setbit (&(((immap_t *) CFG_IMMR)->im_gur.gpiocr), 7, 0); + return FPGA_SUCCESS; +} Index: board/extricom/exsw6000/ft_board.c =================================================================== --- board/extricom/exsw6000/ft_board.c (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/ft_board.c (.../branches/exsw6000) (revision 69) @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom, eran.liberty(a)gmail.com + * + * (C) Copyright 2004 + * Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> + +extern void ft_cpu_setup (void *blob, bd_t * bd); + +static void cds_pci_fixup (void *blob) +{ + int len; + u32 *map; + int slot; + int i; + + map = ft_get_prop (blob, "/" OF_SOC "/pci@8000/interrupt-map", &len); + + len /= sizeof (u32); + + slot = 1; + + for (i = 0; i < len; i += 7) { + /* We rotate the interrupt pins so that the mapping + * changes depending on the slot the carrier card is in. + */ + map[3] = ((map[3] + slot - 2) % 4) + 1; + + map += 7; + } +} +#endif + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup (void *blob, bd_t * bd) +{ + u32 *p; + int len; + +#ifdef CONFIG_PCI + ft_pci_setup (blob, bd); +#endif + ft_cpu_setup (blob, bd); + + p = ft_get_prop (blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32 (bd->bi_memstart); + *p = cpu_to_be32 (bd->bi_memsize); + } + + cds_pci_fixup (blob); +} +#endif Index: board/extricom/exsw6000/init.S =================================================================== --- board/extricom/exsw6000/init.S (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/init.S (.../branches/exsw6000) (revision 69) @@ -0,0 +1,260 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom, eran.liberty(a)gmail.com + * + * (C) Copyright 2004 + * Freescale Semiconductor. + * + * (C) Copyright 2002,2003 + * Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <config.h> +#include <mpc85xx.h> + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 14 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* FIXME: remove SDRAM */ + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M FPGA registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) + .long TLB1_MAS2(E500_TLB_EPN(CONFIG_FPGA_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CONFIG_FPGA_BASE), 0,0,0,0,0,1,0,1,0,1) + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) + +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) + +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ +#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long 6 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 + entry_end Index: board/extricom/exsw6000/u-boot.lds =================================================================== --- board/extricom/exsw6000/u-boot.lds (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/u-boot.lds (.../branches/exsw6000) (revision 69) @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom, eran.liberty(a)gmail.com + * + * (C) Copyright 2004 + * Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/extricom/exsw6000/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/extricom/exsw6000/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} Index: board/extricom/exsw6000/fpga.h =================================================================== --- board/extricom/exsw6000/fpga.h (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/fpga.h (.../branches/exsw6000) (revision 69) @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom, eran.liberty(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _EXSW6000_FPGA_H_ +#define _EXSW6000_FPGA_H_ + +void exsw6000_fpga_init (void); + +#endif /* _EXSW6000_FPGA_H_ */

1 0

[U-Boot-Users] [PATCH 1/2] Adds Extricom EXSW6000 board
by eran.liberty＠gmail.com 03 Jul '07

03 Jul '07

This patch adds Extricom EXSW6000 board, which is based on the Freescale 85xx core. due to size limit it is sagmented to two. on top of that, this patch is not complete without: Altera Stratix II, fpga loadi, and ndelay patches. Without them it will not compile. All three posted just before this post. Signed-off-by: Eran Liberty <eran.liberty(a)gmail.com> Index: CREDITS =================================================================== --- CREDITS (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 69) +++ CREDITS (.../branches/exsw6000) (revision 69) @@ -479,3 +479,8 @@ E: monstr(a)monstr.eu D: Support for Microblaze, ML401, XUPV2P board W: www.monstr.eu + +N: Eran Liberty +E: liberty(a)extricom.com +D: Support for Extricom, EXSW6000 board +W: www.extricom.com Index: include/configs/EXSW6000.h =================================================================== --- include/configs/EXSW6000.h (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ include/configs/EXSW6000.h (.../branches/exsw6000) (revision 69) @@ -0,0 +1,487 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom, eran.liberty(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 /* MPC8548 specific */ +#define CONFIG_EXSW6000 1 /* Extricom EXSW6000 (mega switch) board specific */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the CDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH +#define CONFIG_FORCE_FLASH_BANK_SIZE 0x800000 + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ + +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ + +#define CFG_BR0_PRELIM 0xff801001 +#define CFG_BR1_PRELIM 0xff001001 + +#define CFG_OR0_PRELIM 0xff806e65 +#define CFG_OR1_PRELIM 0xff806e65 + +#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ /* FIXME... understand y it makes a diffrernce to romove me */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (5000 << 10) /* 5MB Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8548@0" +#define OF_SOC "soc8548@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_85XX_PCI2 + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +#define CONFIG_FPGA (CFG_ALTERA_STRATIX_II) +#define CONFIG_MISC_INIT_R /* enable misc initialization including fpga */ +#define CONFIG_FPGA_BASE 0xF8000000 +#define CFG_BR3_PRELIM 0xf8001001 +#define CFG_OR3_PRELIM 0xfff00ff7 + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_FPGA \ + | CFG_CMD_MII ) +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (0x10 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * Reset Method + */ +#define CONFIG_RESET_RSCTR 1 + +#define CONFIG_BZIP2 1 + +#define CONFIG_LAST_STAGE_INIT + +/* + * Exteran Switch detection + */ +#undef CONFIG_EXSW0 /*8 */ +#undef CONFIG_EXSW1 /*9 */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#endif + +#define CONFIG_IPADDR ip_addr + +#define CONFIG_HOSTNAME exsw6000 +#define CONFIG_ROOTPATH nfs_root_fs_path +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP server_ip +#define CONFIG_GATEWAYIP gateway_ip +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=600000\0" \ + "ramdiskfile=ramfs.uboot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=exsw6000.btb\0" \ + "fpga_loadaddr=ff000000\0" \ + "fpga_dev=0\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ Index: Makefile =================================================================== --- Makefile (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 69) +++ Makefile (.../branches/exsw6000) (revision 69) @@ -1769,6 +1769,9 @@ MPC8548CDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds +EXSW6000_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx exsw6000 extricom + MPC8555CDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds Index: board/extricom/exsw6000/config.mk =================================================================== --- board/extricom/exsw6000/config.mk (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/config.mk (.../branches/exsw6000) (revision 69) @@ -0,0 +1,36 @@ +# (C) Copyright 2007 +# Eran Liberty, Extricom, eran.liberty(a)gmail.com. +# +# (C)Copyright 2004 +# Freescale Semiconductor. +# + +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Extricom EXSW6000 (codename Megaswitch) board +# + +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 +PLATFORM_CPPFLAGS += -DCONFIG_EXSW6000=1 Index: board/extricom/exsw6000/Makefile =================================================================== --- board/extricom/exsw6000/Makefile (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/Makefile (.../branches/exsw6000) (revision 69) @@ -0,0 +1,63 @@ +# (C) Copyright 2007 +# Eran Liberty, Extricom, eran.liberty(a)gmail.com +# +# (C) Copyright 2004 +# Freescale Semiconductor. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../../cds/common) +endif + +LIB = $(obj)lib$(BOARD).a + +# FIXME: look up eeprom & via and decide if they should stay or go +COBJS := $(BOARD).o \ + ft_board.o \ + fpga.o \ + +SOBJS := init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### Index: board/extricom/exsw6000/exsw6000.c =================================================================== --- board/extricom/exsw6000/exsw6000.c (.../tags/trunk/20070620_2_merge_to_exsw6000) (revision 0) +++ board/extricom/exsw6000/exsw6000.c (.../branches/exsw6000) (revision 69) @@ -0,0 +1,424 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom, eran.liberty(a)gmail.com + * + * (C) Copyright 2004 + * Freescale Semiconductor. + * + * (C) Copyright 2002 + * Scott McNutt <smcnutt(a)artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <spd.h> +#include <miiphy.h> +#include <../drivers/tsec.h> +#include "fpga.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc (unsigned int dram_size); +#endif + +extern long int spd_sdram (void); + +void local_bus_init (void); +void sdram_init (void); + +int board_early_init_f (void) +{ + /* 0. Add TLB1 entry for FPGA accesss */ + mtspr (MAS0, TLB1_MAS0 (1, 7, 0)); + mtspr (MAS1, TLB1_MAS1 (1, 1, 0, 0, BOOKE_PAGESZ_1K)); + mtspr (MAS2, + TLB1_MAS2 (E500_TLB_EPN (CONFIG_FPGA_BASE), 0, 0, 0, 1, 1, 0, 1, + 0)); + mtspr (MAS3, + TLB1_MAS3 (E500_TLB_RPN (CONFIG_FPGA_BASE), 0, 0, 0, 0, 0, 1, 0, + 1, 0, 1)); + __asm__ __volatile__ ("isync;msync;tlbwe;isync"); + return 0; +} + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ + uint pci1_speed = CONFIG_SYS_CLK_FREQ; + + printf ("Board: EXSW6000\n"); + printf (" PCI1: %d bit, %s MHz, %s\n", + (pci1_32) ? 32 : 64, + (pci1_speed == 33000000) ? "33" : + (pci1_speed == 66000000) ? "66" : "unknown", + pci1_clk_sel ? "sync" : "async"); + + /* + * Initialize local bus. + */ + local_bus_init (); + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + + return 0; +} + +long int initdram (int board_type) +{ + long dram_size = 0; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + puts ("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur = &immap->im_gur; + + gur->ddrdllcr = 0x81000000; + asm ("sync;isync;msync"); + udelay (200); + } +#endif + dram_size = spd_sdram (); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc (dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init (); + + puts (" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void local_bus_init (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + get_sys_info (&sysinfo); + clkdiv = (lbc->lcrr & 0x0f) * 2; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + gur->lbiuiplldcr1 = 0x00078080; + if (clkdiv == 16) { + gur->lbiuiplldcr0 = 0x7c0f1bf0; + } else if (clkdiv == 8) { + gur->lbiuiplldcr0 = 0x6c0f1bf0; + } else if (clkdiv == 4) { + gur->lbiuiplldcr0 = 0x5c0f1bf0; + } + + lbc->lcrr |= 0x00030000; + + asm ("sync;isync;msync"); +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void sdram_init (void) +{ +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + /* FIXME: remove clenaly */ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + lbc->lbcr = CFG_LBC_LBCR; + asm ("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm ("msync"); +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf ("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, CFG_MEMTEST_END); + + printf ("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. + */ +void dummy_func (struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *tab) +{ +} + +static struct pci_config_table pci_exsw6000_config_table[] = { + {0x1556, 0x5555, + PCI_ANY_ID, + 0, + 0xd, + 0, + dummy_func, + {0, 0, 0}}, +}; + +static struct pci_controller hose[] = { + {config_table:pci_exsw6000_config_table,}, +}; + +#endif /* CONFIG_PCI */ + +void pci_init_board (void) +{ +#ifdef CONFIG_PCI + pci_mpc85xx_init ((struct pci_controller *)(&hose)); +#endif +} + +extern int fpga_loadi (int devnum, void *buf); +extern int Exsw6000_stratixII_fpp_pre_fn (int cookie); +extern int Exsw6000_stratixII_fpp_done_fn (int cookie); +extern int Exsw6000_stratixII_fpp_post_fn (int cookie); + +int misc_init_r (void) +{ + char *s; + ulong addr; + int devnum; + int conf_done; + + exsw6000_fpga_init (); + + /* if we have an enviroment fpga_image_addr */ + if ((s = getenv ("fpga_loadaddr")) != NULL) { + addr = simple_strtoul (s, NULL, 16); + if ((s = getenv ("fpga_dev")) != NULL) { + devnum = simple_strtoul (s, NULL, 16); + + Exsw6000_stratixII_fpp_pre_fn (0); + conf_done = Exsw6000_stratixII_fpp_done_fn (0); + Exsw6000_stratixII_fpp_post_fn (0); + if (!conf_done) { + printf ("FPGA loading\n"); + fpga_loadi (devnum, (void *)(addr)); + + /* FIXME make pci work with no re-reset */ + + } else { + printf ("FPGA already loaded\n"); + } + } + } + return 0; +} + +DECLARE_GLOBAL_DATA_PTR; + +extern int tsec_initialize (bd_t *, int, char *); + +#define MDPHY_MASK 0x3FE0 + +int is_connected (int addr1, int addr2) +{ + u16 dev1_ed_save; + u16 data; + char *devname = "exsw6000\0"; + int retval; + u16 test_vals[] = { 0x00e1, 0x0161, 0x01A1 }; + int i; + int timeout; + + /* save current value */ + if (miiphy_read (devname, addr1, 4, &data) != 0) { + printf ("Error reading from addr1 4\n"); + return -1; + } + dev1_ed_save = data; + + printf ("Detecting External switch."); + retval = 0; + for (i = 0; i < sizeof (test_vals) / sizeof (test_vals[0]); i++) { + if (miiphy_write (devname, addr1, 4, test_vals[i]) != 0) { + printf ("Error writing to addr1 4\n"); + return -1; + } + if (miiphy_read (devname, addr1, 0, &data) != 0) { + printf ("Error reading from addr1 0\n"); + return -1; + } + data |= PHY_BMCR_RST_NEG; + if (miiphy_write (devname, addr1, 0, data) != 0) { + printf ("Error writing to addr1 0\n"); + return -1; + } + data = 0; + timeout = 100000; + while (miiphy_read (devname, addr1, 1, &data) == 0 && + (data & PHY_BMSR_AUTN_COMP) == 0 && timeout--) { + if ((timeout % 10000) == 0) + printf ("."); + } + if (timeout == 0 || miiphy_read (devname, addr1, 1, &data) != 0) { + printf ("!"); + retval = 1; + break; + } + if (miiphy_read (devname, addr2, 5, &data) != 0) { + printf ("Error reading from addr2 5\n"); + return -1; + } + if ((data & MDPHY_MASK) != (test_vals[i] & MDPHY_MASK)) { + retval = 1; + break; + } + } + + /* reset saved value */ + if (miiphy_write (devname, addr1, 4, dev1_ed_save) != 0) { + printf ("Error writing to addr1 4\n"); + return -1; + } + if (miiphy_read (devname, addr1, 0, &data) != 0) { + printf ("Error reading from addr1 0\n"); + return -1; + } + data |= PHY_BMCR_RST_NEG; + if (miiphy_write (devname, addr1, 0, data) != 0) { + printf ("Error writing to addr1 0\n"); + return -1; + } + data = 0; + while (data & PHY_BMSR_AUTN_COMP) { + if (miiphy_write (devname, addr1, 1, data) != 0) { + printf ("Error writing to addr1 0\n"); + return -1; + } + } + if (retval == 1) { + printf (" not found\n"); + } else { + printf (" found.\n"); + } + return retval; +} + +/* we steel tsec.c private structure in order to use its function functions */ +struct tsec_info_struct { + unsigned int phyaddr; + u32 flags; + unsigned int phyregidx; +}; +extern void write_phy_reg (struct tsec_private *priv, uint regnum, uint value); +extern uint read_phy_reg (struct tsec_private *priv, uint regnum); + +static int exsw6000_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + struct tsec_private priv; + priv.phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR); + priv.phyaddr = addr; + *value = (unsigned short)read_phy_reg (&priv, reg); + return 0; +} +static int exsw6000_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct tsec_private priv; + priv.phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR); + priv.phyaddr = addr; + write_phy_reg (&priv, reg, value); + return 0; +} + +int last_stage_init (void) +{ + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register ("exsw6000", exsw6000_miiphy_read, + exsw6000_miiphy_write); +#endif + +#if defined(CONFIG_EXSW0) && defined(CONFIG_EXSW1) + /* Try to detect loopback as switch indicators */ + if (is_connected (CONFIG_EXSW0, CONFIG_EXSW1) == 0) { + printf ("Extranl Switch detected\n"); + } else { + printf ("no extranal switch\n"); + } +#endif + return 0; +}

1 0

[U-Boot-Users] u-boot-testing merged
by Wolfgang Denk 03 Jul '07

03 Jul '07

Hi everybody, this is to let you know that I merged the u-boot-testing branch into main. Thanks everybody who contributed. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de The only person who always got his work done by Friday was Robinson Crusoe.

1 0

[U-Boot-Users] CFI support for flash with hardware write-protect.
by Edward Jubenville 03 Jul '07

03 Jul '07

We have a built a custom board with onboard flash and using CFI. Our design supports a jumper that enables hardware write-protection on the flash, but u-boot will not come up with the jumper installed. It fails due to code in drivers/cfi_flash.c that must write a command word to detect the flash configuration. Is there an elegant way to override the CFI discovery process, prefilling flash_info[] with the details of our flash hardware? Our board will boot if we hardcode our flash settings and bypass auto-detection, but I was wondering if somebody has a patch to cfi_flash.c to do it through configuration parameters. In case you are wondering, we cannot use software write-protect because our equipment must conform with a security directive from the U.S. Department of Defense, paraphrased: "There shall be no user-modifiable, non-removable, persistent storage." The onboard flash cannot be removed from the unit, and therefore may not be allowed to be written by an operator (e.g., by stopping in u-boot). Forcing somebody to disassemble the unit to switch a jumper is apparently acceptable to the security guys. Thanks, Ed Jubenville

2 1

[U-Boot-Users] You've received a greeting postcard from a school mate!
by E-Cards.Com 03 Jul '07

03 Jul '07

Good day. Your school mate has sent you a greeting postcard from E-Cards.Com. Send free ecards from E-Cards.Com with your choice of colors, words and music. Your ecard will be available with us for the next 30 days. If you wish to keep the ecard longer, you may save it on your computer or take a print. To view your ecard, choose from any of the following options: -------- OPTION 1 -------- Click on the following Internet address or copy & paste it into your browser's address box. http://68.116.218.203/?ee0c2a4c1c8a8aa50bb1c20bb5 -------- OPTION 2 -------- Copy & paste the ecard number in the "View Your Card" box at http://68.116.218.203/ Your ecard number is ee0c2a4c1c8a8aa50bb1c20bb5 Best wishes, Administrator, E-Cards.Com

1 0

[U-Boot-Users] [PATCH 2/3] Added USB PCI-OHCI chips support, interrupt pipe support and usb event poll support.
by Zhang Wei 03 Jul '07

03 Jul '07

This patch added USB PCI-OHCI chips support, interrupt pipe support and usb event poll support. For supporting the USB interrupt pipe, the globe urb_priv is moved to purb in ed struct. Now, we can process several urbs at one time. The interrupt pipe support codes are ported from Linux kernel 2.4. Signed-off-by: Zhang Wei <wei.zhang(a)freescale.com> --- drivers/usb_ohci.c | 310 +++++++++++++++++++++++++++++++++++++++++++--------- drivers/usb_ohci.h | 12 ++- 2 files changed, 267 insertions(+), 55 deletions(-) diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index 70cb6a3..459c809 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -1,5 +1,11 @@ /* - * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200. + * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. + * + * Interrupt support is added. Now, it has been tested + * on ULI1575 chip and works well with USB keyboard. + * + * (C) Copyright 2007 + * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang(a)freescale.com> * * (C) Copyright 2003 * Gary Jennejohn, DENX Software Engineering <gj(a)denx.de> @@ -35,7 +41,7 @@ * 1 - you MUST define LITTLEENDIAN in the configuration file for the * board or this driver will NOT work! * 2 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + * (BBB) and USB keyboard. There is NO support for Isochronous pipes! * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG * to activate workaround for bug #41 or this driver will NOT work! */ @@ -56,6 +62,8 @@ # include <asm/arch/pxa-regs.h> #elif defined(CONFIG_MPC5200) # include <mpc5xxx.h> +#elif defined(CONFIG_PCI_OHCI) +# include <pci.h> #endif #include <malloc.h> @@ -66,6 +74,7 @@ defined(CONFIG_S3C2400) || \ defined(CONFIG_S3C2410) || \ defined(CONFIG_440EP) || \ + defined(CONFIG_PCI_OHCI) || \ defined(CONFIG_MPC5200) # define OHCI_USE_NPS /* force NoPowerSwitching mode */ #endif @@ -79,12 +88,19 @@ #define OHCI_CONTROL_INIT \ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE -#define readl(a) (*((vu_long *)(a))) -#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) +#define readl(a) m32_swap(*((vu_long *)(a))) +#define writel(a, b) (*((vu_long *)(b)) = m32_swap((vu_long)a)) #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) -#undef DEBUG +#ifdef CONFIG_PCI_OHCI +static struct pci_device_id ohci_pci_ids[] = { + {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ + /* Please add supported PCI OHCI controller ids here */ + {0, 0} +}; +#endif + #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) #else @@ -114,15 +130,11 @@ struct ohci_hcca ghcca[1]; struct ohci_hcca *phcca; /* this allocates EDs for all possible endpoints */ struct ohci_device ohci_dev; -/* urb_priv */ -urb_priv_t urb_priv; /* RHSC flag */ int got_rhsc; /* device which was disconnected */ struct usb_device *devgone; -/* flag guarding URB transation */ -int urb_finished = 0; /*-------------------------------------------------------------------------*/ @@ -177,6 +189,7 @@ static void urb_free_priv (urb_priv_t * urb) } } } + free(urb); } /*-------------------------------------------------------------------------*/ @@ -187,11 +200,10 @@ static int sohci_get_current_frame_number (struct usb_device * dev); /* debug| print the main components of an URB * small: 0) header + data packets 1) just header */ -static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, +static void pkt_print (urb_priv_t *purb, struct usb_device * dev, + unsigned long pipe, void * buffer, int transfer_len, struct devrequest * setup, char * str, int small) { - urb_priv_t * purb = &urb_priv; - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", str, sohci_get_current_frame_number (dev), @@ -200,7 +212,7 @@ static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffe usb_pipeout (pipe)? 'O': 'I', usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): (usb_pipecontrol (pipe)? "CTRL": "BULK"), - purb->actual_length, + (purb ? purb->actual_length : 0), transfer_len, dev->status); #ifdef OHCI_VERBOSE_DEBUG if (!small) { @@ -214,10 +226,11 @@ static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffe } if (transfer_len > 0 && buffer) { printf (__FILE__ ": data(%d/%d):", - purb->actual_length, + (purb ? purb->actual_length : 0), transfer_len); len = usb_pipeout (pipe)? - transfer_len: purb->actual_length; + transfer_len: + (purb ? purb->actual_length : 0); for (i = 0; i < 16 && i < len; i++) printf (" %02x", ((__u8 *) buffer) [i]); printf ("%s\n", i < len? "...": ""); @@ -413,13 +426,17 @@ static void ohci_dump (ohci_t *controller, int verbose) /* get a transfer request */ -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) +int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) { ohci_t *ohci; ed_t * ed; - urb_priv_t *purb_priv; + urb_priv_t *purb_priv = urb; int i, size = 0; + struct usb_device *dev = urb->dev; + unsigned long pipe = urb->pipe; + void *buffer = urb->transfer_buffer; + int transfer_len = urb->transfer_buffer_length; + int interval = urb->interval; ohci = &gohci; @@ -430,18 +447,11 @@ int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, return -1; } - /* if we have an unfinished URB from previous transaction let's - * fail and scream as quickly as possible so as not to corrupt - * further communication */ - if (!urb_finished) { - err("sohci_submit_job: URB NOT FINISHED"); - return -1; - } /* we're about to begin a new transaction here so mark the URB unfinished */ - urb_finished = 0; + urb->finished = 0; /* every endpoint has a ed, locate and fill it */ - if (!(ed = ep_add_ed (dev, pipe))) { + if (!(ed = ep_add_ed (dev, pipe, interval, 1))) { err("sohci_submit_job: ENOMEM"); return -1; } @@ -455,13 +465,17 @@ int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, size = (transfer_len == 0)? 2: (transfer_len - 1) / 4096 + 3; break; + case PIPE_INTERRUPT: /* 1 TD */ + size = 1; + break; } + ed->purb = urb; + if (size >= (N_URB_TD - 1)) { err("need %d TDs, only have %d", size, N_URB_TD); return -1; } - purb_priv = &urb_priv; purb_priv->pipe = pipe; /* fill the private part of the URB */ @@ -497,6 +511,40 @@ int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, return 0; } +static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) +{ + struct ohci_regs *regs = hc->regs; + + switch (usb_pipetype (urb->pipe)) { + case PIPE_INTERRUPT: + /* implicitly requeued */ + if (urb->dev->irq_handle && + (urb->dev->irq_act_len = urb->actual_length)) { + writel (OHCI_INTR_WDH, &regs->intrenable); + readl (&regs->intrenable); /* PCI posting flush */ + urb->dev->irq_handle(urb->dev); + writel (OHCI_INTR_WDH, &regs->intrdisable); + readl (&regs->intrdisable); /* PCI posting flush */ + } + urb->actual_length = 0; + td_submit_job ( + urb->dev, + urb->pipe, + urb->transfer_buffer, + urb->transfer_buffer_length, + NULL, + urb, + urb->interval); + break; + case PIPE_CONTROL: + case PIPE_BULK: + break; + default: + return 0; + } + return 1; +} + /*-------------------------------------------------------------------------*/ #ifdef DEBUG @@ -514,13 +562,73 @@ static int sohci_get_current_frame_number (struct usb_device *usb_dev) * ED handling functions *-------------------------------------------------------------------------*/ +/* search for the right branch to insert an interrupt ed into the int tree + * do some load ballancing; + * returns the branch and + * sets the interval to interval = 2^integer (ld (interval)) */ + +static int ep_int_ballance (ohci_t * ohci, int interval, int load) +{ + int i, branch = 0; + + /* search for the least loaded interrupt endpoint + * branch of all 32 branches + */ + for (i = 0; i < 32; i++) + if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) + branch = i; + + branch = branch % interval; + for (i = branch; i < 32; i += interval) + ohci->ohci_int_load [i] += load; + + return branch; +} + +/*-------------------------------------------------------------------------*/ + +/* 2^int( ld (inter)) */ + +static int ep_2_n_interval (int inter) +{ + int i; + for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++); + return 1 << i; +} + +/*-------------------------------------------------------------------------*/ + +/* the int tree is a binary tree + * in order to process it sequentially the indexes of the branches have to be mapped + * the mapping reverses the bits of a word of num_bits length */ + +static int ep_rev (int num_bits, int word) +{ + int i, wout = 0; + + for (i = 0; i < num_bits; i++) + wout |= (((word >> i) & 1) << (num_bits - i - 1)); + return wout; +} + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + /* link an ed into one of the HC chains */ static int ep_link (ohci_t *ohci, ed_t *edi) { volatile ed_t *ed = edi; + int int_branch; + int i; + int inter; + int interval; + int load; + __u32 * ed_p; ed->state = ED_OPER; + ed->int_interval = 0; switch (ed->type) { case PIPE_CONTROL: @@ -554,12 +662,49 @@ static int ep_link (ohci_t *ohci, ed_t *edi) } ohci->ed_bulktail = edi; break; + + case PIPE_INTERRUPT: + load = ed->int_load; + interval = ep_2_n_interval (ed->int_period); + ed->int_interval = interval; + int_branch = ep_int_ballance (ohci, interval, load); + ed->int_branch = int_branch; + + for (i = 0; i < ep_rev (6, interval); i += inter) { + inter = 1; + for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]); + (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval); + ed_p = &(((ed_t *)ed_p)->hwNextED)) + inter = ep_rev (6, ((ed_t *)ed_p)->int_interval); + ed->hwNextED = *ed_p; + *ed_p = m32_swap(ed); + } + break; } return 0; } /*-------------------------------------------------------------------------*/ +/* scan the periodic table to find and unlink this ED */ +static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed, + unsigned index, unsigned period) +{ + for (; index < NUM_INTS; index += period) { + __u32 *ed_p = &ohci->hcca->int_table [index]; + + /* ED might have been unlinked through another path */ + while (*ed_p != 0) { + if (((struct ed *)m32_swap (ed_p)) == ed) { + *ed_p = ed->hwNextED; + break; + } + ed_p = & (((struct ed *)m32_swap (ed_p))->hwNextED); + } + } +} + + /* unlink an ed from one of the HC chains. * just the link to the ed is unlinked. * the link from the ed still points to another operational ed or 0 @@ -568,6 +713,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi) static int ep_unlink (ohci_t *ohci, ed_t *edi) { volatile ed_t *ed = edi; + int i; ed->hwINFO |= m32_swap (OHCI_ED_SKIP); @@ -605,6 +751,12 @@ static int ep_unlink (ohci_t *ohci, ed_t *edi) ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; } break; + + case PIPE_INTERRUPT: + periodic_unlink (ohci, ed, 0, 1); + for (i = ed->int_branch; i < 32; i += ed->int_interval) + ohci->ohci_int_load[i] -= ed->int_load; + break; } ed->state = ED_UNLINK; return 0; @@ -621,7 +773,8 @@ static int ep_unlink (ohci_t *ohci, ed_t *edi) * info fields are setted anyway even though most of them should not * change */ -static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) +static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe, + int interval, int load) { td_t *td; ed_t *ed_ret; @@ -654,6 +807,11 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) | usb_pipeslow (pipe) << 13 | usb_maxpacket (usb_dev, pipe) << 16); + if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { + ed->int_period = interval; + ed->int_load = load; + } + return ed_ret; } @@ -768,6 +926,13 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf if (!ohci->sleeping) writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ break; + + case PIPE_INTERRUPT: + info = usb_pipeout (urb->pipe)? + TD_CC | TD_DP_OUT | toggle: + TD_CC | TD_R | TD_DP_IN | toggle; + td_fill (ohci, info, data, data_len, dev, cnt++, urb); + break; } if (urb->length != cnt) dbg("TD LENGTH %d != CNT %d", urb->length, cnt); @@ -783,7 +948,7 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf static void dl_transfer_length(td_t * td) { __u32 tdINFO, tdBE, tdCBP; - urb_priv_t *lurb_priv = &urb_priv; + urb_priv_t *lurb_priv = td->ed->purb; tdINFO = m32_swap (td->hwINFO); tdBE = m32_swap (td->hwBE); @@ -820,7 +985,7 @@ static td_t * dl_reverse_done_list (ohci_t *ohci) td_list = (td_t *)td_list_hc; if (TD_CC_GET (m32_swap (td_list->hwINFO))) { - lurb_priv = &urb_priv; + lurb_priv = td_list->ed->purb; dbg(" USB-error/status: %x : %p", TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); if (td_list->ed->hwHeadP & m32_swap (0x1)) { @@ -860,10 +1025,10 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list) while (td_list) { td_list_next = td_list->next_dl_td; - lurb_priv = &urb_priv; tdINFO = m32_swap (td_list->hwINFO); ed = td_list->ed; + lurb_priv = ed->purb; dl_transfer_length(td_list); @@ -882,14 +1047,16 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list) (lurb_priv->state != URB_DEL)) #else if ((ed->state & (ED_OPER | ED_UNLINK))) - urb_finished = 1; +#endif + lurb_priv->finished = sohci_return_job(ohci, + lurb_priv); else dbg("dl_done_list: strange.., ED state %x, ed->state\n"); } else dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt, lurb_priv->length); -#endif - if (ed->state != ED_NEW) { + if (ed->state != ED_NEW && + (usb_pipetype (lurb_priv->pipe) != PIPE_INTERRUPT)) { edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; edTailP = m32_swap (ed->hwTailP); @@ -1063,8 +1230,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, __u16 wLength; #ifdef DEBUG -urb_priv.actual_length = 0; -pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); +pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); #else wait_ms(1); #endif @@ -1279,9 +1445,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); dev->status = stat; #ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); + pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); #else wait_ms(1); #endif @@ -1299,6 +1463,16 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int stat = 0; int maxsize = usb_maxpacket(dev, pipe); int timeout; + urb_priv_t *urb; + + urb = malloc(sizeof(urb_priv_t)); + memset(urb, 0, sizeof(urb_priv_t)); + + urb->dev = dev; + urb->pipe = pipe; + urb->transfer_buffer = buffer; + urb->transfer_buffer_length = transfer_len; + urb->interval = interval; /* device pulled? Shortcut the action. */ if (devgone == dev) { @@ -1307,8 +1481,8 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, } #ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); + urb->actual_length = 0; + pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); #else wait_ms(1); #endif @@ -1318,7 +1492,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, return -1; } - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { + if (sohci_submit_job(urb, setup) < 0) { err("sohci_submit_job failed"); return -1; } @@ -1353,18 +1527,20 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, * finished we need to re-iterate this loop so as * hc_interrupt() gets called again as there needs to be some * more TD's to process still */ - if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { + if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { /* 0xff is returned for an SF-interrupt */ break; } if (--timeout) { wait_ms(1); + if (!urb->finished) + dbg("\%"); + } else { err("CTL:TIMEOUT "); dbg("submit_common_msg: TO status %x\n", stat); - stat = USB_ST_CRC_ERR; - urb_finished = 1; + urb->finished = 1; stat = USB_ST_CRC_ERR; break; } @@ -1374,13 +1550,14 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, dev->act_len = transfer_len; #ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); + pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); #else wait_ms(1); #endif /* free TDs in urb_priv */ - urb_free_priv (&urb_priv); + if (usb_pipetype (pipe) != PIPE_INTERRUPT) + urb_free_priv (urb); return 0; } @@ -1399,8 +1576,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, info("submit_control_msg"); #ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); + pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); #else wait_ms(1); #endif @@ -1423,7 +1599,8 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval) { info("submit_int_msg"); - return -1; + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, + interval); } /*-------------------------------------------------------------------------* @@ -1537,6 +1714,12 @@ static int hc_start (ohci_t * ohci) /*-------------------------------------------------------------------------*/ +/* Poll USB interrupt. */ +void usb_event_poll(void) +{ + hc_interrupt(); +} + /* an interrupt happens */ static int hc_interrupt (void) @@ -1587,8 +1770,10 @@ static int hc_interrupt (void) if (ints & OHCI_INTR_WDH) { wait_ms(1); writel (OHCI_INTR_WDH, &regs->intrdisable); + (void)readl (&regs->intrdisable); /* flush */ stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); writel (OHCI_INTR_WDH, &regs->intrenable); + (void)readl (&regs->intrdisable); /* flush */ } if (ints & OHCI_INTR_SO) { @@ -1634,6 +1819,9 @@ static char ohci_inited = 0; int usb_lowlevel_init(void) { +#ifdef CONFIG_PCI_OHCI + pci_dev_t pdev; +#endif #ifdef CFG_USB_OHCI_CPU_INIT /* cpu dependant init */ @@ -1647,7 +1835,6 @@ int usb_lowlevel_init(void) return -1; #endif memset (&gohci, 0, sizeof (ohci_t)); - memset (&urb_priv, 0, sizeof (urb_priv_t)); /* align the storage */ if ((__u32)&ghcca[0] & 0xff) { @@ -1673,7 +1860,25 @@ int usb_lowlevel_init(void) gohci.disabled = 1; gohci.sleeping = 0; gohci.irq = -1; +#ifdef CONFIG_PCI_OHCI + pdev = pci_find_devices(ohci_pci_ids, 0); + + if (pdev != -1) { + u16 vid, did; + u32 base; + pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); + pci_read_config_word(pdev, PCI_DEVICE_ID, &did); + printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", + vid, did, (pdev >> 16) & 0xff, + (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); + printf("OHCI regs address 0x%08x\n", base); + gohci.regs = (struct ohci_regs *)base; + } else + return -1; +#else gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE; +#endif gohci.flags = 0; gohci.slot_name = CFG_USB_OHCI_SLOT_NAME; @@ -1716,7 +1921,6 @@ int usb_lowlevel_init(void) ohci_dump (&gohci, 1); #else wait_ms(1); - urb_finished = 1; #endif ohci_inited = 1; return 0; diff --git a/drivers/usb_ohci.h b/drivers/usb_ohci.h index 95fbc44..64fa614 100644 --- a/drivers/usb_ohci.h +++ b/drivers/usb_ohci.h @@ -64,7 +64,8 @@ struct ed { struct ed *ed_rm_list; struct usb_device *usb_dev; - __u32 unused[3]; + void *purb; + __u32 unused[2]; } __attribute((aligned(16))); typedef struct ed ed_t; @@ -349,9 +350,14 @@ typedef struct ed_t *ed; __u16 length; /* number of tds associated with this request */ __u16 td_cnt; /* number of tds already serviced */ + struct usb_device *dev; int state; unsigned long pipe; + void *transfer_buffer; + int transfer_buffer_length; + int interval; int actual_length; + int finished; td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ } urb_priv_t; #define URB_DEL 1 @@ -375,6 +381,7 @@ typedef struct ohci { struct ohci_regs *regs; /* OHCI controller's memory */ + int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/ ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ ed_t *ed_bulktail; /* last endpoint of bulk list */ ed_t *ed_controltail; /* last endpoint of control list */ @@ -397,7 +404,8 @@ struct ohci_device { /* endpoint */ static int ep_link(ohci_t * ohci, ed_t * ed); static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); +static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe, + int interval, int load); /*-------------------------------------------------------------------------*/ -- 1.5.1

5 16

[U-Boot-Users] Boot password
by Ori Idan 03 Jul '07

03 Jul '07

I am using a board similar to IXDP425 and would like a password for boot. I have defined CONFIG_AUTOBOOT_KEYED And also defined: CONFIG_AUTOBOOT_PROMPT and CONFIG_AUTOBOOT_DELAY_STR We got the CONFIG_AUTOBOOT_PROMPT but it sayed forever or until we typed the password. When compiling we got undefined reference to get_ticks and get_tbclk We copied these functions from cpu/arm925t/interrupts.c to cpu/ixp/interrupts.c What might have gone wrong? -- Ori Idan

3 3

[U-Boot-Users] u-boot fw_setenv does not write
by Victor Librado 03 Jul '07

03 Jul '07

u-boot environment tool fw_setenv does not work when writing the environment to flash. Working with at91sam9260ek running kernel 2.6.20. These are the traces: # ./fw_setenv bootdelay 4 Warning: Bad CRC, using default environment Unlocking flash... Done Erasing old environment... Done Writing environment to /dev/mtd1... CRC write error on /dev/mtd1: Invalid argument Error: can't write fw_env to flash Kernel printk: nand_write: Attempt to write not page aligned data In /etc/fw_env.config configuration: $ more fw_env.config # Configuration file for fw_(printenv/saveenv) utility. # Up to two entries are valid, in this case the redundand # environment sector is assumed present. # MTD device name Device offset Env. size Flash sector size /dev/mtd1 0x80000 0x20000 0x20000 Offset and environmet size as defined in myboard.h for u-boot compilation. I suppose flash sector size is the erase (block size). Any help please? Victor Librado Sancho Departamento I+D ------------------------------------------------------------------------

2 2

[U-Boot-Users] What is NAND sector size?
by arun c 03 Jul '07

03 Jul '07

Hi all, I am porting uboot to a new omap board. My nand details are given below page size=2111(2047+64) block size=64 pages total size=2047 blocks while going through the uboot configurations i met this NAND settings. #define SECTORSIZE 512 #define CFG_MAX_FLASH_SECT (259) Is this sector size=pagesize? In my case do i need to change this to 2048? And what is CFG_MAX_FLASH_SECT for my nand device? Regards Arun

1 0