May 2007 - U-Boot

[U-Boot-Users] Patch: Add USB OHCI support for MPC8220 - part 3
by TsiChung Liew 11 May '07

11 May '07

- USB Ohci support Regards, TsiChung Liew Signed-off by: TsiChung Liew<Tsi-Chung.Liew(a)freescale.com> diff -rupN u-boot-all.git/cpu/mpc8220/usb_ohci.h u-boot-all-8220- usbh/cpu/mpc8220/usb_ohci.h --- u-boot-all.git/cpu/mpc8220/usb_ohci.h 1969-12-31 18:00:00.000000000 -0600 +++ u-boot-all-8220-usbh/cpu/mpc8220/usb_ohci.h 2007-05-10 17:27:57.000000000 -0500 @@ -0,0 +1,410 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber <weissg(a)vienna.at> + * (C) Copyright 2000-2001 David Brownell <dbrownell(a)users.sourceforge.net> + * + * usb-ohci.h + */ + +static int cc_to_error[16] = { + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +/* ED States */ + +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + __u32 unused[3]; +} __attribute((aligned(16))); +typedef struct ed ed_t; + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u16 hwPSW[MAXPSW]; + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ +#if defined(CONFIG_MPC5200) + __u16 pad1; /* set to 0 on each frame_no change */ + __u16 frame_no; /* current frame number */ +#else + __u16 frame_no; /* current frame number */ + __u16 pad1; /* set to 0 on each frame_no change */ +#endif + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute((aligned(256))); + +/* + * Maximum number of root hub ports. + */ +#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[MAX_ROOT_PORTS]; + } roothub; +} __attribute((aligned(32))); + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status */ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct { + ed_t *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + int state; + unsigned long pipe; + int actual_length; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + +typedef struct ohci { + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma; */ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + struct ohci_regs *regs; /* OHCI controller's memory */ + + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +} ohci_t; + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* hcd */ +/* endpoint */ +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* +1 so we can align the storage */ +td_t gtd[NUM_TD + 1]; +/* pointers to aligned storage */ +td_t *ptd; + +/* TDs ... */ +static inline struct td *td_alloc(struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) { + if (ptd[i].usb_dev == NULL) { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + + return td; +} + +static inline void ed_free(struct ed *ed) +{ + ed->usb_dev = NULL; +}

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[U-Boot-Users] Patch: Add USB OHCI support for MPC8220 - part 2
by TsiChung Liew 11 May '07

11 May '07

- USB Ohci support Regards, TsiChung Liew Signed-off by: TsiChung Liew<Tsi-Chung.Liew(a)freescale.com> +/*-------------------------------------------------------------------------*/ + +/* td done list */ +static int dl_done_list(ohci_t * ohci, td_t * td_list) +{ + td_t *td_list_next = NULL; + ed_t *ed; + int cc = 0; + int stat = 0xff; + /* urb_t *urb; */ + urb_priv_t *lurb_priv; + __u32 tdINFO, edHeadP, edTailP; + + while (td_list) { + td_list_next = td_list->next_dl_td; + + lurb_priv = &urb_priv; + tdINFO = ohci_cpu_to_le32(td_list->hwINFO); + + ed = td_list->ed; + + dl_transfer_length(td_list); + + /* error code of transfer */ + cc = TD_CC_GET(tdINFO); + if (++(lurb_priv->td_cnt) == lurb_priv->length) { + if ((ed->state & (ED_OPER | ED_UNLINK)) + && (lurb_priv->state != URB_DEL)) { + dbg("ConditionCode %#x", cc); + stat = cc_to_error[cc]; + } + } + + if (ed->state != ED_NEW) { + edHeadP = ohci_cpu_to_le32(ed->hwHeadP) & 0xfffffff0; + edTailP = ohci_cpu_to_le32(ed->hwTailP); + + /* unlink eds if they are not busy */ + if ((edHeadP == edTailP) && (ed->state == ED_OPER)) + ep_unlink(ohci, ed); + } + + td_list = td_list_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = { + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = { + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = { + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = { + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'O', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break + +#ifdef DEBUG +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), \ + &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \ + writel((x), &gohci.regs- >roothub.portstatus[wIndex-1]);} +#else +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus [wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t * controller) +{ + __u32 temp, ndp, i; + int res; + + res = -1; + temp = roothub_a(controller); + ndp = (temp & RH_A_NDP); + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus(controller, i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, + struct devrequest *cmd) +{ + void *data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + __u32 datab[4]; + __u8 *data_buf = (__u8 *) datab; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", + usb_pipein(pipe)); +#endif + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + info("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = m16_swap(cmd->value); + wIndex = m16_swap(cmd->index); + wLength = m16_swap(cmd->length); + + info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", + dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(__u16 *) data_buf = m16_swap(1); + OK(2); + case RH_GET_STATUS | RH_INTERFACE: + *(__u16 *) data_buf = m16_swap(0); + OK(2); + case RH_GET_STATUS | RH_ENDPOINT: + *(__u16 *) data_buf = m16_swap(0); + OK(2); + case RH_GET_STATUS | RH_CLASS: + *(__u32 *) data_buf = m32_swap(RD_RH_STAT & + ~(RH_HS_CRWE | RH_HS_DRWE)); + OK(4); + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(__u32 *) data_buf = m32_swap(RD_RH_PORTSTAT); + OK(4); + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): + OK(0); + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + OK(0); + case (RH_C_HUB_OVER_CURRENT): + WR_RH_STAT(RH_HS_OCIC); + OK(0); + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_ENABLE): + WR_RH_PORTSTAT(RH_PS_CCS); + OK(0); + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT(RH_PS_POCI); + OK(0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT(RH_PS_LSDA); + OK(0); + case (RH_C_PORT_CONNECTION): + WR_RH_PORTSTAT(RH_PS_CSC); + OK(0); + case (RH_C_PORT_ENABLE): + WR_RH_PORTSTAT(RH_PS_PESC); + OK(0); + case (RH_C_PORT_SUSPEND): + WR_RH_PORTSTAT(RH_PS_PSSC); + OK(0); + case (RH_C_PORT_OVER_CURRENT): + WR_RH_PORTSTAT(RH_PS_OCIC); + OK(0); + case (RH_C_PORT_RESET): + WR_RH_PORTSTAT(RH_PS_PRSC); + OK(0); + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT(RH_PS_PSS); + OK(0); + case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT(RH_PS_PRS); + OK(0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT(RH_PS_PPS); + OK(0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT(RH_PS_PES); + OK(0); + } + break; + + case RH_SET_ADDRESS: + gohci.rh.devnum = wValue; + OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_dev_des), wLength)); + data_buf = root_hub_dev_des; + OK(len); + case (0x02): /* configuration descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; + OK(len); + case (0x03): /* string descriptors */ + if (wValue == 0x0300) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + + if (wValue == 0x0301) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = roothub_a(&gohci); + + data_buf[0] = 9; /* min length; */ + data_buf[1] = 0x29; + data_buf[2] = temp & RH_A_NDP; + data_buf[3] = 0; + + if (temp & RH_A_PSM) /* per-port power switching? */ + data_buf[3] |= 0x1; + + if (temp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf[3] |= 0x10; + else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ + data_buf[3] |= 0x8; + + /* corresponds to data_buf[4-7] */ + datab[1] = 0; + data_buf[5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b(&gohci); + data_buf[7] = temp & RH_B_DR; + + if (data_buf[2] < 7) + data_buf[8] = 0xff; + else { + data_buf[0] += 2; + data_buf[8] = (temp & RH_B_DR) >> 8; + data_buf[10] = data_buf[9] = 0xff; + } + + len = min_t(unsigned int, leni, + min_t(unsigned int, data_buf[0], wLength)); + OK(len); + } + + case RH_GET_CONFIGURATION: + *(__u8 *) data_buf = 0x01; + OK(1); + + case RH_SET_CONFIGURATION: + WR_RH_STAT(0x10000); + OK(0); + + default: + dbg("unsupported root hub command"); + stat = USB_ST_STALLED; + } + +#ifdef DEBUG + ohci_dump_roothub(&gohci, 1); +#endif + + len = min_t(int, len, leni); + + if (data != data_buf) + memcpy(data, data_buf, len); + + dev->act_len = len; + dev->status = stat; + +#ifdef DEBUG + if (transfer_len) + urb_priv.actual_length = transfer_len; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", + 0 /*usb_pipein(pipe) */ ); +#endif + + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub */ +/* accesses. */ +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + dev->status = USB_ST_CRC_ERR; + return 0; + } +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", + usb_pipein(pipe)); +#endif + if (!maxsize) { + err("submit_common_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + + if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < + 0) { + err("sohci_submit_job failed"); + return -1; + } + + /* allow more time for a BULK device to react - some are slow */ +#define BULK_TO 5000 /* timeout in milliseconds */ + if (usb_pipetype(pipe) == PIPE_BULK) + timeout = BULK_TO; + else + timeout = 100; + + /* wait for it to complete */ + for (;;) { + /* check whether the controller is done */ + stat = hc_interrupt(); + if (stat < 0) { + stat = USB_ST_CRC_ERR; + break; + } + + if (stat >= 0 && stat < 0xff) { + /* 0xff is returned for an SF-interrupt */ + break; + } + + if (--timeout) + wait_ms(1); + else { + err("CTL:TIMEOUT "); + stat = USB_ST_CRC_ERR; + break; + } + } + + /* we got an Root Hub Status Change interrupt */ + if (got_rhsc) { +#ifdef DEBUG + ohci_dump_roothub(&gohci, 1); +#endif + got_rhsc = 0; + /* abuse timeout */ + timeout = rh_check_port_status(&gohci); + if (timeout >= 0) { + /* + * XXX + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } + + dev->status = stat; + dev->act_len = transfer_len; + +#ifdef DEBUG + pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", + usb_pipein(pipe)); +#endif + + /* free TDs in urb_priv */ + urb_free_priv(&urb_priv); + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + int maxsize = usb_maxpacket(dev, pipe); + + info("submit_control_msg"); +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", + usb_pipein(pipe)); +#endif + if (!maxsize) { + err("submit_control_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + + if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { + gohci.rh.dev = dev; + /* root hub - redirect */ + return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + } + + return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return -1; +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset(ohci_t * ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + + if (readl(&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ + writel(OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ + info("USB HC TakeOver from SMM"); + + while (readl(&ohci->regs->control) & OHCI_CTRL_IR) { + wait_ms(10); + if (--smm_timeout == 0) { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + + /* Disable HC interrupts */ + writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); + + dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", + ohci->slot_name, readl(&ohci->regs->control)); + + /* Reset USB (needed by some controllers) */ + ohci->hc_control = 0; + writel(ohci->hc_control, &ohci->regs->control); + + /* HC Reset requires max 10 us delay */ + writel(OHCI_HCR, &ohci->regs->cmdstatus); + + while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { + if (--timeout == 0) { + err("USB HC reset timed out!"); + return -1; + } + udelay(1); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub */ + +static int hc_start(ohci_t * ohci) +{ + __u32 mask; + unsigned int fminterval; + + ohci->disabled = 1; + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + + writel(0, &ohci->regs->ed_controlhead); + writel(0, &ohci->regs->ed_bulkhead); + + writel((__u32) ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ + + fminterval = 0x2edf; + writel((fminterval * 9) / 10, &ohci->regs->periodicstart); + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel(fminterval, &ohci->regs->fminterval); + writel(0x628, &ohci->regs->lsthresh); + + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel(ohci->hc_control, &ohci->regs->control); + + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | + OHCI_INTR_OC | OHCI_INTR_MIE); + writel(mask, &ohci->regs->intrdisable); + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel(mask, &ohci->regs->intrstatus); + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel(mask, &ohci->regs->intrenable); + +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, + &ohci->regs->roothub.a); + writel(RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ + +#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay (1000);}) + /* POTPGT delay is bits 24-31, in 2 ms units. */ + mdelay((roothub_a(ohci) >> 23) & 0x1fe); + + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* an interrupt happens */ + +static int hc_interrupt(void) +{ + ohci_t *ohci = &gohci; + struct ohci_regs *regs = ohci->regs; + int ints; + int stat = -1; + + if ((ohci->hcca->done_head != 0) + && !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) + ints = OHCI_INTR_WDH; + else + ints = readl(&regs->intrstatus); + + /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca- >frame_no)); */ + + if (ints & OHCI_INTR_RHSC) + got_rhsc = 1; + + if (ints & OHCI_INTR_UE) { + ohci->disabled++; + err("OHCI Unrecoverable Error, controller usb-%s disabled", + ohci->slot_name); + /* e.g. due to PCI Master/Target Abort */ + +#ifdef DEBUG + ohci_dump(ohci, 1); +#endif + /* FIXME: be optimistic, hope that bug won't repeat often. */ + /* Make some non-interrupt context restart the controller. */ + /* Count and limit the retries though; either hardware or */ + /* software errors can go forever... */ + hc_reset(ohci); + return -1; + } + + if (ints & OHCI_INTR_WDH) { + writel(OHCI_INTR_WDH, &regs->intrdisable); + stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci)); + writel(OHCI_INTR_WDH, &regs->intrenable); + } + + if (ints & OHCI_INTR_SO) { + dbg("USB Schedule overrun\n"); + writel(OHCI_INTR_SO, &regs->intrenable); + stat = -1; + } + + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if (ints & OHCI_INTR_SF) { + unsigned int frame = ohci_cpu_to_le16(ohci->hcca->frame_no) & 1; + writel(OHCI_INTR_SF, &regs->intrdisable); + + if (ohci->ed_rm_list[frame] != NULL) + writel(OHCI_INTR_SF, &regs->intrenable); + + stat = 0xff; + } + + writel(ints, &regs->intrstatus); + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +/* De-allocate all resources.. */ + +static void hc_release_ohci(ohci_t * ohci) +{ + dbg("USB HC release ohci usb-%s", ohci->slot_name); + + if (!ohci->disabled) + hc_reset(ohci); +} + +/*-------------------------------------------------------------------------*/ + +/* + * low level initalisation routine, called from usb.c + */ +static char ohci_inited = 0; + +int usb_lowlevel_init(void) +{ + /* Set the USB VBus */ + *(vu_long *) (CFG_FPGA_BASE + 0x08) |= 0x00000060; + + memset(&gohci, 0, sizeof(ohci_t)); + memset(&urb_priv, 0, sizeof(urb_priv_t)); + + /* align the storage */ + if ((__u32) & ghcca[0] & 0xff) { + err("HCCA not aligned!!"); + return -1; + } + phcca = &ghcca[0]; + info("aligned ghcca %p", phcca); + memset(&ohci_dev, 0, sizeof(struct ohci_device)); + + if ((__u32) & ohci_dev.ed[0] & 0x7) { + err("EDs not aligned!!"); + return -1; + } + memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); + if ((__u32) gtd & 0x7) { + err("TDs not aligned!!"); + return -1; + } + ptd = gtd; + gohci.hcca = phcca; + memset(phcca, 0, sizeof(struct ohci_hcca)); + + gohci.disabled = 1; + gohci.sleeping = 0; + gohci.irq = -1; + gohci.regs = (struct ohci_regs *)MMAP_USBH; + + gohci.flags = 0; + gohci.slot_name = "mpc8220"; + + if (hc_reset(&gohci) < 0) { + hc_release_ohci(&gohci); + return -1; + } + + if (hc_start(&gohci) < 0) { + err("can't start usb-%s", gohci.slot_name); + hc_release_ohci(&gohci); + return -1; + } +#ifdef DEBUG + ohci_dump(&gohci, 1); +#endif + ohci_inited = 1; + return 0; +} + +int usb_lowlevel_stop(void) +{ + /* this gets called really early - before the controller has */ + /* even been initialized! */ + if (!ohci_inited) + return 0; + /* TODO release any interrupts, etc. */ + /* call hc_release_ohci() here ? */ + hc_reset(&gohci); + return 0; +} + +#endif /* CONFIG_USB_OHCI */

1 0

[U-Boot-Users] Patch: MPC8220 vco frequency update
by TsiChung Liew 11 May '07

11 May '07

- replaced vco to cvco and svco - added CFG_SPEED in speed.c Regards, TsiChung Liew Signed-off by: TsiChung Liew<Tsi-Chung.Liew(a)freescale.com> diff -rupN u-boot-all.git/common/cmd_bdinfo.c u-boot-all-8220- cfgspeed/common/cmd_bdinfo.c --- u-boot-all.git/common/cmd_bdinfo.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-cfgspeed/common/cmd_bdinfo.c 2007-05-10 17:07:48.000000000 -0500 @@ -87,7 +87,8 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int fl print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq)); print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq)); print_str ("pcifreq", strmhz(buf, bd->bi_pcifreq)); - print_str ("vcofreq", strmhz(buf, bd->bi_vcofreq)); + print_str("cvcofreq", strmhz(buf, bd->bi_cvcofreq)); + print_str("svcofreq", strmhz(buf, bd->bi_svcofreq)); print_str ("pevfreq", strmhz(buf, bd->bi_pevfreq)); #endif diff -rupN u-boot-all.git/common/cmd_bootm.c u-boot-all-8220- cfgspeed/common/cmd_bootm.c --- u-boot-all.git/common/cmd_bootm.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-cfgspeed/common/cmd_bootm.c 2007-05-10 17:07:58.000000000 -0500 @@ -606,7 +606,8 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl kbd->bi_pcifreq /= 1000000L; kbd->bi_pevfreq /= 1000000L; kbd->bi_flbfreq /= 1000000L; - kbd->bi_vcofreq /= 1000000L; + kbd->bi_cvcofreq /= 1000000L; + kbd->bi_svcofreq /= 1000000L; #endif #if defined(CONFIG_CPM2) kbd->bi_cpmfreq /= 1000000L; diff -rupN u-boot-all.git/common/cmd_fdt.c u-boot-all-8220- cfgspeed/common/cmd_fdt.c --- u-boot-all.git/common/cmd_fdt.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-cfgspeed/common/cmd_fdt.c 2007-05-10 17:08:04.000000000 -0500 @@ -702,7 +702,8 @@ static const struct { BDM(pcifreq), BDM(pevfreq), BDM(flbfreq), - BDM(vcofreq), + BDM(cvcofreq), + BDM(svcofreq), #endif BDM(bootflags), BDM(ip_addr), diff -rupN u-boot-all.git/common/ft_build.c u-boot-all-8220- cfgspeed/common/ft_build.c --- u-boot-all.git/common/ft_build.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-cfgspeed/common/ft_build.c 2007-05-10 17:08:15.000000000 -0500 @@ -429,7 +429,8 @@ static const struct { BDM(pcifreq), BDM(pevfreq), BDM(flbfreq), - BDM(vcofreq), + BDM(cvcofreq), + BDM(svcofreq), #endif BDM(bootflags), BDM(ip_addr), diff -rupN u-boot-all.git/cpu/mpc8220/speed.c u-boot-all-8220- cfgspeed/cpu/mpc8220/speed.c --- u-boot-all.git/cpu/mpc8220/speed.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-cfgspeed/cpu/mpc8220/speed.c 2007-05-10 17:06:24.000000000 -0500 @@ -27,6 +27,8 @@ DECLARE_GLOBAL_DATA_PTR; +#if !defined(CFG_SPEED) + typedef struct pllmultiplier { u8 hid1; int multi; @@ -35,10 +37,6 @@ typedef struct pllmultiplier { /* ------------------------------------------------------------------------- */ -/* - * - */ - int get_clocks (void) { pllcfg_t bus2core[] = { @@ -97,7 +95,10 @@ int get_clocks (void) for (i = 0; i < size; i++) if (hid1 == bus2core[i].hid1) { gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1; - gd->vco_clk = CFG_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2; + gd->cvco_clk = + CFG_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * + bus2core[i]. + vco_div) / 2; break; } @@ -106,13 +107,22 @@ int get_clocks (void) return (0); } +#endif /* !defined(CFG_SPEED) */ int prt_mpc8220_clks (void) { - printf (" Bus %ld MHz, CPU %ld MHz, PCI %ld MHz, VCO %ld MHz\n", - gd->bus_clk / 1000000, gd->cpu_clk / 1000000, - gd->pci_clk / 1000000, gd->vco_clk / 1000000); - +#ifdef CFG_SPEED + printf(" CPU %ld MHz, BUS %ld MHz, PCI %ld MHz, FBUS %ld Mhz\n", + gd->cpu_clk / 1000000, gd->bus_clk / 1000000, + gd->pci_clk / 1000000, gd->flb_clk / 1000000); + printf(" SVCO %ld MHz, CVCO %ld MHz\n", + gd->svco_clk / 1000000, gd->cvco_clk / 1000000); +#else + printf(" CPU %ld MHz, BUS %ld MHz, PCI %ld MHz, FBUS %ld Mhz\n", + gd->cpu_clk / 1000000, gd->bus_clk / 1000000, + gd->pci_clk / 1000000, gd->flb_clk / 1000000); + printf(" CVCO %ld MHz\n", gd->cvco_clk / 1000000); +#endif /* CFG_SPEED */ return (0); } diff -rupN u-boot-all.git/include/asm-ppc/global_data.h u-boot-all-8220- cfgspeed/include/asm-ppc/global_data.h --- u-boot-all.git/include/asm-ppc/global_data.h 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-cfgspeed/include/asm-ppc/global_data.h 2007-05-10 17:10:53.000000000 -0500 @@ -84,7 +84,8 @@ typedef struct global_data { unsigned long bExtUart; unsigned long inp_clk; unsigned long pci_clk; - unsigned long vco_clk; + unsigned long cvco_clk; + unsigned long svco_clk; unsigned long pev_clk; unsigned long flb_clk; #endif diff -rupN u-boot-all.git/include/asm-ppc/u-boot.h u-boot-all-8220- cfgspeed/include/asm-ppc/u-boot.h --- u-boot-all.git/include/asm-ppc/u-boot.h 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-cfgspeed/include/asm-ppc/u-boot.h 2007-05-10 17:10:59.000000000 -0500 @@ -60,7 +60,8 @@ typedef struct bd_info { unsigned long bi_pcifreq; /* PCI Freq, in MHz */ unsigned long bi_pevfreq; /* PEV Freq, in MHz */ unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */ - unsigned long bi_vcofreq; /* VCO Freq, in MHz */ + unsigned long bi_cvcofreq; /* Core VCO Freq, in MHz */ + unsigned long bi_svcofreq; /* System VCO Freq, in Mhz */ #endif unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ unsigned long bi_ip_addr; /* IP Address */ diff -rupN u-boot-all.git/lib_ppc/board.c u-boot-all-8220- cfgspeed/lib_ppc/board.c --- u-boot-all.git/lib_ppc/board.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-cfgspeed/lib_ppc/board.c 2007-05-10 17:14:06.000000000 -0500 @@ -528,7 +528,8 @@ void board_init_f (ulong bootflag) bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ bd->bi_inpfreq = gd->inp_clk; bd->bi_pcifreq = gd->pci_clk; - bd->bi_vcofreq = gd->vco_clk; + bd->bi_cvcofreq = gd->cvco_clk; + bd->bi_svcofreq = gd->svco_clk; bd->bi_pevfreq = gd->pev_clk; bd->bi_flbfreq = gd->flb_clk; @@ -539,7 +540,7 @@ void board_init_f (ulong bootflag) *sram++ = gd->bus_clk; *sram++ = gd->inp_clk; *sram++ = gd->cpu_clk; - *sram++ = gd->vco_clk; + *sram++ = gd->cvco_clk; *sram++ = gd->flb_clk; *sram++ = 0xb8c3ba11; /* boot signature */ }

1 0

[U-Boot-Users] Patch: MPC8220 - update PCI for Alaska
by TsiChung Liew 11 May '07

11 May '07

- Added PCI feature Regards, TsiChung Liew Signed-off by: TsiChung Liew<Tsi-Chung.Liew(a)freescale.com> diff -rupN u-boot-all.git/board/alaska/alaska.c u-boot-all-8220- pci/board/alaska/alaska.c --- u-boot-all.git/board/alaska/alaska.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-pci/board/alaska/alaska.c 2007-05-10 16:35:11.000000000 -0500 @@ -25,6 +25,9 @@ #include <mpc8220.h> #include <asm/processor.h> #include <asm/mmu.h> +#if defined(CONFIG_PCI) +#include <pci.h> +#endif void setupBat (ulong size) { @@ -151,3 +154,19 @@ int checkboard (void) return 0; } + +#if defined(CONFIG_PCI) +/* + * Initialize PCI devices, report devices found. + */ +static struct pci_controller hose; + +#endif /* CONFIG_PCI */ + +void pci_init_board (void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc8220_init (struct pci_controller *hose); + pci_mpc8220_init (&hose); +#endif /* CONFIG_PCI */ +} diff -rupN u-boot-all.git/cpu/mpc8220/pci.c u-boot-all-8220- pci/cpu/mpc8220/pci.c --- u-boot-all.git/cpu/mpc8220/pci.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-pci/cpu/mpc8220/pci.c 2007-05-10 16:32:34.000000000 -0500 @@ -116,8 +116,10 @@ pci_mpc8220_init(struct pci_controller * out_be32 (&xcpci->init_win_cfg, PCI_INIT_WIN_CFG_WIN0_CTRL_EN | - PCI_INIT_WIN_CFG_WIN1_CTRL_EN | PCI_INIT_WIN_CFG_WIN1_CTRL_IO | - PCI_INIT_WIN_CFG_WIN2_CTRL_EN | PCI_INIT_WIN_CFG_WIN2_CTRL_IO); + PCI_INIT_WIN_CFG_WIN1_CTRL_EN | + PCI_INIT_WIN_CFG_WIN1_CTRL_IO | + PCI_INIT_WIN_CFG_WIN2_CTRL_EN | + PCI_INIT_WIN_CFG_WIN2_CTRL_IO); out_be32 (&xcpci->init_ctrl, 0x00000000);

1 0

[U-Boot-Users] PATCH: MPC8220 update in flash.c
by TsiChung Liew 11 May '07

11 May '07

- Print out KB or MB in flash Regards, TsiChung Liew Signed-off by: TsiChung Liew<Tsi-Chung.Liew(a)freescale.com> diff -rupN u-boot-all.git/board/alaska/flash.c u-boot-all-8220- flash/board/alaska/flash.c --- u-boot-all.git/board/alaska/flash.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-flash/board/alaska/flash.c 2007-05-10 15:40:56.000000000 -0500 @@ -27,7 +27,6 @@ #include <common.h> #include <linux/byteorder/swab.h> - flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ @@ -213,8 +212,12 @@ void flash_print_info (flash_info_t * in break; } + if (info->size > 0x100000) printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); printf (" Sector Start Addresses:"); for (i = 0; i < info->sector_count; ++i) { @@ -308,7 +311,6 @@ static ulong flash_get_size (FPW * addr, return (info->size); } - /* * This function gets the u-boot flash sector protection status * (flash_info_t.protect[]) in sync with the sector protection @@ -331,7 +333,6 @@ static void flash_sync_real_protect (fla } } - /* * checks if "sector" in bank "info" is protected. Should work on intel * strata flash chips 28FxxxJ3x in 8-bit mode. @@ -384,7 +385,6 @@ static unsigned char intel_sector_protec return ret; } - /* * Checks if "bank1" and "bank2" are on the same chip. Returns 1 if they * are and 0 otherwise. @@ -400,7 +400,6 @@ static unsigned char same_chip_banks (in return same_chip[bank1][bank2]; } - /*----------------------------------------------------------------------- */ int flash_erase (flash_info_t * info, int s_first, int s_last)

1 0

[U-Boot-Users] Patch: MPC8220i I2C update
by TsiChung Liew 11 May '07

11 May '07

- Applied I2C frequency divider calculation instead of fixed value in dramSetup.c. - Removed i2cCore.c and i2cCore.h - Update I2C definitions in mpc8220.h Regards, TsiChung Liew Signed-off by: TsiChung Liew<Tsi-Chung.Liew(a)freescale.com> diff -rupN u-boot-all.git/cpu/mpc8220/dramSetup.c u-boot-all-8220- dramsetup/cpu/mpc8220/dramSetup.c --- u-boot-all.git/cpu/mpc8220/dramSetup.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-dramsetup/cpu/mpc8220/dramSetup.c 2007-05-10 15:30:52.000000000 -0500 @@ -29,7 +29,6 @@ characteristics to initialize the dram o #include <common.h> #include <mpc8220.h> -#include "i2cCore.h" #include "dramSetup.h" DECLARE_GLOBAL_DATA_PTR; @@ -91,6 +90,97 @@ int spd_readbyte (volatile i2c8220_t * p return (OK); } +#define I2C_BITRATE_VALUE 100000 +#define ABS(x) ((x < 0)? -x : x) +u8 i2cCalculation(u32 devfreq) +{ +/* Constants */ + const u8 div_hold[8][3] = { {9, 3}, {10, 3}, + {12, 4}, {15, 4}, + {5, 1}, {6, 1}, + {7, 2}, {8, 2} + }; + + const u8 scl_tap[8][2] = { {4, 1}, {4, 2}, + {6, 4}, {6, 8}, + {14, 16}, {30, 32}, + {62, 64}, {126, 128} + }; + + u8 mfdr_bits; + + int i = 0; + int j = 0; + + int Diff, min; + int WhichFreq, iRec, jRec; + int SCL_Period; + int SCL_Hold; + int I2C_Freq; + + /* Initialize */ + mfdr_bits = 0; + min = 0x7fffffff; + WhichFreq = iRec = jRec = 0; + + for (i = 0; i < 8; i++) { + for (j = 0; j < 8; j++) { + /* SCL Period = 2 * (scl2tap + [(SCL_Tap - 1) * tap2tap] + 2) + * SCL Hold = scl2tap + ((SDA_Tap - 1) * tap2tap) + 3 + * Bit Rate (I2C Freq) = System Freq / SCL Period + */ + SCL_Period = + 2 * (scl_tap[i][0] + + ((div_hold[j][0] - 1) * scl_tap[i][1]) + 2); + + /* Now get the I2C Freq */ + I2C_Freq = devfreq / SCL_Period; + + /* Take equal or slower */ + if (I2C_Freq > I2C_BITRATE_VALUE) + continue; + + /* Take the differences */ + Diff = I2C_Freq - I2C_BITRATE_VALUE; + + Diff = ABS(Diff); + + /* Find the closer value */ + if (Diff < min) { + min = Diff; + WhichFreq = I2C_Freq; + iRec = i; + jRec = j; + } + } + } + + SCL_Period = + 2 * (scl_tap[iRec][0] + + ((div_hold[jRec][0] - 1) * scl_tap[iRec][1]) + 2); + + /* This may no require */ + SCL_Hold = + scl_tap[iRec][0] + ((div_hold[jRec][1] - 1) * scl_tap[iRec][1]) + 3; + + /* FDR 4,3,2 */ + if ((iRec & 1) == 1) + mfdr_bits |= 0x04; /* FDR 2 */ + if ((iRec & 2) == 2) + mfdr_bits |= 0x08; /* FDR 3 */ + if ((iRec & 4) == 4) + mfdr_bits |= 0x10; /* FDR 4 */ + /* FDR 5,1,0 */ + if ((jRec & 1) == 1) + mfdr_bits |= 0x01; /* FDR 0 */ + if ((jRec & 2) == 2) + mfdr_bits |= 0x02; /* FDR 1 */ + if ((jRec & 4) == 4) + mfdr_bits |= 0x20; /* FDR 5 */ + + return mfdr_bits; +} + int readSpdData (u8 * spdData) { volatile i2c8220_t *pi2cReg; @@ -109,40 +199,13 @@ int readSpdData (u8 * spdData) /* Points the structure to I2c mbar memory offset */ pi2cReg = (volatile i2c8220_t *) (MMAP_I2C); - /* Clear FDR, ADR, SR and CR reg */ pi2cReg->adr = 0; pi2cReg->fdr = 0; pi2cReg->cr = 0; pi2cReg->sr = 0; - /* Set for fix XLB Bus Frequency */ - switch (gd->bus_clk) { - case 60000000: - pi2cReg->fdr = 0x15; - break; - case 70000000: - pi2cReg->fdr = 0x16; - break; - case 80000000: - pi2cReg->fdr = 0x3a; - break; - case 90000000: - pi2cReg->fdr = 0x17; - break; - case 100000000: - pi2cReg->fdr = 0x3b; - break; - case 110000000: - pi2cReg->fdr = 0x18; - break; - case 120000000: - pi2cReg->fdr = 0x19; - break; - case 130000000: - pi2cReg->fdr = 0x1a; - break; - } + pi2cReg->fdr = i2cCalculation(gd->bus_clk); pi2cReg->adr = CFG_I2C_SLAVE<<1; @@ -167,7 +230,6 @@ int readSpdData (u8 * spdData) if (spd_status (pi2cReg, I2C_STA_BB, 1) != OK) return ERROR; - /* Write slave address */ pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */ pi2cReg->dr = slvAdr; /* Write a byte */ @@ -182,7 +244,6 @@ int readSpdData (u8 * spdData) return ERROR; } - /* Issue the offset to start */ pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */ pi2cReg->dr = 0; /* Write a byte */ @@ -197,7 +258,6 @@ int readSpdData (u8 * spdData) return ERROR; } - /* Set repeat start */ pi2cReg->cr |= I2C_CTL_RSTA; /* Repeat Start */ @@ -257,7 +317,6 @@ int getBankInfo (int bank, draminfo_t * int count; u8 spdData[SPD_SIZE]; - if (bank > 2 || pBank == 0) { /* illegal values */ return (-42); @@ -277,8 +336,7 @@ int getBankInfo (int bank, draminfo_t * return (-2); /* Get the memory type */ - if (! - ((spdData[LOC_TYPE] == TYPE_DDR) + if (!((spdData[LOC_TYPE] == TYPE_DDR) || (spdData[LOC_TYPE] == TYPE_SDR))) /* not one of the types we support */ return (-3); @@ -328,7 +386,6 @@ int getBankInfo (int bank, draminfo_t * return (0); } - /* checkMuxSetting -- given a row/column device geometry, return a mask * of the valid DRAM controller addr_mux settings for * that geometry. @@ -400,7 +457,6 @@ u8 checkMuxSetting (u8 rows, u8 columns) return (mask); } - u32 dramSetup (void) { draminfo_t DramInfo[TOTAL_BANK]; @@ -469,8 +525,7 @@ u32 dramSetup (void) if (columns > 13) columns = 13; - pDramInfo->size = - ((1 << (rows + columns)) * pDramInfo->width); + pDramInfo->size = ((1 << (rows + columns)) * pDramInfo->width); pDramInfo->size *= pDramInfo->banks; pDramInfo->size >>= 3; @@ -494,7 +549,6 @@ u32 dramSetup (void) } /* for loop */ - /* We only allow a burst length of 8! */ if (!(bursts & 8)) bursts = 8; @@ -522,7 +576,6 @@ u32 dramSetup (void) } } - /* Now figure out the base address for each bank. While * we're at it, figure out how much memory there is. * @@ -566,7 +619,6 @@ u32 dramSetup (void) */ cfg_value |= CFG1_RLATENCY ((type == TYPE_DDR) ? 7 : 2); - /* Set the Active to Read/Write delay. This depends * on Trcd which is reported as nanoseconds times 4. * We want to calculate Trcd (in nanoseconds) times XLB clock (in Hz) @@ -615,7 +667,6 @@ u32 dramSetup (void) memctl->cfg1 = cfg_value; /* cfg 1 */ asm volatile ("sync"); - /* ********************** Cfg 2 ************************* */ /* Set the burst read to read/precharge delay */ @@ -639,7 +690,6 @@ u32 dramSetup (void) memctl->cfg2 = cfg_value; /* cfg 2 */ asm volatile ("sync"); - /* ********************** mode ************************* */ /* Set enable bit, CKE high/low bits, and the DDR/SDR mode bit, @@ -677,7 +727,6 @@ u32 dramSetup (void) asm volatile ("sync"); } - /* Set up mode value for CAS latency */ #if (CFG_SDRAM_CAS_LATENCY==5) /* CL=2.5 */ mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) | @@ -711,8 +760,7 @@ u32 dramSetup (void) if (DramInfo[banknum].size & mask) break; } - temp = (DramInfo[banknum].base & 0xfff00000) | (i - - 1); + temp = (DramInfo[banknum].base & 0xfff00000) | (i - 1); sysconf->cscfg[banknum] = temp; asm volatile ("sync"); diff -rupN u-boot-all.git/cpu/mpc8220/i2cCore.c u-boot-all-8220- dramsetup/cpu/mpc8220/i2cCore.c --- u-boot-all.git/cpu/mpc8220/i2cCore.c 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-dramsetup/cpu/mpc8220/i2cCore.c 1969-12-31 18:00:00.000000000 -0600 @@ -1,627 +0,0 @@ -/* I2cCore.c - MPC8220 PPC I2C Library */ - -/* Copyright 2004 Freescale Semiconductor, Inc. */ - -/* -modification history --------------------- -01c,29jun04,tcl 1.3 removed CR. Added two bytes offset support. -01b,19jan04,tcl 1.2 removed i2cMsDelay and sysDecGet. renamed i2cMsDelay - back to sysMsDelay -01a,19jan04,tcl 1.1 created and seperated from i2c.c -*/ - -/* -DESCRIPTION -This file contain I2C low level handling library functions -*/ - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <vxWorks.h> -#include <sysLib.h> -#include <iosLib.h> -#include <logLib.h> -#include <tickLib.h> - -/* BSP Includes */ -#include "config.h" -#include "mpc8220.h" -#include "i2cCore.h" - -#ifdef DEBUG_I2CCORE -int I2CCDbg = 0; -#endif - -#define ABS(x) ((x < 0)? -x : x) - -char *I2CERR[16] = { - "Transfer in Progress\n", /* 0 */ - "Transfer complete\n", - "Not Addressed\n", /* 2 */ - "Addressed as a slave\n", - "Bus is Idle\n", /* 4 */ - "Bus is busy\n", - "Arbitration Lost\n", /* 6 */ - "Arbitration on Track\n", - "Slave receive, master writing to slave\n", /* 8 */ - "Slave transmit, master reading from slave\n", - "Interrupt is pending\n", /* 10 */ - "Interrupt complete\n", - "Acknowledge received\n", /* 12 */ - "No acknowledge received\n", - "Unknown status\n", /* 14 */ - "\n" -}; - -/****************************************************************************** - * - * chk_status - Check I2C status bit - * - * RETURNS: OK, or ERROR if the bit encounter - * - */ - -STATUS chk_status (PSI2C pi2c, UINT8 sta_bit, UINT8 truefalse) -{ - int i, status = 0; - - for (i = 0; i < I2C_POLL_COUNT; i++) { - if ((pi2c->sr & sta_bit) == (truefalse ? sta_bit : 0)) - return (OK); - } - - I2CCDBG (L2, ("--- sr %x stabit %x truefalse %d\n", - pi2c->sr, sta_bit, truefalse, 0, 0, 0)); - - if (i == I2C_POLL_COUNT) { - switch (sta_bit) { - case I2C_STA_CF: - status = 0; - break; - case I2C_STA_AAS: - status = 2; - break; - case I2C_STA_BB: - status = 4; - break; - case I2C_STA_AL: - status = 6; - break; - case I2C_STA_SRW: - status = 8; - break; - case I2C_STA_IF: - status = 10; - break; - case I2C_STA_RXAK: - status = 12; - break; - default: - status = 14; - break; - } - - if (!truefalse) - status++; - - I2CCDBG (NO, ("--- status %d\n", status, 0, 0, 0, 0, 0)); - I2CCDBG (NO, (I2CERR[status], 0, 0, 0, 0, 0, 0)); - } - - return (ERROR); -} - -/****************************************************************************** - * - * I2C Enable - Enable the I2C Controller - * - */ -STATUS i2c_enable (SI2C * pi2c, PI2CSET pi2cSet) -{ - int fdr = pi2cSet->bit_rate; - UINT8 adr = pi2cSet->i2c_adr; - - I2CCDBG (L2, ("i2c_enable fdr %d adr %x\n", fdr, adr, 0, 0, 0, 0)); - - i2c_clear (pi2c); /* Clear FDR, ADR, SR and CR reg */ - - SetI2cFDR (pi2c, fdr); /* Frequency */ - pi2c->adr = adr; - - pi2c->cr = I2C_CTL_EN; /* Set Enable */ - - /* - The I2C bus should be in Idle state. If the bus is busy, - clear the STA bit in control register - */ - if (chk_status (pi2c, I2C_STA_BB, 0) != OK) { - if ((pi2c->cr & I2C_CTL_STA) == I2C_CTL_STA) - pi2c->cr &= ~I2C_CTL_STA; - - /* Check again if it is still busy, return error if found */ - if (chk_status (pi2c, I2C_STA_BB, 1) == OK) - return ERROR; - } - - return (OK); -} - -/****************************************************************************** - * - * I2C Disable - Disable the I2C Controller - * - */ -STATUS i2c_disable (PSI2C pi2c) -{ - i2c_clear (pi2c); - - pi2c->cr &= I2C_CTL_EN; /* Disable I2c */ - - if ((pi2c->cr & I2C_CTL_STA) == I2C_CTL_STA) - pi2c->cr &= ~I2C_CTL_STA; - - if (chk_status (pi2c, I2C_STA_BB, 0) != OK) - return ERROR; - - return (OK); -} - -/****************************************************************************** - * - * I2C Clear - Clear the I2C Controller - * - */ -STATUS i2c_clear (PSI2C pi2c) -{ - pi2c->adr = 0; - pi2c->fdr = 0; - pi2c->cr = 0; - pi2c->sr = 0; - - return (OK); -} - - -STATUS i2c_start (PSI2C pi2c, PI2CSET pi2cSet) -{ -#ifdef TWOBYTES - UINT16 ByteOffset = pi2cSet->str_adr; -#else - UINT8 ByteOffset = pi2cSet->str_adr; -#endif -#if 1 - UINT8 tmp = 0; -#endif - UINT8 Addr = pi2cSet->slv_adr; - - pi2c->cr |= I2C_CTL_STA; /* Generate start signal */ - - if (chk_status (pi2c, I2C_STA_BB, 1) != OK) - return ERROR; - - /* Write slave address */ - if (i2c_writebyte (pi2c, &Addr) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } -#ifdef TWOBYTES -# if 0 - /* Issue the offset to start */ - if (i2c_write2byte (pi2c, &ByteOffset) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } -#endif - tmp = (ByteOffset >> 8) & 0xff; - if (i2c_writebyte (pi2c, &tmp) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } - tmp = ByteOffset & 0xff; - if (i2c_writebyte (pi2c, &tmp) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } -#else - if (i2c_writebyte (pi2c, &ByteOffset) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } -#endif - - return (OK); -} - -STATUS i2c_stop (PSI2C pi2c) -{ - pi2c->cr &= ~I2C_CTL_STA; /* Generate stop signal */ - if (chk_status (pi2c, I2C_STA_BB, 0) != OK) - return ERROR; - - return (OK); -} - -/****************************************************************************** - * - * Read Len bytes to the location pointed to by *Data from the device - * with address Addr. - */ -int i2c_readblock (SI2C * pi2c, PI2CSET pi2cSet, UINT8 * Data) -{ - int i = 0; - UINT8 Tmp; - -/* UINT8 ByteOffset = pi2cSet->str_adr; not used? */ - UINT8 Addr = pi2cSet->slv_adr; - int Length = pi2cSet->xfer_size; - - I2CCDBG (L1, ("i2c_readblock addr %x data 0x%08x len %d offset %d\n", - Addr, (int) Data, Length, ByteOffset, 0, 0)); - - if (pi2c->sr & I2C_STA_AL) { /* Check if Arbitration lost */ - I2CCDBG (FN, ("Arbitration lost\n", 0, 0, 0, 0, 0, 0)); - pi2c->sr &= ~I2C_STA_AL; /* Clear Arbitration status bit */ - return ERROR; - } - - pi2c->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */ - - if (i2c_start (pi2c, pi2cSet) == ERROR) - return ERROR; - - pi2c->cr |= I2C_CTL_RSTA; /* Repeat Start */ - - Tmp = Addr | 1; - - if (i2c_writebyte (pi2c, &Tmp) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } - - if (((pi2c->sr & 0x07) == 0x07) || (pi2c->sr & 0x01)) - return ERROR; - - pi2c->cr &= ~I2C_CTL_TX; /* Set receive mode */ - - if (((pi2c->sr & 0x07) == 0x07) || (pi2c->sr & 0x01)) - return ERROR; - - /* Dummy Read */ - if (i2c_readbyte (pi2c, &Tmp, &i) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } - - i = 0; - while (Length) { - if (Length == 2) - pi2c->cr |= I2C_CTL_TXAK; - - if (Length == 1) - pi2c->cr &= ~I2C_CTL_STA; - - if (i2c_readbyte (pi2c, Data, &Length) != OK) { - return i2c_stop (pi2c); - } - i++; - Length--; - Data++; - } - - if (i2c_stop (pi2c) == ERROR) - return ERROR; - - return i; -} - -STATUS i2c_writeblock (SI2C * pi2c, PI2CSET pi2cSet, UINT8 * Data) -{ - int Length = pi2cSet->xfer_size; - -#ifdef TWOBYTES - UINT16 ByteOffset = pi2cSet->str_adr; -#else - UINT8 ByteOffset = pi2cSet->str_adr; -#endif - int j, k; - - I2CCDBG (L2, ("i2c_writeblock\n", 0, 0, 0, 0, 0, 0)); - - if (pi2c->sr & I2C_STA_AL) { - /* Check if arbitration lost */ - I2CCDBG (L2, ("Arbitration lost\n", 0, 0, 0, 0, 0, 0)); - pi2c->sr &= ~I2C_STA_AL; /* Clear the condition */ - return ERROR; - } - - pi2c->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */ - - /* Do the not even offset first */ - if ((ByteOffset % 8) != 0) { - int remain; - - if (Length > 8) { - remain = 8 - (ByteOffset % 8); - Length -= remain; - - pi2cSet->str_adr = ByteOffset; - - if (i2c_start (pi2c, pi2cSet) == ERROR) - return ERROR; - - for (j = ByteOffset; j < remain; j++) { - if (i2c_writebyte (pi2c, Data++) != OK) - return ERROR; - } - - if (i2c_stop (pi2c) == ERROR) - return ERROR; - - sysMsDelay (32); - - /* Update the new ByteOffset */ - ByteOffset += remain; - } - } - - for (j = ByteOffset, k = 0; j < (Length + ByteOffset); j++) { - if ((j % 8) == 0) { - pi2cSet->str_adr = j; - if (i2c_start (pi2c, pi2cSet) == ERROR) - return ERROR; - } - - k++; - - if (i2c_writebyte (pi2c, Data++) != OK) - return ERROR; - - if ((j == (Length - 1)) || ((k % 8) == 0)) { - if (i2c_stop (pi2c) == ERROR) - return ERROR; - - sysMsDelay (50); - } - - } - - return k; -} - -STATUS i2c_readbyte (SI2C * pi2c, UINT8 * readb, int *index) -{ - pi2c->sr &= ~I2C_STA_IF; /* Clear Interrupt Bit */ - *readb = pi2c->dr; /* Read a byte */ - - /* - Set I2C_CTRL_TXAK will cause Transfer pending and - set I2C_CTRL_STA will cause Interrupt pending - */ - if (*index != 2) { - if (chk_status (pi2c, I2C_STA_CF, 1) != OK) /* Transfer not complete? */ - return ERROR; - } - - if (*index != 1) { - if (chk_status (pi2c, I2C_STA_IF, 1) != OK) - return ERROR; - } - - return (OK); -} - - -STATUS i2c_writebyte (SI2C * pi2c, UINT8 * writeb) -{ - pi2c->sr &= ~I2C_STA_IF; /* Clear Interrupt */ - pi2c->dr = *writeb; /* Write a byte */ - - if (chk_status (pi2c, I2C_STA_CF, 1) != OK) /* Transfer not complete? */ - return ERROR; - - if (chk_status (pi2c, I2C_STA_IF, 1) != OK) - return ERROR; - - return OK; -} - -STATUS i2c_write2byte (SI2C * pi2c, UINT16 * writeb) -{ - UINT8 data; - - data = (UINT8) ((*writeb >> 8) & 0xff); - if (i2c_writebyte (pi2c, &data) != OK) - return ERROR; - data = (UINT8) (*writeb & 0xff); - if (i2c_writebyte (pi2c, &data) != OK) - return ERROR; - return OK; -} - -/* FDR table base on 33Mhz - more detail please refer to Odini2c_dividers.xls -FDR FDR scl sda scl2tap2 -510 432 tap tap tap tap scl_per sda_hold I2C Freq 0 1 2 3 4 5 -000 000 9 3 4 1 28 Clocks 9 Clocks 1190 KHz 0 0 0 0 0 0 -000 001 9 3 4 2 44 Clocks 11 Clocks 758 KHz 0 0 1 0 0 0 -000 010 9 3 6 4 80 Clocks 17 Clocks 417 KHz 0 0 0 1 0 0 -000 011 9 3 6 8 144 Clocks 25 Clocks 231 KHz 0 0 1 1 0 0 -000 100 9 3 14 16 288 Clocks 49 Clocks 116 KHz 0 0 0 0 1 0 -000 101 9 3 30 32 576 Clocks 97 Clocks 58 KHz 0 0 1 0 1 0 -000 110 9 3 62 64 1152 Clocks 193 Clocks 29 KHz 0 0 0 1 1 0 -000 111 9 3 126 128 2304 Clocks 385 Clocks 14 KHz 0 0 1 1 1 0 -001 000 10 3 4 1 30 Clocks 9 Clocks 1111 KHz1 0 0 0 0 0 -001 001 10 3 4 2 48 Clocks 11 Clocks 694 KHz 1 0 1 0 0 0 -001 010 10 3 6 4 88 Clocks 17 Clocks 379 KHz 1 0 0 1 0 0 -001 011 10 3 6 8 160 Clocks 25 Clocks 208 KHz 1 0 1 1 0 0 -001 100 10 3 14 16 320 Clocks 49 Clocks 104 KHz 1 0 0 0 1 0 -001 101 10 3 30 32 640 Clocks 97 Clocks 52 KHz 1 0 1 0 1 0 -001 110 10 3 62 64 1280 Clocks 193 Clocks 26 KHz 1 0 0 1 1 0 -001 111 10 3 126 128 2560 Clocks 385 Clocks 13 KHz 1 0 1 1 1 0 -010 000 12 4 4 1 34 Clocks 10 Clocks 980 KHz 0 1 0 0 0 0 -010 001 12 4 4 2 56 Clocks 13 Clocks 595 KHz 0 1 1 0 0 0 -010 010 12 4 6 4 104 Clocks 21 Clocks 321 KHz 0 1 0 1 0 0 -010 011 12 4 6 8 192 Clocks 33 Clocks 174 KHz 0 1 1 1 0 0 -010 100 12 4 14 16 384 Clocks 65 Clocks 87 KHz 0 1 0 0 1 0 -010 101 12 4 30 32 768 Clocks 129 Clocks 43 KHz 0 1 1 0 1 0 -010 110 12 4 62 64 1536 Clocks 257 Clocks 22 KHz 0 1 0 1 1 0 -010 111 12 4 126 128 3072 Clocks 513 Clocks 11 KHz 0 1 1 1 1 0 -011 000 15 4 4 1 40 Clocks 10 Clocks 833 KHz 1 1 0 0 0 0 -011 001 15 4 4 2 68 Clocks 13 Clocks 490 KHz 1 1 1 0 0 0 -011 010 15 4 6 4 128 Clocks 21 Clocks 260 KHz 1 1 0 1 0 0 -011 011 15 4 6 8 240 Clocks 33 Clocks 139 KHz 1 1 1 1 0 0 -011 100 15 4 14 16 480 Clocks 65 Clocks 69 KHz 1 1 0 0 1 0 -011 101 15 4 30 32 960 Clocks 129 Clocks 35 KHz 1 1 1 0 1 0 -011 110 15 4 62 64 1920 Clocks 257 Clocks 17 KHz 1 1 0 1 1 0 -011 111 15 4 126 128 3840 Clocks 513 Clocks 9 KHz 1 1 1 1 1 0 -100 000 5 1 4 1 20 Clocks 7 Clocks 1667 KHz 0 0 0 0 0 1 -100 001 5 1 4 2 28 Clocks 7 Clocks 1190 KHz 0 0 1 0 0 1 -100 010 5 1 6 4 48 Clocks 9 Clocks 694 KHz 0 0 0 1 0 1 -100 011 5 1 6 8 80 Clocks 9 Clocks 417 KHz 0 0 1 1 0 1 -100 100 5 1 14 16 160 Clocks 17 Clocks 208 KHz 0 0 0 0 1 1 -100 101 5 1 30 32 320 Clocks 33 Clocks 104 KHz 0 0 1 0 1 1 -100 110 5 1 62 64 640 Clocks 65 Clocks 52 KHz 0 0 0 1 1 1 -100 111 5 1 126 128 1280 Clocks 129 Clocks 26 KHz 0 0 1 1 1 1 -101 000 6 1 4 1 22 Clocks 7 Clocks 1515 KHz 1 0 0 0 0 1 -101 001 6 1 4 2 32 Clocks 7 Clocks 1042 KHz 1 0 1 0 0 1 -101 010 6 1 6 4 56 Clocks 9 Clocks 595 KHz 1 0 0 1 0 1 -101 011 6 1 6 8 96 Clocks 9 Clocks 347 KHz 1 0 1 1 0 1 -101 100 6 1 14 16 192 Clocks 17 Clocks 174 KHz 1 0 0 0 1 1 -101 101 6 1 30 32 384 Clocks 33 Clocks 87 KHz 1 0 1 0 1 1 -101 110 6 1 62 64 768 Clocks 65 Clocks 43 KHz 1 0 0 1 1 1 -101 111 6 1 126 128 1536 Clocks 129 Clocks 22 KHz 1 0 1 1 1 1 -110 000 7 2 4 1 24 Clocks 8 Clocks 1389 KHz 0 1 0 0 0 1 -110 001 7 2 4 2 36 Clocks 9 Clocks 926 KHz 0 1 1 0 0 1 -110 010 7 2 6 4 64 Clocks 13 Clocks 521 KHz 0 1 0 1 0 1 -110 011 7 2 6 8 112 Clocks 17 Clocks 298 KHz 0 1 1 1 0 1 -110 100 7 2 14 16 224 Clocks 33 Clocks 149 KHz 0 1 0 0 1 1 -110 101 7 2 30 32 448 Clocks 65 Clocks 74 KHz 0 1 1 0 1 1 -110 110 7 2 62 64 896 Clocks 129 Clocks 37 KHz 0 1 0 1 1 1 -110 111 7 2 126 128 1792 Clocks 257 Clocks 19 KHz 0 1 1 1 1 1 -111 000 8 2 4 1 26 Clocks 8 Clocks 1282 KHz 1 1 0 0 0 1 -111 001 8 2 4 2 40 Clocks 9 Clocks 833 KHz 1 1 1 0 0 1 -111 010 8 2 6 4 72 Clocks 13 Clocks 463 KHz 1 1 0 1 0 1 -111 011 8 2 6 8 128 Clocks 17 Clocks 260 KHz 1 1 1 1 0 1 -111 100 8 2 14 16 256 Clocks 33 Clocks 130 KHz 1 1 0 0 1 1 -111 101 8 2 30 32 512 Clocks 65 Clocks 65 KHz 1 1 1 0 1 1 -111 110 8 2 62 64 1024 Clocks 129 Clocks 33 KHz 1 1 0 1 1 1 -111 111 8 2 126 128 2048 Clocks 257 Clocks 16 KHz 1 1 1 1 1 1 -*/ -STATUS SetI2cFDR (PSI2C pi2cRegs, int bitrate) -{ -/* Constants */ - const UINT8 div_hold[8][3] = { {9, 3}, {10, 3}, - {12, 4}, {15, 4}, - {5, 1}, {6, 1}, - {7, 2}, {8, 2} - }; - - const UINT8 scl_tap[8][2] = { {4, 1}, {4, 2}, - {6, 4}, {6, 8}, - {14, 16}, {30, 32}, - {62, 64}, {126, 128} - }; - - UINT8 mfdr_bits; - - int i = 0; - int j = 0; - - int Diff, min; - int WhichFreq, iRec, jRec; - int SCL_Period; - int SCL_Hold; - int I2C_Freq; - - I2CCDBG (L2, ("Entering getBitRate: bitrate %d pi2cRegs 0x%08x\n", - bitrate, (int) pi2cRegs, 0, 0, 0, 0)); - - if (bitrate < 0) { - I2CCDBG (NO, ("Invalid bitrate\n", 0, 0, 0, 0, 0, 0)); - return ERROR; - } - - /* Initialize */ - mfdr_bits = 0; - min = 0x7fffffff; - WhichFreq = iRec = jRec = 0; - - for (i = 0; i < 8; i++) { - for (j = 0; j < 8; j++) { - /* SCL Period = 2 * (scl2tap + [(SCL_Tap - 1) * tap2tap] + 2) - * SCL Hold = scl2tap + ((SDA_Tap - 1) * tap2tap) + 3 - * Bit Rate (I2C Freq) = System Freq / SCL Period - */ - SCL_Period = - 2 * (scl_tap[i][0] + - ((div_hold[j][0] - 1) * scl_tap[i][1]) + - 2); - - /* Now get the I2C Freq */ - I2C_Freq = DEV_CLOCK_FREQ / SCL_Period; - - /* Take equal or slower */ - if (I2C_Freq > bitrate) - continue; - - /* Take the differences */ - Diff = I2C_Freq - bitrate; - - Diff = ABS (Diff); - - /* Find the closer value */ - if (Diff < min) { - min = Diff; - WhichFreq = I2C_Freq; - iRec = i; - jRec = j; - } - - I2CCDBG (L2, - ("--- (%d,%d) I2C_Freq %d minDiff %d min %d\n", - i, j, I2C_Freq, Diff, min, 0)); - } - } - - SCL_Period = - 2 * (scl_tap[iRec][0] + - ((div_hold[jRec][0] - 1) * scl_tap[iRec][1]) + 2); - - I2CCDBG (L2, ("\nmin %d WhichFreq %d iRec %d jRec %d\n", - min, WhichFreq, iRec, jRec, 0, 0)); - I2CCDBG (L2, ("--- scl2tap %d SCL_Tap %d tap2tap %d\n", - scl_tap[iRec][0], div_hold[jRec][0], scl_tap[iRec][1], - 0, 0, 0)); - - /* This may no require */ - SCL_Hold = - scl_tap[iRec][0] + - ((div_hold[jRec][1] - 1) * scl_tap[iRec][1]) + 3; - I2CCDBG (L2, - ("--- SCL_Period %d SCL_Hold %d\n", SCL_Period, SCL_Hold, 0, - 0, 0, 0)); - - I2CCDBG (L2, ("--- mfdr_bits %x\n", mfdr_bits, 0, 0, 0, 0, 0)); - - /* FDR 4,3,2 */ - if ((iRec & 1) == 1) - mfdr_bits |= 0x04; /* FDR 2 */ - if ((iRec & 2) == 2) - mfdr_bits |= 0x08; /* FDR 3 */ - if ((iRec & 4) == 4) - mfdr_bits |= 0x10; /* FDR 4 */ - /* FDR 5,1,0 */ - if ((jRec & 1) == 1) - mfdr_bits |= 0x01; /* FDR 0 */ - if ((jRec & 2) == 2) - mfdr_bits |= 0x02; /* FDR 1 */ - if ((jRec & 4) == 4) - mfdr_bits |= 0x20; /* FDR 5 */ - - I2CCDBG (L2, ("--- mfdr_bits %x\n", mfdr_bits, 0, 0, 0, 0, 0)); - - pi2cRegs->fdr = mfdr_bits; - - return OK; -} diff -rupN u-boot-all.git/cpu/mpc8220/i2cCore.h u-boot-all-8220- dramsetup/cpu/mpc8220/i2cCore.h --- u-boot-all.git/cpu/mpc8220/i2cCore.h 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-dramsetup/cpu/mpc8220/i2cCore.h 1969-12-31 18:00:00.000000000 -0600 @@ -1,103 +0,0 @@ -/* - * i2cCore.h - * - * Prototypes, etc. for the Motorola MPC8220 - * embedded cpu chips - * - * 2004 (c) Freescale, Inc. - * Author: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __INCi2ccoreh -#define __INCi2ccoreh -#ifndef __ASSEMBLY__ -/* device types */ -#define I2C_DEVICE_TYPE_EEPROM 0 -#define I2C_EEPROM_ADRS 0xa0 -#define I2C_CTRL_ADRS I2C_EEPROM_ADRS -#define EEPROM_ADDR0 0xA2 /* on Dimm SPD eeprom */ -#define EEPROM_ADDR1 0xA4 /* on Board SPD eeprom */ -#define EEPROM_ADDR2 0xD2 /* non-standard eeprom - clock generator */ -/* Control Register */ -#define I2C_CTL_EN 0x80 /* I2C Enable */ -#define I2C_CTL_IEN 0x40 /* I2C Interrupt Enable */ -#define I2C_CTL_STA 0x20 /* Master/Slave Mode select */ -#define I2C_CTL_TX 0x10 /* Transmit/Receive Mode Select */ -#define I2C_CTL_TXAK 0x08 /* Transmit Acknowledge Enable */ -#define I2C_CTL_RSTA 0x04 /* Repeat Start */ -/* Status Register */ -#define I2C_STA_CF 0x80 /* Data Transfer */ -#define I2C_STA_AAS 0x40 /* Adressed As Slave */ -#define I2C_STA_BB 0x20 /* Bus Busy */ -#define I2C_STA_AL 0x10 /* Arbitration Lost */ -#define I2C_STA_SRW 0x04 /* Slave Read/Write */ -#define I2C_STA_IF 0x02 /* I2C Interrupt */ -#define I2C_STA_RXAK 0x01 /* Receive Acknowledge */ -/* Interrupt Contol Register */ -#define I2C_INT_BNBE2 0x80 /* Bus Not Busy Enable 2 */ -#define I2C_INT_TE2 0x40 /* Transmit Enable 2 */ -#define I2C_INT_RE2 0x20 /* Receive Enable 2 */ -#define I2C_INT_IE2 0x10 /* Interrupt Enable 2 */ -#define I2C_INT_BNBE1 0x08 /* Bus Not Busy Enable 1 */ -#define I2C_INT_TE1 0x04 /* Transmit Enable 1 */ -#define I2C_INT_RE1 0x02 /* Receive Enable 1 */ -#define I2C_INT_IE1 0x01 /* Interrupt Enable 1 */ -#define I2C_POLL_COUNT 0x100000 -#define I2C_ENABLE 0x00000001 -#define I2C_DISABLE 0x00000002 -#define I2C_START 0x00000004 -#define I2C_REPSTART 0x00000008 -#define I2C_STOP 0x00000010 -#define I2C_BITRATE 0x00000020 -#define I2C_SLAVEADR 0x00000040 -#define I2C_STARTADR 0x00000080 -#undef TWOBYTES -typedef struct i2c_settings { - /* Device settings */ - int bit_rate; /* Device bit rate */ - u8 i2c_adr; /* I2C address */ - u8 slv_adr; /* Slave address */ -#ifdef TWOBYTES - u16 str_adr; /* Start address */ -#else - u8 str_adr; /* Start address */ -#endif - int xfer_size; /* Transfer Size */ - - int bI2c_en; /* Enable or Disable */ - int cmdFlag; /* I2c Command Flags */ -} i2cset_t; - -/* -int check_status(PSI2C pi2c, u8 sta_bit, u8 truefalse); -int i2c_enable(PSI2C pi2c, PI2CSET pi2cSet); -int i2c_disable(PSI2C pi2c); -int i2c_start(PSI2C pi2c, PI2CSET pi2cSet); -int i2c_stop(PSI2C pi2c); -int i2c_clear(PSI2C pi2c); -int i2c_readblock (PSI2C pi2c, PI2CSET pi2cSet, u8 *Data); -int i2c_writeblock (PSI2C pi2c, PI2CSET pi2cSet, u8 *Data); -int i2c_readbyte(PSI2C pi2c, u8 *readb, int *index); -int i2c_writebyte(PSI2C pi2c, u8 *writeb); -int SetI2cFDR( PSI2C pi2cRegs, int bitrate ); -*/ -#endif /* __ASSEMBLY__ */ - -#endif /* __INCi2ccoreh */ diff -rupN u-boot-all.git/include/mpc8220.h u-boot-all-8220- dramsetup/include/mpc8220.h --- u-boot-all.git/include/mpc8220.h 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-dramsetup/include/mpc8220.h 2007-05-10 15:34:50.000000000 -0500 @@ -689,6 +689,27 @@ typedef struct mpc8220_xcpci { #define PCI_CFG1_CLS_SHIFT 0 #define PCI_CFG1_CLS_MASK 0xf +/* + * I2C + */ +#define I2C_POLL_COUNT 0x100000 + +/* Control Register */ +#define I2C_CTL_EN 0x80 /* I2C Enable */ +#define I2C_CTL_IEN 0x40 /* I2C Interrupt Enable */ +#define I2C_CTL_STA 0x20 /* Master/Slave Mode select */ +#define I2C_CTL_TX 0x10 /* Transmit/Receive Mode Select */ +#define I2C_CTL_TXAK 0x08 /* Transmit Acknowledge Enable */ +#define I2C_CTL_RSTA 0x04 /* Repeat Start */ +/* Status Register */ +#define I2C_STA_CF 0x80 /* Data Transfer */ +#define I2C_STA_AAS 0x40 /* Adressed As Slave */ +#define I2C_STA_BB 0x20 /* Bus Busy */ +#define I2C_STA_AL 0x10 /* Arbitration Lost */ +#define I2C_STA_SRW 0x04 /* Slave Read/Write */ +#define I2C_STA_IF 0x02 /* I2C Interrupt */ +#define I2C_STA_RXAK 0x01 /* Receive Acknowledge */ + /* function prototypes */ void loadtask(int basetask, int tasks); u32 dramSetup(void);

1 0

Re: [U-Boot-Users] IXP425 ethernet & NPE microcode
by Martijn de Gouw 10 May '07

10 May '07

Hi > On Thursday 10 May 2007, Øyvind Repvik wrote: > > > And furthermore, it would be very desireable to drop the > current NPE > > > U-Boot ethernet driver implementation based on the > original Intel code > > > with the complex and ugly Intel access library completely, and > > > re-implement the driver based on the new Linux IXP4xx NPE ethernet > > > drivers. There are currently 2 completely new drivers > without the Intel > > > access library which will result in lower memory > footprint and much less > > > and cleaner code. > > > > That would be Christian Hohnstaedt > <chohnstaedt(a)innominate.com>'s driver > > which is (afaik) in mainstream by now, and > > Krzysztof Halasa <khc(a)pm.waw.pl>'s driver, which is newer. There's a > > discussion about these drivers on linux-arm-kernel. > > Yes, but IIRC the one from Christian never made it into > mainstream. And the > new one from Krzysztof seems to get quite good reactions. this driver is in the linux-2.6 tree of denx I do believe. It fetches the npe binaries out of flash. > > > Getting either of those drivers fixed up and pushed to > u-boot would be > > great. > > Yes, both would be way better than the current > implementation. Hopefully one > of those drivers will make in into mainline and this should > be the one to > pick then. > > > Of course, one will still need to put the microcode somewhere else > > due to licencing, but that's a minor matter. We have changed the intel code a little bit, that the npe microcode is read from flash. loading this binaries seperatly from u-boot is not a license violation. Right now, I'm creating a patch wich I will post later this day. Best regards, Martijn de Gouw

2 1

Re: [U-Boot-Users] IXP425 ethernet & NPE microcode
by Martijn de Gouw 10 May '07

10 May '07

Hi > We have changed the intel code a little bit, that the npe > microcode is read > from flash. loading this binaries seperatly from u-boot is not a > license violation. > > Right now, I'm creating a patch wich I will post later this day. pdnb3: trim u-boot size Signed-off-by: Micha Nelissen <micha.nelissen(a)prodrive.nl> --- commit aa380bf9caed231db860d3cbd040d049355c8dad tree 59ded6605683ef41cc6e53e9671826c53b5c908e parent 36b4fda0083606a54029d539ed838eebe26f71e2 author Micha Nelissen <micha.nelissen(a)prodrive.nl> Mon, 16 Apr 2007 11:48:31 +0200 committer Micha Nelissen <mn(a)linuxsrv1.prodrive.nl> Mon, 16 Apr 2007 11:48:31 +0200 cpu/ixp/npe/IxNpeDl.c | 312 ------------------- cpu/ixp/npe/IxNpeDlImageMgr.c | 503 ++----------------------------- cpu/ixp/npe/Makefile | 3 cpu/ixp/npe/include/IxNpeDlImageMgr_p.h | 3 cpu/ixp/npe/include/IxNpeMicrocode.h | 24 - cpu/ixp/npe/npe.c | 4 include/configs/pdnb3.h | 14 + 7 files changed, 48 insertions(+), 815 deletions(-) diff --git a/cpu/ixp/npe/IxNpeDl.c b/cpu/ixp/npe/IxNpeDl.c index ffe355c..4bddb78 100644 --- a/cpu/ixp/npe/IxNpeDl.c +++ b/cpu/ixp/npe/IxNpeDl.c @@ -106,212 +106,7 @@ static BOOL ixNpeDlNpeStarted[IX_NPEDL_N * static function prototypes. */ PRIVATE IX_STATUS -ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, UINT32 imageId); - -/* - * Function definition: ixNpeDlMicrocodeImageLibraryOverride - */ -PUBLIC IX_STATUS -ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlMicrocodeImageLibraryOverride\n"); - - if (clientImageLibrary == NULL) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlMicrocodeImageLibraryOverride - " - "invalid parameter\n"); - } - else - { - status = ixNpeDlImageMgrMicrocodeImageLibraryOverride (clientImageLibrary); - if (status != IX_SUCCESS) - { - status = IX_FAIL; - } - } /* end of if-else(clientImageLibrary) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlMicrocodeImageLibraryOverride : " - "status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlImageDownload - */ -PUBLIC IX_STATUS -ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr, - BOOL verify) -{ - UINT32 imageSize; - UINT32 *imageCodePtr = NULL; - IX_STATUS status; - IxNpeDlNpeId npeId = imageIdPtr->npeId; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageDownload\n"); - - ixNpeDlStats.attemptedDownloads++; - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageDownload - invalid parameter\n"); - } - else - { - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } - } /* end of if(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEB) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEC) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - } /* end of if(IX_FEATURE_CTRL_SILICON_TYPE_B0) */ /*End of Silicon Type Check*/ - - /* stop and reset the NPE */ - if (IX_SUCCESS != ixNpeDlNpeStopAndReset (npeId)) - { - IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n"); - return IX_FAIL; - } - - /* Locate image */ - status = ixNpeDlImageMgrImageLocate (imageIdPtr, &imageCodePtr, - &imageSize); - if (IX_SUCCESS == status) - { - /* - * If download was successful, store image Id in list of - * currently loaded images. If a critical error occured - * during download, record that the NPE has an invalid image - */ - status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, - verify); - if (IX_SUCCESS == status) - { - ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = TRUE; - ixNpeDlStats.successfulDownloads++; - - status = ixNpeDlNpeExecutionStart (npeId); - } - else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) || - (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) - { - ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = FALSE; - ixNpeDlStats.criticalFailDownloads++; - } - } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */ - } /* end of if-else(npeId) */ /* condition: parameter checks ok */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageDownload : status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlAvailableImagesCountGet - */ -PUBLIC IX_STATUS -ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlAvailableImagesCountGet\n"); - - /* Check input parameters */ - if (numImagesPtr == NULL) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesCountGet - " - "invalid parameter\n"); - } - else - { - /* - * Use ImageMgr module to get no. of images listed in Image Library Header. - * If NULL is passed as imageListPtr parameter to following function, - * it will only fill number of images into numImagesPtr - */ - status = ixNpeDlImageMgrImageListExtract (NULL, numImagesPtr); - } /* end of if-else(numImagesPtr) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlAvailableImagesCountGet : " - "status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlAvailableImagesListGet - */ -PUBLIC IX_STATUS -ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr, - UINT32 *listSizePtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlAvailableImagesListGet\n"); - - /* Check input parameters */ - if ((imageIdListPtr == NULL) || (listSizePtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesListGet - " - "invalid parameter\n"); - } - else - { - /* Call ImageMgr to get list of images listed in Image Library Header */ - status = ixNpeDlImageMgrImageListExtract (imageIdListPtr, - listSizePtr); - } /* end of if-else(imageIdListPtr) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlAvailableImagesListGet : status = %d\n", - status); - return status; -} +ixNpeDlNpeInitAndStartInternal (UINT32 imageId); /* * Function definition: ixNpeDlLoadedImageGet @@ -386,80 +181,6 @@ ixNpeDlLoadedImageGet (IxNpeDlNpeId npeI } /* - * Function definition: ixNpeDlLatestImageGet - */ -PUBLIC IX_STATUS -ixNpeDlLatestImageGet ( - IxNpeDlNpeId npeId, - IxNpeDlFunctionalityId functionalityId, - IxNpeDlImageId *imageIdPtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlLatestImageGet\n"); - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || - (npeId < 0) || - (imageIdPtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlLatestImageGet - " - "invalid parameter\n"); - } /* end of if(npeId) */ - else - { - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEB && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEC && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - } /* end of if not IXP42x-A0 silicon */ - - imageIdPtr->npeId = npeId; - imageIdPtr->functionalityId = functionalityId; - imageIdPtr->major = IMAGEID_MAJOR_NUMBER_DEFAULT; - imageIdPtr->minor = IMAGEID_MINOR_NUMBER_DEFAULT; - /* Call ImageMgr to get list of images listed in Image Library Header */ - status = ixNpeDlImageMgrLatestImageExtract(imageIdPtr); - } /* end of if-else(npeId) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlLatestImageGet : status = %d\n", - status); - - return status; -} - -/* * Function definition: ixNpeDlNpeStopAndReset */ PUBLIC IX_STATUS @@ -770,8 +491,7 @@ ixNpeDlStatsReset (void) * Function definition: ixNpeDlNpeInitAndStartInternal */ PRIVATE IX_STATUS -ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, - UINT32 imageId) +ixNpeDlNpeInitAndStartInternal (UINT32 imageId) { UINT32 imageSize; UINT32 *imageCodePtr = NULL; @@ -863,8 +583,7 @@ ixNpeDlNpeInitAndStartInternal (UINT32 * } /* Locate image */ - status = ixNpeDlImageMgrImageFind (imageLibrary, imageId, - &imageCodePtr, &imageSize); + status = ixNpeDlImageMgrImageFind (imageId, &imageCodePtr, &imageSize); if (IX_SUCCESS == status) { /* @@ -908,35 +627,12 @@ ixNpeDlNpeInitAndStartInternal (UINT32 * } /* - * Function definition: ixNpeDlCustomImageNpeInitAndStart - */ -PUBLIC IX_STATUS -ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary, - UINT32 imageId) -{ - IX_STATUS status; - - if (imageLibrary == NULL) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlCustomImageNpeInitAndStart " - "- invalid parameter\n"); - } - else - { - status = ixNpeDlNpeInitAndStartInternal (imageLibrary, imageId); - } /* end of if-else(imageLibrary) */ - - return status; -} - -/* * Function definition: ixNpeDlNpeInitAndStart */ PUBLIC IX_STATUS ixNpeDlNpeInitAndStart (UINT32 imageId) { - return ixNpeDlNpeInitAndStartInternal (NULL, imageId); + return ixNpeDlNpeInitAndStartInternal (imageId); } /* diff --git a/cpu/ixp/npe/IxNpeDlImageMgr.c b/cpu/ixp/npe/IxNpeDlImageMgr.c index e05c228..2ebc22b 100644 --- a/cpu/ixp/npe/IxNpeDlImageMgr.c +++ b/cpu/ixp/npe/IxNpeDlImageMgr.c @@ -133,369 +133,9 @@ typedef struct */ static IxNpeDlImageMgrStats ixNpeDlImageMgrStats; -/* default image */ -#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE -static UINT32 *IxNpeMicroCodeImageLibrary = NULL; /* Gets set to proper value at runtime */ -#else -static UINT32 *IxNpeMicroCodeImageLibrary = (UINT32 *)IxNpeMicrocode_array; -#endif - - -/* - * static function prototypes. - */ -PRIVATE BOOL -ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary); - -PRIVATE void -ixNpeDlImageMgrImageIdFormat (UINT32 rawImageId, IxNpeDlImageId *imageId); - -PRIVATE BOOL -ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB); - -PRIVATE BOOL -ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB); - -PRIVATE IX_STATUS -ixNpeDlImageMgrImageFind_legacy (UINT32 *imageLibrary, - UINT32 imageId, - UINT32 **imagePtr, - UINT32 *imageSize); - -/* - * Function definition: ixNpeDlImageMgrMicrocodeImageLibraryOverride - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrMicrocodeImageLibraryOverride ( - UINT32 *clientImageLibrary) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrMicrocodeImageLibraryOverride\n"); - - if (ixNpeDlImageMgrSignatureCheck (clientImageLibrary)) - { - IxNpeMicroCodeImageLibrary = clientImageLibrary; - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrMicrocodeImageLibraryOverride: " - "Client-supplied image has invalid signature\n"); - status = IX_FAIL; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrMicrocodeImageLibraryOverride: status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlImageMgrImageListExtract - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrImageListExtract ( - IxNpeDlImageId *imageListPtr, - UINT32 *numImages) -{ - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - IX_STATUS status = IX_SUCCESS; - UINT32 imageCount = 0; - IxNpeDlImageMgrImageLibraryHeader *header; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageListExtract\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) IxNpeMicroCodeImageLibrary; - - if (ixNpeDlImageMgrSignatureCheck (IxNpeMicroCodeImageLibrary)) - { - /* for each image entry in the image header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - /* - * if the image list container from calling function has capacity, - * add the image id to the list - */ - if ((imageListPtr != NULL) && (imageCount < *numImages)) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - imageListPtr[imageCount] = formattedImageId; - } - /* imageCount reflects no. of image entries in image library header */ - imageCount++; - } - - /* - * if image list container from calling function was too small to - * contain all image ids in the header, set return status to FAIL - */ - if ((imageListPtr != NULL) && (imageCount > *numImages)) - { - status = IX_FAIL; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: " - "number of Ids found exceeds list capacity\n"); - ixNpeDlImageMgrStats.imageIdListOverflow++; - } - /* return number of image ids found in image library header */ - *numImages = imageCount; - } - else - { - status = IX_FAIL; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: " - "invalid signature in image\n"); - } +static IX_STATUS ixNpeDlImageMgrImageFindAtAddr( + UINT32 *imageLibrary, UINT32 imageId, UINT32 **imagePtr, UINT32 *imageSize); - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageListExtract: status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlImageMgrImageLocate - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrImageLocate ( - IxNpeDlImageId *imageId, - UINT32 **imagePtr, - UINT32 *imageSize) -{ - UINT32 imageOffset; - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - /* used to index image entries in image library header */ - UINT32 imageCount = 0; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageLocate\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) IxNpeMicroCodeImageLibrary; - - if (ixNpeDlImageMgrSignatureCheck (IxNpeMicroCodeImageLibrary)) - { - /* for each image entry in the image library header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - /* if a match for imageId is found in the image library header... */ - if (ixNpeDlImageMgrImageIdCompare (imageId, &formattedImageId)) - { - /* - * get pointer to the image in the image library using offset from - * 1st word in image library - */ - imageOffset = header->entry[imageCount].image.offset; - *imagePtr = &IxNpeMicroCodeImageLibrary[imageOffset]; - /* get the image size */ - *imageSize = header->entry[imageCount].image.size; - status = IX_SUCCESS; - break; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageLocate: status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlImageMgrLatestImageExtract - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId) -{ - UINT32 imageCount = 0; - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrLatestImageExtract\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) IxNpeMicroCodeImageLibrary; - - if (ixNpeDlImageMgrSignatureCheck (IxNpeMicroCodeImageLibrary)) - { - /* for each image entry in the image library header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - /* - * if a match for the npe Id and functionality Id of the imageId is - * found in the image library header... - */ - if(ixNpeDlImageMgrNpeFunctionIdCompare(imageId, &formattedImageId)) - { - if(imageId->major <= formattedImageId.major) - { - if(imageId->minor < formattedImageId.minor) - { - imageId->minor = formattedImageId.minor; - } - imageId->major = formattedImageId.major; - } - status = IX_SUCCESS; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageExtract: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageGet: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrLatestImageGet: status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlImageMgrSignatureCheck - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary) -{ - IxNpeDlImageMgrImageLibraryHeader *header = - (IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary; - BOOL result = TRUE; - - if (header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE) - { - result = FALSE; - ixNpeDlImageMgrStats.invalidSignature++; - } - - return result; -} - - -/* - * Function definition: ixNpeDlImageMgrImageIdFormat - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE void -ixNpeDlImageMgrImageIdFormat ( - UINT32 rawImageId, - IxNpeDlImageId *imageId) -{ - imageId->npeId = (rawImageId >> - IX_NPEDL_IMAGEID_NPEID_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->functionalityId = (rawImageId >> - IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->major = (rawImageId >> - IX_NPEDL_IMAGEID_MAJOR_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->minor = (rawImageId >> - IX_NPEDL_IMAGEID_MINOR_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - -} - - -/* - * Function definition: ixNpeDlImageMgrImageIdCompare - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrImageIdCompare ( - IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB) -{ - if ((imageIdA->npeId == imageIdB->npeId) && - (imageIdA->functionalityId == imageIdB->functionalityId) && - (imageIdA->major == imageIdB->major) && - (imageIdA->minor == imageIdB->minor)) - { - return TRUE; - } - else - { - return FALSE; - } -} - -/* - * Function definition: ixNpeDlImageMgrNpeFunctionIdCompare - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrNpeFunctionIdCompare ( - IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB) -{ - if ((imageIdA->npeId == imageIdB->npeId) && - (imageIdA->functionalityId == imageIdB->functionalityId)) - { - return TRUE; - } - else - { - return FALSE; - } -} - - /* * Function definition: ixNpeDlImageMgrStatsShow */ @@ -528,143 +168,62 @@ ixNpeDlImageMgrStatsReset (void) /* - * Function definition: ixNpeDlImageMgrImageFind_legacy - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE + * Function definition: ixNpeDlImageMgrImageFind */ -PRIVATE IX_STATUS -ixNpeDlImageMgrImageFind_legacy ( - UINT32 *imageLibrary, +IX_STATUS +ixNpeDlImageMgrImageFind ( UINT32 imageId, UINT32 **imagePtr, UINT32 *imageSize) { - UINT32 imageOffset; - /* used to index image entries in image library header */ - UINT32 imageCount = 0; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - BOOL imageFound = FALSE; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageFind\n"); - - - /* If user didn't specify a library to use, use the default - * one from IxNpeMicrocode.h - */ - if (imageLibrary == NULL) - { - imageLibrary = IxNpeMicroCodeImageLibrary; - } - - if (ixNpeDlImageMgrSignatureCheck (imageLibrary)) - { - header = (IxNpeDlImageMgrImageLibraryHeader *) imageLibrary; + UINT32 *imageLib1, *imageLib2; + IX_STATUS ret; - /* for each image entry in the image library header ... */ - while ((header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) && !(imageFound)) - { - /* if a match for imageId is found in the image library header... */ - if (imageId == header->entry[imageCount].image.id) - { - /* - * get pointer to the image in the image library using offset from - * 1st word in image library - */ - imageOffset = header->entry[imageCount].image.offset; - *imagePtr = &imageLibrary[imageOffset]; - /* get the image size */ - *imageSize = header->entry[imageCount].image.size; - status = IX_SUCCESS; - imageFound = TRUE; - } - imageCount++; - } - if (status != IX_SUCCESS) - { + switch (imageId) { + case IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL: + case IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS: + imageLib1 = (UINT32*)CONFIG_NPE_B_ADDR1; + imageLib2 = (UINT32*)CONFIG_NPE_B_ADDR2; + break; + case IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL: + case IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS: + imageLib1 = (UINT32*)CONFIG_NPE_C_ADDR1; + imageLib2 = (UINT32*)CONFIG_NPE_C_ADDR2; + break; + default: IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " "imageId not found in image library header\n"); ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "invalid signature in image library\n"); + /* reached end of library, image not found */ + return IX_FAIL; } - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageFind: status = %d\n", status); - return status; + ret = ixNpeDlImageMgrImageFindAtAddr(imageLib1, imageId, imagePtr, imageSize); + if (ret != IX_SUCCESS) + ret = ixNpeDlImageMgrImageFindAtAddr(imageLib2, imageId, imagePtr, imageSize); + return ret; } - -/* - * Function definition: ixNpeDlImageMgrImageFind - */ -IX_STATUS -ixNpeDlImageMgrImageFind ( +static IX_STATUS +ixNpeDlImageMgrImageFindAtAddr ( UINT32 *imageLibrary, UINT32 imageId, UINT32 **imagePtr, UINT32 *imageSize) { IxNpeDlImageMgrImageHeader *image; - UINT32 offset = 0; - /* If user didn't specify a library to use, use the default - * one from IxNpeMicrocode.h - */ - if (imageLibrary == NULL) + if (*imageLibrary == NPE_IMAGE_MARKER) { -#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE - if (ixNpeMicrocode_binaryArray == NULL) - { - printk (KERN_ERR "ixp400.o: ERROR, no Microcode found in memory\n"); - return IX_FAIL; - } - else - { - imageLibrary = ixNpeMicrocode_binaryArray; - } -#else - imageLibrary = IxNpeMicroCodeImageLibrary; -#endif /* IX_NPEDL_READ_MICROCODE_FROM_FILE */ - } - - /* For backward's compatibility with previous image format */ - if (ixNpeDlImageMgrSignatureCheck(imageLibrary)) - { - return ixNpeDlImageMgrImageFind_legacy(imageLibrary, - imageId, - imagePtr, - imageSize); - } - - while (*(imageLibrary+offset) == NPE_IMAGE_MARKER) - { - image = (IxNpeDlImageMgrImageHeader *)(imageLibrary+offset); - offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(UINT32); + image = (IxNpeDlImageMgrImageHeader *)imageLibrary; + imageLibrary += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(UINT32); if (image->id == imageId) { - *imagePtr = imageLibrary + offset; + *imagePtr = imageLibrary; *imageSize = image->size; return IX_SUCCESS; } - /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */ - else if (image->id == NPE_IMAGE_MARKER) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - /* reached end of library, image not found */ - return IX_FAIL; - } - offset += image->size; } /* If we get here, our image library may be corrupted */ diff --git a/cpu/ixp/npe/Makefile b/cpu/ixp/npe/Makefile index 4de34fd..4ad1184 100644 --- a/cpu/ixp/npe/Makefile +++ b/cpu/ixp/npe/Makefile @@ -53,13 +53,13 @@ COBJS := npe.o \ IxEthDBHashtable.o \ IxEthDBLearning.o \ IxEthDBMem.o \ + IxEthDBVlan.o \ IxEthDBNPEAdaptor.o \ IxEthDBPortUpdate.o \ IxEthDBReports.o \ IxEthDBSearch.o \ IxEthDBSpanningTree.o \ IxEthDBUtil.o \ - IxEthDBVlan.o \ IxEthDBWiFi.o \ IxEthMii.o \ IxQMgrAqmIf.o \ @@ -72,7 +72,6 @@ COBJS := npe.o \ IxNpeDlImageMgr.o \ IxNpeDlNpeMgr.o \ IxNpeDlNpeMgrUtils.o \ - IxNpeMicrocode.o \ IxNpeMh.o \ IxNpeMhConfig.o \ IxNpeMhReceive.o \ diff --git a/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h b/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h index 622f879..a5592c1 100644 --- a/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h +++ b/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h @@ -350,8 +350,7 @@ ixNpeDlImageMgrStatsReset (void); * - IX_FAIL otherwise */ IX_STATUS -ixNpeDlImageMgrImageFind (UINT32 *imageLibrary, - UINT32 imageId, +ixNpeDlImageMgrImageFind (UINT32 imageId, UINT32 **imagePtr, UINT32 *imageSize); diff --git a/cpu/ixp/npe/include/IxNpeMicrocode.h b/cpu/ixp/npe/include/IxNpeMicrocode.h index 893d803..c17f2d2 100644 --- a/cpu/ixp/npe/include/IxNpeMicrocode.h +++ b/cpu/ixp/npe/include/IxNpeMicrocode.h @@ -267,30 +267,6 @@ extern unsigned IxNpeMicrocode_array[]; #endif #endif -/* - * sr: undef all but the bare minimum to reduce flash usage for U-Boot - */ -#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0 -#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT -#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT -#undef IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT -#undef IX_NPEDL_NPEIMAGE_NPEA_DMA -#undef IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT -#undef IX_NPEDL_NPEIMAGE_NPEA_ETH -#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL -#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS -#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV -#undef IX_NPEDL_NPEIMAGE_NPEB_ETH -#undef IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL -/* #undef IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS */ -#undef IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV -#undef IX_NPEDL_NPEIMAGE_NPEB_DMA -#undef IX_NPEDL_NPEIMAGE_NPEC_ETH -#undef IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL -/* #undef IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS */ -#undef IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV -#undef IX_NPEDL_NPEIMAGE_NPEC_DMA - /** * @} defgroup IxNpeMicrocode */ diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c index ab7ca8b..c37ac62 100644 --- a/cpu/ixp/npe/npe.c +++ b/cpu/ixp/npe/npe.c @@ -310,14 +310,14 @@ static int npe_csr_load(void) } if (npe_used[IX_ETH_PORT_1] && npe_exists[IX_ETH_PORT_1] && - ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIRE WALL_VLAN_QOS) + ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIRE WALL) != IX_SUCCESS) { printf("Error downloading firmware to NPE-B!\n"); return 0; } if (npe_used[IX_ETH_PORT_2] && npe_exists[IX_ETH_PORT_2] && - ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIRE WALL_VLAN_QOS) + ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIRE WALL) != IX_SUCCESS) { printf("Error downloading firmware to NPE-C!\n"); return 0; diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index e23f0cb..b99b65f 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -40,6 +40,10 @@ #define CONFIG_DISPLAY_BOARDINFO 1 /* di * Ethernet */ #define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ +#define CONFIG_NPE_B_ADDR1 0x5003a000 +#define CONFIG_NPE_B_ADDR2 0x50078000 +#define CONFIG_NPE_C_ADDR1 0x5003d000 +#define CONFIG_NPE_C_ADDR2 0x5007c000 #define CONFIG_NET_MULTI 1 #define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */ #define CONFIG_HAS_ETH1 @@ -72,14 +76,14 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_BAUDRATE 115200 #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & \ + ~(CFG_CMD_LOADB | \ + CFG_CMD_LOADS)) | \ CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ CFG_CMD_NET | \ CFG_CMD_MII | \ CFG_CMD_NAND | \ CFG_CMD_I2C | \ - CFG_CMD_ELF | \ CFG_CMD_PING) /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -178,7 +182,7 @@ #define PHYS_SDRAM_1_SIZE 0x020000 #define CFG_FLASH_BASE 0x50000000 #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (472 << 10) /* Reserve 472 kB for Monitor */ +#define CFG_MONITOR_LEN (224 << 10) /* U-boot size */ /* * Expansion bus settings @@ -199,7 +203,7 @@ #define CFG_SDRAM_REFRESH_CNT 0x81a #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ Best regards, Martijn de Gouw

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[U-Boot-Users] [PATCH] Update to stand alone program feature
by Jeff Mann 10 May '07

10 May '07

[PATCH] Update to stand alone program feature This patch contains updates to the stand alone program feature, including: 1. update and document new features in README.standalone 2. add SA= flag to allow for the stand alone program directory to be selected for compiling with u-boot 3. added xf_func_inc() function. See documentation for a description. 4. removal of undesired #ifdef...#endif statements 5. Note: XF_VERSION was not advanced. This will happen in the next patch in this series. This feature does not seem to fall into any category in the list of U-Boot Custodians, so I guess it goes to you, Wolfgang. The patch file is attached. -Jeffrey Mann

4 6

[U-Boot-Users] U-boot & MonteJade start up
by Jonathan Pratt 10 May '07

10 May '07

I'm trying to get u-boot up and running on an Intel MonteJade (IXDPG425) board without much luck. I downloaded version 2.0 of the Npe code and placed it in the appropriate directory and the build worked fine. Getting it up and running on the board has proved more difficulat. I'm using a Macraigor USB wiggler to download to the FLASH. If anyone has done this successfully then I would appreciate some pointers as I'm not sure what I've done thus far is correct. As far as I understand it, the xscale starts up in little endian mode. The application is, however, big-endian. When I program the FLASH it appears to be big-endian, and I don't as yet understand where the transition from little endian occurs. The u-boot code in the current state doesn't go anywhere with no response from the serial port. Is there some pre-bootloader code which does the transition to big-endian? If so, do I need to program this sepeartely? If not, where does the transition to big-endian occur and why does the code I see (in the srec file, for example) appear to start off big-endian? I can imagine ld getting pretty confused trying to link a little-endian snippet to a big-endian application. Thanks Jonathan Pratt ELPRO Technologies Pty Ltd "Wireless Solutions Since 1983" ISO 9001:2000 Accredited ABN 17 010 627 835 9/12 Billabong St, Stafford, QLD, Australia 4053 Telephone: +61 7 3352 4533 Facsimile: +61 7 3352 4577 Web Site: http://www.elprotech.com

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[U-Boot-Users] MPC832xEMDS: ttyS0 output stops mid boot
by Alex Zeffertt 10 May '07

10 May '07

Hi, Sorry about the cross posting, but I'm not sure which list I should send to.... I'm trying to boot an up-to-date kernel on my MPC8323E-MDS-PB board, but I the console output stops early on during the kernel boot. I'm running the latest u-boot (git://www.denx.de/git/u-boot-mpc83xx.git) with its default environment. The kernel is built from Paulus' powerpc.git, after checking out tag 2.6.21-rc5. The dtb is build from arch/powerpc/boot/dts/mpc832x_mds.dts with the latest compiler (git://www.jdl.com/software/dtc.git). Has anyone else been here before...? If so I'd appreciate any help you can offer. TIA, Alex -------------------my ttyS0 output------------------ => => printenv bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr bootdelay=6 baudrate=115200 loads_echo=1 ethaddr=00:04:9f:ef:03:01 eth1addr=00:04:9f:ef:03:02 loadaddr=200000 netdev=eth0 consoledev=ttyS0 ramdiskaddr=1000000 ramdiskfile=ramfs.83xx fdtaddr=400000 fdtfile=mpc832xemds.dtb stdin=serial stdout=serial stderr=serial ethact=FSL UEC0 Environment size: 979/8188 bytes => setenv ramdiskfile uRamdisk => setenv fdtfile mpc832x_mds.dtb => setenv bootfile uImage => setenv serverip 10.0.0.107 => setenv ipaddr 10.0.6.65 => run ramboot Using FSL UEC0 device TFTP from server 10.0.0.107; our IP address is 10.0.6.65 Filename 'uRamdisk'. Load address: 0x1000000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ########################################################### done Bytes transferred = 3296770 (324e02 hex) Using FSL UEC0 device TFTP from server 10.0.0.107; our IP address is 10.0.6.65 Filename 'uImage'. Load address: 0x200000 Loading: ################################################################# ################################################################# ################################################################# ########################################## done Bytes transferred = 1212615 (1280c7 hex) Using FSL UEC0 device TFTP from server 10.0.0.107; our IP address is 10.0.6.65 Filename 'mpc832x_mds.dtb'. Load address: 0x400000 Loading: ### done Bytes transferred = 12288 (3000 hex) ## Booting image at 00200000 ... Image Name: Linux-2.6.21-rc5 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 1212551 Bytes = 1.2 MB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK ## Loading RAMDisk Image at 01000000 ... Image Name: uboot ext2 ramdisk rootfs Image Type: PowerPC Linux RAMDisk Image (gzip compressed) Data Size: 3296706 Bytes = 3.1 MB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Booting using flat device tree at 0x400000 Loading Ramdisk to 07c87000, end 07fabdc2 ... OK Using MPC832x MDS machine description Linux version 2.6.21-rc5 (ajz@zambia) (gcc version 3.4.3) #2 Thu May 3 16:42:54 BST 2007 Found initrd at 0xc7c87000:0xc7fabdc2 setup_arch: bootmem mpc832x_sys_setup_arch() Found MPC83xx PCI host bridge at 0x00000000e0008500. Firmware bus number: 0->0 arch: exit Zone PFN ranges: DMA 0 -> 32768 Normal 32768 -> 32768 early_node_map[1] active PFN ranges 0: 0 -> 32768 Built 1 zonelists. Total pages: 32512 Kernel command line: root=/dev/ram rw console=ttyS0,115200 IPIC (128 IRQ sources) at fddf3700 QEIC (64 IRQ sources) at fddf2080 PID hash table entries: 512 (order: 9, 2048 bytes)

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[U-Boot-Users] Unable to boot linux on ARM based board: gunzip hangs
by Pharaoh . 10 May '07

10 May '07

Hi, I am trying to make Linux work on omap 850 based board which has an ARM926EJS. I have u-boot ported and installed on it and minimal linux support for the board is also there. The kernel image is in format expected by u-boot and I have followed all the needed steps like using mkimage etc. While uncompressing the linux image the system hangs, in gunzip function which is defined in inflate.c. No error is returned, it just hangs. I have checked whether the image overwrites itself after uncompression, but it does not since the addresses etc are given appropriately. I am thinking may be the DDR SDRAM might not be initialized properly (like refresh rate etc), but then how come u-boot is running properly? Any pointers? -pharaoh.

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[U-Boot-Users] USB device configuration
by Rodolfo Giometti 09 May '07

09 May '07

Hello, during my PXA27x USB device support developing adventure I notice that usbtty calls the functions: udc_init: PXA27x usbd start udc_setup_ep: setting up endpoint addr 0 udc_enable: enable device a2077f74, status 0 udc_connect: udc_setup_ep: setting up endpoint addr 1 udc_setup_ep: setting up endpoint addr 82 udc_setup_ep: setting up endpoint addr 83 Looking at PXA27x manual I read that I have to setup the endpoints and __then__ enable UDC for normal operations! But looking above I see that u-boot calls before the udc_enable() and then the function udc_setup_ep()... There are something wrong or I haven't understood well how UDC support works? =:-o Thanks, Rodolfo -- GNU/Linux Solutions e-mail: giometti(a)enneenne.com Linux Device Driver giometti(a)gnudd.com Embedded Systems giometti(a)linux.it UNIX programming phone: +39 349 2432127

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[U-Boot-Users] [PATCH] tsec: Fix PHY code to match first driver
by Andy Fleming 09 May '07

09 May '07

Jarrold Wen noticed that the generic PHY code always matches under the current implementation. Change it so the first match wins, and *only* unknown PHYs trigger the generic driver Signed-off-by: Andy Fleming <afleming(a)freescale.com> --- A third apology for bad tabs. I'll keep better tabs on in the future, I swear. drivers/tsec.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/tsec.c b/drivers/tsec.c index 693328d..31a0aba 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1327,8 +1327,10 @@ struct phy_info *get_phy_info(struct eth_device *dev) /* loop through all the known PHY types, and find one that */ /* matches the ID we read from the PHY. */ for (i = 0; phy_info[i]; i++) { - if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) + if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { theInfo = phy_info[i]; + break; + } } if (theInfo == NULL) { -- 1.5.0.2.230.gfbe3d-dirty

1 0

[U-Boot-Users] [PATCH] Fix Marvell 88e1145 PHY init code
by Andy Fleming 09 May '07

09 May '07

Fix a bug in the Marvell 88e1145 PHY init code in the TSEC driver where the reset was being done after the errata code instead of before. Signed-off-by: Haiying Wang <haiying.wang(a)freescale.com> Signed-off-by: Andy Fleming <afleming(a)freescale.com> --- This one was sent to me a bit ago, but I lost it. It's going in unless there are objections. And again, sorry for the space/tab thing drivers/tsec.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/tsec.c b/drivers/tsec.c index b418773..693328d 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1012,14 +1012,16 @@ static struct phy_info phy_info_M88E1145 = { "Marvell 88E1145", 4, (struct phy_cmd[]){ /* config */ + /* Reset the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + /* Errata E0, E1 */ {29, 0x001b, NULL}, {30, 0x418f, NULL}, {29, 0x0016, NULL}, {30, 0xa2da, NULL}, - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + /* Configure the PHY */ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, -- 1.5.0.2.230.gfbe3d-dirty

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[U-Boot-Users] [PATCH] Add support for CPM device tree configuration to 8560 ADS
by Andy Fleming 09 May '07

09 May '07

* Adds code to modify CPM frequencies * Cleans up the config file to #define TSEC and (for now) #undef FCC * Adds the MII command for all 8560 ADS configurations * Updates config file to provide convenience commands for booting with a device tree Signed-off-by: Vitaly Bordug <vbordug(a)ru.mvista.com> Signed-off-by: Andy Fleming <afleming(a)freescale.com> --- I apologize for the previous version with spaces for tabs. Gmail apparently substitutes things. board/mpc8560ads/mpc8560ads.c | 26 ++++++++++++++++++++++++++ include/configs/MPC8560ADS.h | 32 +++++++++++++++++++++----------- 2 files changed, 47 insertions(+), 11 deletions(-) diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index d19bad6..41acb97 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -550,8 +550,34 @@ pci_init_board(void) #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) void +ft_soc_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + ulong data; + + p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len); + + if (p != NULL) + *p = cpu_to_be32(bd->bi_brgfreq); + + p = ft_get_prop(blob, + "/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed", + &len); + if (p != NULL) + *p = cpu_to_be32(bd->bi_baudrate); + + p = ft_get_prop(blob, + "/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed", + &len); + if (p != NULL) + *p = cpu_to_be32(bd->bi_baudrate); +} + +void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + ft_soc_setup(blob, bd); } #endif diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 21e6637..f16e39d 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -43,9 +43,7 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -349,13 +347,16 @@ #endif /* CONFIG_PCI */ -#if defined(CONFIG_TSEC_ENET) +#ifdef CONFIG_TSEC_ENET #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 #endif +#ifndef CONFIG_MII #define CONFIG_MII 1 /* MII PHY management */ +#endif + #define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_MPC85XX_TSEC2 1 @@ -369,9 +370,10 @@ /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ +#endif /* CONFIG_TSEC_ENET */ + +#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ #undef CONFIG_ETHER_NONE /* define if ether on something else */ #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ @@ -392,7 +394,10 @@ #define FETH3_RST 0x80 #endif /* CONFIG_ETHER_INDEX */ -#define CONFIG_MII /* MII PHY management */ +#ifndef CONFIG_MII +#define CONFIG_MII 1 /* MII PHY management */ +#endif + #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ /* @@ -458,11 +463,13 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PCI \ | CFG_CMD_PING \ + | CFG_CMD_MII \ | CFG_CMD_I2C) #elif defined(CONFIG_TSEC_ENET) #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PING \ - | CFG_CMD_I2C) + | CFG_CMD_I2C \ + | CFG_CMD_MII) #elif defined(CONFIG_ETHER_ON_FCC) #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_MII \ @@ -554,8 +561,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc8560ads.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -563,7 +572,8 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ -- 1.5.0.2.230.gfbe3d-dirty

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[U-Boot-Users] [PATCH] Fix Marvell 88e1145 PHY init code
by Andy Fleming 09 May '07

09 May '07

Fix a bug in the Marvell 88e1145 PHY init code in the TSEC driver where the reset was being done after the errata code instead of before. Signed-off-by: Haiying Wang <haiying.wang(a)freescale.com> Signed-off-by: Andy Fleming <afleming(a)freescale.com> --- This one was sent to me a bit ago, but I lost it. It's going in unless there are objections. drivers/tsec.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/tsec.c b/drivers/tsec.c index b418773..693328d 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1012,14 +1012,16 @@ static struct phy_info phy_info_M88E1145 = { "Marvell 88E1145", 4, (struct phy_cmd[]){ /* config */ + /* Reset the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + /* Errata E0, E1 */ {29, 0x001b, NULL}, {30, 0x418f, NULL}, {29, 0x0016, NULL}, {30, 0xa2da, NULL}, - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + /* Configure the PHY */ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, -- 1.5.0.2.230.gfbe3d-dirty

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[U-Boot-Users] [ERR] U-Boot-Users Digest, Vol 12, Issue 34
by postmaster＠paran.com 09 May '07

09 May '07

Transmit Report: To: kmkh12(a)paran.com, 452 Requested action not taken: insufficient system storage.[9,-1,50][err=File::write Bad file descriptor]

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[U-Boot-Users] [PATCH] Add support for CPM device tree configuration to 8560 ADS
by Andy Fleming 09 May '07

09 May '07

* Adds code to modify CPM frequencies * Cleans up the config file to #define TSEC and (for now) #undef FCC * Adds the MII command for all 8560 ADS configurations * Updates config file to provide convenience commands for booting with a device tree Signed-off-by: Vitaly Bordug <vbordug(a)ru.mvista.com> Signed-off-by: Andy Fleming <afleming(a)freescale.com> --- This makes the 8560 ADS boot for me. It doesn't do anything about large ramdisks, though. I'm still looking into that. board/mpc8560ads/mpc8560ads.c | 26 ++++++++++++++++++++++++++ include/configs/MPC8560ADS.h | 32 +++++++++++++++++++++----------- 2 files changed, 47 insertions(+), 11 deletions(-) diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index d19bad6..41acb97 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -550,8 +550,34 @@ pci_init_board(void) #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) void +ft_soc_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + ulong data; + + p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len); + + if (p != NULL) + *p = cpu_to_be32(bd->bi_brgfreq); + + p = ft_get_prop(blob, + "/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed", + &len); + if (p != NULL) + *p = cpu_to_be32(bd->bi_baudrate); + + p = ft_get_prop(blob, + "/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed", + &len); + if (p != NULL) + *p = cpu_to_be32(bd->bi_baudrate); +} + +void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + ft_soc_setup(blob, bd); } #endif diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 21e6637..f16e39d 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -43,9 +43,7 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -349,13 +347,16 @@ #endif /* CONFIG_PCI */ -#if defined(CONFIG_TSEC_ENET) +#ifdef CONFIG_TSEC_ENET #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 #endif +#ifndef CONFIG_MII #define CONFIG_MII 1 /* MII PHY management */ +#endif + #define CONFIG_MPC85XX_TSEC1 1 #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_MPC85XX_TSEC2 1 @@ -369,9 +370,10 @@ /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ +#endif /* CONFIG_TSEC_ENET */ + +#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ #undef CONFIG_ETHER_NONE /* define if ether on something else */ #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ @@ -392,7 +394,10 @@ #define FETH3_RST 0x80 #endif /* CONFIG_ETHER_INDEX */ -#define CONFIG_MII /* MII PHY management */ +#ifndef CONFIG_MII +#define CONFIG_MII 1 /* MII PHY management */ +#endif + #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ /* @@ -458,11 +463,13 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PCI \ | CFG_CMD_PING \ + | CFG_CMD_MII \ | CFG_CMD_I2C) #elif defined(CONFIG_TSEC_ENET) #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PING \ - | CFG_CMD_I2C) + | CFG_CMD_I2C \ + | CFG_CMD_MII) #elif defined(CONFIG_ETHER_ON_FCC) #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_MII \ @@ -554,8 +561,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc8560ads.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -563,7 +572,8 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ -- 1.5.0.2.230.gfbe3d-dirty

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[U-Boot-Users] [PATCH] 8641hpcn: Fix Makefile after moving pixis to board/freescale.
by Jon Loeliger 09 May '07

09 May '07

From: Ed Swarthout <Ed.Swarthout(a)freescale.com> The OBJTREE != SRCTREE build scenario was broken. This fixes it. Signed-off-by: Ed Swarthout <Ed.Swarthout(a)freescale.com> Signed-off-by: Jon Loeliger <jdl(a)freescale.com> --- Hey jdl, Please pick this up for the 86xx custodian tree. jdl board/mpc8641hpcn/Makefile | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 9625211..df56b31 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -23,6 +23,10 @@ include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../freescale/common) +endif + LIB = $(obj)lib$(BOARD).a COBJS := $(BOARD).o sys_eeprom.o \ -- 1.5.0.3

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[U-Boot-Users] [PATCH] 8544ds: Fix Makefile after moving pixis to board/freescale.
by Jon Loeliger 09 May '07

09 May '07

From: Ed Swarthout <Ed.Swarthout(a)freescale.com> The OBJTREE != SRCTREE build scenario was broken. This fixes it. Signed-off-by: Ed Swarthout <Ed.Swarthout(a)freescale.com> Signed-off-by: Jon Loeliger <jdl(a)freescale.com> --- Andy, Please pick this up for the 85xx custodian tree. jdl board/freescale/mpc8544ds/Makefile | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index bec2168..308f707 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -24,9 +24,9 @@ include $(TOPDIR)/config.mk -# ifneq ($(OBJTREE),$(SRCTREE)) -# $(shell mkdir -p $(obj)./common) -# endif +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).a -- 1.5.0.3

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[U-Boot-Users] POST
by Maximus 09 May '07

09 May '07

Hi, My hardware has an sd/mmc card. I need to write a few tests to check if the card is connected and working before loading linux. any ideas how one should go abt it?. are there any basic tests for mmc card?. any pointers?. Regards, Jo

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Re: [U-Boot-Users] PATCH add SMN42 board from Siemens
by Peter Pearse 09 May '07

09 May '07

Dear list (This is a repeat mail with the patch tarred and bzipped to meet the list limit) Anyone (other than Gary) who can test this patch on a Siemens SMN42 or lpc2292sodimm board please let me know the results. Perhaps someone would like to volunteer as maintainer for either or both....... Regards Peter Pearse

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Re: [U-Boot-Users] Flash Erase/Write error in uboot
by Shiju Mathew 08 May '07

08 May '07

On Sat, 2007-05-05 at 08:48 -0500, Andrew Dyer wrote: > On 5/4/07, Shiju Mathew <mshiju(a)gmail.com> wrote: > > I was debugging the problem further. We have two other bootloaders running > > on this board - redboot and Eboot. Both does not have this problem. Only on > > Uboot I am experiencing this problem. On debugging what I could find is that > > when I erase a sector, the function flash_is_busy() returns immidiatly with > > success(not busy). Usually it should loop for a while in this function > > before returning that the flash is not busy. Before writing to the erased > > sector, the "md" command displayed 0xffffffff for the erased sector. But > > when I tried to write data to the erased location using cp.b, the function > > flash_write_cfiword() returns with error "flash is not erased" since it > > failed to find 0xffffffff in the erased locations(Check if Flash is > > (sufficiently) erased). So why does "md" displays 0xffffffff for erased > > locations and flash routine says it is not 0xffffffff ? Could someone > > I suspect the code is reading the status word instead of the array > data. You have to be careful with handling the array, as there is no > separate status port, so the status data will show up as read data if > you aren't careful. > > One thing you might check is to make sure the flash 'timeout' variable > isn't getting set to zero. I found a problem with this a long time > ago - it had to do with how the CFI timeout data (reported in usec) > was being converted to a value for timeout (in msec). If timeout was > zero, the status read stuff would time out before reding the data the > second time through. I think was fixed, but it's worth checking. > Thanks for all your comments. I could get a few sector erase/write success if I reduce the system clock to 398 MHz and bus speed to 66 MHz and also make the below changes for erase status check. Previouly it was running at 532 MHz/133 MHz (CPU/bus).Now I could update uboot without any problem. But if I try to erase/write large no: of sectors, says 100 sectors, it fails with the same error as before. So I think the problem is realated to timming. #define TIMEOUT 10000000 timeout = TIMEOUT; while (1) { if (flash_isset (info, sect, 0, 0x08)) { debug("Operation complete\n"); break; } if (!timeout--) { printf("Operation Timed Out!!n"); break; } } timeout = TIMEOUT; while (1) { if (flash_isset (info, sect, 0, FLASH_STATUS_DONE)) { debug("Flash erase done\n"); break; } if (!timeout--) { printf("Erase Timed Out!!\n"); break; } } > Check how CS configuration etc. is correctly configured. If it is > working with the extension board not installed but not obviously you > have something wrong. It could be that your CS1 configuration is > incorrect. Possibilities are endless. But I do not see this as a > flash > driver issue. If I disconnected the extension board, I don't have any issues. I could also run the system at 532/133 MHz without any flash write issues. The problem happens when the load increases on the bus. I made sure that the CS are configured right.I disabled CS1( where extension board is connected) without any success. > Wow, 3 bootloaders for one board! What luxury. :) > We got eboot and redboot along with the board. But we want to move to uboot to support all the OS runnning on the board because of its feature rich and has good support from the community. Thanks, Shiju

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Re: [U-Boot-Users] tftp alignment exception
by Dongying_Xu＠us.alphanetworks.com 08 May '07

08 May '07

Hi Does anyone experienced TFTP alignment problem? I am using MPC8347 with 64bits DDR2 memory, when I tftp files, it will throw alignment exception. It happens more frequently on big size file. Anyone have any suggestions? Thanks Best Regards dongy

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