May 2007 - U-Boot

[U-Boot-Users] cache and buffer problems
by chark_uboot＠126.com 16 May '07

16 May '07

Hi, I got a problem about cache and write buffer after I download the u-boot.bin to my board (s3c4510),I found that I can't erase the Flash (at49bv1614) any more ,so the u-boot is still running on my board I can't erase it . First I think it is caused by the Flash sector locked , but I check the status by software , it shows that it isn't be locked . So I think about write buffer and cache ,maybe my erase command cannot arrive flash,but in write buffer. from the datasheet ,it seems that s3c4510 can't close the cache while it is working untill system reset and clear the cache enable bit in SYSCFG register . but after reset ,u-boot enable cache again . plz tell me how to erase the flash or disable the cache. thx!

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[U-Boot-Users] FLASH: flash_init function returns size correctly ?
by Lucas Cyrulski 16 May '07

16 May '07

Hi, I'm still working to get ATMEL flash working with u-boot, my target board is at91rm9200ek. My u-boot source code version is 1.1.6. There is a function in flash.c file in u-boot/board/atmel/at91rm9200ek: ulong flash_init( void) it calculates flash size and stores it in flash_info.size field and then returns this value. But it is not a physical size of flash ( 2Mbits x 16bits organisation = 32Mbits), only a size that this flash takes in address memory space which is 2Mbits. Is this correct ?? I'm concerned about that because when I worked with this source code, I encountered many errors. It seemed like a person who wrote it did not even try to check if it works on hardware. I'm wondering if it is another mistake or it is how u-boot gets info about flash size on board. Thanks for any replies and regards Lucas

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[U-Boot-Users] [PATCH 2/2] NAND: Add mpc831x support.
by Scott Wood 16 May '07

16 May '07

Signed-off-by: Nick Spence <nick.spence(a)freescale.com> Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- cpu/mpc83xx/Makefile | 2 +- cpu/mpc83xx/nand-831x.c | 764 +++++++++++++++++++++++++++++++++++++++++ include/configs/MPC8313ERDB.h | 4 +- 3 files changed, 768 insertions(+), 2 deletions(-) create mode 100644 cpu/mpc83xx/nand-831x.c diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index bb96f77..e698a02 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - spd_sdram.o qe_io.o pci.o + spd_sdram.o qe_io.o pci.o nand-831x.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc83xx/nand-831x.c b/cpu/mpc83xx/nand-831x.c new file mode 100644 index 0000000..4319128 --- /dev/null +++ b/cpu/mpc83xx/nand-831x.c @@ -0,0 +1,764 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * + * Authors: Nick.Spence(a)freescale.com + * Wilson.Lo(a)freescale.com + * scottwood(a)freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#ifdef CFG_NAND_MPC831X +#if defined(CFG_NAND_LEGACY) +#error "U-Boot legacy NAND commands not supported." +#endif + +#include <malloc.h> +#include <asm/errno.h> +#include <nand.h> + +#undef CFG_FCM_DEBUG +#define CFG_FCM_DEBUG_LVL 5 +#ifdef CFG_FCM_DEBUG +#define FCM_DEBUG(n, args...) \ + do { \ + if (n <= CFG_FCM_DEBUG_LVL) \ + printf(args); \ + } while (0) +#else /* CONFIG_FCM_DEBUG */ +#define FCM_DEBUG(n, args...) do { } while (0) +#endif + +#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ +#define FCM_TIMEOUT_USECS 100000 /* Maximum number of uSecs to wait for FCM */ + +/* Private structure holding NAND Flash device specific information */ +struct fcm_nand { + int bank; /* Chip select bank number */ + uint base; /* Chip select base address */ + int pgs; /* NAND page size */ + uint page; /* Last page written to / read from */ + uint fmr; /* FCM Flash Mode Register value */ + uint mdr; /* UPM/FCM Data Register value */ + uint use_mdr; /* Non zero if the MDR is to be set */ + u8 *addr; /* Address of assigned FCM buffer */ + uint read_bytes; /* Number of bytes read during command */ + uint index; /* Pointer to next byte to 'read' */ + uint req_bytes; /* Number of bytes read if command ok */ + uint req_index; /* New read index if command ok */ + uint status; /* status read from LTESR after last op*/ + int use_ecc; /* If non-zero, use ECC on next xfer */ +}; + + +/* These map to the positions used by the FCM hardware ECC generator */ + +/* Small Page FLASH with FMR[ECCM] = 0 */ +static struct nand_oobinfo fcm_oob_sp_eccm0 = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 3, + .eccpos = {6, 7, 8}, + .oobfree = { {0, 5}, {9, 7} } +}; + +/* Small Page FLASH with FMR[ECCM] = 1 */ +static struct nand_oobinfo fcm_oob_sp_eccm1 = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 3, + .eccpos = {8, 9, 10}, + .oobfree = { {0, 5}, {6, 2}, {11, 5} } +}; + +/* Large Page FLASH with FMR[ECCM] = 0 */ +static struct nand_oobinfo fcm_oob_lp_eccm0 = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 12, + .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, + .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} } +}; + +/* Large Page FLASH with FMR[ECCM] = 1 */ +static struct nand_oobinfo fcm_oob_lp_eccm1 = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 12, + .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, + .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} } +}; + +/* + * execute FCM command and wait for it to complete + */ +static int fcm_run_command(struct mtd_info *mtd) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc = &im->lbus; + struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + long long end_tick; + + /* Setup the FMR[OP] to execute without write protection */ + lbc->fmr = fcm->fmr | 3; + if (fcm->use_mdr) + lbc->mdr = fcm->mdr; + + FCM_DEBUG(5, "fcm_run_command: fmr= %08X fir= %08X fcr= %08X\n", + lbc->fmr, lbc->fir, lbc->fcr); + FCM_DEBUG(5, "fcm_run_command: fbar=%08X fpar=%08X fbcr=%08X bank=%d\n", + lbc->fbar, lbc->fpar, lbc->fbcr, fcm->bank); + + /* clear event registers */ + lbc->lteatr = 0; + lbc->ltesr |= LTESR_FCT | LTESR_PAR | LTESR_CC; + + /* execute special operation */ + lbc->lsor = fcm->bank; + + /* wait for FCM complete flag or timeout */ + fcm->status = 0; + end_tick = usec2ticks(FCM_TIMEOUT_USECS) + get_ticks(); + + while (end_tick > get_ticks()) { + if (lbc->ltesr & LTESR_CC) { + fcm->status = lbc->ltesr & + (LTESR_FCT | LTESR_PAR | LTESR_CC); + break; + } + } + + /* store mdr value in case it was needed */ + if (fcm->use_mdr) + fcm->mdr = lbc->mdr; + + fcm->use_mdr = 0; + + FCM_DEBUG(5, "fcm_run_command: stat=%08X mdr= %08X fmr= %08X\n", + fcm->status, fcm->mdr, lbc->fmr); + + /* if the operation completed ok then set the read buffer pointers */ + if (fcm->status == LTESR_CC) { + fcm->read_bytes = fcm->req_bytes; + fcm->index = fcm->req_index; + return 0; + } + + printf("831x NAND flash: "); + + if (fcm->status & LTESR_FCT) { + printf("Timeout"); + + if (fcm->status & LTESR_PAR) + printf(", "); + } + + if (fcm->status & LTESR_PAR) + printf("ECC error"); + + printf("\n"); + return -1; +} + +/* + * Set up the FCM hardware block and page address fields, and the fcm + * structure addr field to point to the correct FCM buffer in memory + */ +static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc = &im->lbus; + struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + int buf_num; + + fcm->page = page_addr; + + lbc->fbar = page_addr >> (this->phys_erase_shift - this->page_shift); + if (fcm->pgs) { + lbc->fpar = ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | + (oob ? FPAR_LP_MS : 0) | column; + buf_num = (page_addr & 1) << 2; + } else { + lbc->fpar = ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | + (oob ? FPAR_SP_MS : 0) | column; + buf_num = page_addr & 7; + } + + fcm->addr = (u8 *)(fcm->base + buf_num * 1024); + + /* for OOB data point to the second half of the buffer */ + if (oob) + fcm->addr += fcm->pgs ? 2048 : 512; +} + +/* not required for FCM */ +static void fcm_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ +} + +/* + * FCM does not support 16 bit data busses + */ +static u16 fcm_read_word(struct mtd_info *mtd) +{ + printf("fcm_read_word: UNIMPLEMENTED.\n"); + return 0; +} + +static void fcm_write_word(struct mtd_info *mtd, u16 word) +{ + printf("fcm_write_word: UNIMPLEMENTED.\n"); +} + +/* + * Write buf to the FCM Controller Data Buffer + */ +static void fcm_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + + FCM_DEBUG(3, "fcm_write_buf: writing %d bytes starting with 0x%x" + " at %d.\n", len, *((u32 *)buf), fcm->index); + + /* copy the data into the FCM hardware buffer and update the index */ + memcpy(&fcm->addr[fcm->index], buf, len); + fcm->index += len; +} + + +/* + * FCM does not support individual writes. Instead these are either commands + * or data being written, both of which are handled through the cmdfunc + * handler. + */ +static void fcm_write_byte(struct mtd_info *mtd, u8 byte) +{ + printf("fcm_write_byte: UNIMPLEMENTED.\n"); +} + +/* + * read a byte from either the FCM hardware buffer if it has any data left + * otherwise issue a command to read a single byte. + */ +static u8 fcm_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + u8 byte; + + /* If there are still bytes in the FCM then use the next byte */ + if (fcm->index < fcm->read_bytes) { + byte = fcm->addr[fcm->index++]; + FCM_DEBUG(4, "fcm_read_byte: byte %u (%02X): %d of %d.\n", + byte, byte, fcm->index - 1, fcm->read_bytes); + return byte; + } + + return ERR_BYTE; +} + +/* + * Read from the FCM Controller Data Buffer + */ +static void fcm_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + + FCM_DEBUG(3, "fcm_read_buf: reading %d bytes.\n", len); + + /* If last read failed then return error bytes */ + if (fcm->status != LTESR_CC) { + /* just keep copying bytes so that the oob works */ + memcpy(buf, &fcm->addr[fcm->index], len); + fcm->index += len; + return; + } + + len = min(len, fcm->read_bytes - fcm->index); + + memcpy(buf, &fcm->addr[fcm->index], len); + fcm->index += len; +} + +/* + * Verify buffer against the FCM Controller Data Buffer + */ +static int fcm_verify_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + + FCM_DEBUG(3, "fcm_verify_buf: checking %d bytes starting with 0x%02x.\n", + len, *((u32 *)buf)); + + /* If last read failed then return error bytes */ + if (fcm->status != LTESR_CC) + return -EFAULT; + + /* see how much is still in the FCM buffer */ + if ((uint)len > fcm->read_bytes - fcm->index) + return -EFAULT; + + if (memcmp(buf, &fcm->addr[fcm->index], len)) { + fcm->index += len; + return -EFAULT; + } + + fcm->index += len; + return 0; +} + +/* This function is called after Program and Erase Operations to + * check for success or failure + */ +static int fcm_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc = &im->lbus; + struct fcm_nand *fcm = this->priv; + + if (fcm->status != LTESR_CC) + return 1; /* Status Read error */ + + /* Use READ_STATUS command, but wait for the device to be ready */ + fcm->use_mdr = 0; + fcm->req_index = 0; + fcm->read_bytes = 0; + fcm->index = 0; + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_RBW << FIR_OP1_SHIFT); + lbc->fcr = NAND_CMD_STATUS << FCR_CMD0_SHIFT; + set_addr(mtd, 0, 0, 0); + lbc->fbcr = 1; + fcm->req_bytes = 1; + fcm_run_command(mtd); + + if (fcm->status != LTESR_CC) + return 1; /* Status Read error */ + + return fcm_read_byte(mtd); +} + +/* cmdfunc send commands to the FCM */ +static void fcm_cmdfunc(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc = &im->lbus; + struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + + fcm->use_mdr = 0; + fcm->req_index = 0; + + /* clear the read buffer */ + fcm->read_bytes = 0; + if (command != NAND_CMD_PAGEPROG) + fcm->index = 0; + + switch (command) { + /* READ0 reads the entire buffer to use hardware ECC. */ + case NAND_CMD_READ0: + FCM_DEBUG(2, "fcm_cmdfunc: NAND_CMD_READ0, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + fcm->req_index = column; + + if (fcm->pgs) { + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RBW << FIR_OP4_SHIFT); + } else { + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_RBW << FIR_OP3_SHIFT); + } + lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | + (NAND_CMD_READSTART << FCR_CMD1_SHIFT); + + fcm->req_bytes = mtd->oobblock + mtd->oobsize; + + if (fcm->use_ecc) + lbc->fbcr = 0; /* read entire page to enable ECC */ + else + lbc->fbcr = fcm->req_bytes; + + set_addr(mtd, 0, page_addr, 0); + goto write_cmd2; + + /* READOOB read only the OOB becasue no ECC is performed */ + case NAND_CMD_READOOB: + FCM_DEBUG(2, "fcm_cmdfunc: NAND_CMD_READOOB, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + if (fcm->pgs) { + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RBW << FIR_OP4_SHIFT); + lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | + (NAND_CMD_READSTART << FCR_CMD1_SHIFT); + } else { + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_RBW << FIR_OP3_SHIFT); + lbc->fcr = NAND_CMD_READOOB << FCR_CMD0_SHIFT; + } + lbc->fbcr = mtd->oobsize - column; + set_addr(mtd, column, page_addr, 1); + goto write_cmd1; + + /* READID must read all 5 possible bytes while CEB is active */ + case NAND_CMD_READID: + FCM_DEBUG(2, "fcm_cmdfunc: NAND_CMD_READID.\n"); + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_UA << FIR_OP1_SHIFT) | + (FIR_OP_RBW << FIR_OP2_SHIFT); + lbc->fcr = NAND_CMD_READID << FCR_CMD0_SHIFT; + lbc->fbcr = 5; /* 5 bytes for manuf, device and exts */ + fcm->use_mdr = 1; + fcm->mdr = 0; + goto write_cmd0; + + /* ERASE1 stores the block and page address */ + case NAND_CMD_ERASE1: + FCM_DEBUG(2, "fcm_cmdfunc: NAND_CMD_ERASE1, page_addr:" + " 0x%x.\n", page_addr); + set_addr(mtd, 0, page_addr, 0); + return; + + /* ERASE2 uses the block and page address from ERASE1 */ + case NAND_CMD_ERASE2: + FCM_DEBUG(2, "fcm_cmdfunc: NAND_CMD_ERASE2.\n"); + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_PA << FIR_OP1_SHIFT) | + (FIR_OP_CM1 << FIR_OP2_SHIFT); + lbc->fcr = (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | + (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT); + lbc->fbcr = 0; + goto write_cmd1; + + /* SEQIN sets up the addr buffer and all registers except the length */ + case NAND_CMD_SEQIN: + FCM_DEBUG(2, "fcm_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + if (column == 0) { + lbc->fbcr = 0; /* write entire page to enable ECC */ + } else { + lbc->fbcr = 1; /* mark as partial page so no HW ECC */ + } + if (fcm->pgs) { + /* always use READ0 for large page devices */ + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_WB << FIR_OP3_SHIFT) | + (FIR_OP_CW1 << FIR_OP4_SHIFT); + lbc->fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | + (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); + set_addr(mtd, column, page_addr, 0); + } else { + lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CM2 << FIR_OP1_SHIFT) | + (FIR_OP_CA << FIR_OP2_SHIFT) | + (FIR_OP_PA << FIR_OP3_SHIFT) | + (FIR_OP_WB << FIR_OP4_SHIFT) | + (FIR_OP_CW1 << FIR_OP5_SHIFT); + if (column >= mtd->oobblock) { + /* OOB area --> READOOB */ + column -= mtd->oobblock; + lbc->fcr = (NAND_CMD_READOOB << FCR_CMD0_SHIFT) + | (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) + | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); + set_addr(mtd, column, page_addr, 1); + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) + | (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) + | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); + set_addr(mtd, column, page_addr, 0); + } else { + /* Second 256 bytes --> READ1 */ + column -= 256; + lbc->fcr = (NAND_CMD_READ1 << FCR_CMD0_SHIFT) + | (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) + | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); + set_addr(mtd, column, page_addr, 0); + } + } + return; + + /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ + case NAND_CMD_PAGEPROG: + FCM_DEBUG(2, "fcm_cmdfunc: NAND_CMD_PAGEPROG" + " writing %d bytes.\n", fcm->index); + /* if the write did not start at 0 or is not a full page */ + /* then set the exact length, otherwise use a full page */ + /* write so the HW generates the ECC. */ + if (lbc->fbcr || fcm->index != mtd->oobblock + mtd->oobsize || + !fcm->use_ecc) + lbc->fbcr = fcm->index; + fcm->req_bytes = 0; + goto write_cmd2; + + /* CMD_STATUS must read the status byte while CEB is active */ + /* Note - it does not wait for the ready line */ + case NAND_CMD_STATUS: + FCM_DEBUG(2, "fcm_cmdfunc: NAND_CMD_STATUS.\n"); + lbc->fir = (FIR_OP_CM0 << FIR_OP0_SHIFT) | + (FIR_OP_RBW << FIR_OP1_SHIFT); + lbc->fcr = NAND_CMD_STATUS << FCR_CMD0_SHIFT; + lbc->fbcr = 1; + goto write_cmd0; + + /* RESET without waiting for the ready line */ + case NAND_CMD_RESET: + FCM_DEBUG(2, "fcm_cmdfunc: NAND_CMD_RESET.\n"); + lbc->fir = FIR_OP_CM0 << FIR_OP0_SHIFT; + lbc->fcr = NAND_CMD_RESET << FCR_CMD0_SHIFT; + lbc->fbcr = 0; + goto write_cmd0; + + default: + printk("fcm_cmdfunc: error, unsupported command.\n"); + return; + } + + /* Short cuts fall through to save code */ + write_cmd0: + set_addr(mtd, 0, 0, 0); + write_cmd1: + fcm->req_bytes = lbc->fbcr; + write_cmd2: + fcm_run_command(mtd); +} + +static void fcm_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + + fcm->use_ecc = 1; +} + +/* + * fcm_correct_data - Detect and correct bit error(s) + * The detection and correction is done automatically by the hardware, + * if the complete page was read. If the status code is okay then there + * was no error, otherwise we return an error code indicating an uncorrectable + * error. + */ +static int fcm_correct_data(struct mtd_info *mtd, u8 *dat, u8 *read_ecc, u8 *calc_ecc) +{ + struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + + /* No errors */ + if (fcm->status == LTESR_CC) + return 0; + + return -1; /* uncorrectable error */ +} + +/* + * Dummy scan_bbt to complete setup of the FMR based on NAND size + */ +static int fcm_scan_bbt (struct mtd_info *mtd) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc = &im->lbus; + struct nand_chip *this = mtd->priv; + struct fcm_nand *fcm = this->priv; + uint al; + + if (!fcm) { + printk (KERN_ERR "fcm_scan_bbt():" \ + " Failed to allocate chip specific data structure\n"); + return -1; + } + + /* calculate FMR Address Length field */ + al = 0; + if (this->pagemask & 0xffff0000) + al++; + if (this->pagemask & 0xff000000) + al++; + + /* add to ECCM mode set in fcm_init */ + fcm->fmr |= 12 << FMR_CWTO_SHIFT | /* Timeout > 12 mSecs */ + al << FMR_AL_SHIFT; + + FCM_DEBUG(1, "fcm_init: nand->options = %08X\n", this->options); + FCM_DEBUG(1, "fcm_init: nand->numchips = %10d\n", this->numchips); + FCM_DEBUG(1, "fcm_init: nand->chipsize = %10d\n", this->chipsize); + FCM_DEBUG(1, "fcm_init: nand->pagemask = %10X\n", this->pagemask); + FCM_DEBUG(1, "fcm_init: nand->eccmode = %10d\n", this->eccmode); + FCM_DEBUG(1, "fcm_init: nand->eccsize = %10d\n", this->eccsize); + FCM_DEBUG(1, "fcm_init: nand->eccbytes = %10d\n", this->eccbytes); + FCM_DEBUG(1, "fcm_init: nand->eccsteps = %10d\n", this->eccsteps); + FCM_DEBUG(1, "fcm_init: nand->chip_delay = %8d\n", this->chip_delay); + FCM_DEBUG(1, "fcm_init: nand->badblockpos = %7d\n", this->badblockpos); + FCM_DEBUG(1, "fcm_init: nand->chip_shift = %8d\n", this->chip_shift); + FCM_DEBUG(1, "fcm_init: nand->page_shift = %8d\n", this->page_shift); + FCM_DEBUG(1, "fcm_init: nand->phys_erase_shift = %2d\n", + this->phys_erase_shift); + FCM_DEBUG(1, "fcm_init: mtd->flags = %08X\n", mtd->flags); + FCM_DEBUG(1, "fcm_init: mtd->size = %10d\n", mtd->size); + FCM_DEBUG(1, "fcm_init: mtd->erasesize = %10d\n", mtd->erasesize); + FCM_DEBUG(1, "fcm_init: mtd->oobblock = %10d\n", mtd->oobblock); + FCM_DEBUG(1, "fcm_init: mtd->oobsize = %10d\n", mtd->oobsize); + FCM_DEBUG(1, "fcm_init: mtd->oobavail = %10d\n", mtd->oobavail); + FCM_DEBUG(1, "fcm_init: mtd->ecctype = %10d\n", mtd->ecctype); + FCM_DEBUG(1, "fcm_init: mtd->eccsize = %10d\n", mtd->eccsize); + + /* adjust Option Register and ECC to match Flash page size */ + if (mtd->oobblock == 512) + lbc->bank[fcm->bank].or &= ~(OR_FCM_PGS); + else if (mtd->oobblock == 2048) { + lbc->bank[fcm->bank].or |= OR_FCM_PGS; + /* adjust ecc setup if needed */ + if ((lbc->bank[fcm->bank].br & BR_DECC) == BR_DECC_CHK_GEN) { + mtd->eccsize = 2048; + mtd->oobavail -= 9; + this->eccsize = 2048; + this->eccbytes += 9; + this->eccsteps = 1; + this->autooob = (fcm->fmr & FMR_ECCM) ? + &fcm_oob_lp_eccm1 : &fcm_oob_lp_eccm0; + memcpy(&mtd->oobinfo, this->autooob, + sizeof(mtd->oobinfo)); + } + } else { + printf("fcm_init: page size %d is not supported\n", + mtd->oobblock); + return -1; + } + + fcm->pgs = (lbc->bank[fcm->bank].or >> OR_FCM_PGS_SHIFT) & 1; + + /* restore default scan_bbt function and call it */ + this->scan_bbt = nand_default_bbt; + return nand_default_bbt(mtd); +} + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand_new.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +int board_nand_init(struct nand_chip *nand) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc = &im->lbus; + struct fcm_nand *fcm; + uint bank; + + /* Enable FCM detection of timeouts, ECC errors and completion */ + lbc->ltedr &= ~(LTESR_FCT | LTESR_PAR | LTESR_CC); + + fcm = kmalloc (sizeof(struct fcm_nand), GFP_KERNEL); + if (!fcm) { + printk (KERN_ERR "board_nand_init():" \ + " Cannot allocate read buffer data structure\n"); + return -1; + } + + /* Find which chip select bank is being used for this device */ + for (bank = 0; bank < 8; bank++) { + /* Not valid */ + if (!(lbc->bank[bank].br & BR_V)) + continue; + + /* Not NAND */ + if ((lbc->bank[bank].br & BR_MSEL) != BR_MS_FCM) + continue; + + /* Wrong address */ + if ((lbc->bank[bank].br & BR_BA) != + ((u32)(nand->IO_ADDR_R) & lbc->bank[bank].or & OR_FCM_AM)) + continue; + + fcm->bank = bank; + fcm->fmr = FMR_ECCM; /* rest filled in later */ + fcm->fmr = 0; /* rest filled in later */ + fcm->read_bytes = 0; + fcm->index = 0; + fcm->pgs = (lbc->bank[bank].or >> OR_FCM_PGS_SHIFT) & 1; + fcm->base = lbc->bank[bank].br & BR_BA; + fcm->addr = (u8 *)fcm->base; + nand->priv = fcm; + break; + } + + if (!nand->priv) { + printk (KERN_ERR "board_nand_init():" \ + " Could not find matching Chip Select\n"); + return -1; + } + + /* set up nand options */ + nand->options = NAND_NO_AUTOINCR; + /* set up function call table */ + nand->hwcontrol = fcm_hwcontrol; + nand->waitfunc = fcm_wait; + nand->read_byte = fcm_read_byte; + nand->write_byte = fcm_write_byte; + nand->read_word = fcm_read_word; + nand->write_word = fcm_write_word; + nand->read_buf = fcm_read_buf; + nand->verify_buf = fcm_verify_buf; + nand->write_buf = fcm_write_buf; + nand->cmdfunc = fcm_cmdfunc; + nand->scan_bbt = fcm_scan_bbt; + + /* If CS Base Register selects full hardware ECC then use it */ + if (((lbc->bank[bank].br & BR_DECC) >> BR_DECC_SHIFT) == 2) { + /* put in small page settings and adjust later if needed */ + nand->eccmode = NAND_ECC_TRANSPARENT; + nand->autooob = (fcm->fmr & FMR_ECCM) ? + &fcm_oob_sp_eccm1 : &fcm_oob_sp_eccm0; + nand->enable_hwecc = fcm_enable_hwecc; + nand->correct_data = fcm_correct_data; + } else { + /* otherwise fall back to default software ECC */ + nand->eccmode = NAND_ECC_SOFT; + } + + return 0; +} + +#endif diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 2519c6b..536f9ce 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -200,6 +200,7 @@ #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ /* drivers/nand/nand.c */ +#define CFG_NAND_MPC831X #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 @@ -355,7 +356,8 @@ | CFG_CMD_I2C \ | CFG_CMD_MII \ | CFG_CMD_DATE \ - | CFG_CMD_PCI) + | CFG_CMD_PCI \ + | CFG_CMD_NAND) #define CONFIG_CMDLINE_EDITING 1 -- 1.5.0.3

1 0

[U-Boot-Users] u-boot for PXA270
by 白栋贤 16 May '07

16 May '07

Dear all, I am John , and I met a problem about uboot migrate for PXA270. My modification as following: 1 add my board johnPxa in Makefile johnPxa_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa270 johnPxa 2 add my board directory under board/ with board/lubbock cp -a lubbock johnPxa 3 add johnPxa.h under include/configs/ with lubbock.h cp lubbock.h johnPxa.h and modified it as my board's configuration. 4 add pxa270 directory under cpu/ with cpu/pxa cp -a pxa pxa270 5 modified config.mk under cpu/pxa270/ PLATFORM_CPPFLAGS += -mapcs-32 -march=armv5 -mtune=xscale 6 add my board information into mach-types.h 7 modified start.S(cpu/pxa270) with blob's start.S and xlli_LowLev_Init.s ps: this blob could run on my board. and I compiled with arm-linux-gcc 3.4.1 At last the u-boot.bin couldn't run on my board. Could you give me some help, thank you very much. Best regards John _________________________________________________________________ 免费下载 MSN Explorer: http://explorer.msn.com/lccn

4 3

[U-Boot-Users] [PATCH] cfi_flash.c: use addr2info
by Ladislav Michl 16 May '07

16 May '07

Hi, cfi_flash.c is providing functionality already present elsewhere as addr2info (in common/flash.c). Lets sava few bytes by using it. Btw, I'm considering name flash_get_info a bit more descriptive than addr2info... I'll eventually send renaming patch on top of this one. Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> Use addr2info instead of private flash_get_info. diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index 5579a1e..0536e20 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -196,9 +196,6 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, ulong tout, char *prompt); ulong flash_get_size (ulong base, int banknum); -#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) -static flash_info_t *flash_get_info(ulong base); -#endif #ifdef CFG_FLASH_USE_BUFFER_WRITE static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len); #endif @@ -401,7 +398,7 @@ unsigned long flash_init (void) flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CFG_MONITOR_BASE)); + addr2info(CFG_MONITOR_BASE)); #endif /* Environment protection ON by default */ @@ -409,7 +406,7 @@ unsigned long flash_init (void) flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - flash_get_info(CFG_ENV_ADDR)); + addr2info(CFG_ENV_ADDR)); #endif /* Redundant environment protection ON by default */ @@ -417,32 +414,13 @@ unsigned long flash_init (void) flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - flash_get_info(CFG_ENV_ADDR_REDUND)); + addr2info(CFG_ENV_ADDR_REDUND)); #endif return (size); } /*----------------------------------------------------------------------- */ -#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} -#endif - -/*----------------------------------------------------------------------- - */ int flash_erase (flash_info_t * info, int s_first, int s_last) { int rcode = 0;

5 8

[U-Boot-Users] FW: WG: No ethernet functionality.
by u-boot＠olivernetzt.de 16 May '07

16 May '07

Dear all, I'm pretty frustrated and discouraged because my ethernet doesn't work. I have an at91sam9260ek based board (we tried to copy layout 'n stuff) and after a week trying to get the ethernet connection working I'd like to give up. :-/ I am here now, i.e. the u-boot hangs here after entering a ping command to reach a host within the same network (ethaddr, ipaddr is set properly; link status is ok; link speed is detected; phy is initialized): -> ether.c: eth_send: entering while ... [my output] In file ether.c in function eth_send there is that while-loop where the AT91C_EMAC_COMP bit is tested in register EMAC_TSR (transm. status register). This bit is never set, that's why the while-loop loops eternaly. The simple question is: Why? Any hints that might lead to the answer? Oliver.

1 0

[U-Boot-Users] Patch: Add USB OHCI support for MPC8220 - part 1
by TsiChung Liew 16 May '07

16 May '07

- USB Ohci support Regards, TsiChung Liew Signed-off by: TsiChung Liew<Tsi-Chung.Liew(a)freescale.com> diff -rupN u-boot-all.git/cpu/mpc8220/usb_ohci.c u-boot-all-8220- usbh/cpu/mpc8220/usb_ohci.c --- u-boot-all.git/cpu/mpc8220/usb_ohci.c 1969-12-31 18:00:00.000000000 -0600 +++ u-boot-all-8220-usbh/cpu/mpc8220/usb_ohci.c 2007-05-10 17:27:57.000000000 -0500 @@ -0,0 +1,1658 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB on the MPC8220. + * + * (C) Copyright 2003-2004 + * Gary Jennejohn, DENX Software Engineering <gj(a)denx.de> + * + * (C) Copyright 2004 + * Pierre Aubert, Staubli Faverges <p.aubert(a)staubli.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: Part of this code has been derived from linux + * + */ +/* + * IMPORTANT NOTES + * 1 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + */ + +#include <common.h> + +#ifdef CONFIG_USB_OHCI + +#include <malloc.h> +#include <usb.h> +#include "usb_ohci.h" + +#include <mpc8220.h> + +#define OHCI_USE_NPS /* force NoPowerSwitching mode */ +#undef OHCI_VERBOSE_DEBUG /* not always helpful */ +#undef DEBUG +#undef SHOW_INFO +#undef OHCI_FILL_TRACE + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +#define readl(a) (*((vu_long *)(a))) +#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) + +#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +#ifdef DEBUG +#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG */ +#define err(format, arg...) printf("ERROR: " format "\n", ## arg) +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\n", ## arg) +#else +#define info(format, arg...) do {} while(0) +#endif + +#define m16_swap(x) swap_16(x) +#define m32_swap(x) swap_32(x) + +#define ohci_cpu_to_le16(x) (x) +#define ohci_cpu_to_le32(x) (x) + +/* global ohci_t */ +static ohci_t gohci; +/* this must be aligned to a 256 byte boundary */ +struct ohci_hcca ghcca[1]; +/* a pointer to the aligned storage */ +struct ohci_hcca *phcca; +/* this allocates EDs for all possible endpoints */ +struct ohci_device ohci_dev; +/* urb_priv */ +urb_priv_t urb_priv; +/* RHSC flag */ +int got_rhsc; +/* device which was disconnected */ +struct usb_device *devgone; + +/*-------------------------------------------------------------------------*/ + +/* AMD-756 (D2 rev) reports corrupt register contents in some cases. + * The erratum (#4) description is incorrect. AMD's workaround waits + * till some bits (mostly reserved) are clear; ok for all revs. + */ +#define OHCI_QUIRK_AMD756 0xabcd +#define read_roothub(hc, register, mask) ({ \ + u32 temp = readl (&hc->regs->roothub.register); \ + if (hc->flags & OHCI_QUIRK_AMD756) \ + while (temp & mask) \ + temp = readl (&hc->regs->roothub.register); \ + temp; }) + +static u32 roothub_a(struct ohci *hc) +{ + return read_roothub(hc, a, 0xfc0fe000); +} +static inline u32 roothub_b(struct ohci *hc) +{ + return readl(&hc->regs->roothub.b); +} +static inline u32 roothub_status(struct ohci *hc) +{ + return readl(&hc->regs->roothub.status); +} +static u32 roothub_portstatus(struct ohci *hc, int i) +{ + return read_roothub(hc, portstatus[i], 0xffe0fce0); +} + +/* forward declaration */ +static int hc_interrupt(void); +static void +td_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, urb_priv_t * urb, + int interval); + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv(urb_priv_t * urb) +{ + int i; + int last; + struct td *td; + + last = urb->length - 1; + if (last >= 0) { + for (i = 0; i <= last; i++) { + td = urb->td[i]; + if (td) { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +static int sohci_get_current_frame_number(struct usb_device *dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, char *str, + int small) +{ + urb_priv_t *purb = &urb_priv; + + dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number(dev), + usb_pipedevice(pipe), + usb_pipeendpoint(pipe), + usb_pipeout(pipe) ? 'O' : 'I', + usb_pipetype(pipe) < 2 ? (usb_pipeint(pipe) ? "INTR" : "ISOC") : + (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), + purb->actual_length, + transfer_len, + dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol(pipe)) { + printf(__FILE__ ": cmd(8):"); + for (i = 0; i < 8; i++) + printf(" %02x", ((__u8 *) setup)[i]); + printf("\n"); + } + if (transfer_len > 0 && buffer) { + printf(__FILE__ ": data(%d/%d):", + purb->actual_length, transfer_len); + len = usb_pipeout(pipe) ? + transfer_len : purb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printf(" %02x", ((__u8 *) buffer)[i]); + printf("%s\n", i < len ? "..." : ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ +void ep_print_int_eds(ohci_t * ohci, char *str) +{ + int i, j; + __u32 *ed_p; + for (i = 0; i < 32; i++) { + j = 5; + ed_p = &(ohci->hcca->int_table[i]); + if (*ed_p == 0) + continue; + printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while (*ed_p != 0 && j--) { + ed_t *ed = (ed_t *) ohci_cpu_to_le32(ed_p); + printf(" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + printf("\n"); + } +} + +static void ohci_dump_intr_mask(char *label, __u32 mask) +{ + dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : ""); +} + +static void maybe_print_eds(char *label, __u32 value) +{ + ed_t *edp = (ed_t *) value; + + if (value) { + dbg("%s %08x", label, value); + dbg("%08x", edp->hwINFO); + dbg("%08x", edp->hwTailP); + dbg("%08x", edp->hwHeadP); + dbg("%08x", edp->hwNextED); + } +} + +static char *hcfs2string(int state) +{ + switch (state) { + case OHCI_USB_RESET: + return "reset"; + case OHCI_USB_RESUME: + return "resume"; + case OHCI_USB_OPER: + return "operational"; + case OHCI_USB_SUSPEND: + return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status(ohci_t * controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp; + + temp = readl(&regs->revision) & 0xff; + if (temp != 0x10) + dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); + + temp = readl(&regs->control); + dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string(temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR); + + temp = readl(&regs->cmdstatus); + dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : ""); + + ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus)); + ohci_dump_intr_mask("intrenable", readl(&regs->intrenable)); + + maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent)); + + maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead)); + maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent)); + + maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead)); + maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent)); + + maybe_print_eds("donehead", readl(&regs->donehead)); +} + +static void ohci_dump_roothub(ohci_t * controller, int verbose) +{ + __u32 temp, ndp, i; + + temp = roothub_a(controller); + ndp = (temp & RH_A_NDP); + + if (verbose) { + dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp); + temp = roothub_b(controller); + dbg("roothub.b: %08x PPCM=%04x DR=%04x", + temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR) + ); + temp = roothub_status(controller); + dbg("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : ""); + } + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus(controller, i); + dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : ""); + } +} + +static void ohci_dump(ohci_t * controller, int verbose) +{ + dbg("OHCI controller usb-%s state", controller->slot_name); + + /* dumps some of the state we know about */ + ohci_dump_status(controller); + if (verbose) + ep_print_int_eds(controller, "hcca"); + dbg("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub(controller, 1); +} + +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + ohci_t *ohci; + ed_t *ed; + urb_priv_t *purb_priv; + int i, size = 0; + + ohci = &gohci; + + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if (ohci->disabled) { + err("sohci_submit_job: EPIPE"); + return -1; + } + + /* every endpoint has a ed, locate and fill it */ + if (!(ed = ep_add_ed(dev, pipe))) { + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype(pipe)) { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3; + break; + } + + if (size >= (N_URB_TD - 1)) { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv = &urb_priv; + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) { + purb_priv->td[i] = td_alloc(dev); + if (!purb_priv->td[i]) { + purb_priv->length = i; + urb_free_priv(purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) { + urb_free_priv(purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + ep_link(ohci, ed); + + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, + interval); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number(struct usb_device *usb_dev) +{ + ohci_t *ohci = &gohci; + + return ohci_cpu_to_le16(ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link(ohci_t * ohci, ed_t * edi) +{ + volatile ed_t *ed = edi; + + ed->state = ED_OPER; + + switch (ed->type) { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) { + writel(ed, &ohci->regs->ed_controlhead); + } else { + ohci->ed_controltail->hwNextED = + ohci_cpu_to_le32((unsigned long)ed); + } + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_CLE; + writel(ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) { + writel(ed, &ohci->regs->ed_bulkhead); + } else { + ohci->ed_bulktail->hwNextED = + ohci_cpu_to_le32((unsigned long)ed); + } + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_BLE; + writel(ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +static int ep_unlink(ohci_t * ohci, ed_t * edi) +{ + volatile ed_t *ed = edi; + + ed->hwINFO |= ohci_cpu_to_le32(OHCI_ED_SKIP); + + switch (ed->type) { + case PIPE_CONTROL: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel(ohci->hc_control, &ohci->regs->control); + } + writel(ohci_cpu_to_le32(*((__u32 *) & ed->hwNextED)), + &ohci->regs->ed_controlhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_controltail == ed) { + ohci->ed_controltail = ed->ed_prev; + } else { + ((ed_t *) + ohci_cpu_to_le32(*((__u32 *) & ed->hwNextED)))-> + ed_prev = ed->ed_prev; + } + break; + + case PIPE_BULK: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel(ohci->hc_control, &ohci->regs->control); + } + writel(ohci_cpu_to_le32(*((__u32 *) & ed->hwNextED)), + &ohci->regs->ed_bulkhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_bulktail == ed) { + ohci->ed_bulktail = ed->ed_prev; + } else { + ((ed_t *) + ohci_cpu_to_le32(*((__u32 *) & ed->hwNextED)))-> + ed_prev = ed->ed_prev; + } + break; + } + ed->state = ED_UNLINK; + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, + * but the USB stack is a little bit stateless so we do it at every transaction + * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK + * in all other cases the state is left unchanged + * the ed info fields are setted anyway even though most of them should not change */ + +static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + + ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) | + (usb_pipecontrol(pipe) ? 0 : + usb_pipeout(pipe))]; + + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) { + ed->hwINFO = ohci_cpu_to_le32(OHCI_ED_SKIP); /* skip ed */ + /* dummy td; end of td list for ed */ + td = td_alloc(usb_dev); + ed->hwTailP = ohci_cpu_to_le32((unsigned long)td); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype(pipe); + ohci_dev.ed_cnt++; + } + + ed->hwINFO = ohci_cpu_to_le32(usb_pipedevice(pipe) + | usb_pipeendpoint(pipe) << 7 + | (usb_pipeisoc(pipe) ? 0x8000 : 0) + | (usb_pipecontrol(pipe) ? 0 + : (usb_pipeout(pipe) ? 0x800 : 0x1000)) + | usb_pipeslow(pipe) << 13 | + usb_maxpacket(usb_dev, pipe) << 16); + + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill(ohci_t * ohci, unsigned int info, + void *data, int len, + struct usb_device *dev, int index, urb_priv_t * urb_priv) +{ + volatile td_t *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + + if (index > urb_priv->length) { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td[index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td[index] = + (td_t *) (ohci_cpu_to_le32(urb_priv->ed->hwTailP) & ~0xf); + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (__u32) data; +#ifdef OHCI_FILL_TRACE + if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) + && usb_pipeout(urb_priv->pipe)) { + for (i = 0; i < len; i++) + printf("td->data[%d] %#2x ", i, + ((unsigned char *)td->data)[i]); + printf("\n"); + } +#endif + if (!len) + data = 0; + + td->hwINFO = ohci_cpu_to_le32(info); + td->hwCBP = ohci_cpu_to_le32((unsigned long)data); + if (data) + td->hwBE = ohci_cpu_to_le32((unsigned long)(data + len - 1)); + else + td->hwBE = 0; + td->hwNextTD = ohci_cpu_to_le32((unsigned long)td_pt); + td->hwPSW[0] = ohci_cpu_to_le16(((__u32) data & 0x0FFF) | 0xE000); + + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ + +static void td_submit_job(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, + struct devrequest *setup, urb_priv_t * urb, + int interval) +{ + ohci_t *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ + if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { + toggle = TD_T_TOGGLE; + } else { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), + 1); + } + urb->td_cnt = 0; + if (data_len) + data = buffer; + else + data = 0; + + switch (usb_pipetype(pipe)) { + case PIPE_BULK: + info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN; + while (data_len > 4096) { + td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data, + 4096, dev, cnt, urb); + data += 4096; + data_len -= 4096; + cnt++; + } + info = usb_pipeout(pipe) ? + TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN; + td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data, + data_len, dev, cnt, urb); + cnt++; + + if (!ohci->sleeping) + writel(OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ + break; + + case PIPE_CONTROL: + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill(ohci, info, setup, 8, dev, cnt++, urb); + if (data_len > 0) { + info = usb_pipeout(pipe) ? + TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R + | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill(ohci, info, data, data_len, dev, cnt++, urb); + } + info = usb_pipeout(pipe) ? + TD_CC | TD_DP_IN | TD_T_DATA1 : TD_CC | TD_DP_OUT | + TD_T_DATA1; + td_fill(ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) + writel(OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(td_t * td) +{ + __u32 tdINFO, tdBE, tdCBP; + urb_priv_t *lurb_priv = &urb_priv; + + tdINFO = ohci_cpu_to_le32(td->hwINFO); + tdBE = ohci_cpu_to_le32(td->hwBE); + tdCBP = ohci_cpu_to_le32(td->hwCBP); + + if (!(usb_pipetype(lurb_priv->pipe) == PIPE_CONTROL && + ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { + if (tdBE != 0) { + if (td->hwCBP == 0) + lurb_priv->actual_length += tdBE - td->data + 1; + else + lurb_priv->actual_length += tdCBP - td->data; + } + } +} + +/*-------------------------------------------------------------------------*/ + +/* replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list */ + +static td_t *dl_reverse_done_list(ohci_t * ohci) +{ + __u32 td_list_hc; + td_t *td_rev = NULL; + td_t *td_list = NULL; + urb_priv_t *lurb_priv = NULL; + + td_list_hc = ohci_cpu_to_le32(ohci->hcca->done_head) & 0xfffffff0; + ohci->hcca->done_head = 0; + + while (td_list_hc) { + td_list = (td_t *) td_list_hc; + + if (TD_CC_GET(ohci_cpu_to_le32(td_list->hwINFO))) { + lurb_priv = &urb_priv; + dbg(" USB-error/status: %x : %p", + TD_CC_GET(ohci_cpu_to_le32(td_list->hwINFO)), + td_list); + if (td_list->ed->hwHeadP & ohci_cpu_to_le32(0x1)) { + if (lurb_priv + && ((td_list->index + 1) < + lurb_priv->length)) { + td_list->ed->hwHeadP = + (lurb_priv-> + td[lurb_priv->length - + 1]-> + hwNextTD & + ohci_cpu_to_le32(0xfffffff0)) | + (td_list->ed-> + hwHeadP & ohci_cpu_to_le32(0x2)); + lurb_priv->td_cnt += + lurb_priv->length - td_list->index - + 1; + } else + td_list->ed->hwHeadP &= + ohci_cpu_to_le32(0xfffffff2); + } +#ifdef CONFIG_MPC8220 + td_list->hwNextTD = 0; +#endif + } + + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = ohci_cpu_to_le32(td_list->hwNextTD) & 0xfffffff0; + } + return td_list; +} +

3 5

[U-Boot-Users] [GIT PULL] mpc83xx: MPC8313ERDB support, memory init fixes
by Kim Phillips 16 May '07

16 May '07

Wolfgang, please pull: git://www.denx.de/git/u-boot-mpc83xx.git to add support for the MPC8313ERDB, plus a couple of memory initialization fixes: Kim Phillips (3): mpc83xx: minor fixups for 8313rdb introduction mpc83xx: replace elaborate boottime verbosity with 'clocks' command mpc83xx: fix trivial error in MAKEALL Scott Wood (7): mpc83xx: Add register definitions for MPC831x. mpc83xx: Recognize SPR values for MPC8311 and MPC8313. mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu(). mpc83xx: Add 831x support to global_data.h mpc83xx: Add 831x support to speed.c. mpc83xx: Add generic PCI setup code. mpc83xx: Add MPC8313ERDB support. Timur Tabi (1): Fix memory initialization on MPC8349E-mITX Xie Xiaobo (1): Fix two bugs for MPC83xx DDR2 controller SPD Init MAKEALL | 4 +- Makefile | 13 + board/mpc8313erdb/Makefile | 50 ++++ board/mpc8313erdb/config.mk | 1 + board/mpc8313erdb/mpc8313erdb.c | 116 ++++++++ board/mpc8313erdb/sdram.c | 133 +++++++++ board/mpc8313erdb/u-boot.lds | 123 +++++++++ board/mpc8349itx/mpc8349itx.c | 3 +- cpu/mpc83xx/Makefile | 2 +- cpu/mpc83xx/cpu.c | 39 +++- cpu/mpc83xx/pci.c | 192 +++++++++++++ cpu/mpc83xx/spd_sdram.c | 11 +- cpu/mpc83xx/speed.c | 78 ++++-- doc/README.mpc8313erdb | 83 ++++++ include/asm-ppc/e300.h | 16 +- include/asm-ppc/global_data.h | 6 +- include/asm-ppc/immap_83xx.h | 56 ++++- include/common.h | 2 - include/configs/MPC8313ERDB.h | 569 +++++++++++++++++++++++++++++++++++++++ include/configs/MPC8349ITX.h | 3 + include/mpc83xx.h | 257 ++++++++++++++++++- lib_ppc/board.c | 4 - 22 files changed, 1686 insertions(+), 75 deletions(-) create mode 100644 board/mpc8313erdb/Makefile create mode 100644 board/mpc8313erdb/config.mk create mode 100644 board/mpc8313erdb/mpc8313erdb.c create mode 100644 board/mpc8313erdb/sdram.c create mode 100644 board/mpc8313erdb/u-boot.lds create mode 100644 cpu/mpc83xx/pci.c create mode 100644 doc/README.mpc8313erdb create mode 100644 include/configs/MPC8313ERDB.h

2 1

[U-Boot-Users] Please pull u-boot-microblaze.git
by Michal Simek 16 May '07

16 May '07

Hi Wolfgang, Please pull u-boot-microblaze.git to mainline. Changes: Support USE_MSR_INTR, FSL links. New FSL commands. Read and Write to SPR register. Clean ASM code. Exception handling for Microblaze v5 FIX bug in interrupt handler Best regards, Michal Simek

2 1

[U-Boot-Users] undefined instruction during bootp
by Junior 15 May '07

15 May '07

Hi all, I'm getting an undefined instruction error at the end of the bootp command: Filename 'kernel_img'. Load address: 0xc0f00000 Loading: ################################################################# ############undefined instruction pc : [<75b1ac08>] lr : [<c1fc139c>] sp : c1f5fb00 ip : ffffffff fp : c1f5fded r10: 8388956c r9 : 328b03e0 r8 : c1f5ffdc r7 : 6bfbb68d r6 : 8ecfd531 r5 : 5faa503d r4 : e926e94c r3 : 70000048 r2 : 6137fe02 r1 : 0000002e r0 : f53c4775 Flags: Nzcv IRQs off FIQs off Mode SVC_32 Resetting CPU ... This seem to happen durint the NetSendUDPPacket functions: c1fc1384: ebffff66 bl c1fc1124 <NetSetIP> c1fc1388: e5970000 ldr r0, [r7] c1fc138c: e0601004 rsb r1, r0, r4 c1fc1390: e0811009 add r1, r1, r9 c1fc1394: e281101c add r1, r1, #28 ; 0x1c c1fc1398: eb000d27 bl c1fc483c <eth_send> c1fc139c: e3a00000 mov r0, #0 ; 0x0 c1fc13a0: e28dd00c add sp, sp, #12 ; 0xc c1fc13a4: e8bd8ef0 ldmia sp!, {r4, r5, r6, r7, r9, sl, fp, pc} c1fc13a8: c1fd60d0 ldrgtsb r6, [sp]! c1fc13ac: c1fd6dd4 ldrgtsb r6, [sp, #212]! c1fc13b0: c1fd8d54 mvngts r8, r4, asr sp c1fc13b4: c1fd6dd0 ldrgtsb r6, [sp, #208]! c1fc13b8: c1fd8d48 mvngts r8, r8, asr #26 c1fc13bc: c1fd8d50 mvngts r8, r0, asr sp c1fc13c0: c1fd8d58 mvngts r8, r8, asr sp c1fc13c4: c1fd9380 mvngts r9, r0, lsl #7 c1fc13c8: c1fd937c mvngts r9, ip, ror r3 Does anyone know how to solve this problem? Thanks, --Jr.

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[U-Boot-Users] [DNX#2007051542000041] [PATCH] Add support for BCM5464 Quad Phy
by U-Boot patch tracking system 15 May '07

15 May '07

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2007051542000041]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

1 0

[U-Boot-Users] [DNX#2007051542000041] [PATCH] Add support for BCM5464 Quad Phy
by DENX Support System 15 May '07

15 May '07

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2007051542000041] was created: <snip> > In message <051f01c78b71$261b5800$6900a8c0@ESIDT> you wrote: > > > > Added support for Broadcom's BCM5464 Quad Phy > > > > Signed-off-by: Joe Hamman <joe.hamman(a)embeddedspecialties.com> > > Applied to u-boot-testing. > > Thanks. > > > > diff --git a/drivers/tsec.c b/drivers/tsec.c > > index 3f11eb0..5c4219d 100644 > ------------------------^^^^^^^^ > > But please keep your file modes under control!!!! > > Best regards, > > Wolfgang Denk > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de > "Spock, did you see the looks on their faces?" > "Yes, Captain, a sort of vacant contentment." </snip> Your U-Boot support team

1 0

[U-Boot-Users] [PATCH re-send] MACOSX support
by Aubrey.Li 15 May '07

15 May '07

The following patch fixes compilation issue on macosx >From 8291cf1d7cf4544312ffd819a401c7de68b7a6bc Mon Sep 17 00:00:00 2001 From: Aubrey Li <aubrey.adi(a)gmail.com> Date: Mon, 14 May 2007 11:17:26 +0800 Subject: [PATCH] MACOSX support Singed-off-by: Marc Hoffman <Marc.Hoffman(a)analog.com> Signed-off-by: Aubrey Li <aubrey.adi(a)gmail.com> --- tools/Makefile | 2 +- tools/mkimage.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index 6177f90..5e26bd7 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -74,7 +74,7 @@ TOOLSUBDIRS = ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) HOST_CFLAGS = -traditional-cpp -Wall HOST_LDFLAGS =-multiply_defined suppress -HOST_ENVIRO_CFLAGS = -traditional-cpp +HOST_ENVIRO_CFLAGS = else ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc) diff --git a/tools/mkimage.c b/tools/mkimage.c index 416e658..2125130 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -446,7 +446,7 @@ NXTARG: ; } /* We're a bit of paranoid */ -#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) +#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__) (void) fdatasync (ifd); #else (void) fsync (ifd); @@ -496,7 +496,7 @@ NXTARG: ; (void) munmap((void *)ptr, sbuf.st_size); /* We're a bit of paranoid */ -#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) +#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__) (void) fdatasync (ifd); #else (void) fsync (ifd); -- 1.5.1.2

2 1

[U-Boot-Users] [patch] Search the exception table with linear algorithm
by Zang Roy-r61911 15 May '07

15 May '07

Search the exception table with linear algorithm instead of bisecting algorithm. Because the exception table might be unsorted. Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- lib_ppc/extable.c | 39 ++++++++++++++++++--------------------- 1 files changed, 18 insertions(+), 21 deletions(-) diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c index b14d661..8354411 100644 --- a/lib_ppc/extable.c +++ b/lib_ppc/extable.c @@ -52,30 +52,27 @@ search_one_table(const struct exception_table_entry *first, const struct exception_table_entry *last, unsigned long value) { - while (first <= last) { - const struct exception_table_entry *mid; - long diff; - - mid = (last - first) / 2 + first; - if ((ulong) mid > CFG_MONITOR_BASE) { - /* exception occurs in FLASH, before u-boot relocation. - * No relocation offset is needed. - */ - diff = mid->insn - value; + long diff; + if ((ulong) first > CFG_MONITOR_BASE) { + /* exception occurs in FLASH, before u-boot relocation. + * No relocation offset is needed. + */ + while (first <= last) { + diff = first->insn - value; if (diff == 0) - return mid->fixup; - } else { - /* exception occurs in RAM, after u-boot relocation. - * A relocation offset should be added. - */ - diff = (mid->insn + gd->reloc_off) - value; + return first->fixup; + first++; + } + } else { + /* exception occurs in RAM, after u-boot relocation. + * A relocation offset should be added. + */ + while (first <= last) { + diff = (first->insn + gd->reloc_off) - value; if (diff == 0) - return (mid->fixup + gd->reloc_off); + return (first->fixup + gd->reloc_off); + first++; } - if (diff < 0) - first = mid + 1; - else - last = mid - 1; } return 0; } -- 1.5.1

2 1

Re: [U-Boot-Users] [PATCH] Add support for BCM5464 Quad Phy
by Wolfgang Denk 15 May '07

15 May '07

In message <051f01c78b71$261b5800$6900a8c0@ESIDT> you wrote: > > Added support for Broadcom's BCM5464 Quad Phy > > Signed-off-by: Joe Hamman <joe.hamman(a)embeddedspecialties.com> Applied to u-boot-testing. Thanks. > diff --git a/drivers/tsec.c b/drivers/tsec.c > index 3f11eb0..5c4219d 100644 ------------------------^^^^^^^^ But please keep your file modes under control!!!! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de "Spock, did you see the looks on their faces?" "Yes, Captain, a sort of vacant contentment."

1 0

Re: [U-Boot-Users] [Fwd: Regarding the Sata patch]
by Wolfgang Denk 15 May '07

15 May '07

In message <46231445.2060109(a)procsys.com> you wrote: > > I had submitted the SATA patch on 26th of march, please let me know the > status and feed-back. This will help me to submit other patchs. > I had added Hynix NAND Flash support for u-boot-1.1.3, i am trying to > bring these changes to current version of u-boot. Your patch did not include a Sigend-off-by: line. Can you please just send this in addition, and I will take care of it ASAP. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk Office: Kirchenstr. 5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Another megabytes the dust.

2 2

[U-Boot-Users] No ethernet functionality.
by Bühn, Oliver 15 May '07

15 May '07

Dear all, I'm pretty frustrated and discouraged because my ethernet doesn't work. I have an at91sam9260ek based board (we tried to copy layout 'n stuff) and after a week trying to get the ethernet connection working I'd like to give up. :-/ I am here now, i.e. the u-boot hangs here after entering a ping command to reach a host within the same network (ethaddr, ipaddr is set properly; link status is ok; link speed is detected; phy is initialized): -> ether.c: eth_send: entering while ... [my output] In file ether.c in function eth_send there is that while-loop where the AT91C_EMAC_COMP bit is tested in register EMAC_TSR (transm. status register). This bit is never set, that's why the while-loop loops eternaly. The simple question is: Why? Any hints that might lead to the answer? Oliver. P.S.: Please excuse any attached disclaimer or note after this. It get's attached out of my control. --- This message (including any attachments) contains confidential and/or proprietary information intended only for the addressee. Any unauthorized disclosure, copying, distribution or reliance on the contents of this information is strictly prohibited and may constitute a violation of law. If you are not the intended recipient, please notify the sender immediately by responding to this e-mail, and delete the message from your system. If you have any questions about this e-mail please notify the sender immediately.

3 5

[U-Boot-Users] Patch: USB Host update for MPC8220
by TsiChung Liew 15 May '07

15 May '07

USB Host update for MPC8220 using generic USB OHCI driver Regards, TsiChung Signed-off by TsiChung Liew<Tsi-Chung.Liew(a)freescale.com> diff -rupN usborg/drivers/usb_ohci.c usbnew/drivers/usb_ohci.c --- usborg/drivers/usb_ohci.c 2007-05-15 14:25:02.000000000 -0500 +++ usbnew/drivers/usb_ohci.c 2007-05-15 15:29:27.466913928 -0500 @@ -66,7 +66,8 @@ defined(CONFIG_S3C2400) || \ defined(CONFIG_S3C2410) || \ defined(CONFIG_440EP) || \ - defined(CONFIG_MPC5200) + defined(CONFIG_MPC5200) || \ + defined(CONFIG_MPC8220) # define OHCI_USE_NPS /* force NoPowerSwitching mode */ #endif @@ -98,7 +99,7 @@ #define info(format, arg...) do {} while(0) #endif -#if defined(CONFIG_440EP) || defined(CONFIG_MPC5200) +#if defined(CONFIG_440EP) || defined(CONFIG_MPC5200) || defined (CONFIG_MPC8220) # define m16_swap(x) (x) # define m32_swap(x) (x) #else @@ -832,7 +833,7 @@ static td_t * dl_reverse_done_list (ohci } else td_list->ed->hwHeadP &= m32_swap (0xfffffff2); } -#ifdef CONFIG_MPC5200 +#if defined(CONFIG_MPC5200) || defined(CONFIG_MPC8220) td_list->hwNextTD = 0; #endif } @@ -882,13 +883,14 @@ static int dl_done_list (ohci_t *ohci, t (lurb_priv->state != URB_DEL)) #else if ((ed->state & (ED_OPER | ED_UNLINK))) +#endif urb_finished = 1; else dbg("dl_done_list: strange.., ED state %x, ed->state\n"); } else dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt, lurb_priv->length); -#endif + if (ed->state != ED_NEW) { edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; edTailP = m32_swap (ed->hwTailP); @@ -1074,7 +1076,7 @@ pkt_print(dev, pipe, buffer, transfer_le } bmRType_bReq = cmd->requesttype | (cmd->request << 8); -#if defined(CONFIG_440EP) || defined(CONFIG_MPC5200) +#if defined(CONFIG_440EP) || defined(CONFIG_MPC5200) || defined (CONFIG_MPC8220) wValue = __swap_16(cmd->value); wIndex = __swap_16(cmd->index); wLength = __swap_16(cmd->length); @@ -1082,7 +1084,7 @@ pkt_print(dev, pipe, buffer, transfer_le wValue = m16_swap (cmd->value); wIndex = m16_swap (cmd->index); wLength = m16_swap (cmd->length); -#endif /* CONFIG_440EP || CONFIG_MPC5200 */ +#endif /* CONFIG_440EP || CONFIG_MPC5200 || CONFIG_MPC8220 */ info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); @@ -1096,7 +1098,7 @@ pkt_print(dev, pipe, buffer, transfer_le RH_OTHER | RH_CLASS almost ever means HUB_PORT here */ -#if defined(CONFIG_440EP) || defined(CONFIG_MPC5200) +#if defined(CONFIG_440EP) || defined(CONFIG_MPC5200) || defined (CONFIG_MPC8220) case RH_GET_STATUS: *(__u16 *) data_buf = __swap_16(1); OK (2); case RH_GET_STATUS | RH_INTERFACE: @@ -1122,7 +1124,7 @@ pkt_print(dev, pipe, buffer, transfer_le OK (4); case RH_GET_STATUS | RH_OTHER | RH_CLASS: *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); -#endif /* CONFIG_440EP || CONFIG_MPC5200 */ +#endif /* CONFIG_440EP || CONFIG_MPC5200 || CONFIG_MPC8220 */ case RH_CLEAR_FEATURE | RH_ENDPOINT: switch (wValue) { diff -rupN usborg/drivers/usb_ohci.h usbnew/drivers/usb_ohci.h --- usborg/drivers/usb_ohci.h 2007-05-15 14:25:20.000000000 -0500 +++ usbnew/drivers/usb_ohci.h 2007-05-15 13:46:30.412968000 -0500 @@ -10,7 +10,7 @@ /* functions for doing board or CPU specific setup/cleanup */ extern int usb_board_init(void); extern int usb_board_stop(void); -extern int usb_cpu_init_fail(void); +extern int usb_board_init_fail(void); extern int usb_cpu_init(void); extern int usb_cpu_stop(void);

1 0

[U-Boot-Users] [PATCH] Support for QNAP TurboStation TS-101/TS-201
by Øyvind Repvik 15 May '07

15 May '07

Hi, This patch adds support for the QNAP Turbostation TS-101 and TS-201 devices (http://www.qnap.com.tw/pro_storage.asp). Applies to git tree. Regards, Øyvind Repvik Signed-off-by: Øyvind Repvik <nail(a)nslu2-linux.org> Signed-off-by: Alessandro Zummo <a.zummo(a)towertech.it> Signed-off-by: Andrew Luyten <u-boot(a)luyten.org.uk> --- u-boot-1.2.0.vanilla/board/qnap/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.2.0/board/qnap/config.mk 2007-02-26 01:55:37.000000000 +0100 @@ -0,0 +1,35 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Valid values for TEXT_BASE are: +# +# Standard configuration +# 0xFFF00000 boot from flash +# +# Standard configuration +# 0xFFE60000 chain boot from flash +# + + +TEXT_BASE = 0xFFE60000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) --- u-boot-1.2.0.vanilla/board/qnap/ide.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.2.0/board/qnap/ide.c 2007-02-26 01:55:37.000000000 +0100 @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + #include <common.h> + +#ifdef CFG_CMD_IDE +#include <ata.h> +#include <ide.h> +#include <pci.h> + +extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; +extern struct pci_controller hose; + +int ide_preinit (void) +{ + int status; + pci_dev_t devbusfn; + int l; + + status = 1; + for (l = 0; l < CFG_IDE_MAXBUS; l++) { + ide_bus_offset[l] = -ATA_STATUS; + } + devbusfn = pci_find_device (0x1095, 0x3512, 0); + + if (devbusfn != -1) { + + status = 0; + + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, + (u32 *) &ide_bus_offset[0]); + ide_bus_offset[0] &= 0xfffffffe; + ide_bus_offset[0] = pci_hose_bus_to_phys(&hose, + ide_bus_offset[0] & 0xfffffffe, + PCI_REGION_IO); + + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, + (u32 *) &ide_bus_offset[1]); + ide_bus_offset[1] &= 0xfffffffe; + ide_bus_offset[1] = pci_hose_bus_to_phys(&hose, + ide_bus_offset[1] & 0xfffffffe, + PCI_REGION_IO); + } + return (status); +} + +#endif /* of CONFIG_CMDS_IDE */ --- u-boot-1.2.0.vanilla/board/qnap/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.2.0/board/qnap/Makefile 2007-02-26 01:55:37.000000000 +0100 @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ide.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### --- u-boot-1.2.0.vanilla/board/qnap/qnap.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.2.0/board/qnap/qnap.c 2007-02-26 01:55:37.000000000 +0100 @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2006 Andrew Luyten <u-boot(a)luyten.org.uk> + * + * Copyright (C) 2000 + * Rob Taylor, Flying Pig Systems. robt(a)flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <mpc824x.h> +#include <pci.h> + +int checkboard (void) +{ + ulong busfreq = get_bus_freq(0); + char buf[32]; + + printf("Board: QNAP TS-101/TS-201 local bus at %s MHz\n", strmhz(buf, busfreq)); + return 0; +} + + +long int initdram (int board_type) +{ + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +} + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP + +static struct pci_config_table pci_qnap_config_table[] = { + /* vendor, device, class */ + /* bus, dev, func */ + + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_ANY_ID, 0x0f, 0, /* RTL8110SC or Intel 82540EM */ + /* Gigabit ethernet controller */ + pci_cfgfunc_config_device, { PCI_ETH_IOADDR, + PCI_ETH_MEMADDR, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_ANY_ID, 0x0d, 0, /* SII3512 */ + /* SATA controller */ + pci_cfgfunc_config_device, { PCI_IDE_IOADDR, + PCI_IDE_MEMADDR, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_ANY_ID, 0x0e, 0, /* D720101 USB controller, 1st USB 1.1 */ + pci_cfgfunc_config_device, { PCI_USB0_IOADDR, + PCI_USB0_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_ANY_ID, 0x0e, 1, /* D720101 USB controller, 2nd USB 1.1 */ + pci_cfgfunc_config_device, { PCI_USB1_IOADDR, + PCI_USB1_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_ANY_ID, 0x0e, 2, /* D720101 USB controller, USB 2.0 */ + pci_cfgfunc_config_device, { PCI_USB2_IOADDR, + PCI_USB2_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_qnap_config_table, +#endif +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); + + /* Reset USB 1.1 !/ + out_le32(PCI_USB0_MEMADDR+8, 1); + out_le32(PCI_USB1_MEMADDR+8, 1); + */ +} --- u-boot-1.2.0.vanilla/board/qnap/README 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.2.0/board/qnap/README 2007-02-26 01:55:37.000000000 +0100 @@ -0,0 +1,10 @@ +*This port of U-Boot will run on a QNAP TS-101/TS-201 NAS* +Andrew Luyten (u-boot(a)luyten.org.uk) + +Adapted from a Linkstation port by Mihai Georgian +http://http://www.linuxnotincluded.org.uk/ + +Adapted from Motorola Sandpoint 3 development system equipped with +a Unity X4 PPMC card (MPC8240 CPU) only. It is a snapshot of work +in progress and far from being completed. +Thomas Koeller --- u-boot-1.2.0.vanilla/board/qnap/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.2.0/board/qnap/u-boot.lds 2007-02-26 01:55:37.000000000 +0100 @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-1.2.0/include/configs/qnap.h 2007-04-07 21:56:55.376393000 +0200 @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2006 Andrew Luyten <u-boot(a)luyten.org.uk> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_MPC8241 1 + +#define CONFIG_IDENT_STRING " OpenTS(c)" +#define CONFIG_TIMESTAMP +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "turbostation> " +#define CONFIG_BOOTDELAY 3 + + +/*---------------------------------------------------------------------- + * Define supported commands + */ + +#define CONFIG_COMMANDS ( \ + CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_EXT2 | \ + CFG_CMD_DATE | \ + CFG_CMD_PCI ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ + +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt*/ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size*/ +#define CFG_MAXARGS 16 /* max number of command args*/ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq:1 ms ticks*/ + + +/*----------------------------------------------------------------------- + * PCI + * + */ + +#define CONFIG_PCI +#undef CONFIG_PCI_PNP + +#define PCI_ETH_IOADDR 0xbffe00 +#define PCI_ETH_MEMADDR 0xbfffce00 + +#define PCI_IDE_IOADDR 0xbfffd0 +#define PCI_IDE_MEMADDR 0xbffffe00 + +#define PCI_USB0_IOADDR 0 +#define PCI_USB0_MEMADDR 0xbfffe000 +#define PCI_USB1_IOADDR 0 +#define PCI_USB1_MEMADDR 0xbfffd000 +#define PCI_USB2_IOADDR 0 +#define PCI_USB2_MEMADDR 0xbfffcf00 + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + */ + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MONITOR_BASE TEXT_BASE +#undef CFG_RAMBOOT + +#define CFG_PCI_MEM_ADDR 0xB0000000 +#define CFG_EUMB_ADDR 0xFC000000 +#define CFG_FLASH_BASE 0xFF000000 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_MONITOR_LEN (256 << 10) +#define CFG_MALLOC_LEN (512 << 10) + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ +#define CFG_MAX_RAM_SIZE 0x10000000 /* up to 256M of SDRAM */ + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + + +/*----------------------------------------------------------------------- + * FLASH organization + */ + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip*/ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_USE_BUFFER_WRITE /* faster writes */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00EA0000) +#define CFG_ENV_SECT_SIZE 0x00020000 /* Total Size of Environment Sector*/ + + +/*----------------------------------------------------------------------- + * Gigabit Ethernet + */ + +#define CONFIG_NET_MULTI +#define CONFIG_RTL8169 + + +/*----------------------------------------------------------------------- + * Filesystems + */ + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +//#define CONFIG_ISO_PARTITION + + +/*----------------------------------------------------------------------- + * IDE/ATA + */ + +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ +#undef CONFIG_ATAPI /* no ATAPI support */ + +#define CONFIG_IDE_PREINIT /* To set up MMIO adresses */ +#define CONFIG_LBA48 /* Large disk support */ + +#define CFG_IDE_MAXBUS 2 /* Two channels x 1 device each */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) + +#define CFG_ATA_BASE_ADDR 0x0000 /* Set up in board specific code */ +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + + +/*---------------------------------------------------------------------- + * On Chip Serial configuration + */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) /* Console port */ +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) /* PIC ? */ + + +/*---------------------------------------------------------------------- + * i2c support configuration + */ + +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CONFIG_RTC_RS5C372A /* Real-time clock chip */ + + +/*---------------------------------------------------------------------- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CFG_ROMNAL 7 /*rom/flash next access time */ +#define CFG_ROMFAL 11 /*rom/flash access time */ + +#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ + +/* the following are for SDRAM only*/ +#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ +#define CFG_REFREC 8 /* Refresh to activate interval */ +#define CFG_RDLAT 4 /* data latency from read command */ +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 3 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ + +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 + + +/*---------------------------------------------------------------------- + * memory bank settings + * + * only bits 20-29 are actually used from these vales to set the + * start/end address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 +#define CFG_BANK7_ENABLE 0 + + +/* + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#define CFG_ODCR 0xff /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ +#define CFG_DBUS_SIZE2 1 +#define CFG_BANK0_ROW 2 + + +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* PCI memory */ +#define CFG_IBAT2L (CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Flash, config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/*----------------------------------------------------------------------- + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,603e" +#define OF_STDOUT_PATH "/soc10x/serial@fc004500" + +#endif /* __CONFIG_H */ + Index: u-boot.git/Makefile =================================================================== --- u-boot.git.orig/Makefile 2007-05-05 20:10:25.000000000 +0200 +++ u-boot.git/Makefile 2007-05-07 12:44:07.000000000 +0200 @@ -1328,6 +1328,9 @@ PN62_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc824x pn62 +qnap_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc824x qnap + Sandpoint8240_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc824x sandpoint

3 2

Re: [U-Boot-Users] u-boot HUSH scripting using local variables.
by Wolfgang Denk 15 May '07

15 May '07

I wrote: > > > " In the current implementation, the local variables space and global > > environment variables space are separated. Local variables are those you > > define by simply typing like name=value. To access a local variable > > later on, you have to write '$name' or '${name}'; to execute the > > contents of a variable directly you can type '$name' at the command > > prompt." > > > > ...which implies that local variables can be used to save commands and > > execute them later. It doesn't contradict with the statement in previous > > bullet that > > I don't see how you derive that. The text above does not mention > commands or execution. Delete that part, please. I was reding a different part of the message then. Sorry. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de "He only drinks when he gets depressed." "Why does he get depressed?" "Sometimes it's because he hasn't had a drink." - Terry Pratchett, _Men at Arms_

2 1

[U-Boot-Users] Uboot Memory access violation
by Shiju 15 May '07

15 May '07

Hello, We have a new board based on imx31. I am trying to bring up uboot on the board.I upload uboot through jtag using RVI debugger and run from RAM. But uboot hangs after printing a few greeting messages.Sometimes it could come till the uboot prompt. When I debug it on RVI, the error message it gives is memory access vioaltion. I don't have a source level degugging available right now. So I compare the disassembly from RVI to the u-boot.map file. WHat I could find is that it fails while printing to console(vsprintf.o).I could not exacly map to the correct line of code. The uboot hangs when trying to branch to a location which is not defined (BLNE 0x89533926). On my board the memory is mapped from 0x80000000 - 87FFFFFF. The uboot is based on the imx31 litekit patch that was posted and it was working well on a imx31 freescale ADS.THe memory map for our custom board is same as that of imx freescale ADS board. But I am not sure why it branches to some undefined location. Any help is appreciated. THanks, Shiju

2 1

[U-Boot-Users] [PATCH] Fix for compile of JSE target
by Stephen Williams 15 May '07

15 May '07

The attached patch fixes the compile of the JSE board in the denx git as of 14 may 2007. It is an extremely simple patch, it just adds the missing define of CFG_SYSTEMACE_WIDTH. Fix to compile JSE against 20070514 git of u-boot --- commit bfedb7c81957634eb13d3dc078b1b57a006c0084 tree 6fe80c95ff42066b76e0fc77b18a87db5fdecea5 parent dea6b2fa2f9175fe6f73ac0bfff78eac2a76caca author Stephen Williams <steve(a)wing.icarus.com> Mon, 14 May 2007 19:18:19 -0700 committer Stephen Williams <steve(a)wing.icarus.com> Mon, 14 May 2007 19:18:19 -0700 include/configs/JSE.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."

1 0

[U-Boot-Users] about "flash extend data"
by 孙彬 15 May '07

15 May '07

/******************************************************************************* * flashDataExt - Extend Data. * DESCRIPTION: * Should be used only for FLASH CFI command sequence. * * Prepare the Data according to the Flash Width and Bus Width. * If flash width = 2 and bus width = 1 data = 0x55 -> data = 0x55 * If flash width = 2 and bus width = 4 data = 0x55 -> data = 0x550055 * If flash width = 1 and bus width = 4 data = 0x55 -> data = 0x55555555 * * INPUT: * data - Data to be expended. * pFlash - flash information. * * OUTPUT: * None * * RETURN: * MV_U32 - Data after extension. * OxFFFFFFFF if pFlash is Null * *******************************************************************************/ MV_U32 flashDataExt( MV_FLASH_INFO *pFlash, MV_U32 data) { MV_U32 i; if(NULL == pFlash) return 0xFFFFFFFF; for(i = 0; i < pFlash->busWidth ; i+= pFlash->devWidth) { data |= data << 8*i; } return data; } This is the code of flash initialization in u-boot,i am not sure what's use of the extend data. regards sun --------------------------------- 抢注雅虎免费邮箱3.5G容量，20M附件！

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[U-Boot-Users] why "go 0x0" and "go 0x0c000000" could start u-boot?
by HoHo_Zhao 15 May '07

15 May '07

hello, everyone: (Will somebody write to me to tell me how i can see your replies?) when reset cpu or power up, u-boot starts, press any key to stop it automaticly boot the kernel, i test "go 0x0" and "go 0x0c000000", but two of them could go to restart u-boot! I am sure u-boot was flashed in 0x0c000000, but why "go 0x0" has the same effect?! With my mxlads board, I know another truth, when power up, cpu exec the first cmd in 0x0c000000. (this could be set by switches) Somebody know why? HoHo_Zhao

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[U-Boot-Users] Patch: MPC8220 FEC and DMA update - part 6
by TsiChung Liew 15 May '07

15 May '07

- Better handling in ethernet MII, applied new DMA functions Regards, TsiChung Liew Signed-off by: TsiChung Liew Tsi-Chung.Liew(a)freescale.com diff -rupN u-boot-all.git/cpu/mpc8220/MCD_tasksInit.c u-boot-all-8220- fec/cpu/mpc8220/MCD_tasksInit.c --- u-boot-all.git/cpu/mpc8220/MCD_tasksInit.c 1969-12-31 18:00:00.000000000 -0600 +++ u-boot-all-8220-fec/cpu/mpc8220/MCD_tasksInit.c 2007-05-10 17:53:38.000000000 -0500 @@ -0,0 +1,253 @@ +/* + * (C) Copyright 2004 + * Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * File: MCD_tasksInit.c + * Purpose: Functions for initializing variable tables of different + * types of tasks. + * + * Notes: + */ + +/* + * Do not edit! + */ + +#include "MCD_dma.h" + +extern dmaRegs *MCD_dmaBar; + +/* + * Task 0 + */ + +void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, + int xferSize, short xferSizeIncr, int *cSave, + volatile TaskTableEntry * taskTable, int channel) +{ + + MCD_SET_VAR(taskTable + channel, 2, (u32) currBD); /* var[2] */ + MCD_SET_VAR(taskTable + channel, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ + MCD_SET_VAR(taskTable + channel, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ + MCD_SET_VAR(taskTable + channel, 11, (u32) xferSize); /* var[11] */ + MCD_SET_VAR(taskTable + channel, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ + MCD_SET_VAR(taskTable + channel, 0, (u32) cSave); /* var[0] */ + MCD_SET_VAR(taskTable + channel, 1, (u32) 0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable + channel, 3, (u32) 0x00000000); /* var[3] */ + MCD_SET_VAR(taskTable + channel, 4, (u32) 0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable + channel, 5, (u32) 0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable + channel, 6, (u32) 0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable + channel, 7, (u32) 0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable + channel, 8, (u32) 0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable + channel, 9, (u32) 0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable + channel, 10, (u32) 0x00000000); /* var[10] */ + MCD_SET_VAR(taskTable + channel, 12, (u32) 0x00000000); /* var[12] */ + MCD_SET_VAR(taskTable + channel, 13, (u32) 0x80000000); /* var[13] */ + MCD_SET_VAR(taskTable + channel, 14, (u32) 0x00000010); /* var[14] */ + MCD_SET_VAR(taskTable + channel, 15, (u32) 0x00000004); /* var[15] */ + MCD_SET_VAR(taskTable + channel, 16, (u32) 0x08000000); /* var[16] */ + MCD_SET_VAR(taskTable + channel, 27, (u32) 0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable + channel, 28, (u32) 0x80000000); /* inc[4] */ + MCD_SET_VAR(taskTable + channel, 29, (u32) 0x80000001); /* inc[5] */ + MCD_SET_VAR(taskTable + channel, 30, (u32) 0x40000000); /* inc[6] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; +} + +/* + * Task 1 + */ + +void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, + short destIncr, int dmaSize, short xferSizeIncr, + int flags, int *currBD, int *cSave, + volatile TaskTableEntry * taskTable, int channel) +{ + + MCD_SET_VAR(taskTable + channel, 7, (u32) srcAddr); /* var[7] */ + MCD_SET_VAR(taskTable + channel, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ + MCD_SET_VAR(taskTable + channel, 2, (u32) destAddr); /* var[2] */ + MCD_SET_VAR(taskTable + channel, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ + MCD_SET_VAR(taskTable + channel, 3, (u32) dmaSize); /* var[3] */ + MCD_SET_VAR(taskTable + channel, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ + MCD_SET_VAR(taskTable + channel, 5, (u32) flags); /* var[5] */ + MCD_SET_VAR(taskTable + channel, 1, (u32) currBD); /* var[1] */ + MCD_SET_VAR(taskTable + channel, 0, (u32) cSave); /* var[0] */ + MCD_SET_VAR(taskTable + channel, 4, (u32) 0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable + channel, 6, (u32) 0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable + channel, 8, (u32) 0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable + channel, 9, (u32) 0x00000004); /* var[9] */ + MCD_SET_VAR(taskTable + channel, 10, (u32) 0x08000000); /* var[10] */ + MCD_SET_VAR(taskTable + channel, 27, (u32) 0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable + channel, 28, (u32) 0x80000001); /* inc[4] */ + MCD_SET_VAR(taskTable + channel, 29, (u32) 0x40000000); /* inc[5] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; +} + +/* + * Task 2 + */ + +void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, + int xferSize, short xferSizeIncr, int *cSave, + volatile TaskTableEntry * taskTable, int channel) +{ + + MCD_SET_VAR(taskTable + channel, 3, (u32) currBD); /* var[3] */ + MCD_SET_VAR(taskTable + channel, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ + MCD_SET_VAR(taskTable + channel, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ + MCD_SET_VAR(taskTable + channel, 12, (u32) xferSize); /* var[12] */ + MCD_SET_VAR(taskTable + channel, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ + MCD_SET_VAR(taskTable + channel, 0, (u32) cSave); /* var[0] */ + MCD_SET_VAR(taskTable + channel, 1, (u32) 0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable + channel, 2, (u32) 0x00000000); /* var[2] */ + MCD_SET_VAR(taskTable + channel, 4, (u32) 0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable + channel, 5, (u32) 0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable + channel, 6, (u32) 0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable + channel, 7, (u32) 0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable + channel, 8, (u32) 0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable + channel, 9, (u32) 0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable + channel, 10, (u32) 0x00000000); /* var[10] */ + MCD_SET_VAR(taskTable + channel, 11, (u32) 0x00000000); /* var[11] */ + MCD_SET_VAR(taskTable + channel, 13, (u32) 0x00000000); /* var[13] */ + MCD_SET_VAR(taskTable + channel, 14, (u32) 0x80000000); /* var[14] */ + MCD_SET_VAR(taskTable + channel, 15, (u32) 0x00000010); /* var[15] */ + MCD_SET_VAR(taskTable + channel, 16, (u32) 0x00000001); /* var[16] */ + MCD_SET_VAR(taskTable + channel, 17, (u32) 0x00000004); /* var[17] */ + MCD_SET_VAR(taskTable + channel, 18, (u32) 0x08000000); /* var[18] */ + MCD_SET_VAR(taskTable + channel, 27, (u32) 0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable + channel, 28, (u32) 0x80000000); /* inc[4] */ + MCD_SET_VAR(taskTable + channel, 29, (u32) 0xc0000000); /* inc[5] */ + MCD_SET_VAR(taskTable + channel, 30, (u32) 0x80000001); /* inc[6] */ + MCD_SET_VAR(taskTable + channel, 31, (u32) 0x40000000); /* inc[7] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; +} + +/* + * Task 3 + */ + +void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, + short destIncr, int dmaSize, short xferSizeIncr, + int flags, int *currBD, int *cSave, + volatile TaskTableEntry * taskTable, int channel) +{ + + MCD_SET_VAR(taskTable + channel, 8, (u32) srcAddr); /* var[8] */ + MCD_SET_VAR(taskTable + channel, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ + MCD_SET_VAR(taskTable + channel, 3, (u32) destAddr); /* var[3] */ + MCD_SET_VAR(taskTable + channel, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ + MCD_SET_VAR(taskTable + channel, 4, (u32) dmaSize); /* var[4] */ + MCD_SET_VAR(taskTable + channel, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ + MCD_SET_VAR(taskTable + channel, 6, (u32) flags); /* var[6] */ + MCD_SET_VAR(taskTable + channel, 2, (u32) currBD); /* var[2] */ + MCD_SET_VAR(taskTable + channel, 0, (u32) cSave); /* var[0] */ + MCD_SET_VAR(taskTable + channel, 1, (u32) 0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable + channel, 5, (u32) 0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable + channel, 7, (u32) 0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable + channel, 9, (u32) 0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable + channel, 10, (u32) 0x00000001); /* var[10] */ + MCD_SET_VAR(taskTable + channel, 11, (u32) 0x00000004); /* var[11] */ + MCD_SET_VAR(taskTable + channel, 12, (u32) 0x08000000); /* var[12] */ + MCD_SET_VAR(taskTable + channel, 27, (u32) 0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable + channel, 28, (u32) 0xc0000000); /* inc[4] */ + MCD_SET_VAR(taskTable + channel, 29, (u32) 0x80000000); /* inc[5] */ + MCD_SET_VAR(taskTable + channel, 30, (u32) 0x80000001); /* inc[6] */ + MCD_SET_VAR(taskTable + channel, 31, (u32) 0x40000000); /* inc[7] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; +} + +/* + * Task 4 + */ + +void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, + volatile TaskTableEntry * taskTable, int channel) +{ + + MCD_SET_VAR(taskTable + channel, 0, (u32) bDBase); /* var[0] */ + MCD_SET_VAR(taskTable + channel, 3, (u32) currBD); /* var[3] */ + MCD_SET_VAR(taskTable + channel, 6, (u32) rcvFifoPtr); /* var[6] */ + MCD_SET_VAR(taskTable + channel, 1, (u32) 0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable + channel, 2, (u32) 0x00000000); /* var[2] */ + MCD_SET_VAR(taskTable + channel, 4, (u32) 0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable + channel, 5, (u32) 0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable + channel, 7, (u32) 0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable + channel, 8, (u32) 0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable + channel, 9, (u32) 0x0000ffff); /* var[9] */ + MCD_SET_VAR(taskTable + channel, 10, (u32) 0x30000000); /* var[10] */ + MCD_SET_VAR(taskTable + channel, 11, (u32) 0x0fffffff); /* var[11] */ + MCD_SET_VAR(taskTable + channel, 12, (u32) 0x00000008); /* var[12] */ + MCD_SET_VAR(taskTable + channel, 24, (u32) 0x00000000); /* inc[0] */ + MCD_SET_VAR(taskTable + channel, 25, (u32) 0x60000000); /* inc[1] */ + MCD_SET_VAR(taskTable + channel, 26, (u32) 0x20000004); /* inc[2] */ + MCD_SET_VAR(taskTable + channel, 27, (u32) 0x40000000); /* inc[3] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; +} + +/* + * Task 5 + */ + +void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, + volatile TaskTableEntry * taskTable, int channel) +{ + + MCD_SET_VAR(taskTable + channel, 0, (u32) bDBase); /* var[0] */ + MCD_SET_VAR(taskTable + channel, 3, (u32) currBD); /* var[3] */ + MCD_SET_VAR(taskTable + channel, 11, (u32) xmitFifoPtr); /* var[11] */ + MCD_SET_VAR(taskTable + channel, 1, (u32) 0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable + channel, 2, (u32) 0x00000000); /* var[2] */ + MCD_SET_VAR(taskTable + channel, 4, (u32) 0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable + channel, 5, (u32) 0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable + channel, 6, (u32) 0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable + channel, 7, (u32) 0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable + channel, 8, (u32) 0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable + channel, 9, (u32) 0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable + channel, 10, (u32) 0x00000000); /* var[10] */ + MCD_SET_VAR(taskTable + channel, 12, (u32) 0x00000000); /* var[12] */ + MCD_SET_VAR(taskTable + channel, 13, (u32) 0x0000ffff); /* var[13] */ + MCD_SET_VAR(taskTable + channel, 14, (u32) 0xffffffff); /* var[14] */ + MCD_SET_VAR(taskTable + channel, 15, (u32) 0x00000004); /* var[15] */ + MCD_SET_VAR(taskTable + channel, 16, (u32) 0x00000008); /* var[16] */ + MCD_SET_VAR(taskTable + channel, 24, (u32) 0x00000000); /* inc[0] */ + MCD_SET_VAR(taskTable + channel, 25, (u32) 0x60000000); /* inc[1] */ + MCD_SET_VAR(taskTable + channel, 26, (u32) 0x40000000); /* inc[2] */ + MCD_SET_VAR(taskTable + channel, 27, (u32) 0xc000fffc); /* inc[3] */ + MCD_SET_VAR(taskTable + channel, 28, (u32) 0xe0000004); /* inc[4] */ + MCD_SET_VAR(taskTable + channel, 29, (u32) 0x80000000); /* inc[5] */ + MCD_SET_VAR(taskTable + channel, 30, (u32) 0x4000ffff); /* inc[6] */ + MCD_SET_VAR(taskTable + channel, 31, (u32) 0xe0000001); /* inc[7] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; +} diff -rupN u-boot-all.git/cpu/mpc8220/MCD_tasksInit.h u-boot-all-8220- fec/cpu/mpc8220/MCD_tasksInit.h --- u-boot-all.git/cpu/mpc8220/MCD_tasksInit.h 1969-12-31 18:00:00.000000000 -0600 +++ u-boot-all-8220-fec/cpu/mpc8220/MCD_tasksInit.h 2007-05-10 17:53:38.000000000 -0500 @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2004 + * Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MCD_TSK_INIT_H +#define MCD_TSK_INIT_H 1 + +/* + * Do not edit! + */ + +/* + * Task 0 + */ +void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, + int xferSize, short xferSizeIncr, int *cSave, + volatile TaskTableEntry * taskTable, int channel); + +/* + * Task 1 + */ +void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, + short destIncr, int dmaSize, short xferSizeIncr, + int flags, int *currBD, int *cSave, + volatile TaskTableEntry * taskTable, int channel); + +/* + * Task 2 + */ +void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, + int xferSize, short xferSizeIncr, int *cSave, + volatile TaskTableEntry * taskTable, int channel); + +/* + * Task 3 + */ +void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, + short destIncr, int dmaSize, short xferSizeIncr, + int flags, int *currBD, int *cSave, + volatile TaskTableEntry * taskTable, int channel); + +/* + * Task 4 + */ +void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, + volatile TaskTableEntry * taskTable, int channel); + +/* + * Task 5 + */ +void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, + volatile TaskTableEntry * taskTable, int channel); + +#endif /* MCD_TSK_INIT_H */ diff -rupN u-boot-all.git/include/configs/Alaska8220.h u-boot-all-8220- fec/include/configs/Alaska8220.h --- u-boot-all.git/include/configs/Alaska8220.h 2007-04-03 19:18:56.000000000 -0500 +++ u-boot-all-8220-fec/include/configs/Alaska8220.h 2007-05-10 19:47:01.438535584 -0500 @@ -274,8 +274,8 @@ */ #define CONFIG_MPC8220_FEC 1 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ -#define CONFIG_PHY_ADDR 0x18 - +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_PHY1_ADDR 0x18 /* * Miscellaneous configurable options

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