April 2007 - U-Boot

[U-Boot-Users] fdt_chosen()
by Timur Tabi 19 Apr '07

19 Apr '07

Jerry, I noticed that fdt_chosen() is called with force=0. Does that mean that if the DTB has a chosen node in it already, that it won't be overwritten? If so, I think that's wrong, because some DTBs have a bogus chosen section in them that has, in the past, always been overwritten by U-Boot. If the chosen node already exists, then it means that it was present in the DTS when it was compiled, and that means the DTS is probably old and the chosen node has bad data in it. -- Timur Tabi Linux Kernel Developer @ Freescale

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[U-Boot-Users] help!!!,where can i find the u-boot-lpc2294.patch
by chenzhixin 19 Apr '07

19 Apr '07

my board is easyarm2200,base on LPC2210 chip, today, i found a uboot.pdf in http://www.nxp.com/acrobat_download/other/uboot.pdf in that pdf ,it says : 2.3 Unpack U-boot Package and add the Lpc2294 patch Unpack the package, and then add the LPC2294 patch(be sure the patch file is in the src directory). Proceed as follows: [root@localhost src]# bunzip2 < u-boot-1.1.3.tar.bz2 | tar xf – [root@localhost src]# cd u-boot-1.1.3 [root@localhost u-boot-1.1.3]# patch –p1 < ../u-boot-lpc2294.patch but the u-boot-lpc2294.patch can't found in the nxp,where can i found it? thanks very much,please help me

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[U-Boot-Users] Internel Memeory test using Uboot
by harsh poshtiwala 19 Apr '07

19 Apr '07

Hi , I am using Nomadik (nmdk88810) / ARM926-EJS processor.It has internel RAM of ( Tightly Coupled Memory ) 40 KB. I would like to test the internel RAM. i.e I want to write some pattern on it and read it. My idea is to use u-boot to check it ,since u -boot has different memory commands for memory check and memory test. I have a u-boot 1.1.1 from ST microelectronics for nmdk88810.After building u-boot the binary ( Uboot.bin) size is 146 KB. Which gets loaded to FLASH and hence RAM of the board. (The Development board has internal (Processor) and external memory). I was thinking of stripping of unnecessary functionality from the u-boot to achieve my goal. i.e i don't want to have networking library / functionality. Simiarly i don't need to have file system library /functionality Am i following the right approch? is it possible to just make changes in the Top level Makefile of uboot and achieve this ? Is there any better way around ? I am looking for some pointers from you. - - Thanks & Regards Harsh

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[U-Boot-Users] where can i find the u-boot-lpc2294.patch
by chenzhixin 19 Apr '07

19 Apr '07

first ,thanks for your coming, today ,i have download a pdf from nxp for lpc22xx,this pdf is created in 07-2-15 http://www.nxp.com/acrobat_download/other/uboot.pdf in this pdf,there are : Unpack U-boot Package and add the Lpc2294 patch Unpack the package, and then add the LPC2294 patch(be sure the patch file is in the src directory). Proceed as follows: [root@localhost src]# bunzip2 < u-boot-1.1.3.tar.bz2 | tar xf – [root@localhost src]# cd u-boot-1.1.3 [root@localhost u-boot-1.1.3]# patch –p1 < ../u-boot-lpc2294.patch where can i find the u-boot-lpc2294.patch?,i find in the nxp.com with long time,but i can found anything about this .

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Re: [U-Boot-Users] [PATCH: dtc take 2] Assemble the blob in memory before writing it out.
by David Gibson 19 Apr '07

19 Apr '07

On Wed, Apr 18, 2007 at 09:59:51PM -0400, Jerry Van Baren wrote: > This makes padding out the blob if the user requested extra size much > easer. The assembly and writing to the file is more straight forward too. > > Signed-off-by: Gerald Van Baren <vanbaren(a)cideas.com> > --- > > Hi David, Jon, > > I wasn't happy with David's suggestion on the -S handling. I also wasn't > all that wild about how the blob was assembled and then written to the > file piecemeal with "ad-hoc" alignment padding. I realized I could fix > both by assembling the blob in memory as a "struct data" and then write > the whole thing out in one fell swoop. > > Makes it a lot simpler and cleaner to my eyes. I like it. (In fact my original suggestion about using data_append_zeroes() was based on a mistaken vague notion that we already did it this way). Acked-by: David Gibson <david(a)gibson.dropbear.id.au> -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson

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[U-Boot-Users] [PATCH 00/07 v2]: Add mpc7448hpc2 (Taiga) board support
by Zang Roy-r61911 19 Apr '07

19 Apr '07

This series of patches add mpc7448hpc2 board support. Mpc7448hpc2 (taiga) board is a high-performance PowerPC server reference design. This is the second version for this board support according to the feedback from mailing list. Roy Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- doc/README.mpc7448hpc2 | 181 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 181 insertions(+), 0 deletions(-) diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2 new file mode 100644 index 0000000..00fda4e --- /dev/null +++ b/doc/README.mpc7448hpc2 @@ -0,0 +1,181 @@ +Freescale MPC7448hpc2 (Taiga) board +-------------------------- +MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference +design, which is optimized for high speed throughput between the processor and +the memory, disk drive and Ethernet port subsystems. + +MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be +used in 1U or 2U rack-mount chassis', as well as in standard ATX/Micro-ATX +chassis. + + +Memory Map +---------- + +The memory map is setup for Linux to operate properly. + +The mapping is: + + Range Start Range End Definition Size + + 0x0000_0000 0x7fff_ffff DDR 2G + 0xe000_0000 0xe7ff_ffff PCI Memory 128M + 0xfa00_0000 0xfaff_ffff PCI IO 16M + 0xfb00_0000 0xfbff_ffff PCI Config 16M + 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M + 0xfe00_0000 0xfeff_ffff PromJet 16M + 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M + 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M + + +Using Flash +----------- + +The MPC7448hpc2 board has two "banks" of flash, each 8MB in size +(2^23 = 0x00800000). + +Note: the "bank" here refers to half of the flash. In fact, there is only one +bank of flash, which is divided into low and high half. Each is controlled by +the most significant bit of the address bus. The so called "bank" is only for +convenience. + +There is a switch which allows the "bank" to be selected. The switch +settings for updating flash are given below. + +The u-boot commands for copying the boot-bank into the secondary bank are +as follows: + + erase ff800000 ff880000 + cp.b ff000000 ff800000 80000 + +U-boot commands for downloading an image via tftp and flashing +it into the secondary bank: + + tftp 10000 <u-boot.bin.image> + erase ff000000 ff080000 + cp.b 10000 ff000000 80000 + + +After copying the image into the second bank of flash, be sure to toggle +SW3[4] on board before resetting the board in order to set the +secondary bank as the boot-bank. + + +Board Switches +---------------------- + + +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks and determining the PCI frequency. + +SW1[1-5]: Processor core voltage + + 12345 Core Voltage + ----- + SW1=01111 1.000V. + SW1=01101 1.100V. + SW1=01011 1.200V. + SW1=01001 1.300V only for MPC7447A. + + +SW2[1-6]: CPU core frequency + + CPU Core Frequency (MHz) + Bus Frequency + 123456 100 133 167 200 Ratio + + ------ + SW2=101100 500 667 833 1000 5x + SW2=100100 550 733 917 1100 5.5x + SW2=110100 600 800 1000 1200 6x + SW2=010100 650 866 1083 1300 6.5x + SW2=001000 700 930 1167 1400 7x + SW2=000100 750 1000 1250 1500 7.5x + SW2=110000 800 1066 1333 1600 8x + SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A + SW2=011110 900 1200 1500 1800 9x + +This table shows only a subset of available frequency options; see the CPU +hardware specifications for more information. + + +SW2[7-8]: Bus Protocol and CPU Reset Option + + 7 + - + SW2=0 System bus uses MPX bus protocol + SW2=1 System bus uses 60x bus protocol + + 8 + - + SW2=0 TSI108 can cause CPU reset + SW2=1 TSI108 can not cause CPU reset + + +SW3[1-8] system options + + 123 + --- + SW3=xxx Connected to GPIO[0:2] on TSI108 + + 4 + - + SW3=0 CPU boots from low half of flash + SW3=1 CPU boots from high half of flash + + 5 + - + SW3=0 SATA and slot2 connected to PCI bus + SW3=1 Only slot1 connected to PCI bus + + 6 + - + SW3=0 USB connected to PCI bus + SW3=1 USB disconnected from PCI bus + + 7 + - + SW3=0 Flash is write protected + SW3=1 Flash is NOT write protected + + 8 + - + SW3=0 CPU will boot from flash + SW3=1 CPU will boot from PromJet + +SW4[1-3]: System bus frequency + + Bus Frequency (MHz) + --- + SW4=010 183 + SW4=011 100 + SW4=100 133 + SW4=101 166 only for MPC7447A + SW4=110 200 only for MPC7448 + others reserved + + +SW4[4-6]: DDR2 SDRAM frequency + + Bus Frequency (MHz) + --- + SW4=000 external clock + SW4=011 system clock + SW4=100 133 + SW4=101 166 + SW4=110 200 + others reserved + + +SW4[7-8]: PCI/PCI-X frequency control + 7 + - + SW4=0 PCI/PCI-X bus operates normally + SW4=1 PCI bus forced to PCI-33 mode + + 8 + - + SW4=0 PCI-X mode at 133 MHz allowed + SW4=1 PCI-X mode limited to 100 MHz + -- 1.4.0

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[U-Boot-Users] loading image with kermit
by Junior 19 Apr '07

19 Apr '07

Hi All, I'm trying to load the image with the loadb command using kermit 8.0.211 with no suscess. It seem to be failing and any retries did not work. I haven't used kermit before but I set it up correctly and used the send_image script in tools/script. I tried to do this by hand when I'm connected to the target but it seem like loadb is stuck and the file is never downloaded. I'm using "loadb k_img 0xc01cf0000" with also no suscess. Could someone give me some directions on how to get downloads to work? Much thanks. --Jr.

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[U-Boot-Users] Spansion flash not detected by CFI driver
by Shiju 18 Apr '07

18 Apr '07

Hello, I have sent this mail in an other mail id. Looks like it hasn't reached the mailing list. Hence forwarding again. I have a spansion flash (S71WS256ND0BFWEP) on my board (Freescale imx31 ADS).I use CFI driver with the below configuration. But I get the following error(debug message). I am not able to write to the flash memory too. Currently I use an other bootloader on the board to flash uboot. Could someone help me to resolve the problem. #define CFG_FLASH_BASE 0xa0000000 #define CFG_MAX_FLASH_BANKS 1 #define CFG_MAX_FLASH_SECT 128 #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_USE_BUFFER_WRITE 1 U-Boot 1.2.0 (Apr 17 2007 - 18:43:30) U-Boot code: 87F00000 -> 87F1BD48 BSS: -> 87F22370 CPU: Freescale i.MX31 at 398 MHz Board: i.MX31 Litekit RAM Configuration: Bank #0: 80000000 128 MB flash detect cfi fwc addr a0000000 cmd 0 0 8bit x 8 bit fwc addr a0000055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr a0000010 is= 14 51 fwc addr a0000555 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr a0000010 is= 14 51 fwc addr a0000000 cmd 0 0000 16bit x 8 bit fwc addr a00000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr a0000020 is= 0100 5151 fwc addr a0000aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr a0000020 is= 0051 5151 fwc addr a0000000 cmd 0 0000 16bit x 16 bit fwc addr a00000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr a0000020 is= 0100 0051 fwc addr a0000aaa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr a0000020 is= 0051 0051 is= cmd 52(R) addr a0000022 is= 0052 0052 is= cmd 59(Y) addr a0000024 is= 0059 0059 ushort addr is at a0000050 info->portwidth = 2 addr[0] = 0x1 addr[1] = 0x0 addr[2] = 0x0 addr[3] = 0x0 retval = 0x1 device interface is 1 found port 2 chip 2 port 16 bits chip 16 bits ushort addr is at a0000026 info->portwidth = 2 addr[0] = 0x2 addr[1] = 0x0 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 fwc addr a0000000 cmd f0 00f0 16bit x 16 bit fwc addr a0000aaa cmd aa 00aa 16bit x 16 bit fwc addr a0000554 cmd 55 0055 16bit x 16 bit fwc addr a0000aaa cmd 90 0090 16bit x 16 bit fwc addr a0000000 cmd f0 00f0 16bit x 16 bit fwc addr a0000aaa cmd 98 0098 16bit x 16 bit ushort addr is at a000002a info->portwidth = 2 addr[0] = 0x40 addr[1] = 0x0 addr[2] = 0x0 addr[3] = 0x0 retval = 0x40 a0000020 : 51 00 52 00 59 00 02 00 00 00 40 00 00 00 00 00 Q.R.Y.....@..... a0000030 : 00 00 00 00 00 00 17 00 19 00 00 00 00 00 06 00 ................ a0000040 : 09 00 0a 00 00 00 04 00 04 00 03 00 00 00 19 00 ................ a0000050 : 01 00 00 00 06 00 00 00 03 00 03 00 00 00 80 00 ................ a0000060 : 00 00 fd 00 00 00 00 00 02 00 03 00 00 00 80 00 ................ a0000070 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ a0000080 : 50 00 52 00 49 00 31 00 34 00 10 00 02 00 01 00 P.R.I.1.4....... a0000090 : 00 00 08 00 f3 00 01 00 00 00 85 00 95 00 01 00 ................ manufacturer is 2 manufacturer id is 0x1 device id is 0x7e device id2 is 0x3000 cfi version is 0x3134 size_ratio 1 port 16 bits chip 16 bits found 3 erase regions long addr is at a000005a info->portwidth = 2 addr[0] = 0x3 addr[1] = 0x0 addr[2] = 0x0 addr[3] = 0x0 addr[4] = 0x80 addr[5] = 0x0 addr[6] = 0x0 addr[7] = 0x0 erase_region_count = 4 erase_region_size = 32768 long addr is at a0000062 info->portwidth = 2 addr[0] = 0xfd addr[1] = 0x0 addr[2] = 0x0 addr[3] = 0x0 addr[4] = 0x0 addr[5] = 0x0 addr[6] = 0x2 addr[7] = 0x0 erase_region_count = 254 erase_region_size = 131072 long addr is at a0000000 info->portwidth = 0 erase_region_count = 65536 erase_region_size = 16776960 ushort addr is at a0000000 info->portwidth = 0 retval = 0xffff Flash Size is 0 flash_protect ON: from 0xA0000000 to 0xA001BD47 flash_protect ON: from 0xA01F0000 to 0xA01FFFFF Flash: 0 kB *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial ### Set environment from HW MAC addr = "00:04:9F:00:0E:B0" ### main_loop entered: bootdelay=3 ### main_loop: bootcmd="run bootcmd_net" Hit any key to stop autoboot: 0 uboot> Thanks, Shiju

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[U-Boot-Users] Please pull u-boot-mpc86xx.git
by Jon Loeliger 18 Apr '07

18 Apr '07

Wolfgang, These changes will be needed for the MPC8544DS port as they contain the common code introduced into the new board/freescale directory. Thanks, jdl The following changes since commit 6db7d0af2336c126e4d4b2f248cc23516bdd46a8: Wolfgang Denk (1): Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xx are found in the git repository at: git://www.denx.de/git/u-boot-mpc86xx.git Haiying Wang (1): Add PIXIS FPGA support for MPC8641HPCN board. board/freescale/common/pixis.c | 472 +++++++++++++++++++++++ board/{mpc8641hpcn => freescale/common}/pixis.h | 4 +- board/mpc8641hpcn/Makefile | 4 +- board/mpc8641hpcn/mpc8641hpcn.c | 113 +------ board/mpc8641hpcn/pixis.c | 321 --------------- cpu/mpc86xx/cpu.c | 8 +- doc/README.mpc8641hpcn | 34 ++ 7 files changed, 514 insertions(+), 442 deletions(-) create mode 100644 board/freescale/common/pixis.c rename board/{mpc8641hpcn => freescale/common}/pixis.h (90%) delete mode 100644 board/mpc8641hpcn/pixis.c

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[U-Boot-Users] [Blackfin] Please pull http://www.denx.de/git/u-boot-blackfin.git
by Aubrey Li 18 Apr '07

18 Apr '07

Dear Wolfgang, The following changes since commit 25b0806fff1f1fd24f69f6d9ef04d8345667e60b: Wolfgang Denk (1): Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx are found in the git repository at: http://www.denx.de/git/u-boot-blackfin.git Aubrey Li (8): [Blackfin][PATCH]: fix flash unaligned copy issue [Blackfin][PATCH] remove asm/page.h as we do not actually use/want any of these definitions nor does any other arch include it [Blackfin][PATCH] call real the system synchronize instruction [Blackfin][PATCH] Add BF537 EMAC driver initialization [Blackfin][PATCH] Fix copyright and update license [Blackfin][PATCH] minior cleanup [Blackfin][PATCH] Fix dynamic CPLB generation issue [Blackfin][PATCH] Kill off a bunch of common local prototypes Best Regards, -Aubrey --------------------------------------------------------------------------------- board/bf533-ezkit/Makefile | 2 +- board/bf533-ezkit/bf533-ezkit.c | 6 +- board/bf533-ezkit/flash-defines.h | 8 +- board/bf533-ezkit/flash.c | 83 +++-- board/bf533-ezkit/psd4256.h | 6 +- board/bf533-stamp/Makefile | 2 +- board/bf533-stamp/bf533-stamp.c | 6 +- board/bf533-stamp/bf533-stamp.h | 6 +- board/bf537-stamp/bf537-stamp.c | 6 +- board/bf537-stamp/flash-defines.h | 6 +- board/bf537-stamp/flash.c | 6 +- board/bf561-ezkit/bf561-ezkit.c | 6 +- cpu/bf533/Makefile | 6 +- cpu/bf533/bf533_serial.h | 6 +- cpu/bf533/config.mk | 6 +- cpu/bf533/cpu.c | 10 +- cpu/bf533/cpu.h | 6 +- cpu/bf533/flush.S | 4 +- cpu/bf533/interrupt.S | 6 +- cpu/bf533/interrupts.c | 6 +- cpu/bf533/ints.c | 6 +- cpu/bf533/serial.c | 6 +- cpu/bf533/start.S | 6 +- cpu/bf533/start1.S | 6 +- cpu/bf533/traps.c | 7 +- cpu/bf537/Makefile | 6 +- cpu/bf537/config.mk | 6 +- cpu/bf537/cpu.c | 6 +- cpu/bf537/cpu.h | 6 +- cpu/bf537/flush.S | 4 +- cpu/bf537/interrupt.S | 6 +- cpu/bf537/interrupts.c | 6 +- cpu/bf537/ints.c | 6 +- cpu/bf537/serial.c | 6 +- cpu/bf537/serial.h | 6 +- cpu/bf537/start.S | 6 +- cpu/bf537/start1.S | 6 +- cpu/bf537/traps.c | 7 +- cpu/bf561/Makefile | 6 +- cpu/bf561/config.mk | 6 +- cpu/bf561/cpu.c | 6 +- cpu/bf561/cpu.h | 6 +- cpu/bf561/flush.S | 4 +- cpu/bf561/interrupt.S | 6 +- cpu/bf561/interrupts.c | 6 +- cpu/bf561/ints.c | 6 +- cpu/bf561/serial.c | 6 +- cpu/bf561/serial.h | 6 +- cpu/bf561/start.S | 6 +- cpu/bf561/start1.S | 6 +- cpu/bf561/traps.c | 6 +- include/asm-blackfin/arch-bf533/bf533_serial.h | 6 +- include/asm-blackfin/arch-bf533/bf5xx_rtc.h | 6 +- include/asm-blackfin/arch-bf533/cplbtab.h | 482 ------------------------ include/asm-blackfin/arch-bf533/irq.h | 6 +- include/asm-blackfin/arch-bf537/bf537_serial.h | 6 +- include/asm-blackfin/arch-bf537/bf5xx_rtc.h | 6 +- include/asm-blackfin/arch-bf537/cplbtab.h | 408 -------------------- include/asm-blackfin/arch-bf537/irq.h | 6 +- include/asm-blackfin/arch-bf561/bf561_serial.h | 6 +- include/asm-blackfin/arch-common/bf53x_rtc.h | 6 +- include/asm-blackfin/bitops.h | 6 +- include/asm-blackfin/blackfin.h | 6 +- include/asm-blackfin/blackfin_defs.h | 6 +- include/asm-blackfin/byteorder.h | 6 +- include/asm-blackfin/cplb.h | 10 +- include/asm-blackfin/current.h | 6 +- include/asm-blackfin/delay.h | 6 +- include/asm-blackfin/entry.h | 7 +- include/asm-blackfin/errno.h | 6 +- include/asm-blackfin/global_data.h | 6 +- include/asm-blackfin/hw_irq.h | 6 +- include/asm-blackfin/io-kernel.h | 6 +- include/asm-blackfin/io.h | 7 +- include/asm-blackfin/irq.h | 6 +- include/asm-blackfin/linkage.h | 6 +- include/asm-blackfin/machdep.h | 6 +- include/asm-blackfin/mem_init.h | 6 +- include/asm-blackfin/page.h | 123 ------ include/asm-blackfin/page_offset.h | 6 +- include/asm-blackfin/posix_types.h | 6 +- include/asm-blackfin/processor.h | 6 +- include/asm-blackfin/ptrace.h | 6 +- include/asm-blackfin/segment.h | 6 +- include/asm-blackfin/setup.h | 6 +- include/asm-blackfin/shared_resources.h | 6 +- include/asm-blackfin/string.h | 7 +- include/asm-blackfin/system.h | 6 +- include/asm-blackfin/traps.h | 6 +- include/asm-blackfin/types.h | 6 +- include/asm-blackfin/u-boot.h | 8 +- include/asm-blackfin/uaccess.h | 6 +- include/asm-blackfin/virtconvert.h | 7 +- lib_blackfin/Makefile | 6 +- lib_blackfin/bf533_linux.c | 6 +- lib_blackfin/bf533_string.c | 90 ++--- lib_blackfin/blackfin_board.h | 6 +- lib_blackfin/board.c | 31 +- lib_blackfin/cache.c | 14 +- lib_blackfin/cache.h | 35 ++ lib_blackfin/memcmp.S | 15 +- lib_blackfin/memcpy.S | 21 +- lib_blackfin/memmove.S | 15 +- lib_blackfin/memset.S | 16 +- lib_blackfin/muldi3.c | 6 +- net/eth.c | 4 + 106 files changed, 441 insertions(+), 1458 deletions(-) delete mode 100644 include/asm-blackfin/arch-bf533/cplbtab.h delete mode 100644 include/asm-blackfin/arch-bf537/cplbtab.h delete mode 100644 include/asm-blackfin/page.h create mode 100644 lib_blackfin/cache.h

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