April 2007 - U-Boot

[U-Boot-Users] U-Boot updates
by Ganesh Chandra Patro 23 Apr '07

23 Apr '07

Hi, I was looking for the patch u-boot-lpc2294.patch for U-Boot. When I searched I only found a set of questions where all are looking for the same. The U-Boot documentation includes the u-boot.1.1.13 version. But the latest is u-boot.1.1.16. I thought this would have the patches updated. But neither I could find the patches anywhere nor in the latest u-boot release. Hi Ori Idan, Is it possible for you to share this patch, if still have a copy with you. Thanks Ganesh

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[U-Boot-Users] [Ticket#2007011742000232] [PATCH] Avoid assigning PCI resources from zero ad [...]
by OTRS Notification Master 23 Apr '07

23 Apr '07

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2007011742000232] was created: <snip> > If a PCI IDE card happens to get a zero address assigned to it, the > Linux IDE > core complains and IDE drivers fails to work. Also, assigning zero to a > BAR > was illegal according to PCI 2.1 (the later revisions seem to have > excluded the > sentence about "0" being considered an invalid address) -- so, use a > reasonable > starting value of 0x1000 (that's what the most Linux archs are using). > > Alternatively, one might have fixed the calls to pci_set_region() > individually > (some code even seems to have taken care of this issue) but that would > have > been a lot more work. :-) > > Signed-off-by: Sergei Shtylyov <sshtylyov(a)ru.mvista.com> > > drivers/pci_auto.c | 7 ++++++- > 1 files changed, 6 insertions(+), 1 deletion(-) > > Index: u-boot/drivers/pci_auto.c > =================================================================== > --- u-boot.orig/drivers/pci_auto.c > +++ u-boot/drivers/pci_auto.c > @@ -34,7 +34,12 @@ > > void pciauto_region_init(struct pci_region* res) > { > - res->bus_lower = res->bus_start; > + /* > + * Avoid allocating PCI resources from address 0 -- this is illegal > + * according to PCI 2.1 and moreover, this is known to cause Linux IDE > + * drivers to fail. Use a reasonable starting value of 0x1000 instead. > + */ > + res->bus_lower = res->bus_start ? res->bus_start : 0x1000; > } > > void pciauto_region_align(struct pci_region *res, unsigned long size) </snip> Your U-Boot support team

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[U-Boot-Users] usb problem
by kow9loon 23 Apr '07

23 Apr '07

Hi, We have problems reading/writing from/to a USB NAND flash having a capacity of 512 MB. What we dicovered was: up to a capacity of 128 MB, the operations looked 'koche', thereafter, the system hanged. Our hardware setup are as follows: (1) a MPC8544E CPU; (2) a ISP 1564 PCI-USB 2.0 Host Controller; (3) a ST72681 Flash Driver Controller; and (4) a 512 MB Nand flash. We also understand that support of the OHCI driver in U-boot is only limited to support of "Mass Storage Device" class device, and rapid reading and writing could post a potential problem. We deliberately slow down the read/write traffic in an attempt to give some breathing rooms to the the driver (and possibly to the controller). Unfortunately, our endeavors, thus far, have only limited success. We would appreciate any comments that could help us to dig our way out of this hole. Thank you. Regards, Kow9loon -- View this message in context: http://www.nabble.com/usb-problem-tf3603390.html#a10066981 Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] Debugging u-boot
by Pharaoh . 23 Apr '07

23 Apr '07

Hi Is there any open leven debugger available for source level debugging of u-boot? Pharaoh.

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[U-Boot-Users] thumb-interwork option
by Alessandro Accattini 23 Apr '07

23 Apr '07

Hi everyone, I am trying to compile u-boot for ARM (mc9328mx1), my target board is similar to ADSMX1 board. My problem is that: I compile u-boot succesfully but my binary image doesn't boot at all. The board is death at all. It seems -mthumb-interwork option is needed to let it work. Anyone know how to pass -mthumb-interwork to u-boot compile process? export CFLAGS=-mthumb-interwork does't seem to work. Thanks.

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[U-Boot-Users] 'fdt set' doesn't work
by Timur Tabi 23 Apr '07

23 Apr '07

What am I missing? => fdt list /qe@e0100000 brg-frequency brg-frequency=<00000000> => fdt set /qe@e0100000 brg-frequency 0bcd3d80 libfdt FDT_ERR_NOSPACE

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[U-Boot-Users] Testing todays u-boot-fdt
by Wolfgang Grandegger 23 Apr '07

23 Apr '07

Hi Jerry, I gave the fdtlib of your git://cideas.us/pub/scm/u-boot/u-boot-fdt.git a try on my Icecube board. I got it built with the attached patch. libfdt was actually not made and the second hunk fixes a warning (=bug?). Then I was able to read and list a blob in memory: => fdt addr 20000 => fdt print / ... A few other things didn't work, especially updating the FDT: => fdt addr 20000 10000 libfdt: FDT_ERR_BADVERSION => fdt env libfdt: FDT_ERR_BADVERSION => fdt bd_t libfdt: FDT_ERR_BADVERSION => fdt chosen libfdt: FDT_ERR_BADVERSION => fdt set /memory reg "<00000000 08000000>" Usage: fdt - flattened device tree utility commands And "fdt mknode" seems not to be implemented. Am I doing something wrong? Wolfgang.

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[U-Boot-Users] SystemACE
by Michal Simek 21 Apr '07

21 Apr '07

Hi, I have debugged systemace driver and ported it on Microblaze. I use SystemACE for loading bitstream to FPGA. But if the SystemACE initializes FPGA this part of code sets to zero CFGDONE bit in STATUSREG. And then release_cf_lock function resets SystemACE. I add this part of code to microblaze-git repository. Please test it if you can. Best regards, Michal Simek +/* + * For FPGA configuration via SystemACE is reset unacceptable + * CFGDONE bit in STATUSREG is not set to 1. + */ +#ifndef SYSTEMACE_CONFIG_FPGA /* Reset the configruation controller */ val = ace_readw(0x18); val |= 0x0080; ace_writew(val, 0x18); +#endif retry = trans * 16; while (retry > 0) {

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[U-Boot-Users] [PATCH] Make Xilinx uartlite driver usable by more than just microblaze
by Grant Likely 21 Apr '07

21 Apr '07

A number of changes which makes the UARTLITE driver suitable for use by other architectures (most notibly ppc405 on the Xilinx Virtex). - Add new config values CONFIG_XILINX_UARTLITE to enable the driver and CONFIG_XILINX_UARTLITE_BASE for specifying the base address - Remove Xilinx supplied driver files from include/asm-microblaze. They don't have GPL compatible copyright notices and they're not needed anyway. - Rework driver to use in_be32() and out_be32() macros for register access. Tested on Xilinx ml403 with ppc405 design. Signed-off-by: Grant Likely <grant.likely(a)secretlab.ca> --- I have not tested this on Microblaze. Can somebody please verify for me? Also can be pulled from: git://git.secretlab.ca/git/u-boot.git for-upstream Thanks, g. drivers/serial_xuartlite.c | 61 ++++-- .../asm-microblaze/arch-microblaze/xuartlite_l.h | 256 -------------------- include/asm-microblaze/serial_xuartlite.h | 25 -- include/configs/suzaku.h | 6 +- 4 files changed, 46 insertions(+), 302 deletions(-) delete mode 100644 include/asm-microblaze/arch-microblaze/xuartlite_l.h delete mode 100644 include/asm-microblaze/serial_xuartlite.h diff --git a/drivers/serial_xuartlite.c b/drivers/serial_xuartlite.c index ed59abe..912744d 100644 --- a/drivers/serial_xuartlite.c +++ b/drivers/serial_xuartlite.c @@ -1,5 +1,7 @@ /* + * (C) Copyright 2007 Secret Lab Technologies Ltd. * (C) Copyright 2004 Atmark Techno, Inc. + * (C) Copyright 2002 Xilinx Inc. * * Yasushi SHOJI <yashi(a)atmark-techno.com> * @@ -24,22 +26,38 @@ #include <config.h> -#ifdef CONFIG_MICROBLAZE +#ifdef CONFIG_XILINX_UARTLITE -#include <asm/serial_xuartlite.h> +#include <asm/io.h> -/* FIXME: we should convert these to in32 and out32 */ -#define IO_WORD(offset) (*(volatile unsigned long *)(offset)) -#define IO_SERIAL(offset) IO_WORD(CONFIG_SERIAL_BASE + (offset)) +/* UART Lite register offsets */ +#define XUL_REG_RX 0 /* receive FIFO, read only */ +#define XUL_REG_TX 4 /* transmit FIFO, write only */ +#define XUL_REG_STATUS 8 /* status register, read only */ +#define XUL_REG_CONTROL 12 /* control register, write only */ + +/* control register bit positions */ +#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */ +#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */ +#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */ -#define IO_SERIAL_RX_FIFO IO_SERIAL(XUL_RX_FIFO_OFFSET) -#define IO_SERIAL_TX_FIFO IO_SERIAL(XUL_TX_FIFO_OFFSET) -#define IO_SERIAL_STATUS IO_SERIAL(XUL_STATUS_REG_OFFSET) -#define IO_SERIAL_CONTROL IO_SERIAL(XUL_CONTROL_REG_OFFSET) +/* status register bit positions */ +#define XUL_SR_PARITY_ERROR 0x80 +#define XUL_SR_FRAMING_ERROR 0x40 +#define XUL_SR_OVERRUN_ERROR 0x20 +#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */ +#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */ +#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */ +#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ + +/* FIXME: we should convert these to in32 and out32 */ +#define xul_write(reg, val) out_be32((void*)CONFIG_XILINX_UARTLITE_BASE + reg, val) +#define xul_read(reg) in_be32((void*)CONFIG_XILINX_UARTLITE_BASE + reg) int serial_init(void) { - /* FIXME: Nothing for now. We should initialize fifo, etc */ + xul_write(XUL_REG_CONTROL, XUL_CR_FIFO_RX_RESET | XUL_CR_FIFO_TX_RESET); return 0; } @@ -50,27 +68,32 @@ void serial_setbrg(void) void serial_putc(const char c) { - if (c == '\n') serial_putc('\r'); - while (IO_SERIAL_STATUS & XUL_SR_TX_FIFO_FULL); - IO_SERIAL_TX_FIFO = (unsigned char) (c & 0xff); + if (c == '\n') + serial_putc('\r'); + + /* spin for room in FIFO */ + while (xul_read(XUL_REG_STATUS) & XUL_SR_TX_FIFO_FULL); + + xul_write(XUL_REG_TX, c & 0xff); } void serial_puts(const char * s) { - while (*s) { + while (*s) serial_putc(*s++); - } } int serial_getc(void) { - while (!(IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA)); - return IO_SERIAL_RX_FIFO & 0xff; + /* spin for data */ + while (!(xul_read(XUL_REG_STATUS) & XUL_SR_RX_FIFO_VALID_DATA)); + + return xul_read(XUL_REG_RX) & 0xff; } int serial_tstc(void) { - return (IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA); + return xul_read(XUL_REG_STATUS) & XUL_SR_RX_FIFO_VALID_DATA; } -#endif /* CONFIG_MICROBLZE */ +#endif /* CONFIG_XILINX_UARTLITE */ diff --git a/include/asm-microblaze/arch-microblaze/xuartlite_l.h b/include/asm-microblaze/arch-microblaze/xuartlite_l.h deleted file mode 100644 index b381a0d..0000000 --- a/include/asm-microblaze/arch-microblaze/xuartlite_l.h +++ /dev/null @@ -1,256 +0,0 @@ -/***************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xuartlite_l.h -* -* This header file contains identifiers and low-level driver functions (or -* macros) that can be used to access the device. High-level driver functions -* are defined in xuartlite.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b rpm 04/25/02 First release -* </pre> -* -*****************************************************************************/ - -#ifndef XUARTLITE_L_H /* prevent circular inclusions */ -#define XUARTLITE_L_H /* by using protection macros */ - -/***************************** Include Files ********************************/ - -#include "xbasic_types.h" -#include "xio.h" - -/************************** Constant Definitions ****************************/ - -/* UART Lite register offsets */ - -#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ -#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */ -#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */ -#define XUL_CONTROL_REG_OFFSET 12 /* control register, write only */ - -/* control register bit positions */ - -#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */ -#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */ -#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */ - -/* status register bit positions */ - -#define XUL_SR_PARITY_ERROR 0x80 -#define XUL_SR_FRAMING_ERROR 0x40 -#define XUL_SR_OVERRUN_ERROR 0x20 -#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */ -#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */ -#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */ -#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ -#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ - -/* the following constant specifies the size of the FIFOs, the size of the - * FIFOs includes the transmitter and receiver such that it is the total number - * of bytes that the UART can buffer - */ -#define XUL_FIFO_SIZE 16 - -/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a - * per instance basis - */ -#define XUL_STOP_BITS 1 - -/* Parity definitions - */ -#define XUL_PARITY_NONE 0 -#define XUL_PARITY_ODD 1 -#define XUL_PARITY_EVEN 2 - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/***************************************************************************** -* -* Low-level driver macros and functions. The list below provides signatures -* to help the user use the macros. -* -* void XUartLite_mSetControlReg(u32 BaseAddress, u32 Mask) -* u32 XUartLite_mGetControlReg(u32 BaseAddress) -* u32 XUartLite_mGetStatusReg(u32 BaseAddress) -* -* Xboolean XUartLite_mIsReceiveEmpty(u32 BaseAddress) -* Xboolean XUartLite_mIsTransmitFull(u32 BaseAddress) -* Xboolean XUartLite_mIsIntrEnabled(u32 BaseAddress) -* -* void XUartLite_mEnableIntr(u32 BaseAddress) -* void XUartLite_mDisableIntr(u32 BaseAddress) -* -* void XUartLite_SendByte(u32 BaseAddress, u8 Data); -* u8 XUartLite_RecvByte(u32 BaseAddress); -* -*****************************************************************************/ - -/****************************************************************************/ -/** -* -* Set the contents of the control register. Use the XUL_CR_* constants defined -* above to create the bit-mask to be written to the register. -* -* @param BaseAddress is the base address of the device -* @param Mask is the 32-bit value to write to the control register -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XUartLite_mSetControlReg(BaseAddress, Mask) \ - XIo_Out32((BaseAddress) + XUL_CONTROL_REG_OFFSET, (Mask)) - - -/****************************************************************************/ -/** -* -* Get the contents of the control register. Use the XUL_CR_* constants defined -* above to interpret the bit-mask returned. -* -* @param BaseAddress is the base address of the device -* -* @return A 32-bit value representing the contents of the control register. -* -* @note None. -* -*****************************************************************************/ -#define XUartLite_mGetControlReg(BaseAddress) \ - XIo_In32((BaseAddress) + XUL_CONTROL_REG_OFFSET) - - -/****************************************************************************/ -/** -* -* Get the contents of the status register. Use the XUL_SR_* constants defined -* above to interpret the bit-mask returned. -* -* @param BaseAddress is the base address of the device -* -* @return A 32-bit value representing the contents of the status register. -* -* @note None. -* -*****************************************************************************/ -#define XUartLite_mGetStatusReg(BaseAddress) \ - XIo_In32((BaseAddress) + XUL_STATUS_REG_OFFSET) - - -/****************************************************************************/ -/** -* -* Check to see if the receiver has data. -* -* @param BaseAddress is the base address of the device -* -* @return XTRUE if the receiver is empty, XFALSE if there is data present. -* -* @note None. -* -*****************************************************************************/ -#define XUartLite_mIsReceiveEmpty(BaseAddress) \ - (!(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA)) - - -/****************************************************************************/ -/** -* -* Check to see if the transmitter is full. -* -* @param BaseAddress is the base address of the device -* -* @return XTRUE if the transmitter is full, XFALSE otherwise. -* -* @note None. -* -*****************************************************************************/ -#define XUartLite_mIsTransmitFull(BaseAddress) \ - (XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) - - -/****************************************************************************/ -/** -* -* Check to see if the interrupt is enabled. -* -* @param BaseAddress is the base address of the device -* -* @return XTRUE if the interrupt is enabled, XFALSE otherwise. -* -* @note None. -* -*****************************************************************************/ -#define XUartLite_mIsIntrEnabled(BaseAddress) \ - (XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) - - -/****************************************************************************/ -/** -* -* Enable the device interrupt. Preserve the contents of the control register. -* -* @param BaseAddress is the base address of the device -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XUartLite_mEnableIntr(BaseAddress) \ - XUartLite_mSetControlReg((BaseAddress), \ - XUartLite_mGetControlReg((BaseAddress)) | XUL_CR_ENABLE_INTR) - - -/****************************************************************************/ -/** -* -* Disable the device interrupt. Preserve the contents of the control register. -* -* @param BaseAddress is the base address of the device -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XUartLite_mDisableIntr(BaseAddress) \ - XUartLite_mSetControlReg((BaseAddress), \ - XUartLite_mGetControlReg((BaseAddress)) & ~XUL_CR_ENABLE_INTR) - - -/************************** Function Prototypes *****************************/ - -void XUartLite_SendByte(u32 BaseAddress, u8 Data); -u8 XUartLite_RecvByte(u32 BaseAddress); - - -#endif /* end of protection macro */ diff --git a/include/asm-microblaze/serial_xuartlite.h b/include/asm-microblaze/serial_xuartlite.h deleted file mode 100644 index 6cd1e83..0000000 --- a/include/asm-microblaze/serial_xuartlite.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI <yashi(a)atmark-techno.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/arch/xuartlite_l.h> diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h index 8224555..b67a2c1 100644 --- a/include/configs/suzaku.h +++ b/include/configs/suzaku.h @@ -60,8 +60,10 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> -#define CFG_UART1_BASE (0xFFFF2000) -#define CONFIG_SERIAL_BASE CFG_UART1_BASE +/* Use Xilinx UARTLITE serial port */ +#define CFG_UART1_BASE (0xFFFF2000) +#define CONFIG_XILINX_UARTLITE 1 +#define CONFIG_XILINX_UARTLITE_BASE CFG_UART1_BASE /* * Miscellaneous configurable options -- 1.5.1

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Re: [U-Boot-Users] Testing todays u-boot-fdt
by Wolfgang Denk 21 Apr '07

21 Apr '07

In message <4629358C.5050401(a)cideas.com> you wrote: > > ...and there's the irony. With it as a library included by BOARDLIBS in > the board config file, it is only compiled if it is called for in the > board's config.mk. Yes, I am aware of this. > It seems like it would be overall a win to have more of a real library > approach. I have not gone down that path hardly at all, however, and it > is likely to have briers that I'm not aware of. It also would take > time. :-/ But "more of a real library approach" still means that you *always* build the library, but some mechanism selects which files get compiled and archived in the libs. > Having said that, I don't have any real issue in applying wg's patch. > It isn't a big deal and will match the rest of u-boot methodology. At > the end of the day, it is a lot easier than converting everything to > true libraries. ;-] Right :-( Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk Office: Kirchenstr. 5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de In C we had to code our own bugs, in C++ we can inherit them.

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