February 2007 - U-Boot

[U-Boot-Users] [Ticket#2007011742000232] [PATCH] Avoid assigning PCI resources from zero ad [...]
by OTRS Notification Master 23 Apr '07

23 Apr '07

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2007011742000232] was created: <snip> > If a PCI IDE card happens to get a zero address assigned to it, the > Linux IDE > core complains and IDE drivers fails to work. Also, assigning zero to a > BAR > was illegal according to PCI 2.1 (the later revisions seem to have > excluded the > sentence about "0" being considered an invalid address) -- so, use a > reasonable > starting value of 0x1000 (that's what the most Linux archs are using). > > Alternatively, one might have fixed the calls to pci_set_region() > individually > (some code even seems to have taken care of this issue) but that would > have > been a lot more work. :-) > > Signed-off-by: Sergei Shtylyov <sshtylyov(a)ru.mvista.com> > > drivers/pci_auto.c | 7 ++++++- > 1 files changed, 6 insertions(+), 1 deletion(-) > > Index: u-boot/drivers/pci_auto.c > =================================================================== > --- u-boot.orig/drivers/pci_auto.c > +++ u-boot/drivers/pci_auto.c > @@ -34,7 +34,12 @@ > > void pciauto_region_init(struct pci_region* res) > { > - res->bus_lower = res->bus_start; > + /* > + * Avoid allocating PCI resources from address 0 -- this is illegal > + * according to PCI 2.1 and moreover, this is known to cause Linux IDE > + * drivers to fail. Use a reasonable starting value of 0x1000 instead. > + */ > + res->bus_lower = res->bus_start ? res->bus_start : 0x1000; > } > > void pciauto_region_align(struct pci_region *res, unsigned long size) </snip> Your U-Boot support team

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[U-Boot-Users] [PATCH 00/07 v2]: Add mpc7448hpc2 (Taiga) board support
by Zang Roy-r61911 19 Apr '07

19 Apr '07

This series of patches add mpc7448hpc2 board support. Mpc7448hpc2 (taiga) board is a high-performance PowerPC server reference design. This is the second version for this board support according to the feedback from mailing list. Roy Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- doc/README.mpc7448hpc2 | 181 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 181 insertions(+), 0 deletions(-) diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2 new file mode 100644 index 0000000..00fda4e --- /dev/null +++ b/doc/README.mpc7448hpc2 @@ -0,0 +1,181 @@ +Freescale MPC7448hpc2 (Taiga) board +-------------------------- +MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference +design, which is optimized for high speed throughput between the processor and +the memory, disk drive and Ethernet port subsystems. + +MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be +used in 1U or 2U rack-mount chassis', as well as in standard ATX/Micro-ATX +chassis. + + +Memory Map +---------- + +The memory map is setup for Linux to operate properly. + +The mapping is: + + Range Start Range End Definition Size + + 0x0000_0000 0x7fff_ffff DDR 2G + 0xe000_0000 0xe7ff_ffff PCI Memory 128M + 0xfa00_0000 0xfaff_ffff PCI IO 16M + 0xfb00_0000 0xfbff_ffff PCI Config 16M + 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M + 0xfe00_0000 0xfeff_ffff PromJet 16M + 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M + 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M + + +Using Flash +----------- + +The MPC7448hpc2 board has two "banks" of flash, each 8MB in size +(2^23 = 0x00800000). + +Note: the "bank" here refers to half of the flash. In fact, there is only one +bank of flash, which is divided into low and high half. Each is controlled by +the most significant bit of the address bus. The so called "bank" is only for +convenience. + +There is a switch which allows the "bank" to be selected. The switch +settings for updating flash are given below. + +The u-boot commands for copying the boot-bank into the secondary bank are +as follows: + + erase ff800000 ff880000 + cp.b ff000000 ff800000 80000 + +U-boot commands for downloading an image via tftp and flashing +it into the secondary bank: + + tftp 10000 <u-boot.bin.image> + erase ff000000 ff080000 + cp.b 10000 ff000000 80000 + + +After copying the image into the second bank of flash, be sure to toggle +SW3[4] on board before resetting the board in order to set the +secondary bank as the boot-bank. + + +Board Switches +---------------------- + + +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks and determining the PCI frequency. + +SW1[1-5]: Processor core voltage + + 12345 Core Voltage + ----- + SW1=01111 1.000V. + SW1=01101 1.100V. + SW1=01011 1.200V. + SW1=01001 1.300V only for MPC7447A. + + +SW2[1-6]: CPU core frequency + + CPU Core Frequency (MHz) + Bus Frequency + 123456 100 133 167 200 Ratio + + ------ + SW2=101100 500 667 833 1000 5x + SW2=100100 550 733 917 1100 5.5x + SW2=110100 600 800 1000 1200 6x + SW2=010100 650 866 1083 1300 6.5x + SW2=001000 700 930 1167 1400 7x + SW2=000100 750 1000 1250 1500 7.5x + SW2=110000 800 1066 1333 1600 8x + SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A + SW2=011110 900 1200 1500 1800 9x + +This table shows only a subset of available frequency options; see the CPU +hardware specifications for more information. + + +SW2[7-8]: Bus Protocol and CPU Reset Option + + 7 + - + SW2=0 System bus uses MPX bus protocol + SW2=1 System bus uses 60x bus protocol + + 8 + - + SW2=0 TSI108 can cause CPU reset + SW2=1 TSI108 can not cause CPU reset + + +SW3[1-8] system options + + 123 + --- + SW3=xxx Connected to GPIO[0:2] on TSI108 + + 4 + - + SW3=0 CPU boots from low half of flash + SW3=1 CPU boots from high half of flash + + 5 + - + SW3=0 SATA and slot2 connected to PCI bus + SW3=1 Only slot1 connected to PCI bus + + 6 + - + SW3=0 USB connected to PCI bus + SW3=1 USB disconnected from PCI bus + + 7 + - + SW3=0 Flash is write protected + SW3=1 Flash is NOT write protected + + 8 + - + SW3=0 CPU will boot from flash + SW3=1 CPU will boot from PromJet + +SW4[1-3]: System bus frequency + + Bus Frequency (MHz) + --- + SW4=010 183 + SW4=011 100 + SW4=100 133 + SW4=101 166 only for MPC7447A + SW4=110 200 only for MPC7448 + others reserved + + +SW4[4-6]: DDR2 SDRAM frequency + + Bus Frequency (MHz) + --- + SW4=000 external clock + SW4=011 system clock + SW4=100 133 + SW4=101 166 + SW4=110 200 + others reserved + + +SW4[7-8]: PCI/PCI-X frequency control + 7 + - + SW4=0 PCI/PCI-X bus operates normally + SW4=1 PCI bus forced to PCI-33 mode + + 8 + - + SW4=0 PCI-X mode at 133 MHz allowed + SW4=1 PCI-X mode limited to 100 MHz + -- 1.4.0

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[U-Boot-Users] [PATCH] Fix: Bug in MIPS linker scripts
by Robert Deliën 11 Apr '07

11 Apr '07

Hi, This patch fixes the possible alignment error between _gp and __got_start in the linker scripts of all MIPS targets. This problem has been previously reported under the title '_gp and __got_start alignment problem in u-boot.lds. Thanks for your comment Andrew! With kind regards, Robert.

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[U-Boot-Users] [PATCH] Add first Netstal board HCU4
by Niklaus Giger 10 Apr '07

10 Apr '07

Hi We at Netstal Maschinen (http://www.netstal.com/) will probably use the U-Boot in our next board, based on a PPC440EPx. The reason we choose u-boot over a proprietary boot eprom are still the same as described in my earlier e-mail from February 2005 http://sourceforge.net/mailarchive/message.php?msg_id=10996256 Outside my activities at Netstal I had ported U-boot in 2005 to run on our current board (based on a PPC405GPr). I used it to get acquainted with Linux and Xenomai and one board is currently used by Xenomais buildbot. I would like to get this board into the U-Boot repository to have a solid base for our new board and to be able to test various features before getting hand onto our new board (somewhere in March/April). As I am new to the U-Boot and Git, I am not sure, whether I got everything right in my first try to submit a patch. I did a) git clone rsync://source.denx.net/git/u-boot.git u-boot.git b) Added my files, testing them, etc c) edited .git/config with my personal info d) git-commit --all --signoff -m "Add first Netstal board HCU4" e) gz'ed the resulting 0001-Add-first-Netstal-board-HCU4.txt to reduce the size from 52KB to 15 KB. f) as between a) and c) passed various week I g) git pull As there were no conflicts, I rebuilded my target, tested again. Then I called h) ./MAKEALL Most target run okay, but I have errors like Configuring for p3mx board... p3mx.c:48:18: error: p3mx.h: No such file or directory p3mx.c:48:18: error: p3mx.h: No such file or directory which I believe are unrelated to my changes. I am unsatisfied that I had to add a flash.c to my board, but I have at the moment no idea how a clean solution should look like. But I think in the various flash.c there is a lot of duplicated code around. As our board has ECC memory, I would like to submit in a second step a patch to get ECC working on PPC405. Any suggestion on how to improve this patch are welcome. Best regards Niklaus Giger -- As my first try from my workplace was considered spam I try it with my home e-mail. Signed-off-by: Niklaus Giger <niklaus.giger(a)netstal.com>

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[U-Boot-Users] PPC 83xx + QE support
by David Saada 07 Apr '07

07 Apr '07

Hello, Are there plans for U-boot to support any PPC 83xx+QE (Quick Engine) based boards? Relevant boards can be Freescale's 8360 or 8323 based ones. Thanks. David.

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[U-Boot-Users] [PATCH] Fix initrd length miscalculation in bootm command
by Timur Tabi 27 Mar '07

27 Mar '07

The do_bootm_linux() function was using the same variable ('len') to calculate the the dtu length and the initrd length, which meant that the initrd length was incorrect. This patch creates renames 'len' and 'data' to 'initrd_len' and 'initrd_data', thereby preventing any future confusion. It also deletes 'len' and 'data' because the dtu calculations don't actually need them. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- common/cmd_bootm.c | 57 +++++++++++++++++++++++---------------------------- 1 files changed, 26 insertions(+), 31 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 7aae8a6..0c092c7 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -518,11 +518,10 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl int verify) { ulong sp; - ulong len, checksum; - ulong initrd_start, initrd_end; + ulong checksum; + ulong initrd_start, initrd_end, initrd_data, initrd_len; ulong cmd_start, cmd_end; ulong initrd_high; - ulong data; int initrd_copy_to_ram = 1; char *cmdline; char *s; @@ -626,7 +625,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl /* Look for a '-' which indicates to ignore the ramdisk argument */ if (argc >= 3 && strcmp(argv[2], "-") == 0) { debug ("Skipping initrd\n"); - len = data = 0; + initrd_len = initrd_data = 0; } else #endif @@ -647,13 +646,10 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl do_reset (cmdtp, flag, argc, argv); } - data = (ulong)&header; - len = sizeof(image_header_t); - checksum = ntohl(hdr->ih_hcrc); hdr->ih_hcrc = 0; - if (crc32 (0, (uchar *)data, len) != checksum) { + if (crc32 (0, (uchar *) &header, sizeof(image_header_t)) != checksum) { puts ("Bad Header Checksum\n"); SHOW_BOOT_PROGRESS (-11); do_reset (cmdtp, flag, argc, argv); @@ -663,13 +659,13 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl print_image_hdr (hdr); - data = addr + sizeof(image_header_t); - len = ntohl(hdr->ih_size); + initrd_data = addr + sizeof(image_header_t); + initrd_len = ntohl(hdr->ih_size); if (verify) { ulong csum = 0; #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - ulong cdata = data, edata = cdata + len; + ulong cdata = initrd_data, edata = cdata + initrd_len; #endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ puts (" Verifying Checksum ... "); @@ -687,7 +683,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl WATCHDOG_RESET(); } #else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ - csum = crc32 (0, (uchar *)data, len); + csum = crc32 (0, (uchar *) initrd_data, initrd_len); #endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ if (csum != ntohl(hdr->ih_dcrc)) { @@ -718,17 +714,17 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl SHOW_BOOT_PROGRESS (13); /* skip kernel length and terminator */ - data = (ulong)(&len_ptr[2]); + initrd_data = (ulong)(&len_ptr[2]); /* skip any additional image length fields */ for (i=1; len_ptr[i]; ++i) - data += 4; + initrd_data += 4; /* add kernel length, and align */ - data += ntohl(len_ptr[0]); + initrd_data += ntohl(len_ptr[0]); if (tail) { - data += 4 - tail; + initrd_data += 4 - tail; } - len = ntohl(len_ptr[1]); + initrd_len = ntohl(len_ptr[1]); } else { /* @@ -736,7 +732,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl */ SHOW_BOOT_PROGRESS (14); - len = data = 0; + initrd_len = initrd_data = 0; } #ifdef CONFIG_OF_FLAT_TREE @@ -771,9 +767,8 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl checksum = ntohl(hdr->ih_dcrc); addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t)); - len = ntohl(hdr->ih_size); - if(checksum != crc32(0, (uchar *)addr, len)) { + if(checksum != crc32(0, (uchar *)addr, ntohl(hdr->ih_size))) { printf("ERROR: Flat Device Tree checksum is invalid\n"); return; } @@ -835,16 +830,16 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl } } #endif - if (!data) { + if (!initrd_data) { debug ("No initrd\n"); } - if (data) { + if (initrd_data) { if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ - initrd_start = data; - initrd_end = initrd_start + len; + initrd_start = initrd_data; + initrd_end = initrd_start + initrd_len; } else { - initrd_start = (ulong)kbd - len; + initrd_start = (ulong)kbd - initrd_len; initrd_start &= ~(4096 - 1); /* align on page */ if (initrd_high) { @@ -865,7 +860,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl nsp &= ~0xF; if (nsp > initrd_high) /* limit as specified */ nsp = initrd_high; - nsp -= len; + nsp -= initrd_len; nsp &= ~(4096 - 1); /* align on page */ if (nsp >= sp) initrd_start = nsp; @@ -874,16 +869,16 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl SHOW_BOOT_PROGRESS (12); debug ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", - data, data + len - 1, len, len); + initrd_data, initrd_data + initrd_len - 1, initrd_len, initrd_len); - initrd_end = initrd_start + len; + initrd_end = initrd_start + initrd_len; printf (" Loading Ramdisk to %08lx, end %08lx ... ", initrd_start, initrd_end); #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) { - size_t l = len; + size_t l = initrd_len; void *to = (void *)initrd_start; - void *from = (void *)data; + void *from = (void *)initrd_data; while (l > 0) { size_t tail = (l > CHUNKSZ) ? CHUNKSZ : l; @@ -895,7 +890,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl } } #else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ - memmove ((void *)initrd_start, (void *)data, len); + memmove ((void *)initrd_start, (void *)initrd_data, initrd_len); #endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ puts ("OK\n"); } -- 1.4.4

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[U-Boot-Users] CFI flash driver problem
by Jeff Mann 15 Mar '07

15 Mar '07

U-Boot users: I am having a problem using the CFI flash drivers on a new board and would appreciate any suggestions to find my mistakes. (Wolfgang: this is the AMCC Acadia board that is on its way to you). The processor is a PPC405ez. When writing or erasing the flash, the processor has an Program Check Exception. Below you can see the exeption handling data I receive when trying to erase a sector on flash: NIP: 00000700 XER: 00000000 LR: 03FDC27C REGS: 03f6a9a0 TRAP: 0700 DAR: 03FD0014 MSR: 00000000 EE: 0 PR: 0 FP: 0 ME: 0 IR/DR: 00 GPR00: 00000000 03F6AA90 FFFFFFFF 03FFD1A8 00000030 03F6AAA0 00000030 BE59D81C GPR08: 00000000 FF000000 03F6AAA5 00000005 574FBDE6 FFFFFFFF 03FF9800 0400D000 GPR16: FFFFFFFF FFFFFFFF DFFFFFFD 03F6ABAA 00000001 00000000 00000000 00000000 GPR24: 00000000 0000007F 03FFD9F4 03FFD1A8 03FFD1A8 03F6AF4C 03FF9E9C 00000040 ** Illegal Instruction ** Call backtrace: Program Check Exception I have debugged the error, and when stepping through code in "human time," I do not get this exeption. So, I put in in some basic debugging printouts and I can see that the problem occuring some place in the flash_write_cmd() function when calling it with "flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);" at around line 490 in flash_erase(). I've added wait states to the flash chip select with no change. Because the flash shares the EBC bus with memory through a bus transiever, I thought that possibly there were problems with the transiever's timing. But after adding the maximum number of wait states, I do not think this is the case. Thanks for you help, JM

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[U-Boot-Users] [DNX#2007012542000021] [PATCH] Abort booting if the DTB version is incomp [...]
by OTRS Notification Master 15 Mar '07

15 Mar '07

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2007012542000021] was created: <snip> > U-Boot only supports version 16 of the device tree file format, although > some > versions of the device tree compiler generate version 3 by default. > With > this patch, U-Boot now checks the version number and aborts the boot > process > if the version of the device tree passed on the bootm command line is > not > compatible. > > Signed-off-by: Timur Tabi <timur(a)freescale.com> > --- > common/cmd_bootm.c | 10 ++++++++++ > 1 files changed, 10 insertions(+), 0 deletions(-) > > diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c > index 0c092c7..9111cbd 100644 > --- a/common/cmd_bootm.c > +++ b/common/cmd_bootm.c > @@ -741,6 +741,16 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl > hdr = (image_header_t *)of_flat_tree; > > if (*(ulong *)of_flat_tree == OF_DT_HEADER) { > + struct boot_param_header *bph = > + (struct boot_param_header *) of_flat_tree; > + > + if ((OF_DT_VERSION < be32_to_cpu(bph->last_comp_version)) || > + (OF_DT_VERSION > be32_to_cpu(bph->version))) { > + printf("ERROR: DTB version %u is not compatible with version %u " \ > + "(last_comp_version=%u)\n", be32_to_cpu(bph->version), > + OF_DT_VERSION, be32_to_cpu(bph->last_comp_version)); > + return; > + } > #ifndef CFG_NO_FLASH > if (addr2info((ulong)of_flat_tree) != NULL) > of_data = (ulong)of_flat_tree; > -- > 1.4.4 </snip> Your U-Boot support team

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[U-Boot-Users] problems using TSEC Ethernet without CONFIG_NET_MULTI
by Michael 09 Mar '07

09 Mar '07

Hi all. I have a question on using TSEC Ethernet on a board with a MPC8541. I don't use CPM2 and FCC. I use only one TSEC for management. Since I only enable one TSEC, I #undef-ed the CONFIG_NET_MULTI flag. But then I couldn't use all the functions under eth.c, since its all under #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI). What is the justification for CONFIG_NET_MULTI there? Should I just remove it, or I am supposed to have some other replacement for the Ethernet access that I miss? Thanks a lot.

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[U-Boot-Users] [PATCH 3/3]Add DDR2 controller fixed/SPD Init for MPC83xx
by Xie Xiaobo 09 Mar '07

09 Mar '07

The code supply fixed and SPD initialization for MPC83xx DDR2 Controller. it pass DDR/DDR2 compliance tests. Signed-off-by: Xie Xiaobo<X.Xie(a)freescale.com> --- This patch applies to the mpc83xx branch of the opensource.freescale.com u-boot-83xx.git tree board/mpc8349emds/mpc8349emds.c | 17 ++- board/mpc8360emds/mpc8360emds.c | 15 ++ cpu/mpc83xx/spd_sdram.c | 384 ++++++++++++++++++++++++++++++++------ 3 files changed, 354 insertions(+), 62 deletions(-) diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 873bdd0..071591e 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -119,6 +119,20 @@ int fixed_sdram(void) #if (CFG_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif +#ifdef CONFIG_DDR_II + im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; + im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; +#else im->ddr.csbnds[2].csbnds = 0x0000000f; im->ddr.cs_config[2] = CFG_DDR_CONFIG; @@ -143,6 +157,7 @@ int fixed_sdram(void) im->ddr.sdram_mode = CFG_DDR_MODE; im->ddr.sdram_interval = CFG_DDR_INTERVAL; +#endif udelay(200); /* enable DDR controller */ @@ -239,7 +254,7 @@ void sdram_init(void) #else void sdram_init(void) { - put("SDRAM on Local Bus is NOT available!\n"); + puts(" SDRAM on Local Bus is NOT available!\n"); } #endif diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index ddc1047..54b9acc 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -158,6 +158,20 @@ int fixed_sdram(void) #if (CFG_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif +#ifdef CONFIG_DDR_II + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; +#else im->ddr.csbnds[0].csbnds = 0x00000007; im->ddr.csbnds[1].csbnds = 0x0008000f; @@ -170,6 +184,7 @@ int fixed_sdram(void) im->ddr.sdram_mode = CFG_DDR_MODE; im->ddr.sdram_interval = CFG_DDR_INTERVAL; +#endif udelay(200); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 108328a..d9b8753 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -106,16 +106,29 @@ long int spd_sdram() volatile ddr83xx_t *ddr = &immap->ddr; volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; spd_eeprom_t spd; + unsigned int n_ranks; + unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned char twr_clk, twtr_clk; + unsigned char sdram_type; unsigned int memsize; unsigned int law_size; unsigned char caslat, caslat_ctrl; + unsigned int trfc, trfc_clk, trfc_low, trfc_high; + unsigned int trcd_clk, trtp_clk; + unsigned char cke_min_clk; + unsigned char add_lat, wr_lat; + unsigned char wr_data_delay; + unsigned char four_act; + unsigned char cpo; unsigned char burstlen; + unsigned char odt_cfg, mode_odt_enable; unsigned int max_bus_clk; unsigned int max_data_rate, effective_data_rate; unsigned int ddrc_clk; unsigned int refresh_clk; - unsigned sdram_cfg; + unsigned int sdram_cfg; unsigned int ddrc_ecc_enable; + unsigned int pvr = get_pvr(); /* Read SPD parameters with I2C */ CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); @@ -123,19 +136,25 @@ long int spd_sdram() spd_debug(&spd); #endif /* Check the memory type */ - if (spd.mem_type != SPD_MEMTYPE_DDR) { + if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) { printf("DDR: Module mem type is %02X\n", spd.mem_type); return 0; } /* Check the number of physical bank */ - if (spd.nrows > 2) { - printf("DDR: The number of physical bank is %02X\n", spd.nrows); + if (spd.mem_type == SPD_MEMTYPE_DDR) { + n_ranks = spd.nrows; + } else { + n_ranks = (spd.nrows & 0x7) + 1; + } + + if (n_ranks > 2) { + printf("DDR: The number of physical bank is %02X\n", n_ranks); return 0; } /* Check if the number of row of the module is in the range of DDRC */ - if (spd.nrow_addr < 12 || spd.nrow_addr > 14) { + if (spd.nrow_addr < 12 || spd.nrow_addr > 15) { printf("DDR: Row number is out of range of DDRC, row=%02X\n", spd.nrow_addr); return 0; @@ -147,20 +166,43 @@ long int spd_sdram() spd.ncol_addr); return 0; } + +#ifdef CFG_DDRCDR_VALUE + /* + * Adjust DDR II IO voltage biasing. It just makes it work. + */ + if(spd.mem_type == SPD_MEMTYPE_DDR2) { + immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + } +#endif + + /* + * ODT configuration recommendation from DDR Controller Chapter. + */ + odt_rd_cfg = 0; /* Never assert ODT */ + odt_wr_cfg = 0; /* Never assert ODT */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + odt_wr_cfg = 1; /* Assert ODT on writes to CSn */ + } + /* Setup DDR chip select register */ #ifdef CFG_83XX_DDR_USES_CS0 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; ddr->cs_config[0] = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("\n"); debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); - if (spd.nrows == 2) { + if (n_ranks == 2) { ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8) | ((banksize(spd.row_dens) >> 23) - 1) ); ddr->cs_config[1] = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) | (spd.nrow_addr-12) << 8 | (spd.ncol_addr-8) ); debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); @@ -170,16 +212,20 @@ long int spd_sdram() #else ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; ddr->cs_config[2] = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("\n"); debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); - if (spd.nrows == 2) { + if (n_ranks == 2) { ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) | ((banksize(spd.row_dens) >> 23) - 1) ); ddr->cs_config[3] = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) | (spd.nrow_addr-12) << 8 | (spd.ncol_addr-8) ); debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); @@ -187,15 +233,10 @@ long int spd_sdram() } #endif - if (spd.mem_type != 0x07) { - puts("No DDR module found!\n"); - return 0; - } - /* * Figure out memory size in Megabytes. */ - memsize = spd.nrows * banksize(spd.row_dens) / 0x100000; + memsize = n_ranks * banksize(spd.row_dens) / 0x100000; /* * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. @@ -215,24 +256,32 @@ long int spd_sdram() * in the spd.cas_lat field. Translate it to a DDR * controller field value: * - * CAS Lat DDR I Ctrl - * Clocks SPD Bit Value - * -------+--------+--------- - * 1.0 0 001 - * 1.5 1 010 - * 2.0 2 011 - * 2.5 3 100 - * 3.0 4 101 - * 3.5 5 110 - * 4.0 6 111 + * CAS Lat DDR I DDR II Ctrl + * Clocks SPD Bit SPD Bit Value + * ------- ------- ------- ----- + * 1.0 0 0001 + * 1.5 1 0010 + * 2.0 2 2 0011 + * 2.5 3 0100 + * 3.0 4 3 0101 + * 3.5 5 0110 + * 4.0 6 4 0111 + * 4.5 1000 + * 5.0 5 1001 */ caslat = __ilog2(spd.cas_lat); - - if (caslat > 6 ) { - printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n", - spd.cas_lat); + if ((spd.mem_type == SPD_MEMTYPE_DDR) + && (caslat > 6)) { + printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); + return 0; + } else if (spd.mem_type == SPD_MEMTYPE_DDR2 + && (caslat < 2 || caslat > 5)) { + printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", + spd.cas_lat); return 0; } + debug("DDR: caslat SPD bit is %d\n", caslat); + max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f)); max_data_rate = max_bus_clk * 2; @@ -240,10 +289,11 @@ long int spd_sdram() debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate); ddrc_clk = gd->ddr_clk / 1000000; + effective_data_rate = 0; - if (max_data_rate >= 390) { /* it is DDR 400 */ - if (ddrc_clk <= 410 && ddrc_clk > 350) { - /* DDR controller clk at 350~410 */ + if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ + if (ddrc_clk <= 460 && ddrc_clk > 350) { + /* DDR controller clk at 350~460 */ effective_data_rate = 400; /* 5ns */ caslat = caslat; } else if (ddrc_clk <= 350 && ddrc_clk > 280) { @@ -258,16 +308,16 @@ long int spd_sdram() effective_data_rate = 266; /* 7.5ns */ if (spd.clk_cycle3 == 0x75) caslat = caslat - 2; - else if (spd.clk_cycle2 == 0x60) + else if (spd.clk_cycle2 == 0x75) caslat = caslat - 1; else caslat = caslat; } else if (ddrc_clk <= 230 && ddrc_clk > 90) { /* DDR controller clk at 90~230 */ effective_data_rate = 200; /* 10ns */ - if (spd.clk_cycle3 == 0x75) + if (spd.clk_cycle3 == 0xa0) caslat = caslat - 2; - else if (spd.clk_cycle2 == 0x60) + else if (spd.clk_cycle2 == 0xa0) caslat = caslat - 1; else caslat = caslat; @@ -289,7 +339,7 @@ long int spd_sdram() effective_data_rate = 200; /* 10ns */ if (spd.clk_cycle3 == 0xa0) caslat = caslat - 2; - else if (spd.clk_cycle2 == 0x75) + else if (spd.clk_cycle2 == 0xa0) caslat = caslat - 1; else caslat = caslat; @@ -330,41 +380,197 @@ long int spd_sdram() * Errata DDR6 work around: input enable 2 cycles earlier. * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2. */ - if (caslat == 2) - ddr->debug_reg = 0x201c0000; /* CL=2 */ - else if (caslat == 3) - ddr->debug_reg = 0x202c0000; /* CL=2.5 */ - else if (caslat == 4) - ddr->debug_reg = 0x202c0000; /* CL=3.0 */ + if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){ + if (caslat == 2) + ddr->debug_reg = 0x201c0000; /* CL=2 */ + else if (caslat == 3) + ddr->debug_reg = 0x202c0000; /* CL=2.5 */ + else if (caslat == 4) + ddr->debug_reg = 0x202c0000; /* CL=3.0 */ - __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("sync"); - debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); + debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); + } /* - * note: caslat must also be programmed into ddr->sdram_mode - * register. - * - * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD, - * use conservative value here. + * Convert caslat clocks to DDR controller value. + * Force caslat_ctrl to be DDR Controller field-sized. */ - caslat_ctrl = (caslat + 1) & 0x07; /* see as above */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + caslat_ctrl = (caslat + 1) & 0x07; + } else { + caslat_ctrl = (2 * caslat - 1) & 0x0f; + } + + debug("DDR: effective data rate is %d MHz\n", effective_data_rate); + debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", + caslat, caslat_ctrl); + + /* + * Timing Config 0. + * Avoid writing for DDR I. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + unsigned char taxpd_clk = 8; /* By the book. */ + unsigned char tmrd_clk = 2; /* By the book. */ + unsigned char act_pd_exit = 2; /* Empirical? */ + unsigned char pre_pd_exit = 6; /* Empirical? */ + + ddr->timing_cfg_0 = (0 + | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ + | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ + | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ + | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ + ); + debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); + } + + /* + * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, + * use conservative value. + * For DDR II, they are bytes 36 and 37, in quarter nanos. + */ + + if (spd.mem_type == SPD_MEMTYPE_DDR) { + twr_clk = 3; /* Clocks */ + twtr_clk = 1; /* Clocks */ + } else { + twr_clk = picos_to_clk(spd.twr * 250); + twtr_clk = picos_to_clk(spd.twtr * 250); + } + + /* + * Calculate Trfc, in picos. + * DDR I: Byte 42 straight up in ns. + * DDR II: Byte 40 and 42 swizzled some, in ns. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + trfc = spd.trfc * 1000; /* up to ps */ + } else { + unsigned int byte40_table_ps[8] = { + 0, + 250, + 330, + 500, + 660, + 750, + 0, + 0 + }; + + trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000 + + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7]; + } + trfc_clk = picos_to_clk(trfc); + + /* + * Trcd, Byte 29, from quarter nanos to ps and clocks. + */ + trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7; + + /* + * Convert trfc_clk to DDR controller fields. DDR I should + * fit in the REFREC field (16-19) of TIMING_CFG_1, but the + * 83xx controller has an extended REFREC field of three bits. + * The controller automatically adds 8 clocks to this value, + * so preadjust it down 8 first before splitting it up. + */ + trfc_low = (trfc_clk - 8) & 0xf; + trfc_high = ((trfc_clk - 8) >> 4) & 0x3; ddr->timing_cfg_1 = - (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | - ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | - ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) | - ((caslat_ctrl & 0x07) << 16 ) | - (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) | - ( 0x300 ) | - ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1); + (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */ + ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */ + (trcd_clk << 20 ) | /* ACTTORW */ + (caslat_ctrl << 16 ) | /* CASLAT */ + (trfc_low << 12 ) | /* REFEC */ + ((twr_clk & 0x07) << 8) | /* WRRREC */ + ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */ + ((twtr_clk & 0x07) << 0) /* WRTORD */ + ); + + /* + * Additive Latency + * For DDR I, 0. + * For DDR II, with ODT enabled, use "a value" less than ACTTORW, + * which comes from Trcd, and also note that: + * add_lat + caslat must be >= 4 + */ + add_lat = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2 + && (odt_wr_cfg || odt_rd_cfg) + && (caslat < 4)) { + add_lat = trcd_clk - 1; + if ((add_lat + caslat) < 4) { + add_lat = 0; + } + } + + /* + * Write Data Delay + * Historically 0x2 == 4/8 clock delay. + * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. + */ + wr_data_delay = 2; + + /* + * Write Latency + * Read to Precharge + * Minimum CKE Pulse Width. + * Four Activate Window + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + /* + * This is a lie. It should really be 1, but if it is + * set to 1, bits overlap into the old controller's + * otherwise unused ACSM field. If we leave it 0, then + * the HW will magically treat it as 1 for DDR 1. Oh Yea. + */ + wr_lat = 0; + + trtp_clk = 2; /* By the book. */ + cke_min_clk = 1; /* By the book. */ + four_act = 1; /* By the book. */ + + } else { + wr_lat = caslat - 1; + + /* Convert SPD value from quarter nanos to picos. */ + trtp_clk = picos_to_clk(spd.trtp * 250); - ddr->timing_cfg_2 = 0x00000800; + cke_min_clk = 3; /* By the book. */ + four_act = picos_to_clk(37500); /* By the book. 1k pages? */ + } + + /* + * Empirically set ~MCAS-to-preamble override for DDR 2. + * Your milage will vary. + */ + cpo = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (effective_data_rate == 266 || effective_data_rate == 333) { + cpo = 0x7; /* READ_LAT + 5/4 */ + } else if (effective_data_rate == 400) { + cpo = 0x9; /* READ_LAT + 7/4 */ + } else { + /* Automatic calibration */ + cpo = 0x1f; + } + } + + ddr->timing_cfg_2 = (0 + | ((add_lat & 0x7) << 28) /* ADD_LAT */ + | ((cpo & 0x1f) << 23) /* CPO */ + | ((wr_lat & 0x7) << 19) /* WR_LAT */ + | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ + | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ + | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */ + | ((four_act & 0x1f) << 0) /* FOUR_ACT */ + ); debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); - /* Setup init value, but not enable */ - ddr->sdram_cfg = 0x42000000; /* Check DIMM data bus width */ if (spd.dataw_lsb == 0x20) { @@ -384,7 +590,8 @@ long int spd_sdram() /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus, Burst type is sequential */ - switch (caslat) { + if (spd.mem_type == SPD_MEMTYPE_DDR) { + switch (caslat) { case 1: ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */ break; @@ -400,9 +607,36 @@ long int spd_sdram() default: printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n"); return 0; + } + } else { + mode_odt_enable = 0x0; /* Default disabled */ + if (odt_wr_cfg || odt_rd_cfg) { + /* + * Bits 6 and 2 in Extended MRS(1) + * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. + * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. + */ + mode_odt_enable = 0x40; /* 150 Ohm */ + } + + ddr->sdram_mode = + (0 + | (1 << (16 + 10)) /* DQS Differential disable */ + | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ + | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ + | ((twr_clk >> 1) << 9) /* Write Recovery Autopre */ + | (caslat << 4) /* caslat */ + | (burstlen << 0) /* Burst length */ + ); } debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); + /* + * Clear EMRS2 and EMRS3. + */ + ddr->sdram_mode2 = 0; + debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2); + switch (spd.refresh) { case 0x00: case 0x80: @@ -440,6 +674,23 @@ long int spd_sdram() ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100; debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); + /* + * SDRAM Cfg 2 + */ + odt_cfg = 0; + if (odt_rd_cfg | odt_wr_cfg) { + odt_cfg = 0x2; /* ODT to IOs during reads */ + } + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + ddr->sdram_cfg2 = (0 + | (0 << 26) /* True DQS */ + | (odt_cfg << 21) /* ODT only read */ + | (1 << 12) /* 1 refresh at a time */ + ); + + debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); + } + #ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; #else @@ -462,11 +713,22 @@ long int spd_sdram() * * sdram_cfg[0] = 1 (ddr sdram logic enable) * sdram_cfg[1] = 1 (self-refresh-enable) - * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM) + * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) + * 010 DDR 1 SDRAM + * 011 DDR 2 SDRAM * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode) * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts) */ - sdram_cfg = 0xC2000000; + if (spd.mem_type == SPD_MEMTYPE_DDR) + sdram_type = 2; + else + sdram_type = 3; + + sdram_cfg = (0 + | (1 << 31) /* DDR enable */ + | (1 << 30) /* Self refresh */ + | (sdram_type << 24) /* SDRAM type */ + ); /* sdram_cfg[3] = RD_EN - registered DIMM enable */ if (spd.mod_attr & 0x02) -- 1.4.4.1

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