February 2007 - U-Boot

[U-Boot-Users] [PATCH 1/4] PXA27x LCD and boot logo support
by Rodolfo Giometti 15 Feb '07

15 Feb '07

Boot logo compilation fixup. Signed-off-by: Rodolfo Giometti <giometti(a)linux.it>

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Re: [U-Boot-Users] U-Boot-Users Digest, Vol 9, Issue 41
by Russell McGuire 15 Feb '07

15 Feb '07

Kim, I assume this change has no affect on boards that are do not have the BCSR registers on them? i.e. I have a tendancy to use your config files, with a board that I designed after your reference design. The only differenc being we don't have the FPGPA sitting in the middle of the board. Oridinarily I wouldn't ask this, but I have seen this hardware timeout with my Engineering sample of a Rev 1.2 <half way to Rev 2.0 CPU, since I was having to add new CPU ID's to U-boot 6 months ago>. Is it purely CPU related or something to do with extra buffers that were created via extra hardware? -Russ > From: Kim Phillips <kim.phillips(a)freescale.com> > Subject: [U-Boot-Users] [PATCH] mpc83xx: Disable G1TXCLK, G2TXCLK h/w > buffers > To: u-boot-users(a)lists.sourceforge.net > Message-ID: <20070215104830.2a00be45.kim.phillips(a)freescale.com> > Content-Type: text/plain; charset=US-ASCII > > Disable G1TXCLK, G2TXCLK h/w buffers. This patch > fixes a networking timeout issue with MPC8360EA (Rev.2) PBs. > > Verified does not break MPC8360 MDS Rev. 1.1, Rev. 1.2 boards. > > Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> > Signed-off-by: Emilian Medve <Emilian.Medve(a)freescale.com> > --- > board/mpc8360emds/mpc8360emds.c | 9 ++++++++- > 1 files changed, 8 insertions(+), 1 deletions(-) > > diff --git a/board/mpc8360emds/mpc8360emds.c > b/board/mpc8360emds/mpc8360emds.c > index 54b9acc..535884c 100644 > --- a/board/mpc8360emds/mpc8360emds.c > +++ b/board/mpc8360emds/mpc8360emds.c > @@ -90,11 +90,18 @@ const qe_iop_conf_t qe_iop_conf_tab[] = > > int board_early_init_f(void) > { > - volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; > + > + u8 *bcsr = (u8 *)CFG_BCSR; > + const immap_t *immr = (immap_t *)CFG_IMMR; > > /* Enable flash write */ > bcsr[0xa] &= ~0x04; > > + /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) > */ > + if (immr->sysconf.spridr == SPR_8360_REV20 || > + immr->sysconf.spridr == SPR_8360E_REV20) > + bcsr[0xe] = 0x30; > + > return 0; > }

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[U-Boot-Users] digit
by Abbott Valentine 15 Feb '07

15 Feb '07

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[U-Boot-Users] [PATCH] mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers
by Kim Phillips 15 Feb '07

15 Feb '07

Disable G1TXCLK, G2TXCLK h/w buffers. This patch fixes a networking timeout issue with MPC8360EA (Rev.2) PBs. Verified does not break MPC8360 MDS Rev. 1.1, Rev. 1.2 boards. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> Signed-off-by: Emilian Medve <Emilian.Medve(a)freescale.com> --- board/mpc8360emds/mpc8360emds.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index 54b9acc..535884c 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -90,11 +90,18 @@ const qe_iop_conf_t qe_iop_conf_tab[] = int board_early_init_f(void) { - volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; + + u8 *bcsr = (u8 *)CFG_BCSR; + const immap_t *immr = (immap_t *)CFG_IMMR; /* Enable flash write */ bcsr[0xa] &= ~0x04; + /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */ + if (immr->sysconf.spridr == SPR_8360_REV20 || + immr->sysconf.spridr == SPR_8360E_REV20) + bcsr[0xe] = 0x30; + return 0; } -- 1.4.2.3

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[U-Boot-Users] reg u-boot 1.1.6 integeration to ISP 1561
by mahendra varman 15 Feb '07

15 Feb '07

Hi Iam using ISP 1561 usb controller in a PPC board While trying to integrate the usb controller iam facing these problems The OHCI root hub is detected but the usb mass storage device( usb flash stick) is not detected I found the following 1. Under common/usb.c struct usb_device * usb_get_dev_index(int index) { if(usb_dev[index].devnum==-1) return NULL; else return &usb_dev[index]; } This structure is returning NULL for me ... Whether the device number for the usb is not allocated ?? 2. If i comment the if statement above and leave alone return &usb_dev[index]; it is proceding but it gets out once it comes to usb_storage_probe routine The endianness is followed correctly becaz i used debug statements and i can see the OHCI registers are written with proper endianness Can u help me to sort out the problem why the storage device is not detected ? Thanks in advance Raja --------------------------------- Heres a new way to find what you're looking for - Yahoo! Answers

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[U-Boot-Users] Fwd: Re: Problem with TFTP in u-boot 1.1.4
by Raúl Sánchez Siles 15 Feb '07

15 Feb '07

---------- Mensaje reenviado ---------- Subject: Re: [U-Boot-Users] Problem with TFTP in u-boot 1.1.4 Date: Miércoles, 14 de Febrero de 2007 20:06 From: Ben Warren <bwarren(a)qstreams.com> To: rss(a)barracuda.es On Wed, 2007-02-14 at 10:57 +0100, Raúl Sánchez Siles wrote: > Ben Warren wrote: > > If this is OK, try to ping your PC from the board. > > Does u-boot provide a ping command? Yes. Make sure you have the CFG_CMD_PING bit set in CONFIG_COMMANDS. regards, Ben I resend this answer to the list. Thanks Ben. -- Raúl Sánchez Siles Barracuda Systems S.L. C/ Luxemburgo, 4 - Local Pozuelo de Alarcón 28224 Madrid Tlf.: +34 91 351 11 20 Fax: +34 91 352 54 44 Nota: Si advierte una archivo adjunto con nombre de la forma attxxxx.dat se trata de mi firma digital. Existen lectores de correo electrónico capaces de interpretar esta información. Si el suyo no la entiende, no se preocupe, no es importante.

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[U-Boot-Users] miscellaneous cleanup patches
by Grant Likely 14 Feb '07

14 Feb '07

Here's a bunch of cleanup patches from my local tree. I've cherry-picked the ones that I think are ready to be merged. I've got a bunch more in the works; but I figure it will be less painless if I send them in smaller chunks. I've tested these changes on my xilinx ppc405 platform, and on a lite5200b. Can someone who has a Dataflash part test the print_buffer patch for me? There shouldn't be any functional changes, but I don't have the board to test it. These patches can also be pulled from the merge branch of my git tree: git://git.secretlab.ca/srv/git-trees/public/git/u-boot.git#merge --or-- http://git.secretlab.ca/git/u-boot.git#merge Thanks, g. board/esd/common/auto_update.c | 3 +- board/mcc200/auto_update.c | 3 +- board/mpl/mip405/mip405.c | 3 - board/trab/auto_update.c | 1 - board/xilinx/ml300/Makefile | 2 +- board/xilinx/ml300/ml300.c | 2 +- board/xilinx/ml300/serial.c | 3 +- board/xilinx/xilinx_enet/emac_adapter.c | 2 +- board/xilinx/xilinx_enet/xemac.h | 2 +- board/xilinx/xilinx_enet/xemac_g.c | 2 +- board/xilinx/xilinx_iic/iic_adapter.c | 2 +- common/cmd_ext2.c | 40 +---------------- common/cmd_fat.c | 37 +---------------- common/cmd_ide.c | 8 +++- common/cmd_mem.c | 64 ++++++---------------------- common/cmd_reiser.c | 40 +---------------- common/cmd_scsi.c | 2 +- common/cmd_usb.c | 1 + common/ft_build.c | 6 +-- common/usb_storage.c | 3 +- cpu/pxa/mmc.c | 2 +- disk/part.c | 49 +++++++++++++++++++++ include/common.h | 2 + include/ide.h | 6 +- include/part.h | 9 ++++ lib_generic/display_options.c | 70 +++++++++++++++++++++++++++++++ 26 files changed, 176 insertions(+), 188 deletions(-)

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Re: [U-Boot-Users] BDI config file - MPC8360e issue
by agnel juni 14 Feb '07

14 Feb '07

Thanks Steve. That solved the issue. ----- Original Message ---- From: agnel juni <junijoseph(a)yahoo.co.in> To: u-boot-users(a)lists.sourceforge.net Sent: Tuesday, 13 February, 2007 2:26:06 PM Subject: BDI config file - MPC8360e issue Hi: I am working with a MPC8360EA MDS processor board with Rev2.0 silicon and DDR2 memory in it. I need to program the flash with u-boot using BDI2000. I downloaded the BDI config gile from the following FTP site as susggested in the mailing list. ftp://83.125.32.26/bdigdb/config/powerpc/mpc83xx/ I verified the DDR2 parameters from u-boot and it matches the configuration section of the BDI config file too. The board has 32MB Spansion flash in it (S29GL256N). But when I connect the BDI to the board , BDI keeps resettingthe board with the following error. /****************************************************************/ TARGET: Target PVR is 0x80830030 - TARGET: resetting target passed - TARGET: processing target startup .... - COP status is 0x01 - Target PVR is 0x80830030 - BDI tries to resynch TAP - COP status is 0x21 - Target PVR is 0x00000000 *** TARGET: processing target startup failed # PPC: timeout while waiting for freeze - TARGET: target will be restarted in 10 sec /**************************************************************/ Any suggestions to solve this issue would be appreciated. Thanks Junita Heres a new way to find what you're looking for - Yahoo! Answers __________________________________________________________ Yahoo! India Answers: Share what you know. Learn something new http://in.answers.yahoo.com/

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Re: [U-Boot-Users] [PATCH] Fixup relocation patch.]
by Joakim Tjernlund 14 Feb '07

14 Feb '07

> From: Txema Lopez [mailto:tlopez@aotek.es] > Sent: 14 February 2007 09:01 > To: Joakim Tjernlund > Cc: u-boot-users(a)lists.sourceforge.net > Subject: Re: [U-Boot-Users] [PATCH] Fixup relocation patch.] > > Joakim Tjernlund wrote: > > >I wonder, how far off is a fully relocatable u-boot? That > is, burn it anywhere > >in flash and start it from there? > > > > Jocke > > > > > > > Hi Jocke, > The patch was done precisely for it. You can copy a U-Boot > image from an > address in flash to another and calculate the new pointers in > the GOT an > FIXUP sections before do the copy. > But you need another change in U-Boot to turn it fully relocatable. > U-Boot is hardly joined with the link address TEXT_BASE. You must > replace it for a label in U-Boot and change the lines in the > U-Boot code > where there is a direct or indirect reference (as > CFG_MONITOR_BASE) to > TEXT_BASE. > > Best regards, > Txema Hi Txema Can you give an example on how to change these references to TEXT_BASE/CFG_MONITOR_BASE? Regards Jocke

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[U-Boot-Users] [PATCH 2/3]Add the cpu specific code for MPC8360E rev2.0 MDS
by Xie Xiaobo 14 Feb '07

14 Feb '07

MPC8360E rev2.0 have new spridr,and PVR value, The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo<X.Xie(a)freescale.com> --- This patch applies to the mpc83xx branch of the opensource.freescale.com u-boot-83xx.git tree cpu/mpc83xx/cpu.c | 2 ++ include/configs/MPC8360EMDS.h | 33 +++++++++++++++++++++++++++++---- include/mpc83xx.h | 2 ++ 3 files changed, 33 insertions(+), 4 deletions(-) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 9f55f18..9462f85 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -93,11 +93,13 @@ int checkcpu(void) case SPR_8360E_REV10: case SPR_8360E_REV11: case SPR_8360E_REV12: + case SPR_8360E_REV20: puts("MPC8360E, "); break; case SPR_8360_REV10: case SPR_8360_REV11: case SPR_8360_REV12: + case SPR_8360_REV20: puts("MPC8360, "); break; case SPR_8323E_REV10: diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index e404bce..f7ebf77 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -100,12 +100,19 @@ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ #define CFG_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #define CFG_83XX_DDR_USES_CS0 -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ +/* + * DDRCDR - DDR Control Driver Register + */ +#define CFG_DDRCDR_VALUE 0x80080001 + #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #if defined(CONFIG_SPD_EEPROM) /* @@ -117,6 +124,21 @@ * Manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CFG_DDRCDR 0x80080001 +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS0_CONFIG 0x80330102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x38357322 +#define CFG_DDR_TIMING_2 0x2f9048c8 +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x47d00432 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03cf0080 +#define CFG_DDR_SDRAM_CFG 0x43000000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#else #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) #define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ #define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */ @@ -124,6 +146,7 @@ #define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ #define CFG_DDR_INTERVAL 0x045b0100 /* page mode */ #endif +#endif /* * Memory test @@ -168,7 +191,7 @@ #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ +#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ @@ -176,10 +199,12 @@ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ -#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ #undef CFG_FLASH_CHECKSUM diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 73f2721..33f02ef 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -83,6 +83,8 @@ #define SPR_8360_REV11 0x80490011 #define SPR_8360E_REV12 0x80480012 #define SPR_8360_REV12 0x80490012 +#define SPR_8360E_REV20 0x80480020 +#define SPR_8360_REV20 0x80490020 #define SPR_8323E_REV10 0x80620010 #define SPR_8323_REV10 0x80630010 -- 1.4.4.1

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