January 2007 - U-Boot

Re: [U-Boot-Users] Atmel DataFlash hooks.
by Grant Likely 29 Jan '07

29 Jan '07

On 1/26/07, Ulf Samuelsson <ulfs(a)dof.se> wrote: > Grant Likely wrote: > > On 1/26/07, Ulf Samuelsson <ulfs(a)dof.se> wrote: > > > >> Are you prepared to make the fixes so that all Atmel development kits > >> are supported by your patches. > >> This means taking the atmnel patches from the Atmel ftp site and > >> test them thoroughly on the appropriate boards. > > > > No. If the board port is not in mainline, then it is the > > responsibility of the port maintainer to keep it synced. > > > > Now with the new approach to introducing patches, > I think the SAM9 patches should be sent in soon > and you will have a significant number of boards > that will break if you screw up. Just because I write the patches doesn't mean they get accepted. They need to be acked by someone who has tested them first. I'm offering to take on the workload of writing the patches, but I cannot take on the testing. A number of the changes that I'm making right now (not just DataFlash) affect every single board, but I cannot test them all. Best I can do is make sure it works on the handful of boards I do have, post the patches for others to test, and only request inclusion in mainline when nobody reports problems with them. > > > For the stuff that *is* in mainline, I will of course make sure that > > the patches compile, but I cannot test them. I do not have the > > hardware to do so, nor will I spend the time to test boards that I > > have absolutely no involvement with. > > > > That sound like a great idea, introduce significant modifications > without testing... The mods I'm interested in are the architectural changes which I can and will test. The DataFlash changes are collateral damage. The alternative for me is to break dataflash support without even attempting to providing a solution. > > I think you should spend time on modifying things you *can* test. Then how does *anybody* attempt to fix common code? Nobody can test all platforms. Cheers, g. -- Grant Likely, B.Sc. P.Eng. Secret Lab Technologies Ltd. grant.likely(a)secretlab.ca (403) 399-0195

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[U-Boot-Users] kernel bootup for PQ2FADS-ZU
by Nethra 29 Jan '07

29 Jan '07

hi, I am using montavista linux kernel 2.6.10 and after nfs mounting it is giving fallowing error. => setenv bootargs root=/dev/nfs nfsroot=192.168.178.110:/mnt ip=192.168.178.234 :192.168.178.110:192.168.178.6:255.255.255.0:cashel:eth1:off => savee Saving Environment to Flash... . Un-Protected 1 sectors Erasing Flash... . done Erased 1 sectors Writing to Flash... done . Protected 1 sectors => printenv bootdelay=5 baudrate=38400 ethact=FCC2 ETHERNET serverip=192.168.178.110 ethaddr=00:99:23:44:ad:de bootcmd=tftpboot 0x1000000 godcome;bootm 0x1000000; ipaddr=192.168.178.234 stdin=serial stdout=serial stderr=serial bootargs=root=/dev/nfs nfsroot=192.168.178.110:/mnt ip=192.168.178.234:192.168.1 78.110:192.168.178.6:255.255.255.0:cashel:eth1:off Environment size: 346/262140 bytes => run bootcmd Using FCC2 ETHERNET device TFTP from server 192.168.178.110; our IP address is 192.168.178.234 Filename 'godcome'. Load address: 0x1000000 Loading: ################################################################# ################################################################# ######################################################## done Bytes transferred = 948671 (e79bf hex) ## Booting image at 01000000 ... Image Name: Linux-2.6.10_mvl401-8272ads Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 948607 Bytes = 926.4 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK Linux version 2.6.10_mvl401-8272ads (root@em178110) (gcc version 3.4.3 (MontaVis ta 3.4.3-25.0.70.0501961 2005-12-18)) #2 Tue Jan 23 16:54:50 IST 2007 Motorola PQ2 ADS PowerPC port Built 1 zonelists Kernel command line: root=/dev/nfs nfsroot=192.168.178.110:/mnt ip=192.168.178.2 34:192.168.178.110:192.168.178.6:255.255.255.0:cashel:eth1:off PID hash table entries: 256 (order: 8, 4096 bytes) hr_time_init: arch_to_nsec = 83886080, nsec_to_arch = 107374182 Warning: real time clock seems stuck! Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 30152k available (1684k kernel code, 468k data, 100k init, 0k highmem) Mount-cache hash table entries: 512 (order: 0, 4096 bytes) spawn_desched_task(00000000) desched cpu_callback 3/00000000 ksoftirqd started up. desched cpu_callback 2/00000000 desched thread 0 started up. NET: Registered protocol family 16 Installing knfsd (copyright (C) 1996 okir(a)monad.swb.de). Initializing Cryptographic API Serial: CPM driver $Revision: 0.01 $ ttyCPM0 at MMIO 0xf0011a00 (irq = 40) is a CPM UART ttyCPM1 at MMIO 0xf0011a60 (irq = 43) is a CPM UART io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize loop: loaded (max 8 devices) fs_enet.c:v1.0 (Aug 8, 2005) Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx eth0: FCC ENET Version 0.3, 00:99:23:c4:ad:de eth1: FCC ENET Version 0.3, 00:99:23:44:ad:de eth2: FCC ENET Version 0.3, 00:99:23:64:ad:de NET: Registered protocol family 2 IP: routing cache hash table of 512 buckets, 4Kbytes TCP: Hash tables configured (established 2048 bind 4096) NET: Registered protocol family 1 NET: Registered protocol family 17 IP-Config: Complete: device=eth1, addr=192.168.178.234, mask=255.255.255.0, gw=192.168.178.6, host=cashel, domain=, nis-domain=(none), bootserver=192.168.178.110, rootserver=192.168.178.110, rootpath= Looking up port of RPC 100003/2 on 192.168.178.110 Looking up port of RPC 100005/1 on 192.168.178.110 VFS: Mounted root (nfs filesystem) readonly. Freeing unused kernel memory: 100k init Warning: unable to open an initial console. Kernel panic - not syncing: No init found. Try passing init= option to kernel. <0>Rebooting in 180 seconds.. is root file system correct? If not, where is the problem? waiting for early response... with regards, Nethra -- View this message in context: http://www.nabble.com/kernel-bootup-for-PQ2FADS-ZU-tf3134550.html#a8685457 Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] gummy psychopath
by Davila P. Gordon 29 Jan '07

29 Jan '07

I might get a chance to! David Carpenter is on Drums, Davee C. band Sleddogs have made a real mark on the Canadian rock landscape. "The rise and fall of nations," he writes, " . As we enter this new and excitin The results were surprising to both musicians. It profiled a 425-pound college kid who cut his weight in half by eating fast food. Finally, someone to compete with Mariah Carey. Harpooning listeners with his soulful mix of haunting ballads and life-altering guitar licks, Alan Robert walks the fine line between genius and insanity- and he walks it well. This album is the one, remarks Brett the bands vocals and guitar man. , whom had found a love for poetry and singing in a Pentecostal church. Web Hosting News: Hostbreak Announces WordPress 2. But if you value narrative coherence and deeply thought-out characters, you're out of luck. It is nothing if not Pynchonian. has the advantage of five lifetimes they brought with them into this enterprise. Well there you have it, The Outfit! Producer Ken Allardyce helmed her debut album, "Beautiful to be Alive," which features a guest appearance by John Rzeznik, lead singer of the Goo Goo Dolls. Tehel and drummer Dennis Joseph were living similar lifestyles. The band went on to headline shows all over Massachusetts at a slew of all ages VFW hall shows.

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[U-Boot-Users] MCF5271 Port.
by adarsh babu 29 Jan '07

29 Jan '07

Hi, A small typ error in the previous mail. The Host system as Red Hat 9 Kernel version 2.4.20.8 Regards, Adarsh. __________________________________________________________ Yahoo! India Answers: Share what you know. Learn something new http://in.answers.yahoo.com/

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Re: [U-Boot-Users] Atmel DataFlash hooks.
by Grant Likely 29 Jan '07

29 Jan '07

On 1/26/07, Ulf Samuelsson <ulfs(a)dof.se> wrote: First, a clarification. I'm coming at this from the point of view of establishing some architectural clarity. Currently, the primary way to access non-memory-mapped memories is via the block device infrastructure (include/part.h, disk/part.c). DataFlash is currently a major exception and I see no reason to treat it as such. My goal is to attack the current #ifdef hell in u-boot. DataFlash just happens to be the first thing I want to clean up. I'm pretty sure I'm going to trod on all kinds of toes as I go through stuff. > Are you prepared to make the fixes so that all Atmel development kits > are supported by your patches. > This means taking the atmnel patches from the Atmel ftp site and > test them thoroughly on the appropriate boards. No. If the board port is not in mainline, then it is the responsibility of the port maintainer to keep it synced. For the stuff that *is* in mainline, I will of course make sure that the patches compile, but I cannot test them. I do not have the hardware to do so, nor will I spend the time to test boards that I have absolutely no involvement with. Once again, this is about establishing some level of architectural clarity; in this case about how to access non memory mapped memories. That *requires* discussion and involvement of the board port maintainers. > > AT91SAM9260EK > AT91SAM9261EK > AT91SAM9263EK > AT91RM9200DK > AT91RM9200EK > ATR0663EK > AT91SAM9XE > and probably several AVR32 boards currently in design. > > I assume there are multiple customer boards that rely on this as well. Even if the owner of the non-mainline boards is not able/willing to migrate to internal u-boot changes, older u-boot releases will of course continue to work as is. However, I refuse to be handcuffed to old design and code if in hindsight it was poorly done. I reference "linux-2.6/Documentation/stable_api_nonsense.txt" here as support. > > Will you patches support byte writes? I don't see any reason why not. Need to settle on a design first. > > 3. Create an abstraction layer for accessing both bus addressable and > > non bus addressable memories. Add a naming convention for commands to > > specify non-bus-addressable devices. ie. "cp.b 00004000 DF:0000 100" > > would copy 0x100 bytes from bus address 0x4000 to dataflash 0x0000. > > (but I really don't think this is the route to go; far to complex. I > > don't think it is unreasonable to require a separate command to copy > > to/from off-bus memories before comparing, booting, etc.) > > > > I think it is unreasonable to require that users of dataflash > has a more complex way of handling that memory. > Computers are good at handling these things, humans are not. Changes to the load sequence can easily be handled in environmental boot scripts. Regardless of how it is changed, the command format should not stay as-is (as I think it is a bad precedence to pretend it has a bus address). Hence it does require changes to how boards are booted (like your example solution below). > > Woudl you accept a patch that required bus addressable devices > to have a prefix? > "cp.b BAD:00004000 0000 100" As I said; I don't particularly like this from an architectural standpoint. However, if it was done in a way that was *generic* (ie. any memory device could register to use it) then I would be cool with it. If it's just another mess of device specific #ifdefs in the memory access routines then I violently disagree. -- Grant Likely, B.Sc. P.Eng. Secret Lab Technologies Ltd. grant.likely(a)secretlab.ca (403) 399-0195

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[U-Boot-Users] [PATCH] Add support for the MPC8349E-mITX-GP
by timur＠freescale.com 29 Jan '07

29 Jan '07

From: Timur Tabi <timur(a)freescale.com> Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- MAINTAINERS | 1 + Makefile | 16 ++- board/mpc8349itx/config.mk | 6 +- board/mpc8349itx/mpc8349itx.c | 105 ++-------- include/configs/MPC8349ITX.h | 463 ++++++++++++++++------------------------- include/mpc83xx.h | 41 ++++ 6 files changed, 264 insertions(+), 368 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ce20def..e65699f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -347,6 +347,7 @@ John Zhan <zhanz(a)sinovee.com> Timur Tabi <timur(a)freescale.com> MPC8349E-mITX MPC8349 + MPC8349E-mITX-GP MPC8349 Kim Phillips <kim.phillips(a)freescale.com> diff --git a/Makefile b/Makefile index 1dbdf4d..10d961f 100644 --- a/Makefile +++ b/Makefile @@ -1624,8 +1624,20 @@ MPC8360EMDS_SLAVE_config: unconfig fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds -MPC8349ITX_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx +MPC8349ITX_config \ +MPC8349ITX_LOWBOOT_config \ +MPC8349ITXGP_config: unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/mpc8349itx + @CTYPE=$(subst MPC,,$(@:_config=)); \ + echo "#define CONFIG_MPC$${CTYPE}" >> $(obj)include/config.h + @if [ "$(findstring GP,$@)" ] ; then \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + fi + @if [ "$(findstring LOWBOOT,$@)" ] ; then \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + fi + @$(MKCONFIG) -a MPC8349ITX ppc mpc83xx mpc8349itx ######################################################################### ## MPC85xx Systems diff --git a/board/mpc8349itx/config.mk b/board/mpc8349itx/config.mk index 2e11311..1901fdc 100644 --- a/board/mpc8349itx/config.mk +++ b/board/mpc8349itx/config.mk @@ -21,10 +21,14 @@ # # -# MPC8349ITX +# MPC8349E-mITX and MPC8349E-mITX-GP # +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE TEXT_BASE = 0xFEF00000 +endif ifneq ($(OBJTREE),$(SRCTREE)) # We are building u-boot in a separate directory, use generated diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 4838e70..aefdaf7 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -134,88 +134,6 @@ volatile static struct pci_controller ho }; #endif /* CONFIG_PCI */ -/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. */ - -void sdram_init(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile lbus83xx_t *lbc = &immap->lbus; - -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) \ - && !defined(CONFIG_COMPACT_FLASH) - - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; - - puts("\n SDRAM on Local Bus: "); - print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - - /*setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode register. - */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ - - lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733; precharge all the banks */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_2; /*0x48636733; auto refresh */ - asm("sync"); - *sdram_addr = 0xff; /*1 time*/ - udelay(100); - *sdram_addr = 0xff; /*2 times*/ - udelay(100); - *sdram_addr = 0xff; /*3 times*/ - udelay(100); - *sdram_addr = 0xff; /*4 times*/ - udelay(100); - *sdram_addr = 0xff; /*5 times*/ - udelay(100); - *sdram_addr = 0xff; /*6 times*/ - udelay(100); - *sdram_addr = 0xff; /*7 times*/ - udelay(100); - *sdram_addr = 0xff; /*8 times*/ - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - -#else - puts("SDRAM on Local Bus is NOT available!\n"); - -#ifdef CFG_BR2_PRELIM - lbc->bank[2].br = CFG_BR2_PRELIM; - lbc->bank[2].or = CFG_OR2_PRELIM; -#endif - -#ifdef CFG_BR3_PRELIM - lbc->bank[3].br = CFG_BR3_PRELIM; - lbc->bank[3].or = CFG_OR3_PRELIM; -#endif -#endif -} - long int initdram(int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; @@ -246,7 +164,6 @@ long int initdram(int board_type) /* * Initialize SDRAM if it is on local bus. */ - sdram_init(); puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return msize * 1024 * 1024; @@ -254,7 +171,11 @@ long int initdram(int board_type) int checkboard(void) { +#ifdef CONFIG_MPC8349ITX puts("Board: Freescale MPC8349E-mITX\n"); +#else + puts("Board: Freescale MPC8349E-mITX-GP\n"); +#endif return 0; } @@ -267,6 +188,7 @@ int checkboard(void) */ int misc_init_f(void) { +#ifdef CFG_VSC7385_BASE volatile u32 *vsc7385_cpuctrl; /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up @@ -286,6 +208,7 @@ int misc_init_f(void) vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); *vsc7385_cpuctrl |= 0x0c; +#endif #ifdef CONFIG_COMPACT_FLASH /* UPM Table Configuration Code */ @@ -355,9 +278,19 @@ int misc_init_r(void) #ifdef CFG_I2C_EEPROM_ADDR static u8 eeprom_data[] = /* HRCW data */ { - 0xaa, 0x55, 0xaa, - 0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00, - 0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00, + 0xAA, 0x55, 0xAA, /* Preamble */ + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ + (CFG_HRCW_LOW >> 24) & 0xFF, + (CFG_HRCW_LOW >> 16) & 0xFF, + (CFG_HRCW_LOW >> 8) & 0xFF, + CFG_HRCW_LOW & 0xFF, + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ + (CFG_HRCW_HIGH >> 24) & 0xFF, + (CFG_HRCW_HIGH >> 16) & 0xFF, + (CFG_HRCW_HIGH >> 8) & 0xFF, + CFG_HRCW_HIGH & 0xFF }; u8 data[sizeof(eeprom_data)]; diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index cbdbb29..2774a65 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -21,7 +21,7 @@ */ /* - MPC8349E-mITX board configuration file + MPC8349E-mITX and MPC8349E-mITX-GP board configuration file Memory map: @@ -31,11 +31,11 @@ 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000-0xF000_FFFF Compact Flash + 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 0xF001_0000-0xF001_FFFF Local bus expansion slot - 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 - 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) - 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) + 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) + 0xFF00_0000-0xFF7F_FFFF First 8MB bank of Flash memory + 0xFF80_0000-0xFFFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) I2C address list: Align. Board @@ -56,7 +56,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#undef DEBUG +#if (TEXT_BASE == 0xFE000000) +#define CFG_LOWBOOT +#endif /* * High Level Configuration Options @@ -64,14 +66,26 @@ #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ #define CONFIG_MPC8349 /* MPC8349 specific */ +#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ + + +/* On-board devices */ + #define CONFIG_PCI +#ifdef CONFIG_MPC8349ITX #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ +#endif #define CONFIG_RTC_DS1337 -/* I2C */ #define CONFIG_HARD_I2C +#define CONFIG_TSEC_ENET /* TSEC Ethernet support */ +/* + * Device configurations + */ + +/* I2C */ #ifdef CONFIG_HARD_I2C #define CONFIG_MISC_INIT_F @@ -111,59 +125,40 @@ #endif -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE +/* Compact Flash */ +#ifdef CONFIG_COMPACT_FLASH -#define PCI_66M -#ifdef PCI_66M -#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#endif +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 1 -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef PCI_66M -#define CONFIG_SYS_CLK_FREQ 66666666 -#else -#define CONFIG_SYS_CLK_FREQ 33333333 -#endif -#endif +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR CFG_CF_BASE +#define CFG_ATA_DATA_OFFSET 0x0000 +#define CFG_ATA_REG_OFFSET 0 +#define CFG_ATA_ALT_OFFSET 0x0200 +#define CFG_ATA_STRIDE 2 -#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ +#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00003000 /* memtest region */ -#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ +#define CONFIG_DOS_PARTITION -/* - * DDR Setup - */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#endif /* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. + * DDR Setup */ -#undef CONFIG_DDR_32BIT - -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#undef CONFIG_DDR_2T_TIMING +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE #define CFG_83XX_DDR_USES_CS0 +#define CFG_MEMTEST_START 0x1000 /* memtest region */ +#define CFG_MEMTEST_END 0x2000 -#ifndef CONFIG_SPD_EEPROM -/* - * Manually set up DDR parameters - */ +#ifdef CONFIG_HARD_I2C +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#endif + +#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* Mb */ #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) @@ -171,46 +166,76 @@ #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ #endif -/* FLASH on the Local Bus */ +/* + *Flash on the Local Bus + */ + #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ #define CFG_FLASH_EMPTY_INFO +#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#ifdef CONFIG_MPC8349ITX + +/* The MPC8349E-mITX has 16MB of flash in two banks */ + +#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ +#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} + +#else + +/* The MPC8349E-mITX-GP has only 8MB of flash in one bank */ + +#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ +#define CFG_FLASH_SIZE_SHIFT 3 /* log2 of the above value */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ + +#endif + +/* + * BRx, ORx, LBLAWBARx, and LBLAWARx + */ + +/* Flash */ + #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE +#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) -/* VSC7385 on the Local Bus */ -#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ +/* Vitesse 7385 */ -#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) -#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ - OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#ifdef CONFIG_MPC8349ITX -#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ -#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ +#define CFG_VSC7385_BASE 0xF8000000 -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ +#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) +#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} +#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE +#define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#endif -#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ +/* LED */ + +#define CFG_LED_BASE 0xF9000000 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ - OR_GPCM_SCY_9 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) + +/* Compact Flash */ #ifdef CONFIG_COMPACT_FLASH @@ -219,32 +244,16 @@ #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) -#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ -#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ - -#undef CONFIG_IDE_RESET -#undef CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 -#define CFG_IDE_MAXDEVICE 1 - -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR CFG_CF_BASE -#define CFG_ATA_DATA_OFFSET 0x0000 -#define CFG_ATA_REG_OFFSET 0 -#define CFG_ATA_ALT_OFFSET 0x0200 -#define CFG_ATA_STRIDE 2 - -#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ +#define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE +#define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) #endif -#define CONFIG_DOS_PARTITION - -#define CFG_MID_FLASH_JUMP 0x7F000000 +/* + * U-Boot memory configuration + */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else @@ -253,10 +262,10 @@ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -272,98 +281,10 @@ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) #define CFG_LBC_LBCR 0x00000000 -#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CFG_LB_SDRAM -/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_LBLAWBAR2_PRELIM 0xF0000000 -#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ - -#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ - OR_SDRAM_XAM | \ - ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ - ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ - OR_SDRAM_EAD) - #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ /* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ - | CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR8 \ - | CFG_LBC_LSDMR_PRETOACT6 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC3 \ - | CFG_LBC_LSDMR_CL3 \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) -#endif - -/* * Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -374,20 +295,16 @@ #define CFG_NS16550_CLK get_bus_freq(0) #define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_BAUDRATE 115200 #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_FLAT_TREE +#define CONFIG_OF_BOARD_SETUP /* maximum size of the flat tree (8K) */ #define OF_FLAT_TREE_MAX_SIZE 8192 @@ -397,6 +314,9 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" +/* + * PCI + */ #ifdef CONFIG_PCI #define CONFIG_MPC83XX_PCI2 @@ -447,14 +367,18 @@ #endif +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#endif + /* TSEC */ #ifdef CONFIG_TSEC_ENET -#ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI -#endif - #define CONFIG_MII #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ @@ -468,6 +392,7 @@ #endif #ifdef CONFIG_MPC83XX_TSEC2 +#define CONFIG_HAS_ETH1 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define CFG_TSEC2_OFFSET 0x25000 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ @@ -479,14 +404,15 @@ #endif - /* * Environment */ +#define CONFIG_ENV_OVERWRITE + #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH /* Flash is not usable now */ @@ -533,16 +459,23 @@ /* Watchdog */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#ifdef CONFIG_WATCHDOG -#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 -#endif /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + #define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#ifdef CONFIG_MPC8349ITX +#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ +#endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -562,15 +495,15 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ +/* + * Cache Configuration + */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ #endif -#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ @@ -578,12 +511,12 @@ HRCWL_VCO_1X2 |\ HRCWL_CORE_TO_CSB_2X1) -#ifdef PCI_64BIT +#ifdef CFG_LOWBOOT #define CFG_HRCW_HIGH (\ HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ + HRCWH_32_BIT_PCI |\ HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0X00000100 |\ HRCWH_BOOTSEQ_DISABLE |\ @@ -596,7 +529,7 @@ HRCWH_PCI_HOST |\ HRCWH_32_BIT_PCI |\ HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0XFFF00100 |\ HRCWH_BOOTSEQ_DISABLE |\ @@ -606,30 +539,33 @@ HRCWH_TSEC2M_IN_GMII ) #endif -/* System performance */ +/* + * System performance + */ #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ -#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ -/* System IO Config */ +/* + * System IO Config + */ #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) -#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE -/* DDR @ 0x00000000 */ +/* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -/* PCI @ 0x80000000 */ +/* PCI */ #ifdef CONFIG_PCI #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) @@ -706,49 +642,27 @@ #endif #ifdef CONFIG_MPC83XX_TSEC2 -#define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif -#if 1 -#define CONFIG_IPADDR 10.82.19.159 -#define CONFIG_SERVERIP 10.82.48.106 -#define CONFIG_GATEWAYIP 10.82.19.254 -#define CONFIG_NETMASK 255.255.252.0 -#define CONFIG_NETDEV eth0 - -#define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs -#define CONFIG_BOOTFILE timur/uImage - -#define CONFIG_UBOOTPATH timur/u-boot.bin -#else #define CONFIG_IPADDR 192.168.1.253 #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.252.0 #define CONFIG_NETDEV eth0 +#ifdef CONFIG_MPC8349ITX #define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot/rootfs -#define CONFIG_BOOTFILE uImage - -#define CONFIG_UBOOTPATH u-boot.bin +#else +#define CONFIG_HOSTNAME mpc8349emitxgp #endif -#define CONFIG_UBOOTSTART fe700000 -#define CONFIG_UBOOTEND fe77ffff - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BAUDRATE 115200 +/* Default path and filenames */ +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTDELAY 6 -#else -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ -#endif +#define CONFIG_BOOTDELAY 0 #define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) @@ -756,47 +670,38 @@ #define CONFIG_BOOTARGS \ "root=/dev/nfs rw" \ " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ - " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ + " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ " console=ttyS0," MK_STR(CONFIG_BAUDRATE) #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ - "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ - "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ - "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "protect off FEF00000 FEF7FFFF; " \ - "erase FEF00000 FEF7FFFF; " \ - "cp.b $loadaddr FEF00000 $filesize; " \ - "protect on FEF00000 FEF7FFFF; " \ - "cmp.b $loadaddr FEF00000 $filesize\0" \ - "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ - "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "fdtaddr=400000\0" \ - "fdtfile=mpc8349emitx.dtb\0" \ - "" + "fdtfile=mpc8349emitx.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ + " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - + "setenv bootargs root=/dev/ram rw" \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #undef MK_STR #undef XMK_STR diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 03dd0ca..41180e8 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -221,6 +221,47 @@ #define OR_SDRAM_EAD 0x00000001 #define OR_SDRAM_EAD_SHIFT 0 +#define OR_AM_32KB 0xFFFF8000 +#define OR_AM_64KB 0xFFFF0000 +#define OR_AM_128KB 0xFFFE0000 +#define OR_AM_256KB 0xFFFC0000 +#define OR_AM_512KB 0xFFF80000 +#define OR_AM_1MB 0xFFF00000 +#define OR_AM_2MB 0xFFE00000 +#define OR_AM_4MB 0xFFC00000 +#define OR_AM_8MB 0xFF800000 +#define OR_AM_16MB 0xFF000000 +#define OR_AM_32MB 0xFE000000 +#define OR_AM_64MB 0xFC000000 +#define OR_AM_128MB 0xF8000000 +#define OR_AM_256MB 0xF0000000 +#define OR_AM_512MB 0xE0000000 +#define OR_AM_1GB 0xC0000000 +#define OR_AM_2GB 0x80000000 +#define OR_AM_4GB 0x00000000 + +#define LBLAWAR_EN 0x80000000 +#define LBLAWAR_4KB 0x0000000B +#define LBLAWAR_8KB 0x0000000C +#define LBLAWAR_16KB 0x0000000D +#define LBLAWAR_32KB 0x0000000E +#define LBLAWAR_64KB 0x0000000F +#define LBLAWAR_128KB 0x00000010 +#define LBLAWAR_256KB 0x00000011 +#define LBLAWAR_512KB 0x00000012 +#define LBLAWAR_1MB 0x00000013 +#define LBLAWAR_2MB 0x00000014 +#define LBLAWAR_4MB 0x00000015 +#define LBLAWAR_8MB 0x00000016 +#define LBLAWAR_16MB 0x00000017 +#define LBLAWAR_32MB 0x00000018 +#define LBLAWAR_64MB 0x00000019 +#define LBLAWAR_128MB 0x0000001A +#define LBLAWAR_256MB 0x0000001B +#define LBLAWAR_512MB 0x0000001C +#define LBLAWAR_1GB 0x0000001D +#define LBLAWAR_2GB 0x0000001E + /* * Hard Reset Configration Word - High */ -- 1.4.4

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[U-Boot-Users] Atmel DataFlash hooks.
by Grant Likely 26 Jan '07

26 Jan '07

There is a mountain of stuff that should probably be reworked in u-boot (notably the maze of #ifdefs), but all I've got is a small spade. So, I'll just pick things off as I come across them... Issue: CONFIG_HAS_DATAFLASH hooks are invasive Background: Atmel DataFlash is a serial FLASH device with an SPI interface. There is code in u-boot that pretends that it is bus-addressable. For all but a handful of boards, the commands in cmd_bootm.c, cmd_flash.c and cmd_mem.c (md, mm, cp, bootm, etc) interface with bus addressable memories. However, when CONFIG_HAS_DATAFLASH is defined, extra code is enabled to make it appear that SPI DataFlash is bus addressable to those commands. IMHO, pretending that a serial flash device occupies a range of bus addresses is a bad precedence and a "Really Bad Idea". It means that every command that manipulates memory needs to have special hooks to be aware of DataFlash. The way the current hooks are implemented are ugly and dangerous. (search for CONFIG_HAS_DATAFLASH to see the hooks). Dangerous because code indentation is messed up which makes the code flow hard to follow, and also it invites a great mess if other non-bus-addressable memories are added in the same way. The current hooks should be removed and the DataFlash support should be reworked so it no longer pretends to be bus addressable memories. This leaves the question, "then how should it be accessed?". There are other non-bus-addressable memories out there which have the same problem. For example, i2c eeproms, USB storage, CF, SCSI & IDE drivers. Currently USB storage, IDE, SCSI and MMC share the block device infrastructure used by the filesystem drivers. However it is read-only at the moment (but I've got some patches to fix that). Possible solutions: 1. Move DataFlash support over to the block device infrastructure and add commands for direct manipulation of block devices. This assumes that it makes sense to look at a DataFlash device as just like any other block device. 2. Create a new set of commands specifically for manipulating dataflash 3. Create an abstraction layer for accessing both bus addressable and non bus addressable memories. Add a naming convention for commands to specify non-bus-addressable devices. ie. "cp.b 00004000 DF:0000 100" would copy 0x100 bytes from bus address 0x4000 to dataflash 0x0000. (but I really don't think this is the route to go; far to complex. I don't think it is unreasonable to require a separate command to copy to/from off-bus memories before comparing, booting, etc.) and for completeness: 3. SImply remove the current hooks and leave DataFlash support out of mainline. 4. Grant is on drugs, do nothing. Comments? If I don't here anything, then I'll go ahead an generate a patch to pull out the DataFlash hooks. -- Grant Likely, B.Sc. P.Eng. Secret Lab Technologies Ltd. grant.likely(a)secretlab.ca (403) 399-0195

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Re: [U-Boot-Users] How to skip network driver?
by Joakim Tjernlund 26 Jan '07

26 Jan '07

> In message > <F6AD7E21CDF4E145A44F61F43EE6D939CBC6FC(a)tmnt04.transmode.se> > you wrote: > > > > How about the bootm stuff? That seems to always be present. > > Indeed. U-Boot is a boot loader, so we assume you will always want to > load and boot. So I am the first that found another use :) > > > I am thinking about doing an very small boot to that will > be quick to > > program over JTAG and that boot will only install other images, > > including replacing > > itself, using tftp. > > -> size common/cmd_bootm.o > text data bss dec hex filename > 7000 520 0 7520 1d60 common/cmd_bootm.o > > Do you really think this will make any visible difference in terms of > download speed? It's probably just 3...5% of the image size. Well, thats one of many. Also I THINK you should be able to loose some other bits needed by bootm such as zlib(10K) possibly crc32 also. Jocke

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[U-Boot-Users] [PATCH] Separate 83xx, 85xx, and 86xx configurations into their own Makefiles
by Timur Tabi 26 Jan '07

26 Jan '07

This patch moves the board configuration rules for 83xx, 85xx, and 86xx boards into their own makefiles. All 83xx boards are now configured in Makefile.83xx, all 85xx boards are in Makefile.85xx, and all 86xx boards are in Makefile.86xx. With separate maintainers for these families, this patch allows new boards to be added without having merge conflicts. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- Makefile | 123 +------------------------------------------------------- Makefile.83xx | 33 +++++++++++++++ Makefile.85xx | 86 ++++++++++++++++++++++++++++++++++++++++ Makefile.86xx | 3 + 4 files changed, 125 insertions(+), 120 deletions(-) diff --git a/Makefile b/Makefile index b1952ed..500d679 100644 --- a/Makefile +++ b/Makefile @@ -1607,136 +1607,19 @@ r5200_config : unconfig ## MPC83xx Systems ######################################################################### -TQM834x_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x - -MPC8349EMDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds - -MPC8360EMDS_config \ -MPC8360EMDS_HOST_33_config \ -MPC8360EMDS_HOST_66_config \ -MPC8360EMDS_SLAVE_config: unconfig - @echo "" >include/config.h ; \ - if [ "$(findstring _HOST_,$@)" ] ; then \ - echo -n "... PCI HOST " ; \ - echo "#define CONFIG_PCI" >>include/config.h ; \ - fi ; \ - if [ "$(findstring _SLAVE_,$@)" ] ; then \ - echo "...PCI SLAVE 66M" ; \ - echo "#define CONFIG_PCI" >>include/config.h ; \ - echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ - fi ; \ - if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "...33M ..." ; \ - echo "#define PCI_33M" >>include/config.h ; \ - fi ; \ - if [ "$(findstring _66_,$@)" ] ; then \ - echo -n "...66M..." ; \ - echo "#define PCI_66M" >>include/config.h ; \ - fi ; - @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds - -MPC8349ITX_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx +include Makefile.83xx ######################################################################### ## MPC85xx Systems ######################################################################### -MPC8540ADS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads - -MPC8540EVAL_config \ -MPC8540EVAL_33_config \ -MPC8540EVAL_66_config \ -MPC8540EVAL_33_slave_config \ -MPC8540EVAL_66_slave_config: unconfig - @mkdir -p $(obj)include - @echo "" >$(obj)include/config.h ; \ - if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "... 33 MHz PCI" ; \ - else \ - echo "#define CONFIG_SYSCLK_66M" >>$(obj)include/config.h ; \ - echo -n "... 66 MHz PCI" ; \ - fi ; \ - if [ "$(findstring _slave_,$@)" ] ; then \ - echo "#define CONFIG_PCI_SLAVE" >>$(obj)include/config.h ; \ - echo " slave" ; \ - else \ - echo " host" ; \ - fi - @$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval - -MPC8560ADS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads - -MPC8541CDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds - -MPC8548CDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds - -MPC8555CDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds - -PM854_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 - -PM856_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm856 - -sbc8540_config \ -sbc8540_33_config \ -sbc8540_66_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _66_,$@)" ] ; then \ - echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \ - echo "... 66 MHz PCI" ; \ - else \ - >$(obj)include/config.h ; \ - echo "... 33 MHz PCI" ; \ - fi - @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 - -sbc8560_config \ -sbc8560_33_config \ -sbc8560_66_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _66_,$@)" ] ; then \ - echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \ - echo "... 66 MHz PCI" ; \ - else \ - >$(obj)include/config.h ; \ - echo "... 33 MHz PCI" ; \ - fi - @$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560 - -stxgp3_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 - -TQM8540_config \ -TQM8541_config \ -TQM8555_config \ -TQM8560_config: unconfig - @mkdir -p $(obj)include - @CTYPE=$(subst TQM,,$(@:_config=)); \ - >$(obj)include/config.h ; \ - echo "... TQM"$${CTYPE}; \ - echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \ - echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \ - echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \ - echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \ - echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>$(obj)include/config.h - @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx +include Makefile.85xx ######################################################################### ## MPC86xx Systems ######################################################################### -MPC8641HPCN_config: unconfig - @./mkconfig $(@:_config=) ppc mpc86xx mpc8641hpcn - +include Makefile.86xx ######################################################################### ## 74xx/7xx Systems diff --git a/Makefile.83xx b/Makefile.83xx new file mode 100644 index 0000000..f9e1400 --- /dev/null +++ b/Makefile.83xx @@ -0,0 +1,33 @@ +TQM834x_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x + +MPC8349EMDS_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds + +MPC8360EMDS_config \ +MPC8360EMDS_HOST_33_config \ +MPC8360EMDS_HOST_66_config \ +MPC8360EMDS_SLAVE_config: unconfig + @echo "" >include/config.h ; \ + if [ "$(findstring _HOST_,$@)" ] ; then \ + echo -n "... PCI HOST " ; \ + echo "#define CONFIG_PCI" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _SLAVE_,$@)" ] ; then \ + echo "...PCI SLAVE 66M" ; \ + echo "#define CONFIG_PCI" >>include/config.h ; \ + echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _33_,$@)" ] ; then \ + echo -n "...33M ..." ; \ + echo "#define PCI_33M" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _66_,$@)" ] ; then \ + echo -n "...66M..." ; \ + echo "#define PCI_66M" >>include/config.h ; \ + fi ; + @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds + +MPC8349ITX_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx + diff --git a/Makefile.85xx b/Makefile.85xx new file mode 100644 index 0000000..04f76a3 --- /dev/null +++ b/Makefile.85xx @@ -0,0 +1,86 @@ +MPC8540ADS_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads + +MPC8540EVAL_config \ +MPC8540EVAL_33_config \ +MPC8540EVAL_66_config \ +MPC8540EVAL_33_slave_config \ +MPC8540EVAL_66_slave_config: unconfig + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ + if [ "$(findstring _33_,$@)" ] ; then \ + echo -n "... 33 MHz PCI" ; \ + else \ + echo "#define CONFIG_SYSCLK_66M" >>$(obj)include/config.h ; \ + echo -n "... 66 MHz PCI" ; \ + fi ; \ + if [ "$(findstring _slave_,$@)" ] ; then \ + echo "#define CONFIG_PCI_SLAVE" >>$(obj)include/config.h ; \ + echo " slave" ; \ + else \ + echo " host" ; \ + fi + @$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval + +MPC8560ADS_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads + +MPC8541CDS_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds + +MPC8548CDS_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds + +MPC8555CDS_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds + +PM854_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 + +PM856_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm856 + +sbc8540_config \ +sbc8540_33_config \ +sbc8540_66_config: unconfig + @mkdir -p $(obj)include + @if [ "$(findstring _66_,$@)" ] ; then \ + echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \ + echo "... 66 MHz PCI" ; \ + else \ + >$(obj)include/config.h ; \ + echo "... 33 MHz PCI" ; \ + fi + @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 + +sbc8560_config \ +sbc8560_33_config \ +sbc8560_66_config: unconfig + @mkdir -p $(obj)include + @if [ "$(findstring _66_,$@)" ] ; then \ + echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \ + echo "... 66 MHz PCI" ; \ + else \ + >$(obj)include/config.h ; \ + echo "... 33 MHz PCI" ; \ + fi + @$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560 + +stxgp3_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 + +TQM8540_config \ +TQM8541_config \ +TQM8555_config \ +TQM8560_config: unconfig + @mkdir -p $(obj)include + @CTYPE=$(subst TQM,,$(@:_config=)); \ + >$(obj)include/config.h ; \ + echo "... TQM"$${CTYPE}; \ + echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \ + echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \ + echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \ + echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \ + echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>$(obj)include/config.h + @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx + diff --git a/Makefile.86xx b/Makefile.86xx new file mode 100644 index 0000000..cec5508 --- /dev/null +++ b/Makefile.86xx @@ -0,0 +1,3 @@ +MPC8641HPCN_config: unconfig + @./mkconfig $(@:_config=) ppc mpc86xx mpc8641hpcn + -- 1.4.4

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[U-Boot-Users] Changes to U-Boot Development Process
by Wolfgang Denk 26 Jan '07

26 Jan '07

Hello, many of you know all too well that we have problems with the development process of U-Boot. The biggest problem is that it takes much too long until new contributed code finds it's way into the public source code repository. Switching from CVS to git helped a lot on the technical side. It was especially important as it also opened the door for organizational changes, which are urgently needed. We've been discussion these issues for some time, and here is our joint proposal. "We", that is mostly Detlev Zundel, Stefan Roese, and me (Wolfgang Denk). Of course we also had input form many other sources. As this mail will propose quite a fundamental change for the U-Boot project, please allow us to introduce it with a few short reflections on the current state of affairs. Being a regular reader of this list you will be well aware that even with all the problems in the development process and some ugly areas in the U-Boot code (like the #ifdef mazes) there is one important feature: that's the quality of the U-Boot code base - being highlighted quite well by the literal absence of temporary breakages in the development code base. This alone allows for the well known "use the latest code from the repository" answer when someone enters the grounds of this project for the first time. It is well worth to reflect on this quality for a little while. Having done that we may well ask where this quality comes from? We think that anybody reading this list only for a limited time will be able to come up with the answer, namely the continuous maintenance effort of Wolfgang and his modus operandi of personally reviewing nearly each and every contribution in this multi-architecture project supporting hundreds of boards. It should be obvious how important such a level of code review is to keep U-Boot from falling into disconnected pieces - just think of the effort to keep aspects of U-Boot similar across all supported architectures. But of course even Wolfgang only has 24 hours per day, and the positive effect of this maintenance mode has shrunk continuously in comparison to the downside of the embarassingly long backlog of patches posted on this mailing list waiting to be processed, rendering new lines of development very difficult to say the least. So the time is more than ripe to change this while explicitely trying to keep the quality of the project on the high grounds that we brazenly claim for it :) Gladly there are other projects in the F/OSS community that are worth taking a peek at to snatch a hint or two on how we can tackle this task. Considering all this we propose a change in maintaining the U-Boot code base to a model similar to what is currently being done with the Linux kernel, namely we would like to establish a community of "custodian" maintainers, responsible for certain sub-systems, aspects, architectures, or board families of the U-Boot source tree. We would like to follow the Linux precedent by assembling a list of people willing to invest time and effort into this; the already existing MAINTAINERS file will serve a new function to list the individual custodians with their corresponding area of responsibilty and contact information. Each custodian will have to administrate his or her git tree to streamline transparent development and integration (pulling) into the "official" U-Boot repository. If the need should arise (for example, if a custodian doesn't have convenient means to host it himself), DENX will of course be glad to host such trees. The stated goal of this change of course is to spread the burden of maintaining U-Boot to more shoulders so we can hopefully dramatically cut down on the current lag between a patch being proposed on the mailing list and being processed - be that accepting, rejecting or openly discussing it with the community. As you must have realized by now, this cannot be done without the community participating, so what do you think of this idea? Any comments or suggestions? Of course we should be honest right upfront and state that as a custodian you would be fully responsible for "your" part of the U-Boot source tree and it is unfortunately necessary, that you are able to commit to a certain amount of time and willingness to discuss topics on the mailing list for this maintenance. Do we have an immediate line of volunteers raising in the first row? Skimming through the archives we came up with a list of people which the U-Boot project already is indebted to and probably being good candidates for custodians. Of course this list cannot and does not want to be a "credits" list of all the valuable people having contributed, so please don't attribute anything else to it as being a starting point for this new maintenance mode. Also there are multiple suggestions where ultimately of course we would like the community to decide. So with all these precautions in place, here we go: ARM architecture Richard Woodruff, Peter Pearse AVR32 architecture Haavard Skinnemoen Blackfin architecture Aubrey Li Intel IXP architecture Stefan Roese ColdFire architecture Stefan Roese Microblaze architecture Michal Simek MIPS architecture Rodolfo Giometti, Andrew Dyer MPC83xx architecture Kim Phillips MPC85xx architecture Jon Loelinger MPC86xx architecture Jon Loelinger MPC8xx architecture Wolfgang Denk NIOS(2) Scott McNutt PPC4xx architecture Stefan Roese CFI FLASH driver Tolunay Orkun NAND FLASH subsystem Ladislav Michl, Stefan Roese USB drivers Markus Klotzbücher So thanks for bearing with us through this longwinded mail that hopefully starts to pave the way to a new level of quality and extent of the U-Boot project that is only possibly through its very active community - you! Best regards, Wolfgang Denk, Stefan Roese, Detlev Zundel

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