January 2007 - U-Boot

[U-Boot-Users] [PATCH 2/2] Bit-bang implementation of 802.3ae MII-PHY framing
by Ben Warren 23 Jan '07

23 Jan '07

Hello, This implements 'IEEE 802.3ae clause 25' on the bit-bang MII-PHY driver. Signed-off-by: Ben Warren <bwarren@.qstreams.com> --- common/miiphybb.c | 121 +++++++++++++++++++++++++++++++++++++++++------------ include/miiphy.h | 4 ++ 2 files changed, 98 insertions(+), 27 deletions(-) diff --git a/common/miiphybb.c b/common/miiphybb.c index 537c15d..296da7f 100644 --- a/common/miiphybb.c +++ b/common/miiphybb.c @@ -29,19 +29,30 @@ #include <common.h> #include <ioports.h> #include <ppc_asm.tmpl> +#include <miiphy.h> #ifdef CONFIG_BITBANGMII +#define OPCODE_BIT_0 0x01 +#define OPCODE_BIT_1 0x02 +#define OPCODE_ADDRESS 0x00 +#define OPCODE_WRITE OPCODE_BIT_0 +#define OPCODE_READ OPCODE_BIT_1 +#define OPCODE_READ_FIXED (OPCODE_BIT_0 | OPCODE_BIT_1) + +#define START_BIT_0 0x10 +#define START_BIT_1 0x20 /***************************************************************************** * * Utility to send the preamble, address, and register (common to read * and write). */ -static void miiphy_pre (char read, unsigned char addr, unsigned char reg) +static void miiphy_pre(unsigned char ops, unsigned char addr, + unsigned char reg) { int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) +#if defined(MDIO_PORT) volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif @@ -62,24 +73,24 @@ #endif MIIDELAY; } - /* send the start bit (01) and the read opcode (10) or write (10) */ + /* send the start bits and the opcode */ MDC (0); - MDIO (0); + MDIO ((ops & START_BIT_1 ? 1 : 0)); MIIDELAY; MDC (1); MIIDELAY; MDC (0); - MDIO (1); + MDIO ((ops & START_BIT_0 ? 1 : 0)); MIIDELAY; MDC (1); MIIDELAY; MDC (0); - MDIO (read); + MDIO ((ops & OPCODE_BIT_1) ? 1 : 0); MIIDELAY; MDC (1); MIIDELAY; MDC (0); - MDIO (!read); + MDIO ((ops & OPCODE_BIT_0) ? 1 : 0); MIIDELAY; MDC (1); MIIDELAY; @@ -114,24 +125,14 @@ #endif } -/***************************************************************************** - * - * Read a MII PHY register. - * - * Returns: - * 0 on success - */ -int bb_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +static int _bb_miiphy_read(unsigned short *value) { short rdreg; /* register working value */ int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) +#if defined(MDIO_PORT) volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif - miiphy_pre (1, addr, reg); - /* tri-state our MDIO I/O pin so we can read */ MDC (0); MDIO_TRISTATE; @@ -181,24 +182,52 @@ #endif return 0; } +/***************************************************************************** + * + * Read a MII PHY register. + * + * Returns: + * 0 on success +*****************************************************************************/ + +int bb_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + unsigned char ops; + + ops = (miiphy_get_flags(devname) & MII_FLAG_802_3ae) ? + 0x00 : START_BIT_0; + ops |= OPCODE_READ; + miiphy_pre (ops, addr, reg); + return _bb_miiphy_read(value); +} /***************************************************************************** * - * Write a MII PHY register. + * Non-incrementing read * * Returns: * 0 on success - */ -int bb_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value) +*****************************************************************************/ + +int bb_miiphy_read_fixed(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + unsigned char ops; + + ops = (miiphy_get_flags(devname) & MII_FLAG_802_3ae) ? + 0x00 : START_BIT_0; + ops |= OPCODE_READ_FIXED; + miiphy_pre (ops, addr, reg); + return _bb_miiphy_read(value); +} + +static int _bb_miiphy_write(unsigned short value) { int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) +#if defined(MDIO_PORT) volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif - - miiphy_pre (0, addr, reg); - /* send the turnaround (10) */ MDC (0); MDIO (1); @@ -237,4 +266,42 @@ #endif return 0; } +/***************************************************************************** + * + * Write a MII PHY register. + * + * Returns: + * 0 on success +*****************************************************************************/ +int bb_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + unsigned char ops; + + ops = (miiphy_get_flags(devname) & MII_FLAG_802_3ae) ? + 0x00 : START_BIT_0; + ops |= OPCODE_WRITE; + miiphy_pre (ops, addr, reg); + return _bb_miiphy_write(value); +} + +/***************************************************************************** + * + * Perform 'address' function + * + * Returns: + * 0 on success +*****************************************************************************/ +int bb_miiphy_address (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + unsigned char ops; + + ops = (miiphy_get_flags(devname) & MII_FLAG_802_3ae) ? + 0x00 : START_BIT_0; + ops |= OPCODE_ADDRESS; + miiphy_pre (ops, addr, reg); + return _bb_miiphy_write(value); +} + #endif /* CONFIG_BITBANGMII */ diff --git a/include/miiphy.h b/include/miiphy.h index 9e7e35f..86ffbb5 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -98,6 +98,10 @@ int bb_miiphy_read (char *devname, unsig unsigned char reg, unsigned short *value); int bb_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value); +int bb_miiphy_address (char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +int bb_miiphy_read_fixed (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); /* phy seed setup */ #define AUTO 99 -- 1.4.1

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[U-Boot-Users] builtin OF tree dtb gone
by Joakim Tjernlund 22 Jan '07

22 Jan '07

While trying out the latest u-boot from my board I noticed that support for using a prebuilt OF tree compiled int u-boot is gone. The oftree_dtb symbol is gone and I can't find a replacement. Why was it removed and is there a replacement? If there isn't a replacement I request that one is added. Jocke

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[U-Boot-Users] Running the example : sched.c
by Bilahari Akkiraju 22 Jan '07

22 Jan '07

Hello, I am trying to run the example sched.bin on the 8343 ppc evaluation board from freescale. (Source is in /u-boot-1.1.4/examples/sched.c.) I dont see what I expect to see. When I do the following => tftp 0x40000 /home/bill/sched.bin => go 0x40004 I get ## Starting application at 0x00040004... ## Application terminated, rc = 0x1 I want to see the output of this example so that I can understand better about on how the scheduler works. Can anyone run or Has anybody previously, ran this example on board with a powerpc processor ?. If so please can I see what the output looks like. Thanks Bilahari

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[U-Boot-Users] Document needed
by mahendra varman 22 Jan '07

22 Jan '07

Hi List Members Can you help me to find any document/tutorial explaining "HOW TO PORT U_BOOT FOR A NEW BOARD ?" ? and "How to port Linux for a new Board ?" "similarities and dissimilarities between u-boot and Linux" Any document/tutorial is welcome Thanks in advance R.Mahendran

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[U-Boot-Users] Running U-boot in cache area.
by sathesh babu 22 Jan '07

22 Jan '07

Hi, I am tring to run U-boot on MIPS 24KE processor. I have done MIPS 24KE cache initilization and configured it for write through mode in the start.S file. If I specify SDRAM start address as uncached area ( start with 0xa0000000), u-boot boots up and able to get the u-boot prompt. It I try SDRAM start address as cached area ( Start with 0x80000000), the u-boot comes up to relocation function and hangs. Could you please tell me what could be the problem. Did i mss any thing?. I see the same behaviour with write back mode also. Should i call any cache invalidation ( doing this as part of cache initilization in the start.S) or flush functions before calling relocation(). I am enabling primary cache only and no secondary cache. Thanks in advance. Regards. Sathesh --------------------------------- Heres a new way to find what you're looking for - Yahoo! Answers

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[U-Boot-Users] [DNX#2007012242000017] now popularl
by OTRS Notification Master 22 Jan '07

22 Jan '07

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2007012242000017] was created: <snip> > Hi, > > When you need it now VIAxxGRA ( from $3, 35 ) > When you need it later CIAxxLIS ( from $3, 35 ) > > http://www.fod*rx.com > ( remove "*" from the domain name ) > > ---- > Ignore it, Hermione said in a dignified voice, holding her head in the > air and stalking past the sniggering Slytherin girls as though she > couldnt hear them. Just ignore it, Harry. </snip> Your U-Boot support team

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[U-Boot-Users] [DNX#2007012242000017] now popularl
by U-Boot patch tracking system 22 Jan '07

22 Jan '07

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2007012242000017]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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[U-Boot-Users] u-boot delay on OMAP2430 SDP
by sandeep prabhu 22 Jan '07

22 Jan '07

Hi, I am using the "u-boot_16.3.tar.gz" ( u-boot version 1.1.4 ) sources downloaded from the "linux.omap.com" site, for booting the OMAP2430 SDP board from NOR flash. I built the sources for booting from NOR flash and burn it using the CSST tool onto the OMAP2430 SDP board. It takes around 2 to 4 minutes for u-boot command prompt. I am also not able to boot the linux kernel with this version. I have tried to track exactly where is it getting delayed, as it hangs for 2-3 minutes in function "dram_init" in file "board/omap2430sdp/omap2430sdp.c". But it doesnt hang at the same code everytime I test, the problem is not consistent. I have tried with Icache both enabling and disabling, but it did not make any difference. Could anyone give some pointers about what could be the issue ? Thanks in advance, -- Warm Regards, Sandeep

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Re: [U-Boot-Users] RFC: miiphy changes
by Ben Warren 21 Jan '07

21 Jan '07

--- Andy Fleming <afleming(a)gmail.com> wrote: > > Sorry, I asked my question a little unclearly. > > Right now, my board's code has something like: > > miiphy_read_reg(TSEC1_NAME, addr, reg); > > I understand under your suggested system that it > would become: > > miiphy_read_reg(tsec1_ptr, addr, reg); > > What I don't understand is how the board code is > supposed to get > access to tsec1_ptr. Is there already a global > pointer to the mii_dev > list that anyone can scan through? > I don't have access to the code right now, so forgive me if some of the names aren't quite right. Currently, the list is built by a series of miiphy_register("name", read_fn(), write_fn()) calls in board (or driver, I guess) code. I'll change this to: miiphy_register(miidev) which will also be called from board (or driver) code. So your board will have all the structs already. Do you think this makes sense? Ben

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[U-Boot-Users] U-Boot wrong cpu frequency calculation when setting PLPRCR directly
by Antonio Di Bacco 20 Jan '07

20 Jan '07

Hi all, I setup the cpu frequency of a Freescale MPC880 directly providing a value for the PLPRCR register. When the u-boot (1.2.0 and previous) starts, in file speed.c it makes a calculation to display the CPU frequency based on fields in PLPRCR. Working with integers it makes an approximation that leads to a wrong cpu frequency in my case 130 Mhz instead of 132 Mhz). As a consequence my clock was wrong gaining 20 minutes per day. It is easy to patch the problem. If someone is interested I'll give him the patch. Bye, Antonio.

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