July 2006 - U-Boot

[U-Boot-Users] [patch 1/2] add-additional-error-messages-to-flash-driver-on-trab-board
by Martin Krause 07 Aug '06

07 Aug '06

Add additional error messages to flash driver on TRAB board (for erase errors and timeout errors) Patch by Martin Krause, 14 Feb 2006 Signed-off-by: Martin Krause <martin.kraus(a)tqs.de> CHANGELOG: * Add additional error messages to flash driver on TRAB board (for erase errors and timeout errors) Patch by Martin Krause, 14 Feb 2006

2 2

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support
by Zang Roy-r61911 07 Aug '06

07 Aug '06

Mpc7448hpc2 board flash driver support. Signed-off-by: Alexandre Bounine <alexandreb(a)tundra.com> Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- board/mpc7448hpc2/cfi_flash.c | 1273 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 1273 insertions(+), 0 deletions(-) diff --git a/board/mpc7448hpc2/cfi_flash.c b/board/mpc7448hpc2/cfi_flash.c new file mode 100644 index 0000000..c901abf --- /dev/null +++ b/board/mpc7448hpc2/cfi_flash.c @@ -0,0 +1,1273 @@ +/* + * (C) Copyright 2002-2004 + * Brad Kemp, Seranoa Networks, Brad.Kemp(a)seranoa.com + * + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen <yuli(a)arabellasw.com> + * Modified to work with AMD flashes + * + * Copyright (C) 2004 + * Ed Okerson + * Modified to work with little-endian systems. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * History + * 01/20/2004 - combined variants of original driver. + * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay) + * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud) + * 01/27/2004 - Little endian support Ed Okerson + * + * Tested Architectures + * Port Width Chip Width # of banks Flash Chip Board + * 32 16 1 28F128J3 seranoa/eagle + * 64 16 1 28F128J3 seranoa/falcon + * + */ + +/* The DEBUG define must be before common to enable debugging */ +/* #define DEBUG */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/byteorder.h> +#include <linux/byteorder/swab.h> +#ifdef CFG_HPC2_FLASH_CFI_DRIVER + +/* + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation and AMD 29F016D. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query + * Table (ALT) to determine if protection is available + * + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#ifndef CFG_FLASH_BANKS_LIST +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define AMD_CMD_RESET 0xF0 +#define AMD_CMD_WRITE 0xA0 +#define AMD_CMD_ERASE_START 0x80 +#define AMD_CMD_ERASE_SECTOR 0x30 +#define AMD_CMD_UNLOCK_START 0xAA +#define AMD_CMD_UNLOCK_ACK 0x55 + +#define AMD_STATUS_TOGGLE 0x40 +#define AMD_STATUS_ERROR 0x20 +#define AMD_ADDR_ERASE_START 0x555 +#define AMD_ADDR_START 0x555 +#define AMD_ADDR_ACK 0x2AA + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_PRIMARY_VENDOR 0x13 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + +#define FLASH_MAN_CFI 0x01000000 + +#define CFI_CMDSET_NONE 0 +#define CFI_CMDSET_INTEL_EXTENDED 1 +#define CFI_CMDSET_AMD_STANDARD 2 +#define CFI_CMDSET_INTEL_STANDARD 3 +#define CFI_CMDSET_AMD_EXTENDED 4 +#define CFI_CMDSET_MITSU_STANDARD 256 +#define CFI_CMDSET_MITSU_EXTENDED 257 +#define CFI_CMDSET_SST 258 + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; + unsigned long long ll; +} cfiword_t; + +typedef union { + volatile unsigned char *cp; + volatile unsigned short *wp; + volatile unsigned long *lp; + volatile unsigned long long *llp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*--------------------------------------------------------------------- -- + * Functions + */ + +typedef unsigned long flash_sect_t; + +static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf); +static void flash_write_cmd(flash_info_t * info, flash_sect_t sect, uint offset, + uchar cmd); +static void flash_unlock_seq(flash_info_t * info, flash_sect_t sect); +static int flash_isequal(flash_info_t * info, flash_sect_t sect, uint offset, + uchar cmd); +static int flash_isset(flash_info_t * info, flash_sect_t sect, uint offset, + uchar cmd); +static int flash_toggle(flash_info_t * info, flash_sect_t sect, uint offset, + uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size(ulong base, int banknum); +static int flash_write_cfiword(flash_info_t * info, ulong dest, + cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, + int len); +#endif + +/*--------------------------------------------------------------------- -- + * create an address based on the offset and the port width + */ +inline uchar *flash_make_addr(flash_info_t * info, flash_sect_t sect, + uint offset) +{ + return ((uchar *) (info->start[sect] + (offset * info->portwidth))); +} + +#ifdef DEBUG +/*--------------------------------------------------------------------- -- + * Debug support + */ +void print_longlong(char *str, unsigned long long data) +{ + int i; + char *cp; + + cp = (unsigned char *)&data; + for (i = 0; i < 8; i++) + sprintf(&str[i * 2], "%2.2x", *cp++); +} +static void flash_printqry(flash_info_t * info, flash_sect_t sect) +{ + cfiptr_t cptr; + int x, y; + + for (x = 0; x < 0x40; x += 16 / info->portwidth) { + cptr.cp = + flash_make_addr(info, sect, x + FLASH_OFFSET_CFI_RESP); + debug("%p : ", cptr.cp); + for (y = 0; y < 16; y++) { + debug("%2.2x ", cptr.cp[y]); + } + debug(" "); + for (y = 0; y < 16; y++) { + if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) { + debug("%c", cptr.cp[y]); + } else { + debug("."); + } + } + debug("\n"); + } +} +#endif + +/*--------------------------------------------------------------------- -- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uint offset) +{ + uchar *cp; + + cp = flash_make_addr(info, 0, offset); +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_MPC7448HPC2) + return (cp[0]); +#else + return (cp[info->portwidth - 1]); +#endif +} + +/*--------------------------------------------------------------------- -- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, flash_sect_t sect, uint offset) +{ + uchar *addr; + ushort retval; + +#ifdef DEBUG + int x; +#endif + addr = flash_make_addr(info, sect, offset); + +#ifdef DEBUG + debug("ushort addr is at %p info->portwidth = %d\n", addr, + info->portwidth); + for (x = 0; x < 2 * info->portwidth; x++) { + debug("addr[%x] = 0x%x\n", x, addr[x]); + } +#endif +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_MPC7448HPC2) + retval = ((addr[(info->portwidth)] << 8) | addr[0]); +#else + retval = ((addr[(2 * info->portwidth) - 1] << 8) | + addr[info->portwidth - 1]); +#endif + + debug("retval = 0x%x\n", retval); + return retval; +} + +/*--------------------------------------------------------------------- -- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, flash_sect_t sect, uint offset) +{ + uchar *addr; + ulong retval; + +#ifdef DEBUG + int x; +#endif + addr = flash_make_addr(info, sect, offset); + +#ifdef DEBUG + debug("long addr is at %p info->portwidth = %d\n", addr, + info->portwidth); + for (x = 0; x < 4 * info->portwidth; x++) { + debug("addr[%x] = 0x%x\n", x, addr[x]); + } +#endif +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_MPC7448HPC2) + retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) | + (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8); +#else + retval = (addr[(2 * info->portwidth) - 1] << 24) | + (addr[(info->portwidth) - 1] << 16) | + (addr[(4 * info->portwidth) - 1] << 8) | + addr[(3 * info->portwidth) - 1]; +#endif + return retval; +} + +/*--------------------------------------------------------------------- -- + */ +unsigned long flash_init(void) +{ + unsigned long size = 0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + size += flash_info[i].size = flash_get_size(bank_base[i], i); + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + debug + ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, flash_info[i].size, flash_info[i].size << 20); + } + } + + /* Monitor protection ON by default */ +#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, &flash_info[0]); +#endif + + return (size); +} + +/*--------------------------------------------------------------------- -- + */ +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + flash_sect_t sect; + + if (info->flash_id != FLASH_MAN_CFI) { + puts("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + puts("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + putc('\n'); + } + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + flash_write_cmd(info, sect, 0, + FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, + FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, + FLASH_CMD_ERASE_CONFIRM); + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + flash_unlock_seq(info, sect); + flash_write_cmd(info, sect, + AMD_ADDR_ERASE_START, + AMD_CMD_ERASE_START); + flash_unlock_seq(info, sect); + flash_write_cmd(info, sect, 0, + AMD_CMD_ERASE_SECTOR); + break; + default: + debug("Unkown flash vendor %d\n", info->vendor); + break; + } + + if (flash_full_status_check + (info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + putc('.'); + } + } + puts(" done\n"); + return rcode; +} + +/*--------------------------------------------------------------------- -- + */ +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + puts("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3), (info->chipwidth << 3)); + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf + (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, + info->buffer_size); + + puts(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + int k; + int size; + int erased; + volatile unsigned long *flash; + + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf("\n"); + /* print empty and read-only info */ + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); +#endif + } + putc('\n'); + return; +} + +/*--------------------------------------------------------------------- -- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + int buffered_size; +#endif + /* get lower aligned address */ + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if ((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for (i = 0; i < aln; ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *) cp)); + + for (; (i < info->portwidth) && (cnt > 0); i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *) cp)); + if ((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } + + /* handle the aligned part */ +#ifdef CFG_FLASH_USE_BUFFER_WRITE + buffered_size = (info->portwidth / info->chipwidth); + buffered_size *= info->buffer_size; + while (cnt >= info->portwidth) { + i = buffered_size > cnt ? cnt : buffered_size; + if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -= i; + } +#else + while (cnt >= info->portwidth) { + cword.l = 0; + for (i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if ((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; i < info->portwidth; ++i, ++cp) { + flash_add_byte(info, &cword, (*(uchar *) cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*--------------------------------------------------------------------- -- + */ +#ifdef CFG_FLASH_PROTECTION + +int flash_real_protect(flash_info_t * info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if (prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if ((retcode = + flash_full_status_check(info, sector, info->erase_blk_tout, + prot ? "protect" : "unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if (prot == 0) { + flash_sect_t i; + + for (i = 0; i < info->sector_count; i++) { + if (info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + return retcode; +} + +/*--------------------------------------------------------------------- -- + * flash_read_user_serial - read the OneTimeProgramming cells + */ +void flash_read_user_serial(flash_info_t * info, void *buffer, int offset, + int len) +{ + uchar *src; + uchar *dst; + + dst = buffer; + src = flash_make_addr(info, 0, FLASH_OFFSET_USER_PROTECTION); + flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); + memcpy(dst, src + offset, len); + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); +} + +/* + * flash_read_factory_serial - read the device Id from the protection area + */ +void flash_read_factory_serial(flash_info_t * info, void *buffer, int offset, + int len) +{ + uchar *src; + + src = flash_make_addr(info, 0, FLASH_OFFSET_INTEL_PROTECTION); + flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); + memcpy(buffer, src + offset, len); + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); +} + +#endif /* CFG_FLASH_PROTECTION */ + +/* + * flash_is_busy - check to see if the flash is busy + * This routine checks the status of the chip and returns true if the chip is busy + */ +static int flash_is_busy(flash_info_t * info, flash_sect_t sect) +{ + int retval; + + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE); + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + retval = flash_toggle(info, sect, 0, AMD_STATUS_TOGGLE); + break; + default: + retval = 0; + } + debug("flash_is_busy: %d\n", retval); + return retval; +} + +/*--------------------------------------------------------------------- -- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer(0); + while (flash_is_busy(info, sector)) { + if (get_timer(start) > info->erase_blk_tout * CFG_HZ) { + printf("Flash %s timeout at address %lx data %lx\n", + prompt, info->start[sector], + flash_read_long(info, sector, 0)); + flash_write_cmd(info, sector, 0, info->cmd_reset); + return ERR_TIMOUT; + } + } + return ERR_OK; +} + +/*--------------------------------------------------------------------- -- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt) +{ + int retcode; + + retcode = flash_status_check(info, sector, tout, prompt); + switch (info->vendor) { + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_STANDARD: + if ((retcode != ERR_OK) + && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt, + info->start[sector]); + if (flash_isset + (info, sector, 0, + FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { + puts("Command Sequence Error.\n"); + } else + if (flash_isset + (info, sector, 0, FLASH_STATUS_ECLBS)) { + puts("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else + if (flash_isset + (info, sector, 0, FLASH_STATUS_PSLBS)) { + puts("Locking Error\n"); + } + if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) { + puts("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + puts("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + break; + default: + break; + } + return retcode; +} + +/*--------------------------------------------------------------------- -- + */ +static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c) +{ +#if defined(__LITTLE_ENDIAN) + unsigned short w; + unsigned int l; + unsigned long long ll; +#endif + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: +#if defined(__LITTLE_ENDIAN) + w = c; + w <<= 8; + cword->w = (cword->w >> 8) | w; +#else + cword->w = (cword->w << 8) | c; +#endif + break; + case FLASH_CFI_32BIT: +#if defined(__LITTLE_ENDIAN) + l = c; + l <<= 24; + cword->l = (cword->l >> 8) | l; +#else + cword->l = (cword->l << 8) | c; +#endif + break; + case FLASH_CFI_64BIT: +#if defined(__LITTLE_ENDIAN) + ll = c; + ll <<= 56; + cword->ll = (cword->ll >> 8) | ll; +#else + cword->ll = (cword->ll << 8) | c; +#endif + break; + } +} + +/*--------------------------------------------------------------------- -- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf) +{ + int i; + +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_MPC7448HPC2) + ushort stmpw; + uint stmpi; + uint stmpi2; +#endif + uchar *cp = (uchar *) cmdbuf; + + for (i = 0; i < info->portwidth; i++) + *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd; +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_MPC7448HPC2) + switch (info->portwidth) { + case FLASH_CFI_8BIT: + break; + case FLASH_CFI_16BIT: + stmpw = *(ushort *) cmdbuf; + *(ushort *) cmdbuf = __swab16(stmpw); + break; + case FLASH_CFI_32BIT: + stmpi = *(uint *) cmdbuf; + *(uint *) cmdbuf = __swab32(stmpi); + break; + case FLASH_CFI_64BIT: + cp = (uchar *) cmdbuf; + stmpi = *(uint *) cp; + cp += 4; + stmpi2 = *(uint *) cp; + cp -= 4; + *(uint *) cp = __swab32(stmpi2); + cp += 4; + *(uint *) cp = __swab32(stmpi); + break; + default: + puts("WARNING: flash_make_cmd: unsuppported LittleEndian mode\n"); + break; + } +#endif +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, flash_sect_t sect, uint offset, + uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + debug("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd, + cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp, + cmd, cword.w, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + debug("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp, + cmd, cword.l, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + *addr.lp = cword.l; + break; + case FLASH_CFI_64BIT: +#ifdef DEBUG + { + char str[20]; + + print_longlong(str, cword.ll); + + debug("fwrite addr %p cmd %x %s 64 bit x %d bit\n", + addr.llp, cmd, str, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + } +#endif + *addr.llp = cword.ll; + break; + } +} + +static void flash_unlock_seq(flash_info_t * info, flash_sect_t sect) +{ + flash_write_cmd(info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START); + flash_write_cmd(info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK); +} + +/*--------------------------------------------------------------------- -- + */ +static int flash_isequal(flash_info_t * info, flash_sect_t sect, uint offset, + uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + + debug("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + debug("is= %x %x\n", cptr.cp[0], cword.c); + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + debug("is= %4.4x %4.4x\n", cptr.wp[0], cword.w); + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + debug("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l); + retval = (cptr.lp[0] == cword.l); + break; + case FLASH_CFI_64BIT: +#ifdef DEBUG + { + char str1[20]; + char str2[20]; + + print_longlong(str1, cptr.llp[0]); + print_longlong(str2, cword.ll); + debug("is= %s %s\n", str1, str2); + } +#endif + retval = (cptr.llp[0] == cword.ll); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*--------------------------------------------------------------------- -- + */ +static int flash_isset(flash_info_t * info, flash_sect_t sect, uint offset, + uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + case FLASH_CFI_64BIT: + retval = ((cptr.llp[0] & cword.ll) == cword.ll); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*--------------------------------------------------------------------- -- + */ +static int flash_toggle(flash_info_t * info, flash_sect_t sect, uint offset, + uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c)); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w)); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l)); + break; + case FLASH_CFI_64BIT: + retval = ((cptr.llp[0] & cword.ll) != (cptr.llp[0] & cword.ll)); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*--------------------------------------------------------------------- -- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +*/ +static int flash_detect_cfi(flash_info_t * info) +{ + debug("flash detect cfi\n"); + + for (info->portwidth = FLASH_CFI_8BIT; + info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { + for (info->chipwidth = FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, + FLASH_CMD_CFI); + if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') + && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, + 'R') + && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, + 'Y')) { + info->interface = + flash_read_ushort(info, 0, + FLASH_OFFSET_INTERFACE); + debug("device interface is %d\n", + info->interface); + debug("found port %d chip %d ", info->portwidth, + info->chipwidth); + debug("port %d bits chip %d bits\n", + info->portwidth << CFI_FLASH_SHIFT_WIDTH, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + return 1; + } + } + } + debug("not found\n"); + return 0; +} + +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size(ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + int i, j; + flash_sect_t sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if (flash_detect_cfi(info)) { + info->vendor = + flash_read_ushort(info, 0, FLASH_OFFSET_PRIMARY_VENDOR); +#ifdef DEBUG + flash_printqry(info, 0); +#endif + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + default: + info->cmd_reset = FLASH_CMD_RESET; + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + info->cmd_reset = AMD_CMD_RESET; + break; + } + + debug("manufacturer is %d\n", info->vendor); + size_ratio = info->portwidth / info->chipwidth; + /* if the chip is x8/x16 reduce the ratio by half */ + if ((info->interface == FLASH_CFI_X8X16) + && (info->chipwidth == FLASH_CFI_BY8)) { + size_ratio >>= 1; + } + num_erase_regions = + flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); + debug("size_ratio %d port %d bits chip %d bits\n", size_ratio, + info->portwidth << CFI_FLASH_SHIFT_WIDTH, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + debug("found %d erase regions\n", num_erase_regions); + sect_cnt = 0; + sector = base; + for (i = 0; i < num_erase_regions; i++) { + if (i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long(info, 0, + FLASH_OFFSET_ERASE_REGIONS + + i * 4); + erase_region_size = + (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) + 1; + debug + ("erase_region_count = %d erase_region_size = %d\n", + erase_region_count, erase_region_size); + for (j = 0; j < erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = + flash_isset(info, sect_cnt, + FLASH_OFFSET_PROTECT, + FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = + (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * + size_ratio; + info->buffer_size = + (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = + (tmp * + (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = + (tmp * + (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = + (tmp * + (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) / + 1000; + info->flash_id = FLASH_MAN_CFI; + if ((info->interface == FLASH_CFI_X8X16) + && (info->chipwidth == FLASH_CFI_BY8)) { + info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */ + } + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + } + + return (info->size); +} + +/*--------------------------------------------------------------------- -- + */ +static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *) dest; + + /* Check if Flash is (sufficiently) erased */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + case FLASH_CFI_64BIT: + flag = ((cptr.lp[0] & cword.ll) == cword.ll); + break; + default: + return 2; + } + if (!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + switch (info->vendor) { + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_STANDARD: + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + break; + case CFI_CMDSET_AMD_EXTENDED: + case CFI_CMDSET_AMD_STANDARD: + flash_unlock_seq(info, 0); + flash_write_cmd(info, 0, AMD_ADDR_START, AMD_CMD_WRITE); + break; + } + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + case FLASH_CFI_64BIT: + cptr.llp[0] = cword.ll; + break; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static flash_sect_t find_sector(flash_info_t * info, ulong addr) +{ + flash_sect_t sector; + + for (sector = info->sector_count - 1; sector >= 0; sector--) { + if (addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, + int len) +{ + flash_sect_t sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + /* buffered writes in the AMD chip set is not supported yet */ + if ((info->vendor == CFI_CMDSET_AMD_STANDARD) || + (info->vendor == CFI_CMDSET_AMD_EXTENDED)) + return ERR_INVAL; + + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if ((retcode = + flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + /* reduce the number of loops by the width of the port */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + case FLASH_CFI_64BIT: + cnt = len >> 3; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + case FLASH_CFI_64BIT: + *dst.llp++ = *src.llp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, + FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = + flash_full_status_check(info, sector, + info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ +#endif /* CFG_FLASH_CFI */ -- 1.4.0

4 19

[U-Boot-Users] u-boot link fails after removing -Os compilation option.
by Leonid 04 Aug '06

04 Aug '06

Hi: I'm using u-boot v1.1.4. I wanted to remove any optimization to make debug simpler and the only optimization I have found was "-Os" option in the config.mk file; below is the change I've done: 112c112 < OPTFLAGS= -Os #-fomit-frame-pointer --- > OPTFLAGS= #-Os #-fomit-frame-pointer Unfortunately after that change link is always failing - certain inline functions (not all) somehow cannot be resolved: cpu/ppc4xx/libppc4xx.a(405gp_pci.o)(.text+0x8c): In function `pci_440_init': /home/leonid/pd/ppc/uboot/u-boot-1.1.4/cpu/ppc4xx/405gp_pci.c:467: undefined reference to `pci_set_region' cpu/ppc4xx/libppc4xx.a(405gp_pci.o)(.text+0xc8):/home/leonid/pd/ppc/uboo t/u-boot-1.1.4/cpu/ppc4xx/405gp_pci.c:473: undefined reference to `pci_set_region' drivers/libdrivers.a(pci_indirect.o)(.text+0x64): In function `indirect_read_config_byte': /home/leonid/pd/ppc/uboot/u-boot-1.1.4/drivers/pci_indirect.c:94: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x8c):/home/leonid/pd/ppc/ubo ot/u-boot-1.1.4/drivers/pci_indirect.c:94: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0xac):/home/leonid/pd/ppc/ubo ot/u-boot-1.1.4/drivers/pci_indirect.c:94: undefined reference to `in_8' drivers/libdrivers.a(pci_indirect.o)(.text+0x144): In function `indirect_read_config_word': /home/leonid/pd/ppc/uboot/u-boot-1.1.4/drivers/pci_indirect.c:95: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x16c):/home/leonid/pd/ppc/ub oot/u-boot-1.1.4/drivers/pci_indirect.c:95: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x18c):/home/leonid/pd/ppc/ub oot/u-boot-1.1.4/drivers/pci_indirect.c:95: undefined reference to `in_le16' drivers/libdrivers.a(pci_indirect.o)(.text+0x21c): In function `indirect_read_config_dword': /home/leonid/pd/ppc/uboot/u-boot-1.1.4/drivers/pci_indirect.c:96: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x244):/home/leonid/pd/ppc/ub oot/u-boot-1.1.4/drivers/pci_indirect.c:96: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x250):/home/leonid/pd/ppc/ub oot/u-boot-1.1.4/drivers/pci_indirect.c:96: undefined reference to `in_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x2e0): In function `indirect_write_config_byte': /home/leonid/pd/ppc/uboot/u-boot-1.1.4/drivers/pci_indirect.c:102: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x308):/home/leonid/pd/ppc/ub oot/u-boot-1.1.4/drivers/pci_indirect.c:102: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x330):/home/leonid/pd/ppc/ub oot/u-boot-1.1.4/drivers/pci_indirect.c:102: undefined reference to `out_8' drivers/libdrivers.a(pci_indirect.o)(.text+0x3b4): In function `indirect_write_config_word': /home/leonid/pd/ppc/uboot/u-boot-1.1.4/drivers/pci_indirect.c:103: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x3dc):/home/leonid/pd/ppc/ub oot/u-boot-1.1.4/drivers/pci_indirect.c:103: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x404):/home/leonid/pd/ppc/ub oot/u-boot-1.1.4/drivers/pci_indirect.c:103: undefined reference to `out_le16' drivers/libdrivers.a(pci_indirect.o)(.text+0x484): In function `indirect_write_config_dword': /home/leonid/pd/ppc/uboot/u-boot-1.1.4/drivers/pci_indirect.c:104: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x4ac):/home/leonid/pd/ppc/ub oot/u-boot-1.1.4/drivers/pci_indirect.c:104: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x4bc):/home/leonid/pd/ppc/ub oot/u-boot-1.1.4/drivers/pci_indirect.c:104: undefined reference to `out_le32' drivers/libdrivers.a(pci_indirect.o)(.text+0x534): In function `pci_setup_indirect': /home/leonid/pd/ppc/uboot/u-boot-1.1.4/drivers/pci_indirect.c:109: undefined reference to `pci_set_ops' make: *** [u-boot] Error 1 What can be a problem? Only PCI part looks not happy... Thanks, Leonid.

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[U-Boot-Users] 440SP DDR2 Issue
by Jeff Stevens 02 Aug '06

02 Aug '06

I have a custom board I am trying to bring up that is a pretty close architecture to the Luan2 board. I have an unregistered 2GB DDR2 module in the DIMM slot, and it works fine using the BDI2000. However, using the same DDR2 configuration in U-Boot doesn't work. It boots up until the point it transfers over to memory. I have enabled the memory test and it fails at the first address. I have verified all of the memory configuration registers, and all seem to be set correctly. I know there is something in the configuration I am missing, but I can't seem to figure it out. Please help. I would greatly appreciate it. Thanks, Jeff Stevens __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

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[U-Boot-Users] UBOOT - Arm Floating Point
by Carlos Coelho 01 Aug '06

01 Aug '06

Hi, I am doing the following commands: make mrproper OK make at91rm9200dk_config OK make u-boot and I=B4ve got the following error message: ... -Map u-boot.map -o u-boot arm-linux-ld: ERROR: = /usr/local/arm/3.4.1/lib/gcc/arm-linux/3.4.1/libgcc.a(_divsi3.oS) uses = hardware FP, whereas u-boot uses software FP The "cpu/arm920t/config.mk" file has the "-msoft-float" option set, but = the arm-linux-gcc seems to be compiling everything for a hardware FP. Does someone had this problem before?=20 Regards, Carlos

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Re: [U-Boot-Users] UBOOT - Arm Floating Point
by Woodruff, Richard 01 Aug '06

01 Aug '06

> Fix your toolchain. > > [BTW: have you ever seen an ARM processor with FPU?] They are about. The ARM1136/ARM1176/CortexA8 cores (ARMv6 & ARMv7) all can have FPU via VFP. You can find this in several TI-OMAP chips. I think you can also get an ARMv5 core with VFP. Regards, Richard W.

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Re: [U-Boot-Users] [PATCH] Fix control-c handing inCONFIG_CMDLINE_EDITING
by Jeff Mann 31 Jul '06

31 Jul '06

> + return rc < 0 ? rc : len; Use of the conditional assignment operator is generally considered bad practice because it affects readability.

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[U-Boot-Users] TFTP timeout
by Philippe Villet 31 Jul '06

31 Jul '06

Browsing the mailing list i saw that some people met my problem but i can' find the answer. Here is my problem : TFTP transfer with u-boot (1.1.4) sometimes ended with timeout (TTT) and then a MAL error. I'am using a 440EP, with 2 PHY from Micrel (KSZ8001) in SMII mode. Under linux (ELDK 4.0, kernel 2.6.16) we have no problem (nfs, ftp, tftp work well). We used a Etheral to sniff and found out that u-boot ack one datapackage but when the next datapackage arrives u-boot doesn't seem to hear it. Instead u-boot timesout listening and sends another ack on the previous datapackage. The tftp server then retransmits the last datapackage again witch u-boot doesn't hear, u-boot times out and send another ack on the previous datapackage, and we are stuck in this loop. A previous discussion "[U-Boot-Users] TFTP times out?" ended with a bad timer implementation. Could someone help me ? Thanks - Philippe.

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[U-Boot-Users] hi, everyone
by zhenhua zou 31 Jul '06

31 Jul '06

Hi, everyone I am porting U-Boot-1.1.4 to my board based on s3c44b0x and using /board/dave/B2 as a referrence. My cross compiler is (DENX ELDK 3.1 3.3.3-8). The variable ----base_address in the file /common/cmd_mem.c is not correctly initialized. It ought to be zero after the initialization. But when I type "base" command, it shows 0xFFFFFFFF instead of 0x00000000. Is there anybody who has such problems before? Could you give me some hints about it? Another question is about the function malloc. Sometimes when I downloaded the modified code, in the function env_relocate()(/common/env_common.c) the line "env_ptr = (env_t *)malloc (CFG_ENV_SIZE);" returned NULL. The modified code was about the ethernet and TFTP. And I think it is irrelevant with the malloc. I couldn't figure out why it happens. Any hints would be appreciated. By the way I have checked the change log in the git repository since 1.1.4. Most of the changes about B2 board are the supporting of GCC 4.x and updating of CFI_FLASH. Is it necessary to update it to the top tree of the git repository? And the cross compiler? Thanks in advance. -- Best regards Zou Zhenhua

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Re: [U-Boot-Users] TFTP timeout
by Philippe Villet 31 Jul '06

31 Jul '06

Stefan, >What did you define "CFG_RX_ETH_BUFFER" in your board config file to? Did you >try to enable the debug output in the 4xx ethernet driver "INFO_4XX_ENET"? <Are you using top-of-git UBoot version? No i'am using the plain 1.1.4 UBoot version (customized for our board). I try several values for "CFG_RX_ETH_BUFFER" : 32,31,16 and 8. It does not change anything. Here is a trace with debug output. I've also added a trace in the eneInt routine to trace interrupts (UIC0MSR and UIC1MSR contents. When it works, i've got UIC0MSR : 0x100000, UIC1MSR : 0x0 (=> MRE interrupt) and just before the MAL error UIC0MSR : 0x2, UIC1MSR : 0xa0000000 (=> MS + MRDE innterrupts). Any idea? Philippe. [BASE6000]> tftpboot 4000000 pMulti6000 tftpboot 4000000 pMulti6000 About preceeding transfer (eth0): - Sent packet number 2890 - Received packet number 2898 - Handled packet number 2898 ENET Speed is 100 Mbps - FULL duplex connection Using ppc_4xx_eth0 device TFTP from server 10.33.17.251; our IP address is 10.33.17.162 Filename 'pMulti6000'. Load address: 0x4000000 Loading: send option "timeout 5" Got OACK: timeout 5 ################################################################# ... ################################################################# ################################################################# ################################################################# ########################################### MAL error occured.... ISR = c0100010 UIC = = 2 MAL_DEF = e0100000 MAL_ERR= e0000000 About preceeding transfer (eth0): - Sent packet number 30974 - Received packet number 31059 - Handled packet number 31059 MAL error occured.... ISR = c0100010 UIC = = 2 MAL_DEF = e0100000 MAL_ERR= e0000000 About preceeding transfer (eth0): - Sent packet number 0 - Received packet number 0 - Handled packet number 0 T T MAL error occured.... ISR = c0100010 UIC = = 2 MAL_DEF = e0100000 MAL_ERR= e0000000 About preceeding transfer (eth0): - Sent packet number 2 - Received packet number 0 - Handled packet number 0 MAL error occured.... ISR = c0100010 UIC = = 2 MAL_DEF = e0100000 MAL_ERR= e0000000 About preceeding transfer (eth0): - Sent packet number 0 - Received packet number 0 - Handled packet number 0 T MAL error occured.... ISR = c0100010 UIC = = 2 MAL_DEF = e0100000 MAL_ERR= e0000000 About preceeding transfer (eth0): - Sent packet number 1 - Received packet number 0 - Handled packet number 0 T MAL error occured.... ISR = c0100010 UIC = = 2 MAL_DEF = e0100000 MAL_ERR= e0000000 About preceeding transfer (eth0): - Sent packet number 1 - Received packet number 0 - Handled packet number 0 T

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