April 2006 - U-Boot

[U-Boot-Users] patch: PK1C20 for Nios-II 5.0
by Scott McNutt 10 Jun '06

10 Jun '06

Update PK1C20 board for Nios-II 5.0 -Update base addresses for standard configuration -Eliminate use of CACHE_BYPASS in board code Regards, --Scott diff -Naurb u-boot-current/CHANGELOG u-boot-new/CHANGELOG --- u-boot-current/CHANGELOG 2005-08-11 10:31:52.000000000 -0400 +++ u-boot-new/CHANGELOG 2005-08-11 10:38:07.000000000 -0400 @@ -26,6 +26,11 @@ Command line of course produces bigger images, and may be inappropriate for some targets, so by default it's off. +* Update PK1C20 board for Nios-II 5.0 + Patch by Scott McNutt + -Update base addresses for standard configuration + -Eliminate use of CACHE_BYPASS in board code + * Fix I/O Macros and mini-app stubs for Nios-II Patch by Scott McNutt -Fix asm/io.h macros diff -Naurb u-boot-current/board/psyent/pk1c20/config.mk u-boot-new/board/psyent/pk1c20/config.mk --- u-boot-current/board/psyent/pk1c20/config.mk 2004-10-10 17:27:32.000000000 -0400 +++ u-boot-new/board/psyent/pk1c20/config.mk 2005-08-09 17:34:46.000000000 -0400 @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x018e0000 +TEXT_BASE = 0x01fc0000 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include diff -Naurb u-boot-current/board/psyent/pk1c20/led.c u-boot-new/board/psyent/pk1c20/led.c --- u-boot-current/board/psyent/pk1c20/led.c 2004-10-10 17:27:32.000000000 -0400 +++ u-boot-new/board/psyent/pk1c20/led.c 2005-08-09 11:33:38.000000000 -0400 @@ -22,7 +22,7 @@ */ #include <common.h> -#include <nios2.h> +#include <asm/io.h> #include <nios2-io.h> #include <status_led.h> @@ -33,30 +33,30 @@ void __led_init (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); + nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; if (state == STATUS_LED_ON) val &= ~mask; else val |= mask; - pio->data = val; + writel (&pio->data, val); } void __led_set (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); + nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; if (state == STATUS_LED_ON) val &= ~mask; else val |= mask; - pio->data = val; + writel (&pio->data, val); } void __led_toggle (led_id_t mask) { - nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); + nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; val ^= mask; - pio->data = val; + writel (&pio->data, val); } diff -Naurb u-boot-current/include/configs/PK1C20.h u-boot-new/include/configs/PK1C20.h --- u-boot-current/include/configs/PK1C20.h 2005-03-30 18:28:19.000000000 -0500 +++ u-boot-new/include/configs/PK1C20.h 2005-08-09 18:04:01.000000000 -0400 @@ -32,7 +32,7 @@ #define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ #define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */ +#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ /*------------------------------------------------------------------------ @@ -51,7 +51,7 @@ #define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ #define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ #define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */ +#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */ #define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ /*------------------------------------------------------------------------ @@ -61,7 +61,7 @@ * -Global data is placed below the heap. * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 128k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) @@ -95,9 +95,9 @@ * CONSOLE *----------------------------------------------------------------------*/ #if defined(CONFIG_CONSOLE_JTAG) -#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ +#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else -#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */ +#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */ #endif #define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ @@ -110,9 +110,9 @@ * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for * epcs device access is enabled. The base address is the epcs * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. - * The register base is currently at offset 0x400 from the memory base. + * The register base is currently at offset 0x600 from the memory base. *----------------------------------------------------------------------*/ -#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */ +#define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ /*------------------------------------------------------------------------ * DEBUG @@ -126,7 +126,7 @@ * registers, we can slow it down to 10 msec using TMRCNT. If the default * period is acceptable, TMRCNT can be left undefined. *----------------------------------------------------------------------*/ -#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ +#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ #define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ #define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ #define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) @@ -137,7 +137,7 @@ * must implement its own led routines -- leds are, after all, * board-specific, no? *----------------------------------------------------------------------*/ -#define CFG_LEDPIO_ADDR 0x00920840 /* LED PIO base addr */ +#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ #define CONFIG_STATUS_LED /* Enable status driver */ #define STATUS_LED_BIT 1 /* Bit-0 on PIO */ @@ -150,7 +150,7 @@ * way out to avoid changes there -- define the base address to ensure * cache bypass so there's no need to monkey with inx/outx macros. *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x80910300 /* Base addr (bypass) */ +#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ #define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ diff -Naurb u-boot-current/board/psyent/common/AMDLV065D.c u-boot-new/board/psyent/common/AMDLV065D.c --- u-boot-current/board/psyent/common/AMDLV065D.c 2004-10-10 17:27:31.000000000 -0400 +++ u-boot-new/board/psyent/common/AMDLV065D.c 2005-08-10 14:01:24.000000000 -0400 @@ -26,7 +26,7 @@ #if defined(CONFIG_NIOS) #include <nios.h> #else -#include <nios2.h> +#include <asm/io.h> #endif #define SECTSZ (64 * 1024) @@ -56,9 +56,8 @@ void flash_print_info (flash_info_t * info) { int i, k; - unsigned long size; int erased; - volatile unsigned char *flash; + unsigned long *addr; printf (" Size: %ld KB in %d Sectors\n", info->size >> 10, info->sector_count); @@ -66,14 +65,10 @@ for (i = 0; i < info->sector_count; ++i) { /* Check if whole sector is erased */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; erased = 1; - flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]); - for (k = 0; k < size; k++) { - if (*flash++ != 0xff) { + addr = (unsigned long *) info->start[i]; + for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) { + if ( readl(addr++) != (unsigned long)-1) { erased = 0; break; } @@ -83,7 +78,7 @@ if ((i % 5) == 0) printf ("\n "); printf (" %08lX%s%s", - CACHE_NO_BYPASS(info->start[i]), + info->start[i], erased ? " E" : " ", info->protect[i] ? "RO " : " "); } @@ -95,9 +90,8 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) - CACHE_BYPASS(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + unsigned char *addr = (unsigned char *) info->start[0]; + unsigned char *addr2; int prot, sect; ulong start; @@ -127,19 +121,18 @@ */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) - CACHE_BYPASS((info->start[sect])); - *addr = 0xaa; - *addr = 0x55; - *addr = 0x80; - *addr = 0xaa; - *addr = 0x55; - *addr2 = 0x30; + addr2 = (unsigned char *) info->start[sect]; + writeb (addr, 0xaa); + writeb (addr, 0x55); + writeb (addr, 0x80); + writeb (addr, 0xaa); + writeb (addr, 0x55); + writeb (addr2, 0x30); /* Now just wait for 0xff & provide some user * feedback while we wait. */ start = get_timer (0); - while (*addr2 != 0xff) { + while ( readb (addr2) != 0xff) { udelay (1000 * 1000); putc ('.'); if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { @@ -163,27 +156,27 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) { - vu_char *cmd = (vu_char *) CACHE_BYPASS(info->start[0]); - vu_char *dst = (vu_char *) CACHE_BYPASS(addr); + vu_char *cmd = (vu_char *) info->start[0]; + vu_char *dst = (vu_char *) addr; unsigned char b; ulong start; while (cnt) { /* Check for sufficient erase */ b = *src; - if ((*dst & b) != b) { - printf ("%02x : %02x\n", *dst, b); + if ((readb (dst) & b) != b) { + printf ("%02x : %02x\n", readb (dst), b); return (2); } - *cmd = 0xaa; - *cmd = 0x55; - *cmd = 0xa0; - *dst = b; + writeb (cmd, 0xaa); + writeb (cmd, 0x55); + writeb (cmd, 0xa0); + writeb (dst, b); /* Verify write */ start = get_timer (0); - while (*dst != b) { + while (readb (dst) != b) { if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { return 1; }

2 1

[U-Boot-Users] patch: Nios-II mini-app and I/O macros
by Scott McNutt 10 Jun '06

10 Jun '06

Fix I/O Macros and mini-app stubs for Nios-II -Fix asm/io.h macros -Eliminate use of CACHE_BYPASS in cpu code -Eliminate assembler warnings -Fix mini-app stubs and force no small data Regards, --Scott diff -Naurb u-boot-current/CHANGELOG u-boot-new/CHANGELOG --- u-boot-current/CHANGELOG 2005-08-07 19:06:32.000000000 -0400 +++ u-boot-new/CHANGELOG 2005-08-11 10:30:51.000000000 -0400 @@ -26,6 +26,13 @@ Command line of course produces bigger images, and may be inappropriate for some targets, so by default it's off. +* Fix I/O Macros and mini-app stubs for Nios-II + Patch by Scott McNutt + -Fix asm/io.h macros + -Eliminate use of CACHE_BYPASS in cpu code + -Eliminate assembler warnings + -Fix mini-app stubs and force no small data + * Fix build problems for PM856 Board * Fix sign extension bug in 'fpga loadb' command; diff -Naurb u-boot-20050809/cpu/nios2/epcs.c u-boot-new/cpu/nios2/epcs.c --- u-boot-20050809/cpu/nios2/epcs.c 2005-03-30 18:28:19.000000000 -0500 +++ u-boot-new/cpu/nios2/epcs.c 2005-08-09 11:05:32.781250000 -0400 @@ -25,7 +25,7 @@ #if defined(CFG_NIOS_EPCSBASE) #include <command.h> -#include <nios2.h> +#include <asm/io.h> #include <nios2-io.h> #include <nios2-epcs.h> @@ -72,8 +72,7 @@ */ #define EPCS_TIMEOUT 100 /* 100 msec timeout */ -static nios_spi_t *epcs = - (nios_spi_t *)CACHE_BYPASS(CFG_NIOS_EPCSBASE); +static nios_spi_t *epcs = (nios_spi_t *)CFG_NIOS_EPCSBASE; /*********************************************************************** * Device access @@ -81,16 +80,20 @@ static int epcs_cs (int assert) { ulong start; + unsigned tmp; + if (assert) { - epcs->control |= NIOS_SPI_SSO; + tmp = readl (&epcs->control); + writel (&epcs->control, tmp | NIOS_SPI_SSO); } else { /* Let all bits shift out */ start = get_timer (0); - while ((epcs->status & NIOS_SPI_TMT) == 0) + while ((readl (&epcs->status) & NIOS_SPI_TMT) == 0) if (get_timer (start) > EPCS_TIMEOUT) return (-1); - epcs->control &= ~NIOS_SPI_SSO; + tmp = readl (&epcs->control); + writel (&epcs->control, tmp & ~NIOS_SPI_SSO); } return (0); } @@ -100,10 +103,10 @@ ulong start; start = get_timer (0); - while ((epcs->status & NIOS_SPI_TRDY) == 0) + while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0) if (get_timer (start) > EPCS_TIMEOUT) return (-1); - epcs->txdata = c; + writel (&epcs->txdata, c); return (0); } @@ -112,10 +115,10 @@ ulong start; start = get_timer (0); - while ((epcs->status & NIOS_SPI_RRDY) == 0) + while ((readl (&epcs->status) & NIOS_SPI_RRDY) == 0) if (get_timer (start) > EPCS_TIMEOUT) return (-1); - return (epcs->rxdata); + return (readl (&epcs->rxdata)); } static unsigned char bitrev[] = { diff -Naurb u-boot-20050809/cpu/nios2/interrupts.c u-boot-new/cpu/nios2/interrupts.c --- u-boot-20050809/cpu/nios2/interrupts.c 2004-10-10 17:27:33.000000000 -0400 +++ u-boot-new/cpu/nios2/interrupts.c 2005-08-09 11:27:39.515625000 -0400 @@ -27,6 +27,7 @@ #include <nios2.h> #include <nios2-io.h> +#include <asm/io.h> #include <asm/ptrace.h> #include <common.h> #include <command.h> @@ -79,7 +80,7 @@ /* Interrupt is cleared by writing anything to the * status register. */ - tmr->status = 0; + writel (&tmr->status, 0); timestamp += CFG_NIOS_TMRMS; #ifdef CONFIG_STATUS_LED status_led_tick(timestamp); @@ -88,16 +89,17 @@ static void tmr_init (void) { - nios_timer_t *tmr =(nios_timer_t *)CACHE_BYPASS(CFG_NIOS_TMRBASE); + nios_timer_t *tmr =(nios_timer_t *)CFG_NIOS_TMRBASE; + + writel (&tmr->status, 0); + writel (&tmr->control, 0); + writel (&tmr->control, NIOS_TIMER_STOP); - tmr->control &= ~(NIOS_TIMER_START | NIOS_TIMER_ITO); - tmr->control |= NIOS_TIMER_STOP; #if defined(CFG_NIOS_TMRCNT) - tmr->periodl = CFG_NIOS_TMRCNT & 0xffff; - tmr->periodh = (CFG_NIOS_TMRCNT >> 16) & 0xffff; + writel (&tmr->periodl, CFG_NIOS_TMRCNT & 0xffff); + writel (&tmr->periodh, (CFG_NIOS_TMRCNT >> 16) & 0xffff); #endif - tmr->control |= ( NIOS_TIMER_ITO | - NIOS_TIMER_CONT | + writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START ); irq_install_handler (CFG_NIOS_TMRIRQ, tmr_isr, (void *)tmr); } diff -Naurb u-boot-20050809/cpu/nios2/serial.c u-boot-new/cpu/nios2/serial.c --- u-boot-20050809/cpu/nios2/serial.c 2004-10-10 17:27:33.000000000 -0400 +++ u-boot-new/cpu/nios2/serial.c 2005-08-09 10:49:40.203125000 -0400 @@ -24,7 +24,7 @@ #include <common.h> #include <watchdog.h> -#include <nios2.h> +#include <asm/io.h> #include <nios2-io.h> /*------------------------------------------------------------------ @@ -32,8 +32,7 @@ *-----------------------------------------------------------------*/ #if defined(CONFIG_CONSOLE_JTAG) -static nios_jtag_t *jtag = - (nios_jtag_t *)CACHE_BYPASS(CFG_NIOS_CONSOLE); +static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE; void serial_setbrg( void ){ return; } int serial_init( void ) { return(0);} @@ -42,9 +41,9 @@ { unsigned val; - while (NIOS_JTAG_WSPACE (jtag->control) == 0) + while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0) WATCHDOG_RESET (); - jtag->data = (unsigned char)c; + writel (&jtag->data, (unsigned char)c); } void serial_puts (const char *s) @@ -55,7 +54,7 @@ int serial_tstc (void) { - return (jtag->control & NIOS_JTAG_RRDY); + return ( readl (&jtag->control) & NIOS_JTAG_RRDY); } int serial_getc (void) @@ -65,7 +64,7 @@ while (1) { WATCHDOG_RESET (); - val = jtag->data; + val = readl (&jtag->data); if (val & NIOS_JTAG_RVALID) break; } @@ -78,8 +77,7 @@ *-----------------------------------------------------------------*/ #else -static nios_uart_t *uart = (nios_uart_t *) - CACHE_BYPASS(CFG_NIOS_CONSOLE); +static nios_uart_t *uart = (nios_uart_t *) CFG_NIOS_CONSOLE; #if defined(CFG_NIOS_FIXEDBAUD) @@ -97,7 +95,7 @@ unsigned div; div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; - uart->divisor = div; + writel (&uart->divisor,div); return; } @@ -117,9 +115,9 @@ { if (c == '\n') serial_putc ('\r'); - while ((uart->status & NIOS_UART_TRDY) == 0) + while ((readl (&uart->status) & NIOS_UART_TRDY) == 0) WATCHDOG_RESET (); - uart->txdata = (unsigned char)c; + writel (&uart->txdata,(unsigned char)c); } void serial_puts (const char *s) @@ -131,14 +129,14 @@ int serial_tstc (void) { - return (uart->status & NIOS_UART_RRDY); + return (readl (&uart->status) & NIOS_UART_RRDY); } int serial_getc (void) { while (serial_tstc () == 0) WATCHDOG_RESET (); - return( uart->rxdata & 0x00ff ); + return (readl (&uart->rxdata) & 0x00ff ); } #endif /* CONFIG_JTAG_CONSOLE */ diff -Naurb u-boot-20050809/cpu/nios2/sysid.c u-boot-new/cpu/nios2/sysid.c --- u-boot-20050809/cpu/nios2/sysid.c 2005-03-30 18:28:19.000000000 -0500 +++ u-boot-new/cpu/nios2/sysid.c 2005-08-09 10:55:19.234375000 -0400 @@ -26,20 +26,21 @@ #if defined (CFG_NIOS_SYSID_BASE) #include <command.h> -#include <nios2.h> +#include <asm/io.h> #include <nios2-io.h> #include <linux/time.h> void display_sysid (void) { - struct nios_sysid_t *sysid = - (struct nios_sysid_t *)CACHE_BYPASS(CFG_NIOS_SYSID_BASE); + struct nios_sysid_t *sysid = (struct nios_sysid_t *)CFG_NIOS_SYSID_BASE; struct tm t; char asc[32]; + time_t stamp; - localtime_r ((time_t *)&sysid->timestamp, &t); + stamp = readl (&sysid->timestamp); + localtime_r (&stamp, &t); asctime_r (&t, asc); - printf ("SYSID : %08x, %s", sysid->id, asc); + printf ("SYSID : %08x, %s", readl (&sysid->id), asc); } diff -Naurb u-boot-20050809/include/asm-nios2/io.h u-boot-new/include/asm-nios2/io.h --- u-boot-20050809/include/asm-nios2/io.h 2005-03-30 18:28:19.000000000 -0500 +++ u-boot-new/include/asm-nios2/io.h 2005-05-26 14:50:50.421875000 -0400 @@ -39,12 +39,13 @@ #define readl(addr)\ ({unsigned long val;\ asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) + #define writeb(addr,val)\ - asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val)) + asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val)) #define writew(addr,val)\ - asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val)) + asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val)) #define writel(addr,val)\ - asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val)) + asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val)) #define inb(addr) readb(addr) #define inw(addr) readw(addr) diff -Naurb u-boot-current/cpu/nios2/exceptions.S u-boot-new/cpu/nios2/exceptions.S --- u-boot-current/cpu/nios2/exceptions.S 2004-10-10 17:27:33.000000000 -0400 +++ u-boot-new/cpu/nios2/exceptions.S 2005-08-09 14:04:34.000000000 -0400 @@ -30,6 +30,9 @@ .global _exception + .set noat + .set nobreak + _exception: /* SAVE ALL REGS -- this allows trap and unimplemented * instruction handlers to be coded conveniently in C diff -Naurb u-boot-current/examples/Makefile u-boot-new/examples/Makefile --- u-boot-current/examples/Makefile 2005-05-16 10:19:50.000000000 -0400 +++ u-boot-new/examples/Makefile 2005-08-09 17:43:17.000000000 -0400 @@ -42,7 +42,7 @@ endif ifeq ($(ARCH),nios2) -LOAD_ADDR = 0x00800000 -L $(gcclibdir) -T nios2.lds +LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds endif ifeq ($(ARCH),m68k) diff -Naurb u-boot-current/examples/stubs.c u-boot-new/examples/stubs.c --- u-boot-current/examples/stubs.c 2004-10-10 17:27:33.000000000 -0400 +++ u-boot-new/examples/stubs.c 2005-08-09 16:59:16.000000000 -0400 @@ -92,7 +92,7 @@ #x ":\n" \ " movhi r8, %%hi(%0)\n" \ " ori r8, r0, %%lo(%0)\n" \ -" add r8, r0, r15\n" \ +" add r8, r8, r15\n" \ " ldw r8, 0(r8)\n" \ " ldw r8, %1(r8)\n" \ " jmp r8\n" \ diff -Naurb u-boot-current/nios2_config.mk u-boot-new/nios2_config.mk --- u-boot-current/nios2_config.mk 2004-10-10 17:27:30.000000000 -0400 +++ u-boot-new/nios2_config.mk 2005-08-09 16:02:12.000000000 -0400 @@ -23,4 +23,4 @@ # PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ -PLATFORM_CPPFLAGS += -ffixed-r15 +PLATFORM_CPPFLAGS += -ffixed-r15 -G0

2 1

[U-Boot-Users] [PATCH] cleanup duplicated ARM interrupt code
by Andreas Engel 24 May '06

24 May '06

CHANGELOG: Cleaned up duplicated code: moved common ARM interrupt handling code from cpu specific interrupts.c files into lib_arm/interrupts.c. Patch by Andreas Engel, 21 Nov 2005 Signed-off-by: Andreas Engel Note: there were two cases (cpu/arm720t/ and cpu/sa1100/) where the disable_interrupts function only disabled IRQ, but not FIQ. I just ignored this in the generic function in lib_arm/, which disables both IRQ and FIQ. Perhaps someone with more knowledge of ARM cores can check whether or not this is ok. Regards, Andreas Engel

2 1

[U-Boot-Users] mips cache and relocate_code()
by Burch, John T. 23 May '06

23 May '06

Code is relocated from flash to RAM in cpu/mips/start.S/relocate_code(). After the code is moved a comment in the code says, "If caches were enabled, we would have to flush them here." Based on code in the same file, the caches are enabled - and I agree that the data cache needs to be flushed, (and instruction cached invalidated to be safe) but it isn't. Is there a reason it's not? Also, flush_cache() is not implemented in cpu/mips/cpu.c. This function appears to be required by cmd_net.c/netboot_common(). Is there a reason flush_cache() is not implemented? I ask because I'm seeing unexplained code behavior that goes away if I don't enable the caches. John ============================================================ The information contained in this message may be privileged and confidential and protected from disclosure. If the reader of this message is not the intended recipient, or an employee or agent responsible for delivering this message to the intended recipient, you are hereby notified that any reproduction, dissemination or distribution of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by replying to the message and deleting it from your computer. Thank you. Tellabs ============================================================

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[U-Boot-Users] Redundant environment
by Tolunay Orkun 22 May '06

22 May '06

Dear Wolfgang, After exchanging emails with some list members, I have the feeling that there is some interest in a redundant environment implementation that is synchronized. If I am allowed to introduce this enhancement, I pledge that existing implementations would not be effected unless CONFIG_ENV_REDUND_SYNC is defined and generated code would be virtually identical. Of course, I will also document both behavior in README properly, introduce the same functionality in env_flash.c, env_nand.c etc. (i.e. all mediums that redundant environment is implemented) and fixup fw_setenv/fw_getenv utility. Best regards, Tolunay

4 9

[U-Boot-Users] Kernel XIP
by shivappa.kushtagi＠wipro.com 19 May '06

19 May '06

Hello, I configured for kernel XIP and created xipImage. When I tried to load it through u-boot, it complained about invalid magic number. Later I added a 64 byte header required for u-boot with the following mkimage command: mkimage -A arm -O linux -T kernel -C none -a 0x00080000 -e 0x00080040 -d xipImage XIPImage. Actually some of the document found at CELF wiki specifies that we need to give "-x" option to mkimage. With -x option, mkimage fails with the following error message : mkimage: Bad file: "xipImage" has invalid buffer for XIP. After looking into the mkimage source code, found that it expects 0xFF for the first 64 bytes of xipImage. Which is missing in the xipImage I have built. There must be some in-consistency between the way xipImage is built or mkimage command. Also, I didn't find any significance of the code for "-x" if we specify the "entry point" correctly (load address + 0x40). After the mkimage, I flashed the XIPImage at address 0x00080000. After resetting the board, I got the following boot messages : ## Booting image at 00080000 ... Image Name: Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 2009016 Bytes = 1.9 MB Load Address: 00080000 Entry Point: 00080040 Verifying Checksum ... OK XIP Kernel Image ... OK Starting kernel ... And it stops here.... Any idea what is going wrong here ? My configuration: Processor : ARM926EJ-Sid(wb) rev 3 (v5l) Kernel : 2.6.10 Regards Shivappa

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Re: [DNX#2006040142001034] [U-Boot-Users] M5235EVB port
by DENX Support System 15 May '06

15 May '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006040142001034] was created: <snip> > Attached is my recent port to coldfire 5235. Please take a look at > it as it is my first look at U-Boot (which by the way, is very > nice!) I'd be happy if this code was added to the archive for others > to use. > > thanks, wilson </snip> Your U-Boot support team

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[U-Boot-Users] FPGA loading
by Andre Schwarz 05 May '06

05 May '06

Hi all, looks like there is a little bit of code missing in "common/cmd_fpga.c". The code intends to load a FPGA with the command "fpga load <dev> <data> <datasize>". Variable argc is supported, so <dev> <data> <datasize> is optional. The 2 operands <dev> and <data> are obtained from the environment (->"fpga" and "fpgadata"). But <datasize> is not. This results in an error as soon as you try to do a "fpga load" having "fpga=0" and "fpgadata=Address" set up correctly in the environment, since "fpgadata" is NULL. This patch gets rid of this problem. 201a202 > char *sizestr = getenv ("fpgadatasize"); 207a209,210 > if (sizestr) > data_size = (size_t) simple_strtoul (sizestr, NULL, 16); regards, Andre

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[U-Boot-Users] about ohci in pxa27x
by eric.liao 05 May '06

05 May '06

hi, Recently I have being porting u-boot to pxa27x,but I also want to use the ohci function of this chip, so I copy the usb_ohci.c and usb_ohci.h from at91rm9200, but when I use usb commands, it seemed that the programme could not find usb_storage(I have defined usb_storage),so I hope someone who have ported this part could share me some experience and source code. thanks -- View this message in context: http://www.nabble.com/about-ohci-in-pxa27x-t1479259.html#a4003541 Sent from the Uboot - Users forum at Nabble.com.

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[U-Boot-Users] quit unclear code in cpu/arm920t/at91rm9200/ether.c Line:220
by Udo Jakobza 02 May '06

02 May '06

Hello, inside of arm_init() in the part: /* MII management start from here */ if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) { if (!(ret = PhyOps.Init (p_mac))) { printf ("MAC: error during MII initialization\n"); return 0; } } the software checks the status of a LINK-Bit. I thing the EMAC_SR register is wrong, because the EMAC_ISR has this valid LINK bit (AT91C_EMAC_LINK on bit 9). Did anybody find this problem? If not, so I will check it with our hardware and then I will prepare a patch. Thanks and Regards Udo Forschungs- und Transferzentrum Leipzig e. V. an der HTWK Leipzig Udo Jakobza Wächterstr. 13 04107 Leipzig Tel: +49(0)341 3076 1136 Fax: +49(0)341 3076 1220

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[U-Boot-Users] Cannot set bootcount
by Antonio Di Bacco 01 May '06

01 May '06

I don't manage to reset bootcount on a MBX with MPC860. I imagine the variable is in MPC internal ram or in a register and setting its value and saving the environment has no effect. Bye, Antonio.

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[U-Boot-Users] the difference between two instructions
by Min Chen 30 Apr '06

30 Apr '06

Hello guys, Here are two lines of arm assemble code: ldr pc, _undefined_instruction ldr pc, =_undefined_instruction What's the difference between them? Do they act in the same way in some cases? I know it seems to be independent of u-boot, but I just can't solve it and have been puzzled today after searching for answers on the web. Thank you for your advice. Best regard, Min Chan

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[U-Boot-Users] u-boot scripts can contain "if" and "loops"?
by Antonio Di Bacco 29 Apr '06

29 Apr '06

Anyone knows how to write an environment variable with a script inside containing if or loops? Bye, Antonio.

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[U-Boot-Users] Is there any way to just compile files relative to my board?
by Min Chen 29 Apr '06

29 Apr '06

Hello guys, To compile a u-boot, follow the steps below: make clean make <your_board_name>_config make all But I'm suspicious of using 'make all' will compile other boards useless to me. Is there any way to just compile files relative to my board? Thank you. Best regards,

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[U-Boot-Users] Re: VtAyGRA new
by Bernadine Boydstun 29 Apr '06

29 Apr '06

Hi X y A c N k A d X s C t I x A w L f I a S i V s A u L e I v U o M a V o I h A v G n R e A f http://www.vametalbo.com mensura tinde chatte youngste insoucianc I dont understand. You dont have to, its symbolic. How could he get in here? He couldnt. Every guard in every tunnel up the line has the name and serial numbers of the Novgorod papers he took from the agent he killed in Moscow. If he shows up, theyll stop him and shoot him on sight. I told Krupkin not to do that.

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[U-Boot-Users] Accessing mkimage checksum
by NZG 29 Apr '06

29 Apr '06

We want to create a utiltiy to reflash a u-boot package created with mkimage through the MTD layer of uClinux. First off, is there already have a GNUtool to do this? If not, what is the offset of the checksum in a package made by mkimage? thx, NZG

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[U-Boot-Users] flash interconnection
by Tiago 29 Apr '06

29 Apr '06

Hi All I'm observing electric diagram of Freescale board PQ27e-ADS (MPC8272) about the interconnection between cpu MPC 8272 and flash memory. The data bus is linked inverted, i.e., flash DQ0 is connected to processor DQ7, flash DQ7 is connected to processor DQ0. For the other bytes it is the same (flash DQ8 is connected to processor DQ15 and so on). My question: Is it possible to connect the flash memory to the processor in a different way (such as flash DQ0 to processor DQ15, flash DQ1 to proc. DQ14, ..., flash DQ15 to proc. DQ0)? Is there a pin or register to configure the processor to behave this way? I've been searching for this in data sheet of MPC8272, but I didn't find any information about this. Regards, Tiago

2 1

[U-Boot-Users] U-boot patch for Avnet/Memec Design MDFF1152 board
by Dave Ashley 28 Apr '06

28 Apr '06

Hi, Attached is a patch for uboot based on the git version from 2006/04/27. It adds support for the Memec Design FF1152 board labelled VIRTEX-II PRO DEVELOPMENT BOARD DS-BD-2VPxx-FF1152 REVISION 3 There are instructions on how to build the bitstream file with Xilinx EDK 8.1i. This work was sponsored by Carts, LLC http://www.carts.com -Dave

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RE: [U-Boot-Users] Re: FT u-boot shim
by Rune Torgersen 28 Apr '06

28 Apr '06

> -----Original Message----- > From: Tolunay Orkun > Why can't we have dts compiled into 'vmlinux' perhaps marked > as __init > (or something like it). If kernel is going to patch it > anyway, why do we > pass a static file from u-boot? > Have it in there with space reserved for the variables bootm need to fill in. That way bootm only needs to look in the dts, find the variables it needs to update, and patch them.

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[U-Boot-Users] Re: FT u-boot shim
by Kumar Gala 28 Apr '06

28 Apr '06

On Apr 26, 2006, at 2:19 PM, Wolfgang Denk wrote: > In message <A8793E99-83C1-4FD9-8735- > D2E8F98B3003(a)kernel.crashing.org> you wrote: >> >> I think thats part of the idea with arch/powerpc defining a standard >> mechanism for how a boot loader should pass information to the kernel >> (via a flat device tree). > > Yet another standard. > >> How would you propose that we handle booting arch/powerpc kernels >> from u-boot going forward? (for new board ports and existing board >> ports). > > Ideally, I'd like to see a common kernel interface for all archi- > tectures, PowerPC and ARM and MIPS and ... But last time I dared to > suggest this I've been told what a nincompoop I am. > > I will accept what is decided by the P.T.B., but I request not to > break backwards compatibility with existing systems. I've been thinking about the various issues related to booting an arch/powerpc kernel via u-boot. I was hoping to get some ideas/ comments on what people thought about the various issues/questions related to producing a system that can boot an arch/powerpc kernel for an embedded system. I'm using u-boot as the boot loader since its a popular choice (I imagine the issues are similar for others): [NOTE: dts, flat dev tree, etc are used interchangeably] 1. boot with an "old" u-boot (via bd_t): * Have a boot wrapper that takes bd_t and dts and merges them @ runtime * Boot wrapper has to be custom based on bd_t definition for the system * dts owned by kernel?? 2. boot with a "new" u-boot (has a .dts in it): * capable of booting arch/powerpc kernel directly w/o modification * in a production system don't want to update u-boot * dts owned by u-boot?? Some questions/issues: * ownership of .dts is problematic. I hate having a file duplicated by both u-boot and kernel. However it also seems bad to make the build of either depend on the user grabbing a dts from some third party. Ideas? A concrete example would be the MPC8349 ADS/SYS/MDS port. Boards ship with an "old" u-boot, thus we need a kernel wrapper with .dts. However, newer u-boot's can (hopefully will) have a dts in them * updating of dts: In case 1, this is trivial since its part of the kernel blob. Case 2. is more difficult. What do people think of treating the dts like the environment. You have a version compiled in, but can alternately have a blob in another location that will be used if exists. This would allow one to update the dts portion w/o effecting the actual boot loader. * one solution to the copies of .dts is that we make the wrapper portion of the kernel the owner of the official latest and greatest .dts. Every so often a maintainer can sync their .dts with u-boot to keep them relatively in sync. However, the main mechanism would be to load the latest .dts blob into the secondary location. We can provide scripts/tools to do this via u-boot and linux. comments, other issues people have thought of? - kumar

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[U-Boot-Users] NAND ECC: S3C2410
by Steve Finney 28 Apr '06

28 Apr '06

I'm interested in adding NAND single bit error-correction support for the S3C2410 processor (and a Samsung K9F560* NAND flash). At the moment, it looks like cmd_nand.c hard-wires some alternate ECC scheme (is this for a Toshiba chip?). Is there any move towards trying to cleanly factor out the ECC code, or is my most direct path to simply hack my own version of cmd_nand.c? Thanks, sf

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Re: [U-Boot-Users] Accessing mkimage checksum
by Wolfgang Denk 28 Apr '06

28 Apr '06

In message <20060428080933.11288.qmail(a)web15903.mail.cnb.yahoo.com> you wrote: > > Ummm, the rule is that you should provide the > crc32 checksum first to check before sending > it out. Some unexpection would happen to the > file via email or transferring process. This > is also true for md5sum file for download > cases:-) I don't think that crc32 is a good choice for such purposes. But YMMV. I think we should stop this discussion now. It is off topic anyway. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Perl itself is usually pretty good about telling you what you shouldn't do. :-) - Larry Wall in <11091(a)jpl-devvax.JPL.NASA.GOV>

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[U-Boot-Users] [PATCH] complains on bad CFG_MAX_FLASH_SECT description
by Mirco Fuchs 28 Apr '06

28 Apr '06

Hello, this Patch complains if the macro CFG_MAX_FLASH_SECT is smaller than the truly available flash sectors. best regards Mirco Signed-off-by: Mirco Fuchs <mircofuchs(a)web.de> --- --- u-boot_1.1.4/u-boot-1.1.4/drivers/cfi_flash.c 2006-03-12 02:13:21.000000000 +0100 +++ u-boot-1.1.4/drivers/cfi_flash.c 2006-04-27 17:41:54.495071792 +0200 @@ -1131,6 +1131,10 @@ ulong flash_get_size (ulong base, int ba erase_region_count = (tmp & 0xffff) + 1; debug ("erase_region_count = %d erase_region_size = %d\n", erase_region_count, erase_region_size); + if (erase_region_count > CFG_MAX_FLASH_SECT) { + printf ("*** Warning - nbr. of erase regions > CFG_MAX_FLASH_SECT\n"); + return 0; + } for (j = 0; j < erase_region_count; j++) { info->start[sect_cnt] = sector; sector += (erase_region_size * size_ratio);

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[U-Boot-Users] crc32 and md5sum
by Antonio Di Bacco 27 Apr '06

27 Apr '06

Anyone knows if crc32 and md5sum give the same result? Which is better? In the u-boot only crc32 is used. Bye, Antonio.

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[U-Boot-Users] RE: FT u-boot shim
by Rune Torgersen 27 Apr '06

27 Apr '06

Would it be possible to have the kernel smart enough that if it gets passed a bd_t pointer, it updates the dts before booting fully. Newer u-boot versions that support dts then would pass a NULL bd_t pointer to a kernel that supports dts. Kernel would then not update the dts, but use the one it gets handed. bootm should be able to see if the kernel has an attached dts, update it with runtime parameters, and hand it off to the kernel. If it is an old kernel, hand it the bd_t pointer.

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[U-Boot-Users] Redundant environment expected behavior vs current
by Tolunay Orkun 27 Apr '06

27 Apr '06

Hi, I have an inquiry regarding how the U-Boot environment redundancy is supposed to work. For the new embedded board I have decided to implement redundant u-boot environment to make it more resilient against corruption. I had not done this before so I did not know how it was actually implemented. I've found that redundant environment does not really create an exact duplicate environment (as far as environment variables are concerned). Instead, the active environment is rotated each save and only the new active environment copy contains the changes to the environment. So, at this stage if your active environment is lost/corrupted your latest changes to the environment is lost as well which might be important to boot your system. The idea behind redundancy (IMHO) is such that if one environment is lost the backup can provide all that was in active but in current implementation it is not be possible simply using one saveenv command. To get truly redundant environment that is exactly duplicate, you are supposed to save the environment twice. I personally think this is not quite how redundant environment should be implemented. I think once the update of one environment is completed, second environment should be updated with the same. What do you think? Am I the only one that expect complete sync of both sectors? Should I submit a patch? Best regards, Tolunay Other cosmetic issues noticed: 1) Defining CFG_ENV_ADDR_REDUND or CFG_ENV_OFFSET_REDUND results in definition of CFG_REDUNDAND_ENVIRONMENT. I might be nitpicking but the correct spelling should have been CFG_REDUNDANT_ENVIRONMENT 2) The output of saveenv intermixed with output from flash driver is looking rather untidy and confusing. For example, ". done" below is coming from "driver/cfi_flash.c". We get ". done" right after "Saving Environment to Flash..." message and other messages follow. However, the first ". done" was really for unprotect which is reported after. I think like U-Boot does for Erasing part, we should announce the operation first (i.e. Un-protecting ... Protecting...) so flash driver output can match the current operation properly. => saveenv Saving Environment to Flash... . done Un-Protected 1 sectors . done Un-Protected 1 sectors Erasing Flash... . done Erased 1 sectors Writing to Flash... done . done Protected 1 sectors . done Protected 1 sectors

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RE: [U-Boot-Users] quit unclear code in cpu/arm920t/at91rm9200/ether.c Line:220
by Martin Krause 27 Apr '06

27 Apr '06

Hi, u-boot-users-admin(a)lists.sourceforge.net wrote on : > inside of arm_init() in the part: It's in eth_init() ... > /* MII management start from here */ > if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) { > if (!(ret = PhyOps.Init (p_mac))) { > printf ("MAC: error during MII initialization\n"); > return 0; > } > } > the software checks the status of a LINK-Bit. I thing the EMAC_SR > register is wrong, because the EMAC_ISR has this valid LINK bit > (AT91C_EMAC_LINK on bit 9). I think you are right. Due to the AT91RM9200 datasheet (Rev. 1768B-ATRM-08/03) bit 0 of the EMAC_SR (ETH_SR) is labeld with "LINK" and not bit 9. But the description for the "LINK" bit (bit 0) is "reserved". So this bit couldn't be used at all. Im'n not sure, if EMAC_ISR register bit 9 is suitable for testing the link satus. The datasheet says for this bit: "LINK: Set when LINK pin changes value. Optional.". Wich pin is the "link" pin? In my opinion the AT91RM9200 doesn't has such a pin . And is a LINK change really what we want to test here (a "link" to "no link" transition is also a link change, not only a "no link" to "link" transition)? > Did anybody find this problem? No, no problem. The current code is wrong, anyway. > If not, so I will check it with our hardware and then I will prepare > a patch. This would be great! Regards, Martin

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[U-Boot-Users] cg-clone u-boot problem
by Demke Torsten-atd012 27 Apr '06

27 Apr '06

Hi, Im trying to download a fresh copy of the u-boot git repositoy with: #: cg-clone http://www.denx.de/git/u-boot.git my-uboot defaulting to local storage area Fetching head... cg-fetch: unable to get the HEAD branch A cg-update command from another local repository works. Is there a known problem or do I make something wrong? Regards, Torsten

1 0

[U-Boot-Users] uClinux on Phytec board using U-BOOT
by Kaushik karandikar 27 Apr '06

27 Apr '06

Hi All, I am having Phytec ARM board with LPC2294 chip (ARM7TDMI) with 1MB flash , 2MB RAM. I wanted to boot the uClinux on this board. What all changes i need to do as there is no entry i found for this particular board and cpu. Looking at the u-boot README file, i added the board entry under u-boot/boards as well as did all the required changes in Makefiles. Is the arm720t cpu is tuned for arm7tdmi? (Can i use teh same cpu for arm7tdmi?) I am able to get the u-boot.srec images. Please let me know the changes i need to do for this to make uClinux boot on my board. But its not working when i put it in the flash. Thanks and Regards, Kaushik --------------------------------- Blab-away for as little as 1¢/min. Make PC-to-Phone Calls using Yahoo! Messenger with Voice.

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Re: [U-Boot-Users] How do you test a bit set/clear from U-Boot command line/script?
by Tolunay Orkun 27 Apr '06

27 Apr '06

Wolfgang Denk wrote: > In message <444FDD08.2010101(a)orkun.us> you wrote: > >> I know I can compare a simple value using itest command. e.g. >> >> itest *4000 -eq 1234 && echo 'Addr 4000 contains 1234' >> >> Now my problem is how can I test a bit of 32 bit quantity (say bit 4) >> stored at location 4000? This is a question about general hush/u-boot >> shell capability? It is a generic question... >> > > At the moment there is no command that implements this. As you > probaly are aware, the "itest" command just implements the following > operations: > I did hope there was some clever way to do this using existing commands. > Feel free to add new commands for AND, OR, and XOR... > I will send a patch. I am not sure how OR or XOR could be useful though... We do not support multiple operations or store computed expression results anywhere. Tolunay

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Re: [U-Boot-Users] How do you test a bit set/clear from U-Boot command line/script?
by Tolunay Orkun 27 Apr '06

27 Apr '06

Wolfgang Denk wrote: > In message <444FD06D.4060309(a)orkun.us> you wrote: > >> Within a u-boot script (to be executed by autoscr command), I need to >> read a GPIO port and if a particular GPIO bit is set execute some >> conditional commands. I am not sure how to do this with test/itest >> commands. Any ideas? >> > > This is obviously highly hardware specific. > > > I am not asking anything about hardware. Forget I said GPIO. Let's say a value in general memory space. It could be in ram or flash.... I know I can compare a simple value using itest command. e.g. itest *4000 -eq 1234 && echo 'Addr 4000 contains 1234' Now my problem is how can I test a bit of 32 bit quantity (say bit 4) stored at location 4000? This is a question about general hush/u-boot shell capability? It is a generic question... Best regards, Tolunay

2 1

[U-Boot-Users] How do you test a bit set/clear from U-Boot command line/script?
by Tolunay Orkun 26 Apr '06

26 Apr '06

Within a u-boot script (to be executed by autoscr command), I need to read a GPIO port and if a particular GPIO bit is set execute some conditional commands. I am not sure how to do this with test/itest commands. Any ideas? Best regards, Tolunay

1 0

[U-Boot-Users] How can I make a smallest u-boot?
by Min Chen 26 Apr '06

26 Apr '06

Hello guys, I don't want to get involved in boads and processors that have nothing to do with my porting. Can I simply remove some directories in 'u-boot-1.1.4\board' and 'u-boot-1.1.4\cpu'? Or are there more things I have to do to make a smallest u-boot? Thanks. Best regards,

2 1

[U-Boot-Users] OMAP5912 OSK - BDI2000 config file / flash instructions?
by Wolfgang Denk 26 Apr '06

26 Apr '06

Hello, has anybody a BDI2000 config file (with working configuration of the flash) and/or instructions how to flash an U-Boot image on an OMAP5912 OSK board? Thanks in advance. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de In C we had to code our own bugs, in C++ we can inherit them.

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[U-Boot-Users] Bug in cfi_flash.c
by Mirco Fuchs 26 Apr '06

26 Apr '06

Hello, there is a bug in cfi_flash.c in function flash_get_size(). The problem appears if the board specific CFG_MAX_FLASH_SECT macro is smaller than the real number of sectors. In this case i use a 32 MiB Spansion flash (S29GL256), but we only want respectivly can use 16 MiB of the flash because of the broken A24 line on the AT91RM9200. Therefore i defined CFG_MAX_FLASH_SECT to 128, but the real value is 256. The structure allocation of flash_info_t in flash.h defines the size of the protect array to CFG_MAX_FLASH_SECT (in my case 128). The for-loop in flash_get_size() initialises this array, but it does it for all sectors (erase_region_count) which is 256 in my case. This will cause the info->portwidth variable (and of course all following too) to be overwritten. flash.h **************************************** typedef struct { ulong size; /* total bank size in bytes */ ushort sector_count; /* number of erase units */ ulong flash_id; /* combined device & manufacturer code */ ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */ uchar protect[CFG_MAX_FLASH_SECT]; /* sector protection status */ #ifdef CFG_FLASH_CFI uchar portwidth; /* the width of the port */ uchar chipwidth; /* the width of the chip */ ushort buffer_size; /* # of bytes in write buffer */ ulong erase_blk_tout; /* maximum block erase timeout */ ulong write_tout; /* maximum write timeout */ ulong buffer_write_tout; /* maximum buffer write timeout */ ushort vendor; /* the primary vendor id */ ushort cmd_reset; /* Vendor specific reset command */ ushort interface; /* used for x8/x16 adjustments */ ushort legacy_unlock; /* support Intel legacy (un)locking */ #endif } flash_info_t; **************************************** cfi_flash.c, flash_get_size() **************************************** debug ("erase_region_count = %d erase_region_size = %d\n", erase_region_count, erase_region_size); for (j = 0; j < erase_region_count; j++) { info->start[sect_cnt] = sector; sector += (erase_region_size * size_ratio); /* * Only read protection status from supported devices (intel...) */ switch (info->vendor) { case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: info->protect[sect_cnt] = flash_isset (info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); break; default: info->protect[sect_cnt] = 0; /* default: not protected */ } sect_cnt++; } } ****************************************** regards Mirco

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[U-Boot-Users] AMCC 4XX (specially 405EP) and CFG_RX_ETH_BUFFERS
by Tolunay Orkun 26 Apr '06

26 Apr '06

Hi, Is there a valid range for number of RX buffers for AMCC405EP Ethernet driver? I am using a fairly recent U-Boot from GIT and if I define CFG_RX_ETH_BUFFERS 31 it works but if I use CFG_RX_ETH_BUFFERS 32 it has a lot of timeouts in tftp etc. Best regards, Tolunay

2 1

[U-Boot-Users] Image date output from imls/iminfo when no rtc chip is present
by Tolunay Orkun 26 Apr '06

26 Apr '06

Creation date of the U-Boot Image is suppressed from output of imls/iminfo commands if CFG_CMD_DATE is not included in CONFIG_COMMANDS. However, CFG_CMD_DATE cannot be included unless you have an RTC chip on board. I think the date of U-Boot image is useful information that we would like to see even if CFG_CMD_DATE is not defined. To such end, I thought of the following solution: Define CONFIG_RTC_NONE so that CFG_CMD_DATE could be defined. Obviously, date/time commands will display error message when user attempts to use these commands with CONFIG_RTC_NONE. I might even exclude the definition of date/time commands altogether keeping only supporting date functionality needed for imls/iminfo. What do you think? If there is agreement on CONFIG_RTC_NONE, I can submit a patch... Best regards, Tolunay

2 2

[U-Boot-Users] Elf loader
by nico 25 Apr '06

25 Apr '06

Hi all, I'm investigating the integrated elf loader procedure in the cmd_elf.c file. And I'm wondering why the function "load_elf_image()" relocates the elf file using only the Symbol table... this is not wrong, but doing this only allows to follow the virtual adresses scheme. So if you have differences between virtual adresses and physical adresses (ex: loading a kernel that will enable the MMU...) you will f*** this up... Why not using the Program table, isn't this supposed to give you all the relocations to do ? thx, nicolas

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RE: [U-Boot-Users] FW: mpc8347 TSEC1 (Got Error 4)
by Aziz Mzili 24 Apr '06

24 Apr '06

Hi, I've seen that. I'm still looking for what can cause that. The Phy's are initialized the same way. I Can read the MII registers and see that are the same. The Hw guy double checked and can't see anything. If anybody have any idea where i can investigate it will be verry helpful. Thak you all. -----Original Message----- From: u-boot-users-admin(a)lists.sourceforge.net [mailto:u-boot-users-admin@lists.sourceforge.net]On Behalf Of Rick Nardone Sent: Monday, April 24, 2006 11:21 AM To: u-boot-users(a)lists.sourceforge.net Subject: RE: [U-Boot-Users] FW: mpc8347 TSEC1 (Got Error 4) Aziz, "Got error 4" is a CRC error indication in the status bits of the receive buffer descriptor (tsec.h). - Rick Nardone ________________________________________ From: u-boot-users-admin(a)lists.sourceforge.net [mailto:u-boot-users-admin@lists.sourceforge.net] On Behalf Of Aziz Mzili Sent: Friday, April 21, 2006 4:34 PM To: u-boot-users(a)lists.sourceforge.net Subject: [U-Boot-Users] FW: mpc8347 TSEC1 (Got Error 4) -----Original Message----- From: Aziz Mzili Sent: Friday, April 21, 2006 4:24 PM To: 'u-boot-users-admin(a)lists.sourceforge.net' Subject: mpc8347 TSEC1 (Got Error 4) Hi All, with our MPC8347 based board, we get the message "Got error 4" eveytime we unplug TSEC0 and try to ping on TSEC1. TSEC0 when plugged works fine. Anyone have any idea where this error come from? thank you Aziz MZILI ------------------------------------------------------- Using Tomcat but need to do more? Need to support web services, security? Get stuff done quickly with pre-integrated technology to make your job easier Download IBM WebSphere Application Server v.1.0.1 based on Apache Geronimo http://sel.as-us.falkag.net/sel?cmd=k&kid0709&bid&3057&dat1642 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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RE: [U-Boot-Users] FW: mpc8347 TSEC1 (Got Error 4)
by Rick Nardone 24 Apr '06

24 Apr '06

Aziz, "Got error 4" is a CRC error indication in the status bits of the receive buffer descriptor (tsec.h). - Rick Nardone ________________________________________ From: u-boot-users-admin(a)lists.sourceforge.net [mailto:u-boot-users-admin@lists.sourceforge.net] On Behalf Of Aziz Mzili Sent: Friday, April 21, 2006 4:34 PM To: u-boot-users(a)lists.sourceforge.net Subject: [U-Boot-Users] FW: mpc8347 TSEC1 (Got Error 4) -----Original Message----- From: Aziz Mzili Sent: Friday, April 21, 2006 4:24 PM To: 'u-boot-users-admin(a)lists.sourceforge.net' Subject: mpc8347 TSEC1 (Got Error 4) Hi All, with our MPC8347 based board, we get the message "Got error 4" eveytime we unplug TSEC0 and try to ping on TSEC1. TSEC0 when plugged works fine. Anyone have any idea where this error come from? thank you Aziz MZILI

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Re: [U-Boot-Users] TQM866M CPU glitch
by Nicholas Mc Guire 23 Apr '06

23 Apr '06

> X-EYOU-SPAMVALUE:100 > X-EYOU-DEALDRC: > X-Auth-Info: zjvJMUdItuLN4XakZSaDhHT7x1SrUScONjZbUp+td5M= > X-Auth-Info: zjvJMUdItuLN4XakZSaDhHT7x1SrUScONjZbUp+td5M= > cc: u-boot-users(a)lists.sourceforge.net > from: wolfgang denk <wd(a)denx.de> > Date: Fri, 21 Apr 2006 00:08:06 +0200 > Sender: wd(a)denx.de > > Hello, > > in message <200604191447.k3JElKhT003105(a)opentech.lzu.edu.cn> you wrote: > > > > I have a TQM866M board here, and it seems that the ID that this board is > > using is not checked for in cpu/mpc8xx/cpu.c - not sure if this patch is > > usable - but it fixes the problem of indentifying the right CPU for me > > Any chance that you use old code? > > This is supposed to be solved by this commit: > > commit 7b4fd36b0322ec98836a8459d9be80e2777fdc05 > tree 92deb9ddf1153c64ff1ced9392816e60b4ecaa03 > parent 0a112d8696dcffdf87a7066e2dade1eacbdd80d9 > author Wolfgang Denk <wd(a)atlas.denx.de> Sat, 18 Mar 2006 23:31:12 +0100 > committer Wolfgang Denk <wd(a)atlas.denx.de> Sat, 18 Mar 2006 23:31:12 +0100 > > Add support for MPC859/866 Rev. A.0 > > > A different issue is that I can't get the ehternet to work, the error on > > network access is: > > Works fine here. > > Did you set the jumpers on the board correctly? See the FAQ: > http://www.denx.de/wiki/view/DULG/EthernetProblemsOnTQM8xxL > > Best regards, > thanks - just pulled the current git tree and the CPU shows up correctly now - and as the above URL suggest - it was the jumpers - we actually did consult the manual regarding jumpers - but we meesed up some how any way :) thx ! hofrat

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[U-Boot-Users] remove include/bmp_logo.h
by Matthias Fuchs 22 Apr '06

22 Apr '06

Hi Wolfgang, is there any special reason why include/bmp_logo.h is a) under version control by git b) not removed by "make clobber" ? The file is automatically regenerated during make. I noticed that "cg-commit" or "git diff" report a difference after each make run on a clean source tree. My suggestion is to remove it from therepository and to add a rm in the clobber rule in the main makefile. Am I missing something? Matthias

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[U-Boot-Users] FW: mpc8347 TSEC1 (Got Error 4)
by Aziz Mzili 21 Apr '06

21 Apr '06

> -----Original Message----- > From: Aziz Mzili > Sent: Friday, April 21, 2006 4:24 PM > To: 'u-boot-users-admin(a)lists.sourceforge.net' > Subject: mpc8347 TSEC1 (Got Error 4) > > > Hi All, > > with our MPC8347 based board, we get the message "Got error 4" eveytime we unplug TSEC0 and try to ping on TSEC1. TSEC0 when plugged works fine. > > Anyone have any idea where this error come from? > > thank you > > Aziz MZILI

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RE: [U-Boot-Users] MPC83xx: CF in True IDE mode
by Joao, Nuno (ext) 21 Apr '06

21 Apr '06

We're using a CF card in TrueIDE mode, on a board with u-boot and MPC8541E. A CPLD maps the CF bus (only the signals needed for IDE mode) into MPC's memory map; this makes the "IDE physical" interface. UPM machines are used for the accesses timing. 2 chipselects are also used, one for the "normal" register file and another for the "alternative register file". u-boot's "ide" command is used; it was only changed in the register access routines, because of different address calculation and endianess. You have to be careful when interfacing the CF card (or any IDE device) with the MPCs. Keep in mind that register 0 (the data register) is accessed at address 0 and is 16 bit wide; the remaining registers are accessed in the next consecutive addresses (1, 2, ...), but are 8 bit wide. Best Regards -----Original Message----- From: u-boot-users-admin(a)lists.sourceforge.net [mailto:u-boot-users-admin@lists.sourceforge.net] On Behalf Of Yogi Sent: quinta-feira, 20 de Abril de 2006 23:36 Subject: [U-Boot-Users] MPC83xx: CF in True IDE mode > Is there support for CF access in true IDE mode for > 83xx with Reiser File system ?

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[U-Boot-Users] precious boot sectors @ lowboot
by Andre Schwarz 21 Apr '06

21 Apr '06

Hi all, a lot of embedded systems have no other non-volatile memory than the boot flash. This is mostly Nor technology, which is quite expensive. In case you are not using a uniform sector flash you'll have smaller "boot sectors" on top or bottom of memory. They are ideally suited for storing small amounts of data (counting operation time, stats or some application specific configuration data). Using a large sector, e.g. 64k would be a waste ... I've the following scenario : MPC5200 processor using low boot, i.e. reset vector @ 0x00000100. 8MB bottom boot sector flash with 8*8k sectors + 127*64k. u-boot startup code uses the first 2 sectors, followed by the 8k embedded environment @ 0x8000. After that follows the rest of u-boot code. It would be very fine if there would be a possibility to place the rest of u-boot code @ offset 0x10000, i.e. sector 8+. I have modified "common/environment.c" with the attached patch, so there is a possibility to define "CFG_ENV_ADD_SPACE" which results in the above mentioned code offset. Of course "CFG_ENV_ADD_SPACE" must end on a sector boundary .... I'm using 0x4000 and therefore having 2 small sectors availabe under linux through /dev/mtd. Nested partitions are no problem at all. Any other ideas ? Should I use u-boot.lds instead ? diff --git a/common/environment.c b/common/environment.c index c7f54c6..dc8c89c 100644 --- a/common/environment.c +++ b/common/environment.c @@ -99,6 +99,10 @@ #if !defined(ENV_CRC) # define ENV_CRC ~0 #endif +#ifdef CFG_ENV_ADD_SPACE +unsigned char env_add_space[CFG_ENV_ADD_SPACE] __PPCENV__; +#endif + env_t environment __PPCENV__ = { ENV_CRC, /* CRC Sum */ #ifdef CFG_REDUNDAND_ENVIRONMENT regards, Andre

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[U-Boot-Users] [PATCH] 4/4 add new Board MIP470 (MPC8347 based)
by Denis Peter 21 Apr '06

21 Apr '06

See my previous message Patch 4: Add MIP470 specific files With best regards, Denis

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[U-Boot-Users] [PATCH] 3/4 add new Board MIP470 (MPC8347 based)
by Denis Peter 21 Apr '06

21 Apr '06

See my previous message Patch 3: Fixed MPC83xx i2c.c to work also before relocation With best regards, Denis

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[U-Boot-Users] [PATCH] 2/4 add new Board MIP470 (MPC8347 based)
by Denis Peter 21 Apr '06

21 Apr '06

See my previous message Patch 2: Add support for MPC834x TSEC in reduced Gigabit Mode & add Broadcom BMC5461 PHY With best regards, Denis

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[U-Boot-Users] [PATCH] 1/4 add new Board MIP470 (MPC8347 based)
by Denis Peter 21 Apr '06

21 Apr '06

Hello Wolfgang, Attached are the patches for the MIP470 board. Here is the Changlog entry: * Patch by Denis Peter, 21. Apr 2006 add MIP470 Board Patch 1: Add support for the RTC7301 Real Time Clock With best regards, Denis

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[U-Boot-Users] CF card in memory mapped mode without PCMCIA controller
by Andriy Korud 21 Apr '06

21 Apr '06

Hi, I'm going to use CF card in memory-mapped mode (not true IDE because HS is required), but without PCMCIA interface chip (necessary signals will be software/glue-logic generated). Will U-Boot like this? Or, will it be difficult to port it to use such mode? Maybe somebody has an example of such solution? Thank in advance, -- Andriy Korud

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