December 2006 - U-Boot

[U-Boot-Users] Please pull from 'mpc83xx' branch
by Kumar Gala 14 Dec '06

14 Dec '06

Please pull from 'mpc83xx' branch of git://git.kernel.org/pub/scm/boot/u-boot/galak/u-boot.git to receive the following updates: cpu/mpc83xx/cpu.c | 2 - cpu/mpc83xx/cpu_init.c | 12 +++---- cpu/mpc83xx/speed.c | 12 +++---- include/asm-ppc/global_data.h | 4 +- include/asm-ppc/immap_83xx.h | 66 +++++++++++++++++++++--------------------- include/mpc83xx.h | 10 +++--- 6 files changed, 53 insertions(+), 53 deletions(-) commit 05bdedd9ecd8819557b111b39309eb1ef9219d16 Author: Kumar Gala <galak(a)kernel.crashing.org> Date: Tue Dec 5 14:35:24 2006 -0600 Fix config of Arbiter, System Priority, and Clock Mode on MPC83xx The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Wasn't not being used when setting the appropriate register Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> commit 8a764deca0349437b6030e49fba208ec5d11ccff Author: Kumar Gala <galak(a)kernel.crashing.org> Date: Tue Dec 5 14:34:51 2006 -0600 Remove CONFIG_MPC8349 and use CONFIG_MPC834X instead CONFIG_MPC8349 is redudant with CONFIG_MPC834X. Additionally CONFIG_MPC834X truly states the class of processors the code is applicable for. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 1b51078..7efe7c5 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -97,7 +97,7 @@ int checkcpu(void) return -1; /* Not sure what this is */ } -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock)); #else printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock)); diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index e5725fb..442937c 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -69,31 +69,31 @@ void cpu_init_f (volatile immap_t * im) #ifdef CFG_ACR_PIPE_DEP /* Arbiter pipeline depth */ - im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT); + im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); #endif #ifdef CFG_SPCR_TSEC1EP /* TSEC1 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT); + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); #endif #ifdef CFG_SPCR_TSEC2EP /* TSEC2 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT); + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); #endif #ifdef CFG_SCCR_TSEC1CM /* TSEC1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT); + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); #endif #ifdef CFG_SCCR_TSEC2CM /* TSEC2 & I2C1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT); + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); #endif #ifdef CFG_ACR_RPTCNT /* Arbiter repeat count */ - im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT)); + im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT)); #endif /* RSR - Reset Status Register - clear all status (4.6.1.3) */ diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 7e53b1e..d0fe34a 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -99,7 +99,7 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbmph_clk; @@ -144,7 +144,7 @@ #endif sccr = im->clk.sccr; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -249,7 +249,7 @@ #endif /* unkown SCCR_ENCCM value */ return -6; } -#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8360) lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); #else @@ -266,7 +266,7 @@ #endif /* unknown lcrr */ return -10; } -#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8360) ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; @@ -314,7 +314,7 @@ #if defined (CONFIG_MPC8360) #endif gd->csb_clk = csb_clk; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) gd->tsec1_clk = tsec1_clk; gd->tsec2_clk = tsec2_clk; gd->usbmph_clk = usbmph_clk; @@ -364,7 +364,7 @@ #endif printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000); printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000); printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000); diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 8bc61b6..c113b7e 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -52,12 +52,12 @@ #endif #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbmph_clk; u32 usbdr_clk; -#endif /* CONFIG_MPC8349 */ +#endif /* CONFIG_MPC834X */ u32 core_clk; u32 i2c1_clk; u32 i2c2_clk; diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 43cde5e..b6f5bc4 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -90,7 +90,7 @@ #define SPCR_TBEN 0x00400000 /* E300 #define SPCR_TBEN_SHIFT (31-9) #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ #define SPCR_COREPR_SHIFT (31-11) -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ #define SPCR_TSEC1DP_SHIFT (31-19) #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ @@ -110,7 +110,7 @@ #elif defined (CONFIG_MPC8360) #define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR) #endif u32 sicrl; /* System General Purpose Register Low */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SICRL_LDP_A 0x80000000 #define SICRL_USB1 0x40000000 #define SICRL_USB0 0x20000000 @@ -143,7 +143,7 @@ #define SICRL_RES ~(SICRL_LDP_A | SI #endif u32 sicrh; /* System General Purpose Register High */ #define SICRH_DDR 0x80000000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SICRH_TSEC1_A 0x10000000 #define SICRH_TSEC1_B 0x08000000 #define SICRH_TSEC1_C 0x04000000 @@ -314,7 +314,7 @@ #define SICVR_IVECX 0xfc000000 /* Inter #define SICVR_IVEC 0x0000007f /* Interrupt vector */ #define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ #define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ #define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ @@ -333,7 +333,7 @@ #define SIIH_UART2 0x00000040 /* UART #define SIIH_SEC 0x00000020 /* SEC interrupt */ #define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ #define SIIH_I2C2 0x00000002 /* I2C2 interrupt */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SIIH_SPI 0x00000001 /* SPI interrupt */ #define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \ @@ -349,7 +349,7 @@ #endif #define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ #define SIIL_PIT 0x40000000 /* PIT interrupt */ #define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ #endif #define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ @@ -358,7 +358,7 @@ #define SIIL_SBA 0x02000000 /* System #define SIIL_DMA 0x01000000 /* DMA interrupt */ #define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ #define SIIL_GTM8 0x00400000 /* GTM8 interrupt */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */ #define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ #endif @@ -376,7 +376,7 @@ #define SIIL_GTM7 0x00000400 /* GTM7 i #define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ #define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ #define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \ | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \ | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \ @@ -444,7 +444,7 @@ #define SECNR_RES ~( SECNR_MIXB0T | SECN #define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ #define SERR_WDT 0x40000000 /* WDT MCP request */ #define SERR_SBA 0x20000000 /* SBA MCP request */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SERR_DDR 0x10000000 /* DDR MCP request */ #define SERR_LBC 0x08000000 /* LBC MCP request */ #define SERR_PCI1 0x04000000 /* PCI1 MCP request */ @@ -457,7 +457,7 @@ #define SERR_PCI 0x04000000 /* PCI MCP #endif #define SERR_MU 0x01000000 /* MU MCP request */ #define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \ |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \ |SERR_RNC ) @@ -540,7 +540,7 @@ #define RCWL_LBIUCM 0x80000000 /* LBIUC #define RCWL_LBIUCM_SHIFT 31 #define RCWL_DDRCM 0x40000000 /* DDRCM */ #define RCWL_DDRCM_SHIFT 30 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define RCWL_SVCOD 0x30000000 /* SVCOD */ #endif #define RCWL_SPMF 0x0f000000 /* SPMF */ @@ -552,7 +552,7 @@ #define RCWL_CEPDF 0x00000020 /* CEPDF #define RCWL_CEPDF_SHIFT 5 #define RCWL_CEPMF 0x0000001F /* CEPMF */ #define RCWL_CEPMF_SHIFT 0 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) #elif defined (CONFIG_MPC8360) #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF) @@ -560,7 +560,7 @@ #endif u32 rcwh; /* RCHL Register */ #define RCWH_PCIHOST 0x80000000 /* PCIHOST */ #define RCWH_PCIHOST_SHIFT 31 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define RCWH_PCI64 0x40000000 /* PCI64 */ #define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ #define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ @@ -573,7 +573,7 @@ #define RCWH_BMS 0x04000000 /* BMS * #define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ #define RCWH_SWEN 0x00800000 /* SWEN */ #define RCWH_ROMLOC 0x00700000 /* ROMLOC */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ #define RCWH_TSEC2M 0x00003000 /* TSEC2M */ #define RCWH_TPR 0x00000100 /* TPR */ @@ -582,7 +582,7 @@ #define RCWH_SDDRIOE 0x00000010 /* Seco #endif #define RCWH_TLE 0x00000008 /* TLE */ #define RCWH_LALE 0x00000004 /* LALE */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \ | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \ | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \ @@ -637,7 +637,7 @@ typedef struct clk83xx { u32 spmr; /* system PLL mode Register */ #define SPMR_LBIUCM 0x80000000 /* LBIUCM */ #define SPMR_DDRCM 0x40000000 /* DDRCM */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SPMR_SVCOD 0x30000000 /* SVCOD */ #endif #define SPMR_SPMF 0x0F000000 /* SPMF */ @@ -647,7 +647,7 @@ #define SPMR_COREPLL 0x007F0000 /* COREP #define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ #define SPMR_CEPDF 0x00000020 /* CEPDF */ #define SPMR_CEPMF 0x0000001F /* CEPMF */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \ | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \ | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF) @@ -660,7 +660,7 @@ #endif #define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ #define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ #define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ #define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ #define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ @@ -670,7 +670,7 @@ #endif #define OCCR_PCICD0 0x00800000 /* PCICD0 */ #define OCCR_PCICD1 0x00400000 /* PCICD1 */ #define OCCR_PCICD2 0x00200000 /* PCICD2 */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define OCCR_PCICD3 0x00100000 /* PCICD3 */ #define OCCR_PCICD4 0x00080000 /* PCICD4 */ #define OCCR_PCICD5 0x00040000 /* PCICD5 */ @@ -691,7 +691,7 @@ #define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCI |OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR ) #endif u32 sccr; /* system clock control Register */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ @@ -699,14 +699,14 @@ #define SCCR_TSEC2CM_SHIFT 28 #endif #define SCCR_ENCCM 0x03000000 /* ENCCM */ #define SCCR_ENCCM_SHIFT 24 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */ #define SCCR_USBMPHCM_SHIFT 22 #define SCCR_USBDRCM 0x00300000 /* USBDRCM */ #define SCCR_USBDRCM_SHIFT 20 #endif #define SCCR_PCICM 0x00010000 /* PCICM */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \ | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM) #endif @@ -726,7 +726,7 @@ #define PMCCR_DLPEN 0x00000002 /* DDR SD #if defined (CONFIG_MPC8360) #define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */ #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN) -#elif defined (CONFIG_MPC8349) +#elif defined (CONFIG_MPC834X) #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) #endif u32 pmcer; /* PMC Event Register */ @@ -738,7 +738,7 @@ #define PMCMR_RES ~(PMCMR_PMCIE) u8 res0[0xF4]; } pmc83xx_t; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) /* * general purpose I/O module */ @@ -1173,7 +1173,7 @@ #define LCRR_CLKDIV_SHIFT 0 u8 res8[0xF00]; } lbus83xx_t; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) /* * Serial Peripheral Interface */ @@ -1403,18 +1403,18 @@ #define EATCR_ES_MASK 0x000f0000 /* err #define EATCR_ES_EM 0x00000000 /* external master */ #define EATCR_ES_DMA 0x00050000 #define EATCR_CMD_MASK 0x0000f000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */ #endif #define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define EATCR_HPB 0x00000004 /* high parity bit */ #endif #define EATCR_PB 0x00000002 /* parity bit */ #define EATCR_VI 0x00000001 /* error information valid */ u32 eacr; u32 eeacr; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u32 edlcr; u32 edhcr; #elif defined (CONFIG_MPC8360) @@ -1477,7 +1477,7 @@ #define PIWAR_IWS_1G 0x0000001D #define PIWAR_IWS_2G 0x0000001E } pcictrl83xx_t; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) /* * USB */ @@ -1988,7 +1988,7 @@ typedef struct immap { reset83xx_t reset; /* Reset Module */ clk83xx_t clk; /* System Clock Module */ pmc83xx_t pmc; /* Power Management Control Module */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) gpio83xx_t pgio[2]; /* general purpose I/O module */ #elif defined (CONFIG_MPC8360) qepi83xx_t qepi; /* QE Ports Interrupts Registers */ @@ -1999,7 +1999,7 @@ #if defined (CONFIG_MPC8360) #endif u8 DDL_DDR[0x100]; u8 DDL_LBIU[0x100]; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u8 res1[0xE00]; #elif defined (CONFIG_MPC8360) u8 res1[0x200]; @@ -2010,7 +2010,7 @@ #endif fsl_i2c_t i2c[2]; /* I2C Controllers */ u8 res2[0x1300]; duart83xx_t duart[2]; /* DUART */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u8 res3[0x900]; lbus83xx_t lbus; /* Local Bus Controller Registers */ u8 res4[0x1000]; @@ -2022,7 +2022,7 @@ #elif defined (CONFIG_MPC8360) u8 res4[0x2000]; #endif dma83xx_t dma; /* DMA */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ ios83xx_t ios; /* Sequencer */ pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 03dd0ca..005c043 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -140,7 +140,7 @@ #define BR_ATOM_SHIFT 2 #endif #define BR_V 0x00000001 #define BR_V_SHIFT 0 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) #elif defined (CONFIG_MPC8360) #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V) @@ -227,7 +227,7 @@ #define OR_SDRAM_EAD_SHIFT 0 #define HRCWH_PCI_AGENT 0x00000000 #define HRCWH_PCI_HOST 0x80000000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define HRCWH_32_BIT_PCI 0x00000000 #define HRCWH_64_BIT_PCI 0x40000000 #endif @@ -235,7 +235,7 @@ #endif #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 #elif defined (CONFIG_MPC8360) @@ -258,14 +258,14 @@ #define HRCWH_SW_WATCHDOG_ENABLE 0x0 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 #define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define HRCWH_TSEC1M_IN_RGMII 0x00000000 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 #define HRCWH_TSEC1M_IN_GMII 0x00008000

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[U-Boot-Users] Bug in MIPS linker scripts?
by Robert Deliën 14 Dec '06

14 Dec '06

Hi, I believe I have found a nasty bug in my target's linker script. And since all MIPS targets use copies of more-or-less the same linker script, I think all MIPS targets suffer from this bug. It's alignment dependent whether the bug will cause a problem or not. The symptoms can vary from hang-ups in find_cmd for any command to a hang-up if the first command in the command table is used (usually bdinfo). The cause of this problem is the 'Update GOT' part in the function relocate in cpu/mips/start.S. Depending on alignment, this update part will update a number of entries too many, corrupting whatever is next in memory: The command table. The cause of the problem is a misalignment between the _gp linker variable and the actual '.'. This is what's in board/mipstarget/u-boot.lds now: . = ALIGN(4); .sdata : { *(.sdata) } _gp = ALIGN(16); __got_start = .; .got : { *(.got) } __got_end = .; .sdata : { *(.sdata) } __u_boot_cmd_start = .; And this is what it's supposed to be: . = ALIGN(4); .sdata : { *(.sdata) } . = ALIGN(16); _gp = .; __got_start = .; .got : { *(.got) } __got_end = .; .sdata : { *(.sdata) } __u_boot_cmd_start = .; Who can give me any comments? With kind regards, Robert.

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[U-Boot-Users] [Patch] Remove a redundant semicolon in mpc8349itx.c
by Sam Song 14 Dec '06

14 Dec '06

Hi, A redundant semicolon existed in mpc8349itx.c should be removed. Signed-off-by: Sam Song <samsongshu(a)yahoo.com.cn> ___________________________________________________________ Mp3疯狂搜-新歌热歌高速下 http://music.yahoo.com.cn/?source=mail_mailbox_footer

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[U-Boot-Users] [PATCH] Proposed change to PL010 serial driver (fixed)
by Robert Deliën 14 Dec '06

14 Dec '06

Hi, Thanks to the valuable review and feedback of Daniel Hobi I have now fixed the macro in my earlier proposed patch for the PL010 serial port driver. This fix increases round-off accuracy of the UART_PL010_BAUD2DIVISOR macro. Below is my original comment for this patch: I am currently cleaning up my patch that provides ADM5120 support in U-Boot. But before submitting it I'd like to propose a change to the PL010 serial port driver. As far as I know, the PL010 uart is mostly used in ARM based SoCs. It's currently implemented for big endian only. The ADM5120 is MIPS based and has two PL010 serial ports on board. Most of the targets using the ADM5120 are configured for little endian mode. The patch below replaces the IO_READ and IO_WRITE macros with the readl and writel functions from asm/io.h, the designated functions for reading from and writing to IO, swapping endianness if necessary. It also replaces the various bitrate macros with one macro containing a unified bitrate calculation formula, using the newly introduced CFG_UART_PL010_CLOCK macro. The only other target using this serial port driver is intergratorap.h. I have backward calculated the uart clock for this target and added it to its configuration. With kind regards, Robert.

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[U-Boot-Users] how to set active partition in the u-boot?
by thomas.luo 14 Dec '06

14 Dec '06

hi,all how to set active partition in the u-boot? the problem: i'm partion the nand to 3 partions. and the second partion is the jffs file system. how do i set the active partition to 2? thanks Br Thomas

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[U-Boot-Users] [PATCH] for u-boot 1.1.6 nand IDS
by thomas.luo 14 Dec '06

14 Dec '06

Dear All: i found an bug in the u-boot when using 512MiB NAND flash. there have two type of flash defined it's ID as 0xDC. But In the MTD driver, the smallblock is abandoned. BR Thomas here list the patch. ---------------------------------------------------------------------------- --- u-boot-1.1.6.org/drivers/nand/nand_ids.c 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/drivers/nand/nand_ids.c 2006-12-14 10:12:13.000000000 +0800 @@ -67,8 +67,6 @@ struct nand_flash_dev nand_flash_ids[] = {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0}, - {"NAND 512MiB 3,3V 8-bit", 0xDC, 512, 512, 0x4000, 0}, - /* These are the new chips with large page size. The pagesize * and the erasesize is determined from the extended id bytes */

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[U-Boot-Users] CFI and non-CFI
by Matvejchikov Ilya 13 Dec '06

13 Dec '06

Hi all! Some times ago, there was a discussion about non-CFI abilities of the CFI-flash driver (drivers/cfi_flash.c). I suggest to go on within few fresh ideas... Look at the attached patch for details... It is not _real_ patch, but it is like a concept-car, my concept-car. Best regards, Matvejchikov Ilya, Russia, Moscow.

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[U-Boot-Users] clock doubling and console garbage problems
by Brandon Clarke 13 Dec '06

13 Dec '06

Hi, This is my first time writing to this list so if I mess something up my apologies in advance. The platform is an 8541E running on a custom board using uboot 1.1.5. In uboot I noticed that the bdinfo is reading twice the expected vco clock speed (bd->vco) given the crystal oscillator I'm using. Also, sometimes when I add code (i.e. debug printf statements, etc.), in random locations; uboot will give me garbage on the console that has similar characteristics to a faulty baud-rate. I was curious to see if anyone has seen a clock frequency doubling behavior or this weird console characteristics when adding code to uboot? Thanks, Brandon ____________________________________________________________________________________ Cheap talk? Check out Yahoo! Messenger's low PC-to-Phone call rates. http://voice.yahoo.com

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[U-Boot-Users] Adding support to M5282Lite
by Alan Carvalho de Assis 13 Dec '06

13 Dec '06

Hi all, I want port U-Boot to M5282Lite board. To it create a new target in U-Boot Makefile and create the directory boards/m5282lite and include/configs/M5282LITE.h based on M5282EVB. Also added the SDRAM init code to initdram(). These is my main defines: TEXT_BASE = 0xFFE00000 #define CFG_LOAD_ADDR 0x20000 #define CFG_FLASH_BASE 0xffe00000 #define CFG_MONITOR_BASE (CFG_INT_FLASH_BASE + 0x400) Using the m68k-bdm-elf-gdb I am trying to start u-boot: (gdb) target bdm /dev/bdmcf0 Detected V2 core GDB target bdm connected to /dev/bdmcf0 Coldfire debug module version is 0 (5206(e)/5272/5282) (gdb) symbol u-boot Reading symbols from u-boot...done. (gdb) load u-boot Loading section .text, size 0xcd0a lma 0xffe00000 Loading section .rodata, size 0x37b1 lma 0xffe0cd0a Loading section .reloc, size 0xc3c lma 0xffe10500 Loading section .data, size 0xae8 lma 0xffe1113c Loading section .got.plt, size 0xc lma 0xffe11c24 Loading section .u_boot_cmd, size 0x378 lma 0xffe11c30 Start address 0xffe00000, load size 73571 Transfer rate: 98094 bits/sec, 500 bytes/write. (gdb) b cpu_init_f Breakpoint 1 at 0xffe04638: file cpu_init.c, line 178. (gdb) c Continuing. ^ C [New process 42000] Program received signal SIGTSTP, Stopped (user). [Switching to process 42000] 0xffe0808a in do_bootm (cmdtp=0xffffffff, flag=-1, argc=-1, argv=0xffffffff) at cmd_bootm.c:345 345 printf (" Uncompressing %s ... ", name); (gdb) But it never goes to cpu_init_f ... Am I doing some misconfiguration or some wrong step? Cheers, Alan

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[U-Boot-Users] STD_C and STDC_
by xyyiezi 13 Dec '06

13 Dec '06

Hello! Everyone,I was reading the U-boot of the mpc8260 in recent months. And I was a freshman. Yesterday,When I was reading the U-boot1.1.4\include\malloc.h, I was puzzled by the ln223 and the ln224 (#ifndef _STD_C #ifdef _STDC_). I don't understand the differeces between the "_STD_C" and "_STDC_".Could anyone can help me? Thank you very much! py

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[U-Boot-Users] what should i do (for uboot1.1.2): *** [depend] Error 2
by wanghf＠keylab.net 13 Dec '06

13 Dec '06

Hi,everyone,I ran "make"command to U-BOOT1.1.2 after the "make clean" and"make lubbock_config" commands ,but the PC(linux2.4.20)showed the information as followed: make[1]: Entering directory `/usr/u-boot-1.1.2wang/post' make[1]: `.depend' is up to date. make[1]: Leaving directory `/usr/u-boot-1.1.2wang/post' make[1]: Entering directory `/usr/u-boot-1.1.2wang/post/cpu' make[1]: *** No rule to make target `asm.S', needed by `.depend'. Stop. make[1]: Leaving directory `/usr/u-boot-1.1.2wang/post/cpu' make: *** [depend] Error 2 Please do advice. Regards, haifeng wang

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[U-Boot-Users] RTL8169 driver not work on PPC8241
by Roger Yang(楊仁存) 13 Dec '06

13 Dec '06

Hi, My ethernet can not work based on RTL8169 and MPC8241. I try to use TFTP command to load files. But It can not send out the packets. I found it caused by TxDescriptor not work. Since the owner bit on TxDescriptor can not auto clean by descriptor in the function rtl_send( ). When compile RTL8169.C, a function "virt_to_bus( )" lost. So i define it as the following #undef virt_to_bus #define virt_to_bus(x) ((unsigned long)x) Can any one advise me if this definition ok? Or anything I should check? Thanks Roger Yang

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Re: [U-Boot-Users] RTL8169 driver not work on PPC8241
by Roger Yang(楊仁存) 13 Dec '06

13 Dec '06

Hi, Wolfgang, According to your message, there is a new driver for RTL8169. Since my RTL8169 can not work based on PPC824x. How can I get the new driver your mail mentioned? Best Regards Roger Yang -----Original Message----- From: wd(a)denx.de [mailto:wd@denx.de] Sent: Wednesday, December 13, 2006 5:01 AM To: Masami Komiya Cc: Roger Yang(楊仁存); u-boot-users(a)lists.sourceforge.net Subject: Re: [U-Boot-Users] RTL8169 driver not work on PPC8241 In message <457EDE2D.9030801(a)sonare.it> you wrote: > > Attached file is a new driver for RTL8169. Ummm... "new" driver is a bit strong given the fact that you changed less than 5 % of the lines in the driver. May I ask you to submit your changes as a proper patch, with expla- nations which problems you are fixing and why you change the code the way you change it? Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de As far as the laws of mathematics refer to reality, they are not certain; and as far as they are certain, they do not refer to reality. -- Albert Einstein

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[U-Boot-Users] consuming cork
by Archie W. Bullock 13 Dec '06

13 Dec '06

I now right about issues related to Chronic Illness, environment and health for their new publication, LEADING IDEAS. All of the sudden, the fuming customer who was going to campaign against you is your best supporter. They are not based on statistical assumptions. Don't get me wrong, I am grateful that you were willing to buy her new teeth, but I think it's important that your nurses and cleaning ladies check the KFC cups in the future. Knowing the purpose of each view will help you to select the correct one. It removes unused files from your system - allowing Windows to run faster and freeing up valuable hard disk space. Without giving away Advisory Board's IP, the conference made me think about patient's decision-making in choosing a hospital. The Firefox Web browser is Open Source and free, and comes from the Mozilla Foundation. Select the paragraph you want to indent. When one of the indent buttons is selected, Word will change the indent by one tab stop. Their primary justifications for expanding their scope of care are the issues of access and patient safety in geographic regions that lack physicians. There are a multitude of other turf wars developing or that have developed. We saw the world as our partner. Anyway, if anyone has any other good articles or tips that have worked for you, I'm all ears! Always unpack everything before you start setting the system up. homeperspectivesleadershiplinksaboutscoop Post details: just a question. No time limits ,Resume anytime,No bandwith limits,No content limits at all. , Katrina, the War in Iraq, corruption, abuse of power and secrecy to name a few. Do you, as the employed leader make every argument against them? We even got a greenhouse DONATED for this purpose. com Recipes and Cooking CommunityBowlingFans. ToniArts may not be held accountable in any way if EasyCleaner affects your computer in a negative way.

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[U-Boot-Users] [PATCH] drivers/serial.c: Correct divisor calculation
by Daniel Hobi 13 Dec '06

13 Dec '06

Hi, This patch fixes the UART divisor calculation in the generic serial driver by doing a division with correct rounding. Note: There are quite a few board-specific serial drivers which calculate the UART divisor without correct rounding. These need to be fixed too. Note: The patch to drivers/serial_pl010.c proposed by Robert Deliën on 5. Dec 2006 has the same problem (macro UART_PL010_BAUD2DIVISOR). Regards, Daniel diff --git a/drivers/serial.c b/drivers/serial.c index 76425d8..c122cf4 100644 --- a/drivers/serial.c +++ b/drivers/serial.c @@ -124,6 +124,7 @@ static NS16550_t serial_ports[4] = { static int calc_divisor (NS16550_t port) { + unsigned long tmp; #ifdef CONFIG_OMAP1510 /* If can't cleanly clock 115200 set div to 1 */ if ((CFG_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) { @@ -144,7 +145,8 @@ static int calc_divisor (NS16550_t port) #else #define MODE_X_DIV 16 #endif - return (CFG_NS16550_CLK / MODE_X_DIV / gd->baudrate); + tmp = MODE_X_DIV * gd->baudrate; + return (CFG_NS16550_CLK + tmp / 2) / tmp; }

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Re: [U-Boot-Users] LAN9118 ethernet controller
by Jonas Mark (ST-FIR/ENG1) 13 Dec '06

13 Dec '06

Hello William, > Hi, Jonas, > > Sorry I missed you email until today. Thanks very much for you kind > response. You are welcome. > I did downloaded the code from SMSC and got a patch from another > developer. I think I am on the right path to make it work. If it is possible please send a patch to the U-Boot mailing list once you are done. Most likely the patch that Tim Braun posted will be of great help for you. Please always keep the mailing list on copy when replying posts. > Thanks again! > > William > On Mon, 2006-12-04 at 09:09 +0100, Jonas Mark (ST-FIR/ENG1) wrote: > > Hi William, > > > > > I have an ARM board which has a LAN9118 ethernet controller (SMSC) > > > instead of a LAN91C111 which is supported in u-boot. Is there any > > > existing patch or ongoing work to support it? > > > > To my understanding the SMSC LAN91C111 and the LAN911x family are quite > > different. So a simple patch is most likely not enough. The good news is > > that SMSC offers a Linux driver for download (see > > http://www.smsc.com/main/catalog/lan9115.html). So you could start from > > there. > > > > Regards, > > Mark Jonas Regards, Mark Jonas

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[U-Boot-Users] [Patch] Fix a compiling warning if enable DEBUG in cfi_flash.c
by Sam Song 12 Dec '06

12 Dec '06

Hi, This small patch fixes the compiling warning if enable DEBUG in cfi_flash.c. Signed-off-by: Sam Song <samsongshu(a)yahoo.com.cn> ___________________________________________________________ 雅虎免费邮箱-3.5G容量，20M附件 http://cn.mail.yahoo.com/

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[U-Boot-Users] Warnings caused by const qualifier in include/s3c2410h
by Martin Krause 12 Dec '06

12 Dec '06

Hello List, if I compile U-Boot for the smdk2410, I get the following warnings: mkr@tq-sewsrv-4:~/git/u-boot_trab2> ./MAKEALL smdk2410 Configuring for smdk2410 board... In file included from smdk2410.c:29: /home/mkr/git/u-boot_trab2/include/s3c2410.h:73: warning: type qualifiers ignored on function return type /home/mkr/git/u-boot_trab2/include/s3c2410.h:77: warning: type qualifiers ignored on function return type [...] The source of the warnings are function definitions like this (from include/s3c2410.h): static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void) { return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE; } In my opinion the 'const' qualifier for the return value is the cause of the warning. In the header file for the older S3C2400 cpu (include/s3c2400.h) the functions were defined without this qualifier: static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void) { return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE; } And with this definition the compiler produces no warnings. Are the additional 'const' qualifiers in the s3c2410.h definitions of any use? In my opinion they could be removed (without side effects??). I could provide a patch, if this is the right way to go. Regards --- Martin Krause TQ-Systems GmbH Mühlstraße 2, Gut Delling, 82229 Seefeld Tel. +49 (8153) 93 08-157, Fax +49 (8153) 93 08-7157 martin.krause(a)tqs.de www.tq-group.com

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[U-Boot-Users] about the mtd partions
by thomas.luo 12 Dec '06

12 Dec '06

Hi, every one, do you know how to support MTD partions in the u-boot MTD driver? Br Thomas

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Re: [U-Boot-Users] [DNX#2006121242000026] [PATCH 1/1] Add functions to list of exported functions
by U-Boot patch tracking system 12 Dec '06

12 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006121242000026]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006121242000026] [PATCH 1/1] Add functions to list of exported func [...]
by DENX Support System 12 Dec '06

12 Dec '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006121242000026] was created: <snip> > Additionally export the following fuctions (to make trab_config build > again): > - simple_strtol() > - strcmp() > > Also bump the ABI version to reflect this change > > Signed-off-by: Martin Krause <martin.krause(a)tqs.de> > --- > board/trab/Makefile | 1 - > common/exports.c | 2 ++ > include/_exports.h | 2 ++ > include/exports.h | 4 +++- > 4 files changed, 7 insertions(+), 2 deletions(-) </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006121242000017] unaffected new
by U-Boot patch tracking system 12 Dec '06

12 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006121242000017]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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[U-Boot-Users] [PATCH 1/1] Add functions to list of exported functions
by Martin Krause 12 Dec '06

12 Dec '06

Additionally export the following fuctions (to make trab_config build again): - simple_strtol() - strcmp() Also bump the ABI version to reflect this change Signed-off-by: Martin Krause <martin.krause(a)tqs.de> --- board/trab/Makefile | 1 - common/exports.c | 2 ++ include/_exports.h | 2 ++ include/exports.h | 4 +++- 4 files changed, 7 insertions(+), 2 deletions(-)

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[U-Boot-Users] serial debug during init
by William Oppermann 11 Dec '06

11 Dec '06

My target is a PPC 440 Spe processor. In the ./lib_ppc/board.c file there is a debug function to dump serial status during the init process. I presume there is some compile option to activate this feature! Can someone point me in the right direction please? regards, WO -- No virus found in this outgoing message. Checked by AVG Free Edition. Version: 7.1.409 / Virus Database: 268.15.15/581 - Release Date: 09/12/2006

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[U-Boot-Users] ARM versatile EB
by William Feng 11 Dec '06

11 Dec '06

Hi, In current u-boot archive, I can find support for versatile AB and PB. I could not find any support for versatile EB (emulation board). Has anyone tried using u-boot on this board? Is there a patch available to add this support? Thanks, William

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