December 2006 - U-Boot

[U-Boot-Users] SMC91111 driver
by Wang, Qingjun 01 Dec '06

01 Dec '06

Hi, I am developing a new board which uses LAN91C1111. I wrote the commands in board.h file as: #define CONFIG_DRIVER_SMC91111 #define CONFIG_SMC91111_BASE 0x2A000000 #undef CONFIG_SMC91111_EXT_PHY #undef CONFIG_SMC_USE_32_BITS After I got prompt in SuperTerm, and typed "dhcp" to get ip address: I got an error of "Memory allocation failed". Can you help me with this problem? I found SMC91111.c driver is updated in 2003. Do you a new one? Thanks in advance Qingjun

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[U-Boot-Users] [PATCH] MPC8641HPCN u-boot.lds problem with ELDK 4.0
by Chris Fester 01 Dec '06

01 Dec '06

Hi all, I recently have been attempting to get u-boot working on my MPC8641HPCN evaulation board (AKA the Argo Navis platform). I faced a problem compiling the latest git source with the ELDK 4.0 and getting it to work on the board. The processor would run off into the weeds when doing the command table relocation step in lib_ppc/board.c:633. After debugging with a BDI, some head scratching, and a few google searches, it came down to an issue with the linker, which seems to have been a common problem in the past for this mail list. Please see the thread at: http://sourceware.org/ml/binutils/2005-08/msg00412.html. The information from that link is what I used to compose the patch below. (Synopsis of the above web link - the newer linker needs to be told more specifically where to put the __u_boot_cmd_start symbol, otherwise it decides to put other misc symbols between __u_boot_cmd_start and __u_boot_cmd_end, causing all sorts of funk when iterating through the command array.) After I apply this patch the u-boot is hunky-dory and happy. Happy holidays! :) Chris Fester CHANGELOG * Fix to linker script for mpc8641hpcn platform to enable a correct symbol table with ELDK 4.0 linker. diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index b34de8e..c2f6727 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -120,7 +120,7 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; + __u_boot_cmd_start = ADDR(.u_boot_cmd); .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .;

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[U-Boot-Users] cannot read flash manufact. id on 405EP with u-boot-1.1.6
by Tom Brown 01 Dec '06

01 Dec '06

Hi, We currently use u-boot-1.0.0 successfully on our 405EP SBC. Last year, we upgraded our toolchain from gcc-3.2.2-uClibc-0.9.20-binutils-2.13.2.1-linux-2.4.21-powerpc to gcc-3.4.3-uClibc-0.9.27-binutils-2.15.91.0.2-linux-2.4.27-powerpc When we made the upgrade we couldn't get u-boot-1.0.0 to compile with the new toolchain. Now, we'd like to upgrade u-boot so it compiles with the same toolchain as our firmware image. I am able to get u-boot-1.1.6 to compile with the new toolchain. However, it will not get past recognizing the flash during boot. The output is given below. As you can see, it is reading a value of 0x1f8b08 for the manufacturer type when it should be reading 0x0001 for AMD. We get the same problem when we try to use u-boot-1.1.0. Any ideas on what we need to look at? Thanks, Tom U-Boot 1.1.6.1 for the 195Eg CPU: AMCC PowerPC 405EP Rev. B at 250 MHz (PLB=125, OPB=62, EBC=31 MHz) I2C boot EEPROM disabled Internal PCI arbiter enabled 16 kB I-Cache 16 kB D-Cache I2C: ready DRAM: 16 MB Top of RAM usable for U-Boot at: 01000000 Reserving 251k for U-Boot at: 00fc1000 Reserving 256k for malloc() at: 00f81000 Reserving 140 Bytes for Board Info at: 00f80f74 Reserving 48 Bytes for Global Data at: 00f80f44 Stack Pointer at: 00f80f28 New Stack Pointer is: 00f80f28 Now running in RAM - U-Boot at: 00fc1000 FLASH: flash_get_size begin manufact type value == 1f8b08 flash_id == FLASH_UNKOWN flash_get_size end ## Unknown FLASH on Bank 0 - Size = 0x00000000 = 0 MB flash_protect ON: from 0xFFFC0000 to 0xFFFFFFFF

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[U-Boot-Users] [Patch02]AS352X:U-Boot1.1.6 patch 2 for AS352X SOC
by Luo Thomas 01 Dec '06

01 Dec '06

From:thomas.luo@austriamicrosystems. U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. Part 2: Br Signed-off-by: Thomas Luo ------------------------------------------------------------------------ ---- diff -urN u-boot-1.1.6.org/cpu/arm922t/as352x/Makefile u-boot-1.1.6/cpu/arm922t/as352x/Makefile --- u-boot-1.1.6.org/cpu/arm922t/as352x/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/Makefile 2006-11-29 17:29:07.000000000 +0800 @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = interrupts.o serial.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +####################################################################### ## + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +####################################################################### ## diff -urN u-boot-1.1.6.org/cpu/arm922t/as352x/serial.c u-boot-1.1.6/cpu/arm922t/as352x/serial.c --- u-boot-1.1.6.org/cpu/arm922t/as352x/serial.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/serial.c 2006-12-01 17:43:18.000000000 +0800 @@ -0,0 +1,145 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#if defined(CONFIG_AS352X) +#include <as352x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* +* Initialise the serial port with the given baudrate. The settings +* are always 8 data bits, no parity, 1 stop bit, no start bits. +*/ +void serial_setbrg (void) +{ + u8 controlData; + set_reg_bits32(CCU_IO,CCU_IO_UART); + + /* reset the uart + */ + set_reg_bits32(CCU_SRC, CCU_SRC_UART0); + wreg32(CCU_SRL, CCU_SRL_MAGIC_NUMBER); + clr_reg_bits32(CCU_SRC, CCU_SRC_UART0); + wreg32(CCU_SRL, 0x0); + wreg32(UART_FCTL_REG, 0); + wreg32(UART_INTEN_REG, 0); + controlData = 3; + wreg32(UART_LNCTL_REG,controlData| UART_LNCTL_DLSEN); + wreg32(UART_DLO_REG,0x68); + wreg32(UART_DHI_REG,0x0); + wreg32(UART_LNCTL_REG,controlData& (~UART_LNCTL_DLSEN)); + +} +int serial_init (void) +{ + int i; + serial_setbrg(); + for (i = 0; i < 100; i++); + return (0); +} + +/* +* Read a single byte from the serial port. Returns 1 on success, 0 +* otherwise. When the function is succesfull, the character read is +* written into its argument c. +*/ +int serial_getc (void) +{ + u8 c; + + while (!(rreg32(UART_LNSTATUS_REG) & UART_RX_DATA_READY)); + c = rreg32(UART_DATA_REG); + return c&0xff; +} + +#ifdef CONFIG_HWFLOW +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ + switch(on) { + case 0: + default: + break; /* return current */ + case 1: + hwflow = 0; /* turn on */ + break; + case -1: + hwflow = 0; /* turn off */ + break; + } + return hwflow; +} +#endif + +#ifdef CONFIG_MODEM_SUPPORT +static int be_quiet = 0; +void disable_putc(void) +{ + be_quiet = 1; +} + +void enable_putc(void) +{ + be_quiet = 0; +} +#endif + + +/* +* Output a single byte to the serial port. +*/ +void serial_putc (const char c) +{ +#ifdef CONFIG_MODEM_SUPPORT + if (be_quiet) + return; +#endif + + /* wait for room in the tx FIFO */ + while (!(rreg32(UART_LNSTATUS_REG) & UART_TX_HOLD_REG_EMPTY)); + wreg32(UART_DATA_REG,c); + + + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* +* Test whether a character is in the RX buffer +*/ +int serial_tstc (void) +{ + return (rreg32(UART_LNSTATUS_REG) & UART_RX_DATA_READY); +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#endif /* defined(CONFIG_AS352X)*/ diff -urN u-boot-1.1.6.org/cpu/arm922t/config.mk u-boot-1.1.6/cpu/arm922t/config.mk --- u-boot-1.1.6.org/cpu/arm922t/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/config.mk 2006-11-24 16:43:15.000000000 +0800 @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + + +PLATFORM_CPPFLAGS += -march=armv4 +# ======================================================================== = +# +# Supply options according to compiler version +# +# ======================================================================== = +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff -urN u-boot-1.1.6.org/cpu/arm922t/cpu.c u-boot-1.1.6/cpu/arm922t/cpu.c --- u-boot-1.1.6.org/cpu/arm922t/cpu.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/cpu.c 2006-12-01 17:43:54.000000000 +0800 @@ -0,0 +1,185 @@ +/* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Marius Groeger <mgroeger(a)sysgo.de> +* +* (C) Copyright 2002 +* Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +/* +* CPU specific code +*/ + +#include <common.h> +#include <command.h> +#include <arm922t.h> + +#ifdef CONFIG_USE_IRQ +DECLARE_GLOBAL_DATA_PTR; +#endif + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + +#ifdef MMU_DEBUG + printf ("p15/c1 is = %08lx\n", value); +#endif + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ +#ifdef MMU_DEBUG + printf ("write %08lx to p15/c1\n", value); +#endif + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM920T Technical reference Manual */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ + +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ + + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); /* get control reg. */ + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IC) != 0; +} + +#ifdef USE_922T_MMU +/* It makes no sense to use the dcache if the MMU is not enabled */ +void dcache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_DC); +} + +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + reg &= ~C1_DC; + write_p15_c1 (reg); +} + +int dcache_status (void) +{ + return (read_p15_c1 () & C1_DC) != 0; +} +#endif diff -urN u-boot-1.1.6.org/cpu/arm922t/interrupts.c u-boot-1.1.6/cpu/arm922t/interrupts.c --- u-boot-1.1.6.org/cpu/arm922t/interrupts.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/interrupts.c 2006-11-23 17:01:25.000000000 +0800 @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <arm920t.h> +#include <asm/proc-armv/ptrace.h> + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} diff -urN u-boot-1.1.6.org/cpu/arm922t/Makefile u-boot-1.1.6/cpu/arm922t/Makefile --- u-boot-1.1.6.org/cpu/arm922t/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/Makefile 2006-11-02 22:15:02.000000000 +0800 @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = cpu.o interrupts.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +####################################################################### ## + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +####################################################################### ## diff -urN u-boot-1.1.6.org/cpu/arm922t/start.S u-boot-1.1.6/cpu/arm922t/start.S --- u-boot-1.1.6.org/cpu/arm922t/start.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/start.S 2006-11-30 10:25:41.000000000 +0800 @@ -0,0 +1,353 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + + +/* + ************************************************************************ * + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************ * + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************ * + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * relocate armboot to ram + * setup stack + * jump to second stage + * + ************************************************************************ * + */ + +RAM_END: + .word 0x50000 + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word _end+200 + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word _end+400 +#endif + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + /* Set up the stack */ +stack_setup: + ldr r0, RAM_END /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + ldr r0,RAM_END + ldr r1,_bss_end + str r0,_armboot_start + add r1,r1,r0 + str r1,_bss_end + ldr r1,_bss_start + add r1,r1,r0 + str r1,_bss_start + ldr pc,_start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************ * + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************ * + */ + + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + mrc p15, 0, r0, c1, c0, 0 @ read CP15 register 1 into r0 + bic r0, r0, #0x0001 @ clear bit 0 MMU disable + bic r0, r0, #0x0004 @ clear bit 2 D-cache disable + bic r0, r0, #0x1000 @ clear bit 12 I-cache disable + bic r0, r0, #0xc0000000 @ clear bit 30,31 fast bus mode + mcr p15, 0, r0, c1, c0, 0 @ write value back + + @ invalidate all caches to have a clean startup + mov r2, #0 + mcr p15, 0, r2, c7, c7, 0 @ Invalidate D- and I-Cache + mcr p15, 0, r2, c8, c7, 0 @ invalidate all TLBs + + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + mov ip, lr + bl lowlevel_init + mov lr, ip + mov pc, lr +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + ************************************************************************ * + * + * Interrupt handling + * + ************************************************************************ * + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get pc, cpsr + add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif diff -urN u-boot-1.1.6.org/CREDITS u-boot-1.1.6/CREDITS --- u-boot-1.1.6.org/CREDITS 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/CREDITS 2006-11-30 10:30:13.000000000 +0800 @@ -465,3 +465,8 @@ E: james.macaulay(a)amirix.com D: Suppport for Amirix AP1000 W: www.amirix.com + +N: Thomas Luo +E: thomas.luo(a)austriamicrosystems.com +D: Port to ARM base SOC AS352X. +W: www.austriamicrosystems.com diff -urN u-boot-1.1.6.org/include/arm922t.h u-boot-1.1.6/include/arm922t.h --- u-boot-1.1.6.org/include/arm922t.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/arm922t.h 2006-11-23 16:30:48.000000000 +0800 @@ -0,0 +1,12 @@ +/************************************************ + * NAME : arm922t.h + * Version : 30 April 2002 * + * + * empty for now + ************************************************/ + +#ifndef __ARM922T_H__ +#define __ARM922T_H__ + + +#endif /*__ARM922T_H__*/

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[U-Boot-Users] [Patch03]AS352X:U-Boot1.1.6 patch 3 for AS352X SOC
by Luo Thomas 01 Dec '06

01 Dec '06

From:thomas.luo@austriamicrosystems. U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. Part 3: Br Signed-off-by: Thomas Luo ------------------------------------------------------------------------ ---- diff -urN u-boot-1.1.6.org/include/as352x.h u-boot-1.1.6/include/as352x.h --- u-boot-1.1.6.org/include/as352x.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/as352x.h 2006-12-01 17:42:16.000000000 +0800 @@ -0,0 +1,352 @@ +/* +* (C) Copyright 2006 +* Copyright (C) 2006 Austriamicrosystems, by thomas.luo +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ +#ifndef __AS352X_H__ +#define __AS352X_H__ + +#define AS352X_UART_CHANNELS 1 + +/* AS352X only supports 512 Byte HW ECC */ +#define AS352X_ECCSIZE 512 +#define AS352X_ECCBYTES 3 + + +/* AS352X device base addresses */ + + +/* ------------------------------------------------------------------------ +* AS352X Registers +* ------------------------------------------------------------------------ +* +*/ + + +/* AHB */ +#define AS352X_USB_BASE 0xC6000000 +#define AS352X_VIC_BASE 0xC6010000 +#define AS352X_DMAC_BASE 0xC6020000 +#define AS352X_MPMC_BASE 0xC6030000 +#define AS352X_MEMSTICK_BASE 0xC6040000 +#define AS352X_CF_IDE_BASE 0xC6050000 + +/* APB */ +#define AS352X_NAND_FLASH_BASE 0xC8000000 +#define AS352X_BIST_MANAGER_BASE 0xC8010000 +#define AS352X_SD_MCI_BASE 0xC8020000 +#define AS352X_TIMER_BASE 0xC8040000 +#define AS352X_WDT_BASE 0xC8050000 +#define AS352X_I2C_MS_BASE 0xC8060000 +#define AS352X_I2C_AUDIO_BASE 0xC8070000 +#define AS352X_SSP_BASE 0xC8080000 +#define AS352X_I2SIN_BASE 0xC8090000 +#define AS352X_I2SOUT_BASE 0xC80A0000 +#define AS352X_GPIO1_BASE 0xC80B0000 +#define AS352X_GPIO2_BASE 0xC80C0000 +#define AS352X_GPIO3_BASE 0xC80D0000 +#define AS352X_GPIO4_BASE 0xC80E0000 +#define AS352X_CGU_BASE 0xC80F0000 +#define AS352X_CCU_BASE 0xC8100000 +#define AS352X_UART0_BASE 0xC8110000 +#define AS352X_DBOP_BASE 0xC8120000 + + + + + + + + +/* ------------------------------------------------------------------------ +* AS352X control registers +* ------------------------------------------------------------------------ +*/ + +#define CCU_SRC ( (AS352X_CCU_BASE) + 0x00) +#define CCU_SRL ( (AS352X_CCU_BASE) + 0x04) +#define CCU_MEMMAP ( (AS352X_CCU_BASE) + 0x08) +#define CCU_IO ( (AS352X_CCU_BASE) + 0x0C) +#define CCU_SCON ( (AS352X_CCU_BASE) + 0x10) +#define CCU_VERS ( (AS352X_CCU_BASE) + 0x14) + + +/** +* Reset Control Lines in CCU_SRC register +**/ +#define CCU_SRC_DBOP_EN ( 1 << 24 ) +#define CCU_SRC_SPDIF_EN ( 1 << 22 ) +#define CCU_SRC_TIMER_EN ( 1 << 21 ) +#define CCU_SRC_SSP_EN ( 1 << 20 ) +#define CCU_SRC_WDO_EN ( 1 << 19 ) +#define CCU_SRC_IDE_EN ( 1 << 18 ) +#define CCU_SRC_IDE_AHB_EN ( 1 << 17 ) +#define CCU_SRC_UART0 ( 1 << 16 ) +#define CCU_SRC_NAF_EN ( 1 << 15 ) +#define CCU_SRC_SDMCI_EN ( 1 << 14 ) +#define CCU_SRC_GPIO_EN ( 1 << 13 ) +#define CCU_SRC_I2C_AUDIO_EN ( 1 << 12 ) +#define CCU_SRC_I2C_EN ( 1 << 11 ) +#define CCU_SRC_MST_EN ( 1 << 10 ) +#define CCU_SRC_I2SIN ( 1 << 9 ) +#define CCU_SRC_I2SOUT ( 1 << 8 ) +#define CCU_SRC_USB_AHB_EN ( 1 << 7 ) +#define CCU_SRC_USB_PHY_EN ( 1 << 6 ) +#define CCU_SRC_DMAC_EN ( 1 << 5 ) +#define CCU_SRC_VIC_EN ( 1 << 4 ) + +/** +* Magic number for CCU_SRL for reset. +**/ +#define CCU_SRL_MAGIC_NUMBER 0x1A720212 + +/** +* Chip select lines for NAF. Use these constants to select/deselct the CE lines +* for NAND flashes in Register CCU_IO. +**/ +#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 ) +#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 ) +#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 ) +#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 ) + +/* CCU IO Select/Deselect IDE */ +#define CCU_IO_IDE ( 1 << 5 ) + +/* CCU IO Select/desect I2C */ +#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 ) + +/* CCU IO Select/desect UART */ +#define CCU_IO_UART0 ( 1 << 0 ) + + +#define CCU_RESET_ALL_BUT_MEMORY \ + ( CCU_SRC_DBOP_EN \ + | CCU_SRC_SPDIF_EN \ + | CCU_SRC_TIMER_EN \ + | CCU_SRC_SSP_EN \ + | CCU_SRC_WDO_EN \ + | CCU_SRC_IDE_EN \ + | CCU_SRC_IDE_AHB_EN \ + | CCU_SRC_UART0 \ + | CCU_SRC_NAF_EN \ + | CCU_SRC_SDMCI_EN \ + | CCU_SRC_GPIO_EN \ + | CCU_SRC_I2C_AUDIO_EN \ + | CCU_SRC_I2C_EN \ + | CCU_SRC_MST_EN \ + | CCU_SRC_I2SIN \ + | CCU_SRC_I2SOUT \ + | CCU_SRC_USB_AHB_EN \ + | CCU_SRC_USB_PHY_EN \ + | CCU_SRC_DMAC_EN \ + | CCU_SRC_VIC_EN \ + ) + +/** +* Magic number for CCU_SRL for reset. +**/ +#define CCU_SRL_MAGIC_NUMBER 0x1A720212 + +/** +* Chip select lines for NAF. Use these constants to select/deselct the CE lines +* for NAND flashes in Register CCU_IO. +**/ +#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 ) +#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 ) +#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 ) +#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 ) + +/* CCU IO Select/Deselect IDE */ +#define CCU_IO_IDE ( 1 << 5 ) + +/* CCU IO Select/desect I2C */ +#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 ) + +/* CCU IO Select/desect UART */ +#define CCU_IO_UART ( 1 << 0 ) +/* ------------------------------------------------------------------------ +* AS352X clock control registers +* ------------------------------------------------------------------------ +*/ + +#define CGU_REG_PLLA ( (AS352X_CGU_BASE) + 0x00 ) +#define CGU_REG_PLLB ( (AS352X_CGU_BASE) + 0x04 ) +#define CGU_REG_PLLASUP ( (AS352X_CGU_BASE) + 0x08 ) +#define CGU_REG_PLLBSUP ( (AS352X_CGU_BASE) + 0x0C ) +#define CGU_REG_PROC ( (AS352X_CGU_BASE) + 0x10 ) +#define CGU_REG_PERI ( (AS352X_CGU_BASE) + 0x14 ) +#define CGU_REG_AUDIO ( (AS352X_CGU_BASE) + 0x18 ) +#define CGU_REG_USB ( (AS352X_CGU_BASE) + 0x1C ) +#define CGU_REG_INTCTRL ( (AS352X_CGU_BASE) + 0x20 ) +#define CGU_REG_IRQ ( (AS352X_CGU_BASE) + 0x24 ) +#define CGU_REG_COUNTA ( (AS352X_CGU_BASE) + 0x28 ) +#define CGU_REG_COUNTB ( (AS352X_CGU_BASE) + 0x2C ) +#define CGU_REG_IDE ( (AS352X_CGU_BASE) + 0x30 ) +#define CGU_REG_MEMSTICK ( (AS352X_CGU_BASE) + 0x34 ) +#define CGU_REG_DBOP ( (AS352X_CGU_BASE) + 0x38 ) + + +/* --- are disabled after reset --- */ +#define CGU_DMA_CLOCK_ENABLE ( 1 << 22 ) /* dma */ +#define CGU_USB_CLOCK_ENABLE ( 1 << 21 ) /* usb */ +#define CGU_I2SOUT_APB_CLOCK_ENABLE ( 1 << 20 ) /* i2sout */ +#define CGU_I2SIN_APB_CLOCK_ENABLE ( 1 << 19 ) /* i2sin */ +#define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE ( 1 << 18 ) /* i2c master/slave */ +#define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE ( 1 << 17 ) /* i2c audio master */ +#define CGU_GPIO_CLOCK_ENABLE ( 1 << 16 ) /* gpio */ +#define CGU_MCI_CLOCK_ENABLE ( 1 << 15 ) /* mmc + sd */ +#define CGU_NAF_CLOCK_ENABLE ( 1 << 14 ) /* naf */ +#define CGU_UART_APB_CLOCK_ENABLE ( 1 << 13 ) /* uart */ +#define CGU_WDOCNT_CLOCK_ENABLE ( 1 << 12 ) /* watchdog counter */ +#define CGU_WDOIF_CLOCK_ENABLE ( 1 << 11 ) /* watchdog timer module */ +#define CGU_SSP_CLOCK_ENABLE ( 1 << 10 ) /* ssp */ +#define CGU_TIMER1_CLOCK_ENABLE ( 1 << 9 ) /* timer 1 */ +#define CGU_TIMER2_CLOCK_ENABLE ( 1 << 8 ) /* timer 2 */ +#define CGU_TIMERIF_CLOCK_ENABLE ( 1 << 7 ) /* timer interface */ + +/** ------------------------------------------------------------------ +* Number of cycles to wait before cgu is safely locked. +**/ +#define CGU_LOCK_CNT 0xFF + +/* FIFO depth is 16 for tx and rx fifo */ +#define UART_FIFO_DEPTH 16 + +/* ------------------- UART Line Control Register bit fields -------------------- */ + +#define UART_LNCTL_DLSEN (1 << 7) /* Device latch select bit */ + + +/* -------------- UART Interrupt Control Register bit fields --------------- */ + +#define UART_INTR_RXDRDY 0x1 /* Data ready interrupt */ +#define UART_INTR_TXEMT 0x2 /* Transmit data empty interrupt */ +#define UART_INTR_RXLINESTATUS 0x4 /* Receive line status interrupt */ + +/* ------------------- UART Line Status Register bit fields -------------------- */ + +#define UART_ERRORBITS 0x1E +#define UART_RX_DATA_READY (1 << 0) +#define UART_TX_HOLD_REG_EMPTY (1 << 5) + +/* ------------------- FIFO CNTL Register contants -------------------*/ + +#define UART_FIFO_EN (1 << 0) /* Enable the UART FIFO */ +#define UART_TX_FIFO_RST (1 << 1) /* Enable the UART FIFO */ +#define UART_RX_FIFO_RST (1 << 2) +#define UART_RXFIFO_TRIGLVL_1 (0 << 4) /* RX FIFO TRIGGER_LEVEL 1 */ +#define UART_RXFIFO_TRIGLVL_4 0x08 /* RX FIFO TRIGGER_LEVEL 4 */ +#define UART_RXFIFO_TRIGLVL_8 0x10 /* RX FIFO TRIGGER_LEVEL 8 */ +#define UART_RXFIFO_TRIGLVL_14 0x18 /* RX FIFO TRIGGER_LEVEL 14 */ + + +/* ------------------- FIFO status Register contants ------------------*/ +#define UART_TX_FIFO_FULL (1 << 0) +#define UART_RX_FIFO_FULL (1 << 1) +#define UART_TX_FIFO_EMPTY (1 << 2) +#define UART_RX_FIFO_EMPTY (1 << 3) + + +/* ----------------------- defines ---------------------------------------- */ + +#define UART_DATA_REG ( (AS352X_UART0_BASE) + 0x00 ) /* Data register */ +#define UART_DLO_REG ( (AS352X_UART0_BASE) + 0x00 ) /* Clock divider(lower byte) register */ +#define UART_DHI_REG ( (AS352X_UART0_BASE) + 0x04 ) /* Clock divider(higher byte) register */ +#define UART_INTEN_REG ( (AS352X_UART0_BASE) + 0x04 ) /* Interrupt enable register */ +#define UART_INTSTATUS_REG ( (AS352X_UART0_BASE) + 0x08 ) /* Interrupt status register */ +#define UART_FCTL_REG ( (AS352X_UART0_BASE) + 0x0C ) /* Fifo control register */ +#define UART_FSTATUS_REG ( (AS352X_UART0_BASE) + 0x0C ) /* Fifo status register */ +#define UART_LNCTL_REG ( (AS352X_UART0_BASE) + 0x10 ) /* Line control register */ +#define UART_LNSTATUS_REG ( (AS352X_UART0_BASE) + 0x14 ) /* Line status register */ + + +#define TIMER_LOAD ( (AS352X_TIMER_BASE) + 0x00 ) /* 32-bit width */ +#define TIMER_VALUE ( (AS352X_TIMER_BASE) + 0x04 ) /* 32 bit width */ +#define TIMER_CONTROL ( (AS352X_TIMER_BASE) + 0x08 ) /* 8 bit width */ +#define TIMER_INTCLR ( (AS352X_TIMER_BASE) + 0x0C ) /* clears ir by write access */ +#define TIMER_RIS ( (AS352X_TIMER_BASE) + 0x10 ) /* 1 bit width */ +#define TIMER_MIS ( (AS352X_TIMER_BASE) + 0x14 ) /* 1 bit width */ + +/** +* Counter/Timer control register bits +**/ +#define TIMER_ENABLE 0x80 +#define TIMER_PERIODIC 0x40 +#define TIMER_INT_ENABLE 0x20 +#define TIMER_32_BIT 0x02 +#define TIMER_ONE_SHOT 0x01 +#define TIMER_PRESCALE_1 0x00 +#define TIMER_PRESCALE_16 0x04 +#define TIMER_PRESCALE_256 0x08 + + + +#define NAF_CONFIG ( (AS352X_NAND_FLASH_BASE) + 0x00 ) +#define NAF_CONTROL ( (AS352X_NAND_FLASH_BASE) + 0x04 ) +#define NAF_ECC ( (AS352X_NAND_FLASH_BASE) + 0x08 ) +#define NAF_DATA ( (AS352X_NAND_FLASH_BASE) + 0x0C ) +#define NAF_MODE ( (AS352X_NAND_FLASH_BASE) + 0x10 ) +#define NAF_STATUS ( (AS352X_NAND_FLASH_BASE) + 0x14 ) +#define NAF_MASK ( (AS352X_NAND_FLASH_BASE) + 0x18 ) +#define NAF_FIFODATA ( (AS352X_NAND_FLASH_BASE) + 0x1C ) +#define NAF_WORDS ( (AS352X_NAND_FLASH_BASE) + 0x20 ) +#define NAF_CLEAR ( (AS352X_NAND_FLASH_BASE) + 0x24 ) +#define NAF_TEST ( (AS352X_NAND_FLASH_BASE) + 0x28 ) + + + +#define set_reg_bits32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) |= ( (u32)(value) ) ) + + +#define clr_reg_bits32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) &= ( ~( (u32)(value) ) ) ) + +#define rreg32( registerAddress ) \ + ( *( ( const volatile u32 * )( registerAddress ) ) ) + +#define wreg32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) = ( (u32)(value) ) ) + + + +#define rreg16( registerAddress ) \ + ( *( ( const volatile u16 * )( registerAddress ) ) ) + +#define wreg16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) = ( (u16)(value) ) ) + +#define set_reg_bits16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) |= ( (u16)(value) ) ) + +#define clr_reg_bits16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) &= ( ~( (u16)(value) ) ) ) + + +#define rreg8( registerAddress ) \ + ( *( ( const volatile u8 * )( registerAddress ) ) ) + +#define wreg8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) = ( (u8)(value) ) ) + +#define set_reg_bits8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) |= ( (u8)(value) ) ) + +#define clr_reg_bits8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) &= ( ~( (u8)(value) ) ) ) +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#endif /*__AS352X_H__*/ diff -urN u-boot-1.1.6.org/include/asm-arm/mach-types.h u-boot-1.1.6/include/asm-arm/mach-types.h --- u-boot-1.1.6.org/include/asm-arm/mach-types.h 2006-12-01 17:49:35.000000000 +0800 +++ u-boot-1.1.6/include/asm-arm/mach-types.h 2006-12-01 18:01:45.000000000 +0800 @@ -737,6 +737,7 @@ #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 #define MACH_TYPE_PDNB3 1002 +#define MACH_TYPE_AS352X 1166 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -6054,7 +6055,7 @@ # define machine_is_ess710() (0) #endif -#ifdef CONFIG_MACH_MX3ADS +#ifdef CONFIG_MACH_MX31ADS # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type @@ -9401,6 +9402,18 @@ #else # define machine_is_mp2usb() (0) #endif +#ifdef CONFIG_MACH_AS352X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS352X +# endif +# define machine_is_as352x() (machine_arch_type == MACH_TYPE_AS352X) +#else +# define machine_is_as352x() (0) +#endif + /* * These have not yet been registered diff -urN u-boot-1.1.6.org/include/configs/as352xpb.h u-boot-1.1.6/include/configs/as352xpb.h --- u-boot-1.1.6.org/include/configs/as352xpb.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/configs/as352xpb.h 2006-12-01 17:42:50.000000000 +0800 @@ -0,0 +1,218 @@ +/* +* (C) Copyright 2006 +* Copyright (C) 2006 Austriamicrosystems, by thomas.luo +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* +* High Level Configuration Options +* (easy to change) +*/ +#define CONFIG_ARM922T 1 /* This is an ARM922T Core */ +#define CONFIG_AS352X 1 /* in a AS352X SoC */ +#define CONFIG_AS352XPB 1 /* on a AS352XPB Board */ +#define CFG_NO_FLASH 1 + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 24000000/* the AS352XPB has 24MHz input clock */ + + +#define USE_922T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* +* Size of malloc() pool +*/ +#define CFG_MALLOC_LEN (((CFG_ENV_SIZE + 128*1024 + 0x4000-1) /0x4000)*0x4000) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* +* Hardware drivers +*/ + +/* +* select serial console configuration +*/ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on AS352XPB */ + +/************************************************************ +* RTC +************************************************************/ +#define CONFIG_RTC_AS352X 0 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +/*********************************************************** +* Command definition +***********************************************************/ +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + /* CFG_CMD_CACHE |*/ \ + CFG_CMD_NAND | \ + /*CFG_CMD_EEPROM |*/ \ + /*CFG_CMD_I2C |*/ \ + /*CFG_CMD_USB |*/ \ + CFG_CMD_REGINFO \ + /*CFG_CMD_ELF*/ )& ~(CFG_CMD_FLASH|CFG_CMD_IMLS|CFG_CMD_NET|CFG_CMD_XIMG)) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTARGS "root=/dev/ram0 rw init=/linuxrc console=ttyS0 mem=64M" +#define CONFIG_BOOTCOMMAND "nand read 0x30007FC0 0x80000 0x200000; nand read 0x32000000 0x280000 0x200000;bootm 0x30007FC0 0x32000000" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n" +#define CONFIG_AUTOBOOT_STOP_STR "s" +/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ +/*#define CONFIG_NETMASK 255.255.255.0*/ +/*#define CONFIG_IPADDR 10.0.0.110*/ +/*#define CONFIG_SERVERIP 10.0.0.1*/ +/*#define CONFIG_BOOTFILE "" */ +/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +#undef CFG_ENV_IS_IN_FLASH +/* +* Miscellaneous configurable options +*/ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "AS352X # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 8 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x30008000 /* default load address */ + +#define CFG_HZ 1500000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_ENV_IS_IN_NAND 1 + +#define CFG_ENV_NAND_ERASE_SIZE 0x20000 +#define CFG_ENV_SIZE 0x800 /* Total Size of Environment Sector */ +#if CFG_ENV_IS_IN_NAND +#define CFG_ENV_OFFSET 0x60000 + +#endif +/*--------------------------------------------------------------------- -- +* Stack sizes +* +* The stack sizes are set up in start.S using the settings below +*/ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*--------------------------------------------------------------------- -- +* Physical Memory Map +*/ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*--------------------------------------------------------------------- -- +* FLASH and environment organization +*/ + +#define CONFIG_AMD_LV400 0 /* uncomment this if you have a LV400 flash */ +#if 0 +#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ +#endif + +#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks */ +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ +#endif +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ +#endif + + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + + +#define NAND_DISABLE_CE(nand) do { } while(0) +#define NAND_ENABLE_CE(nand) do { } while(0) + +#define NAND_WAIT_READY(nand) + +#define WRITE_NAND_COMMAND(d, adr) do{ } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ } while(0) +#define WRITE_NAND(d, adr) do{} while(0) +#define READ_NAND(adr) () +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + + + + + + +#include <as352x.h> +#define CFG_NAND_BASE NAF_DATA +#include <cmd_confdefs.h> + +#define NAND_ALLOW_ERASE_ALL + + + +#endif /* __CONFIG_H */ diff -urN u-boot-1.1.6.org/MAINTAINERS u-boot-1.1.6/MAINTAINERS --- u-boot-1.1.6.org/MAINTAINERS 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/MAINTAINERS 2006-11-30 09:40:51.000000000 +0800 @@ -566,6 +566,17 @@ Haavard Skinnemoen <hskinnemoen(a)atmel.com> ATSTK1000 AT32AP7000 +####################################################################### ## +# AS352X Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +####################################################################### ## + +Thomas Luo <thomas.luo(a)austriamicrosystems.com> + + AS352XPB AS352X + ######################################################################## # # End of MAINTAINERS list # diff -urN u-boot-1.1.6.org/MAKEALL u-boot-1.1.6/MAKEALL --- u-boot-1.1.6.org/MAKEALL 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/MAKEALL 2006-11-30 09:33:22.000000000 +0800 @@ -189,13 +189,13 @@ LIST_ARM9=" \ at91rm9200dk cmc_pu2 \ ap920t ap922_XA10 ap926ejs ap946es \ - ap966 cp920t cp922_XA10 cp926ejs \ + ap966 cp920t cp922t cp922_XA10 cp926ejs \ cp946es cp966 lpd7a400 mp2usb \ mx1ads mx1fs2 netstar omap1510inn \ omap1610h2 omap1610inn omap730p2 sbc2410x \ scb9328 smdk2400 smdk2410 trab \ VCMA9 versatile versatileab versatilepb \ - voiceblue \ + voiceblue as3525pb \ " ######################################################################## # diff -urN u-boot-1.1.6.org/Makefile u-boot-1.1.6/Makefile --- u-boot-1.1.6.org/Makefile 2006-12-01 17:49:33.000000000 +0800 +++ u-boot-1.1.6/Makefile 2006-11-30 09:38:22.000000000 +0800 @@ -2253,6 +2253,9 @@ @./mkconfig $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000 ######################################################################## # +as352xpb_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm922t as352xpb NULL as352x + ######################################################################## # ######################################################################## #

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[U-Boot-Users] [PATCH] MPC8360EMDS lowboot option
by Jerry Van Baren 01 Dec '06

01 Dec '06

Hi Dave Liu, The following patch adds a configuration to do "low boot" (HRCW.BMS = 0) as well as "high boot" (HRCW.BMS = 1). Many people, myself included :o) prefer to boot out of low memory. It has an added benefit that, if you screw up the image of of u-boot in low memory, you can switch SW9.3 FCFG and boot using the BCSR, which "high boots" (assuming you smart enough to keep a valid u-boot image at 0xFFF00000). The patch is against the top of the denx.de repository (thanks, Wolfgang, for pulling the fsl patches). gvb Add a configuration option to "low boot" (boot memory space 0x00000000) as well as the default "high boot" (0xFFF00000). Signed-off-by: Jerry Van Baren <vanbaren(a)cideas.com> --- Makefile | 18 +++++++++++++----- board/mpc8360emds/config.mk | 7 ++++++- include/configs/MPC8360EMDS.h | 14 ++++++++++++-- 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index d2534ab..684b862 100644 --- a/Makefile +++ b/Makefile @@ -1595,27 +1595,35 @@ MPC8349EMDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds MPC8360EMDS_config \ +MPC8360EMDS_lowboot_config \ MPC8360EMDS_HOST_33_config \ +MPC8360EMDS_HOST_33_lowboot_config \ MPC8360EMDS_HOST_66_config \ +MPC8360EMDS_HOST_66_lowboot_config \ +MPC8360EMDS_SLAVE_lowboot_config \ MPC8360EMDS_SLAVE_config: unconfig @echo "" >include/config.h ; \ if [ "$(findstring _HOST_,$@)" ] ; then \ - echo -n "... PCI HOST " ; \ + echo -n "...PCI HOST" ; \ echo "#define CONFIG_PCI" >>include/config.h ; \ fi ; \ if [ "$(findstring _SLAVE_,$@)" ] ; then \ - echo "...PCI SLAVE 66M" ; \ + echo "...PCI SLAVE 66M..." ; \ echo "#define CONFIG_PCI" >>include/config.h ; \ echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ fi ; \ if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "...33M ..." ; \ + echo -n " 33M..." ; \ echo "#define PCI_33M" >>include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ - echo -n "...66M..." ; \ + echo -n " 66M..." ; \ echo "#define PCI_66M" >>include/config.h ; \ - fi ; + fi ; \ + if [ "$(findstring lowboot_,$@)" ] ; then \ + echo -n " (lowboot) " ; \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8360emds/config.tmp ; \ + fi @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds MPC8349ITX_config: unconfig diff --git a/board/mpc8360emds/config.mk b/board/mpc8360emds/config.mk index 9ace886..dd560cc 100644 --- a/board/mpc8360emds/config.mk +++ b/board/mpc8360emds/config.mk @@ -25,4 +25,9 @@ # MPC8360EMDS # -TEXT_BASE = 0xFE000000 +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Default: boot high +TEXT_BASE = 0xFFF00000 +endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 8ad6551..c4fff07 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -47,6 +47,16 @@ #endif /* + * Figure out if we are booting low or high. Flash and I2C can boot either + * low or high, the BCSR is hardwired to boot high. + */ +#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ +# define BOOT_MEMORY_SPACE HRCWH_FROM_0X00000100 +#else +# define BOOT_MEMORY_SPACE HRCWH_FROM_0XFFF00100 +#endif + +/* * Hardware Reset Configuration Word */ #define CFG_HRCW_LOW (\ @@ -65,7 +75,7 @@ HRCWH_PCI1_ARBITER_DISABLE |\ HRCWH_PCICKDRV_DISABLE |\ HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ + BOOT_MEMORY_SPACE |\ HRCWH_BOOTSEQ_DISABLE |\ HRCWH_SW_WATCHDOG_DISABLE |\ HRCWH_ROM_LOC_LOCAL_16BIT) @@ -75,7 +85,7 @@ HRCWH_PCI1_ARBITER_ENABLE |\ HRCWH_PCICKDRV_ENABLE |\ HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ + BOOT_MEMORY_SPACE |\ HRCWH_BOOTSEQ_DISABLE |\ HRCWH_SW_WATCHDOG_DISABLE |\ HRCWH_ROM_LOC_LOCAL_16BIT) -- 1.4.3.3

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[U-Boot-Users] [PATCH]Fix the UEC driver bug of QE
by Dave Liu 01 Dec '06

01 Dec '06

Hello, The patch prevents the GCC tool chain from striping useful code for optimization. It will make UEC ethernet driver workable, Otherwise the UEC will fail in tx when you are using gcc4.x. but the driver can work when using gcc3.4.3. Wolfgang and Stefan, I am really sorry for that. I used gcc3.4.3 when I developed it, so I didn't find it. please apply it, TIA. CHANGELOG *Prevent the GCC from striping code for optimization, Otherwise the UEC will tx failed when you are using gcc4.x. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index f640c81..c44a5be 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1122,7 +1122,7 @@ static int uec_send(struct eth_device* d uec_private_t *uec; ucc_fast_private_t *uccf; volatile qe_bd_t *bd; - volatile u16 status; + u16 status; int i; int result = 0; @@ -1131,7 +1131,7 @@ static int uec_send(struct eth_device* d bd = uec->txBd; /* Find an empty TxBD */ - for (i = 0; BD_STATUS(bd) & TxBD_READY; i++) { + for (i = 0; bd->status & TxBD_READY; i++) { if (i > 0x100000) { printf("%s: tx buffer not ready\n", dev->name); return result; @@ -1150,13 +1150,11 @@ static int uec_send(struct eth_device* d ucc_fast_transmit_on_demand(uccf); /* Wait for buffer to be transmitted */ - status = BD_STATUS(bd); - for (i = 0; status & TxBD_READY; i++) { + for (i = 0; bd->status & TxBD_READY; i++) { if (i > 0x100000) { printf("%s: tx error\n", dev->name); return result; } - status = BD_STATUS(bd); } /* Ok, the buffer be transimitted */ @@ -1171,12 +1169,12 @@ static int uec_recv(struct eth_device* d { uec_private_t *uec = dev->priv; volatile qe_bd_t *bd; - volatile u16 status; + u16 status; u16 len; u8 *data; bd = uec->rxBd; - status = BD_STATUS(bd); + status = bd->status; while (!(status & RxBD_EMPTY)) { if (!(status & RxBD_ERROR)) { @@ -1190,7 +1188,7 @@ static int uec_recv(struct eth_device* d BD_LENGTH_SET(bd, 0); BD_STATUS_SET(bd, status | RxBD_EMPTY); BD_ADVANCE(bd, status, uec->p_rx_bd_ring); - status = BD_STATUS(bd); + status = bd->status; } uec->rxBd = bd;

1 0