December 2006 - U-Boot

[U-Boot-Users] U boot modification...
by Kiran Jammula 23 May '12

23 May '12

Hi, I am using U boot for my project. I need to configure the console while booting by prompting the user from target board LCD and Keypad. So please let me know which file of the U-boot I have to modify to achieve this. Kiran _________________________________________________________________ Special offer for NRIs! http://creative.mediaturf.net/creatives/citibankrca/rca_msntagofline.htm Get a zero balance account for next 20 years. From Citibank

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[U-Boot-Users] Ethernet loopback command
by Thomas Schäfer 17 Apr '12

17 Apr '12

Hi, The patch attached provides a command called 'ethloop' which allows to perform loopback testing on the current eth device. To achieve this, a new ethernet packet type (PROT_TEST, 0x0808, AFAIK this is not used otherwise) is introduced in net/net.c. The patch is against SF CVS from 20050307. The functions EthLoopStart, EthLoopSend and EthLoopHandler generate a simple ethernet frame with NetOurEther as destination address and packet type PROT_TEST. The looped back package is compared with the original one and a message is displayed. It is necessary to set the ethernet line into loopback mode either by programming the PHY or using a loopback plug. I've tested this on our PPC405 custom board, but it should also work on all other systems because packet generation is independent of the underlying ethernet hardware. Example usage: => mii w 0 0 7100 <-- sets PHY into loopback mode => ethloop Using ppc_405x_eth0 device Got ethernet loopback frame, len=64 loopback test successfully completed => mii w 0 0 8000 <-- PHY reset after test is completed Maybe this is also useful for others.. Best regards, Thomas Schäfer ____________________________________ Kontron Modular Computers GmbH Konrad-Zuse-Str. 9 66115 Saarbrücken Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: thomas.schaefer(a)kontron.com

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[U-Boot-Users] Add a new command to U-Boot
by Carlos Filipe Silva 20 May '09

20 May '09

Hi all! I have one doubt. How can I add a new command to U-Boot? Do I have to use only the macro U_BOOT_CMD() like files .../common/cmd_* or do I have to do more things, like defines, etc.? And after this is compliled with no error, if I type help in U-Boot's shell, do I see this command like the others? Best regards, Carlos Silva

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Re: [U-Boot-Users] NAND boot from file
by Charles Krinke 06 Mar '09

06 Mar '09

Dear Wolfgang: >Um... if this is JFFS2, then why not simply "fsload" + "bootm" ? Although I can format the flash in Linux and run fsinfo, ls or fsload in u-boot, there is a time of several minutes after Scanning JFFS2 FS Before ls can find the directory or fsload can attempt to load the uImage file. I am thinking that the 'flash_eraseall -j' command I am using may not be quite setup correctly with the u-boot environment. It should not take several minutes to pull a directory off a formatted flash. Here is what I do: Linux# flash_eraseall -j /dev/mtd0 Linux# mount -t jffs2 /dev/mtdblock0 /mnt/flash1 Linux# cp /uImage /mnt/flash1 Linux# ls /mnt/flash1 uImage is here, now reboot uboot> ls uImage is here, but it takes several minutes to get the listing. Fsload takes several minutes also. Can you think of what other assumptions I may be making that may be invalid? Charles

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[U-Boot-Users] [PATCH] part 2. Embedded PlanetBoards
by Jeff Mann 29 Nov '08

29 Nov '08

*CHANGELOG Added Support for Embedded Planet Boards EP852 EP866 and EP85xxm. See respective board config file for original author information. Merged from internal company port and QUICCstart kit into the most recent u-boot git by J. Mann, Embedded Planet, 2006-JUL-27. (this is part 2 of 2 split in half for size reasons.) (the first attempt to send this e-mail resulted in a message too big error. Sorry if you get two on acident)

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[U-Boot-Users] how to support usbtty
by zhuzhenhua 31 Aug '08

31 Aug '08

becides set CONFIG_USB_TTY, what other modification need to do for the usbtty support? thanks for any hints

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[U-Boot-Users] bootargs for partitioned nand flash
by Terence Soh 30 Apr '08

30 Apr '08

Hi, I'm trying to get a 64 MByte nand flash to be partitioned in a 32MB cramfs and 32MB jffs2 partition. In case anyone's curious, I would like the cramfs to be root as it would be a faster mount and its read-only feature. I tried to do this in the kernel by static struct mtd_partition partition_info[] = { [0] = { .name = "CRAM", .offset = 0, .size = 32 * 1024 * 1024, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, [1] = { .name = "JFFS2", .offset = 32 * 1024 * 1024, .size = MTDPART_SIZ_FULL, } }; but when I cat/proc/mtd, I get / # cat /proc/mtd dev: size erasesize name mtd0: 04000000 00004000 "rootfs" so I realise that this is affected by the bootargs passed by u-bootloader which is "bootargs=console=ttyS0 mtdparts=a9m9750:0x4000000@0(rootfs) root=mtdblock/0 rootfstype=jffs2" How should I passed the bootargs? Thanks in advance, Terence.

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[U-Boot-Users] CramFS endianness
by Laurent Pinchart 04 Mar '08

04 Mar '08

Hi everybody, I recently had a problem with cramfs endianness. cramfs tools generates a host-endian file system, which was incompatible with my big-endian MPC8260 system. I patched mkcramfs to reverse the bit order, and was able to read the cramfs image from Linux. However, even though Linux doesn't do any byte swapping, U-Boot assumes little-endian byte order and swap bytes on big-endian architectures. Why is that ? U-Boot and Linux are clearly not compatible on big-endian architectures, and I'd like to fix the problem in the right place. Laurent Pinchart

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[U-Boot-Users] Linux kernel hang (infinite loop)
by Madhu Saravana Sibi Govindan 02 Jan '08

02 Jan '08

Hello all, I'm using U-boot to bring up a custom 440gp-based board. We are able to transfer the kernel image (uImage) to the target board's memory and jump to it. But, the kernel seems to hang after that. We have verified that the board info struct and the clock frequencies are ok. We also have a BDI2000 hardware debugger with us, but we are unable to set any breakpoints using this (both using telnet or using gdb). However, I can use the telnet interface and single-step the 440gp after it seems to hang. I found that 440gp is infinitely looping through the "DataTLBError" routine. It is unclear to me what might have caused this in the first place. Has anyone seen this behaviour before? We are currently working on getting breakpoints to work using the BDI2000. Any help is greatly appreciated. Regards, G.Sibi

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Re: [U-Boot-Users] boot up u-boot from RAM
by Nghiem, Tien 26 Nov '07

26 Nov '07

Lei, You have to rebuild your code to put your code in the RAM area (other than the FLASH area). Don't use the address 0x00-0x2fff because its reserved for the exception vectors usually. I have a Lite5200 EVB. I use the address 0x20000 to put my u-boot in RAM and it works. I don't know if it could be done for the mpc8270. Tien -----Original Message----- From: u-boot-users-bounces(a)lists.sourceforge.net [mailto:u-boot-users-bounces@lists.sourceforge.net]On Behalf Of Lei Sun Sent: Thursday, October 26, 2006 4:15 PM To: u-boot-users(a)lists.sourceforge.net Subject: [U-Boot-Users] boot up u-boot from RAM Hi all: I am debugging a costomized board based on mpc8270, due to the design flaw, we can't boot up the system using flash, so I was trying to debug u-boot by loading it into the RAM. I used JTAG debugger to initialize the SDRAM and load the u-boot to 0x0, after reset, the PC is at 0x100. the disassembled code looks correct on that location, however, i can't single step start from 0x100. Is that because 0x100 is the reset vector ? I tried to put some breakpoint at some places not far from start point, but it gave me "unknown halt at 0x00000000" error after "run" command. after that the memory seems corrupted. Too bad I was using a bad debugger(Guardian-SE), I have a evaluation copy of the codewarrior plus USB+TAP from freescale. I tried that on our PQ2FADS-VR SDK. After reset, and CPU halt, I can't see any disassembed code on 0x100 (the uboot is already in the flash, and I assume it should read data from CS0 upon reset). Although the code does execute after hitting "run" button. I wonder why can't I see the disassembed code after reset? Thanks lei ------------------------------------------------------------------------- Using Tomcat but need to do more? Need to support web services, security? Get stuff done quickly with pre-integrated technology to make your job easier Download IBM WebSphere Application Server v.1.0.1 based on Apache Geronimo http://sel.as-us.falkag.net/sel?cmd=lnk&kid=120709&bid=263057&dat=121642 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] AMCC440SPe & PCI Express
by Patil, Pankaj P. 26 Nov '07

26 Nov '07

Hi, I have been using u-boot-1.1.5 on my custom 440SPe based board. I am able to establish a link on PCIE0. However, I am having trouble accessing outbound Memory on PCIE0. My memory map seetings for Outbound PCIE memory are the default U-boot Settings. I was curious if anybody's tried accessing PCIE Outbound memory with the default settings. I seem to get a bus error when I try to access that region. Thanks Pankaj

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Re: [U-Boot-Users] adding support to new board
by Jeff Mann 26 Sep '07

26 Sep '07

See http://www.freescale.com/files/32bit/doc/app_note/AN3220.pdf -JM -----Original Message----- From: u-boot-users-bounces(a)lists.sourceforge.net [mailto:u-boot-users-bounces@lists.sourceforge.net] On Behalf Of Maximus Sent: Saturday, July 15, 2006 5:31 AM To: U-Boot-Users(a)lists.sourceforge.net Subject: [U-Boot-Users] adding support to new board Hi, Is there any document (step by step) approach on how to add u-boot support to a new board? any advices, Regards, jo ------------------------------------------------------------------------ - Using Tomcat but need to do more? Need to support web services, security? Get stuff done quickly with pre-integrated technology to make your job easier Download IBM WebSphere Application Server v.1.0.1 based on Apache Geronimo http://sel.as-us.falkag.net/sel?cmd=lnk&kid=120709&bid=263057&dat=121642 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] helloworld app from flash?
by Ram 08 Sep '07

08 Sep '07

Hi, im trying to run the helloworld application 1st Option: download the hello_world.bin to some location on RAM and execute it OMAP5912OSK: tftpboot 0x10000000 hello_world.bin OMAP5912OSK: go 0x10000004 This works fine. no problem 2nd Option: I want to burn the hello_world.bin into flash. During startup i want u-boot to launch it after booting - just like the way it boots the kernel. It does not work for me, this is what i did. $ ../tools/mkimage -A arm -O linux -T kernel -C gzip -a 0x10000000 -e 0x10000004 -n 'Hello Image' -d hello_world.bin.gz hello.img I downloaded the hello.img and burnt it to 0x40000 I did: setenv bootcmd bootm 0x40000 Now when i restarted the boot i get the following:- Example expects ABI version 2 Actual U-Boot ABI version 2 Hello World argc = 0 data abort pc : [<10000058>] lr : [<10000048>] sp : 1103fc10 ip : ffffffff fp : 00000001 r10: 110996d8 r9 : 1103fca4 r8 : 1103ffdc r7 : 110996d8 r6 : 00000203 r5 : 00000000 r4 : 00000000 r3 : 00000020 r2 : 00000001 r1 : 0000000a r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... All i am doing in the hello world example is to read a line and print the line entered. I am using readline function for doing that. The programs works fine if i download it to RAM and say go. but if i flash it it does not work?. Am i missing something?. Regards, sriram

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[U-Boot-Users] u-boot for MPC8548
by Rupesh S 07 Jun '07

07 Jun '07

Hi Does u-boot support any evaluation boards based on the MPC8548 processor ? Thanks in advance -- Rupesh S

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[U-Boot-Users] PCI OHCI / testing-USB branch
by Matthias Fuchs 07 Jun '07

07 Jun '07

Hi, is someone currently working on the testing-USB branch? Does it contain the most up to date USB code? I have to add support for a PCI OHCI controller on a 405 board. This will result in some modifications (endianess + bus offsets) of drivers/usb_ohci.c. Is someone else using a PCI OHCI controller on a board that I might have missed to check? Matthias

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[U-Boot-Users] [PATCH 1/1] Support for National DP83848 Ethernet Phy
by kim M 22 May '07

22 May '07

Hi all If anyone interested, this is a patch which adds support for the National DP83848 Ethernet Phy. It allows derivatives of the at91rm9200dk board to use this Phy. You will have to edit your at91rm9200.c to use this Phy instead of the default dm9161. I think it makes sense to include it in the main branch, since it is a free feature and it does not occupy space unless used. BR Kim

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[U-Boot-Users] POST
by Maximus 09 May '07

09 May '07

Hi, My hardware has an sd/mmc card. I need to write a few tests to check if the card is connected and working before loading linux. any ideas how one should go abt it?. are there any basic tests for mmc card?. any pointers?. Regards, Jo

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[U-Boot-Users] [PATCH] simplify silent console
by Ladislav Michl 24 Apr '07

24 Apr '07

Wolfgang, silent console output is currently implemented by assigning nulldev as output device. This is a bit overcomplicated, since there is also GD_FLG_SILENT flag. Patch bellow tries to simplify silencing console by honouring GD_FLG_SILENT in console output functions, so there is no need to mess with output device. Comments? Best regards, ladis Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> CHANGELOG * Silent console code simplification. Patch by Ladislav Michl, 25 Jul 2006 diff --git a/common/console.c b/common/console.c index e9f23be..d8a0cb6 100644 --- a/common/console.c +++ b/common/console.c @@ -494,13 +494,7 @@ #ifdef CONFIG_SPLASH_SCREEN /* suppress all output if splash screen is enabled and we have a bmp to display */ if (getenv("splashimage") != NULL) - outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev"); -#endif - -#ifdef CONFIG_SILENT_CONSOLE - /* Suppress all output if "silent" mode requested */ - if (gd->flags & GD_FLG_SILENT) - outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev"); + gd->flags |= GD_FLG_SILENT; #endif /* Scan devices looking for input and output devices */ diff --git a/common/main.c b/common/main.c index ef28b3f..1ff3296 100644 --- a/common/main.c +++ b/common/main.c @@ -113,15 +113,17 @@ static __inline__ int abortboot(int boot u_int i; #ifdef CONFIG_SILENT_CONSOLE + int silent = 0; + if (gd->flags & GD_FLG_SILENT) { - /* Restore serial console */ - console_assign (stdout, "serial"); - console_assign (stderr, "serial"); + /* Restore console */ + gd->flags &= ~GD_FLG_SILENT; + silent = 1; } #endif # ifdef CONFIG_AUTOBOOT_PROMPT - printf (CONFIG_AUTOBOOT_PROMPT, bootdelay); + serial_printf (CONFIG_AUTOBOOT_PROMPT, bootdelay); # endif # ifdef CONFIG_AUTOBOOT_DELAY_STR @@ -199,14 +201,8 @@ # if DEBUG_BOOTKEYS # endif #ifdef CONFIG_SILENT_CONSOLE - if (abort) { - /* permanently enable normal console output */ - gd->flags &= ~(GD_FLG_SILENT); - } else if (gd->flags & GD_FLG_SILENT) { - /* Restore silent console */ - console_assign (stdout, "nulldev"); - console_assign (stderr, "nulldev"); - } + if (!abort && silent) + gd->flags |= GD_FLG_SILENT; #endif return abort; @@ -223,10 +219,12 @@ static __inline__ int abortboot(int boot int abort = 0; #ifdef CONFIG_SILENT_CONSOLE + int silent = 0; + if (gd->flags & GD_FLG_SILENT) { - /* Restore serial console */ - console_assign (stdout, "serial"); - console_assign (stderr, "serial"); + /* Restore output */ + silent = 1; + gd->flags &= ~GD_FLG_SILENT; } #endif @@ -275,14 +273,8 @@ # endif putc ('\n'); #ifdef CONFIG_SILENT_CONSOLE - if (abort) { - /* permanently enable normal console output */ - gd->flags &= ~(GD_FLG_SILENT); - } else if (gd->flags & GD_FLG_SILENT) { - /* Restore silent console */ - console_assign (stdout, "nulldev"); - console_assign (stderr, "nulldev"); - } + if (!abort && silent) + gd->flags |= GD_FLG_SILENT; #endif return abort;

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[U-Boot-Users] [PATCH 00/07 v2]: Add mpc7448hpc2 (Taiga) board support
by Zang Roy-r61911 19 Apr '07

19 Apr '07

This series of patches add mpc7448hpc2 board support. Mpc7448hpc2 (taiga) board is a high-performance PowerPC server reference design. This is the second version for this board support according to the feedback from mailing list. Roy Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- doc/README.mpc7448hpc2 | 181 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 181 insertions(+), 0 deletions(-) diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2 new file mode 100644 index 0000000..00fda4e --- /dev/null +++ b/doc/README.mpc7448hpc2 @@ -0,0 +1,181 @@ +Freescale MPC7448hpc2 (Taiga) board +-------------------------- +MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference +design, which is optimized for high speed throughput between the processor and +the memory, disk drive and Ethernet port subsystems. + +MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be +used in 1U or 2U rack-mount chassis', as well as in standard ATX/Micro-ATX +chassis. + + +Memory Map +---------- + +The memory map is setup for Linux to operate properly. + +The mapping is: + + Range Start Range End Definition Size + + 0x0000_0000 0x7fff_ffff DDR 2G + 0xe000_0000 0xe7ff_ffff PCI Memory 128M + 0xfa00_0000 0xfaff_ffff PCI IO 16M + 0xfb00_0000 0xfbff_ffff PCI Config 16M + 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M + 0xfe00_0000 0xfeff_ffff PromJet 16M + 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M + 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M + + +Using Flash +----------- + +The MPC7448hpc2 board has two "banks" of flash, each 8MB in size +(2^23 = 0x00800000). + +Note: the "bank" here refers to half of the flash. In fact, there is only one +bank of flash, which is divided into low and high half. Each is controlled by +the most significant bit of the address bus. The so called "bank" is only for +convenience. + +There is a switch which allows the "bank" to be selected. The switch +settings for updating flash are given below. + +The u-boot commands for copying the boot-bank into the secondary bank are +as follows: + + erase ff800000 ff880000 + cp.b ff000000 ff800000 80000 + +U-boot commands for downloading an image via tftp and flashing +it into the secondary bank: + + tftp 10000 <u-boot.bin.image> + erase ff000000 ff080000 + cp.b 10000 ff000000 80000 + + +After copying the image into the second bank of flash, be sure to toggle +SW3[4] on board before resetting the board in order to set the +secondary bank as the boot-bank. + + +Board Switches +---------------------- + + +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks and determining the PCI frequency. + +SW1[1-5]: Processor core voltage + + 12345 Core Voltage + ----- + SW1=01111 1.000V. + SW1=01101 1.100V. + SW1=01011 1.200V. + SW1=01001 1.300V only for MPC7447A. + + +SW2[1-6]: CPU core frequency + + CPU Core Frequency (MHz) + Bus Frequency + 123456 100 133 167 200 Ratio + + ------ + SW2=101100 500 667 833 1000 5x + SW2=100100 550 733 917 1100 5.5x + SW2=110100 600 800 1000 1200 6x + SW2=010100 650 866 1083 1300 6.5x + SW2=001000 700 930 1167 1400 7x + SW2=000100 750 1000 1250 1500 7.5x + SW2=110000 800 1066 1333 1600 8x + SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A + SW2=011110 900 1200 1500 1800 9x + +This table shows only a subset of available frequency options; see the CPU +hardware specifications for more information. + + +SW2[7-8]: Bus Protocol and CPU Reset Option + + 7 + - + SW2=0 System bus uses MPX bus protocol + SW2=1 System bus uses 60x bus protocol + + 8 + - + SW2=0 TSI108 can cause CPU reset + SW2=1 TSI108 can not cause CPU reset + + +SW3[1-8] system options + + 123 + --- + SW3=xxx Connected to GPIO[0:2] on TSI108 + + 4 + - + SW3=0 CPU boots from low half of flash + SW3=1 CPU boots from high half of flash + + 5 + - + SW3=0 SATA and slot2 connected to PCI bus + SW3=1 Only slot1 connected to PCI bus + + 6 + - + SW3=0 USB connected to PCI bus + SW3=1 USB disconnected from PCI bus + + 7 + - + SW3=0 Flash is write protected + SW3=1 Flash is NOT write protected + + 8 + - + SW3=0 CPU will boot from flash + SW3=1 CPU will boot from PromJet + +SW4[1-3]: System bus frequency + + Bus Frequency (MHz) + --- + SW4=010 183 + SW4=011 100 + SW4=100 133 + SW4=101 166 only for MPC7447A + SW4=110 200 only for MPC7448 + others reserved + + +SW4[4-6]: DDR2 SDRAM frequency + + Bus Frequency (MHz) + --- + SW4=000 external clock + SW4=011 system clock + SW4=100 133 + SW4=101 166 + SW4=110 200 + others reserved + + +SW4[7-8]: PCI/PCI-X frequency control + 7 + - + SW4=0 PCI/PCI-X bus operates normally + SW4=1 PCI bus forced to PCI-33 mode + + 8 + - + SW4=0 PCI-X mode at 133 MHz allowed + SW4=1 PCI-X mode limited to 100 MHz + -- 1.4.0

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[U-Boot-Users] [PATCH] Fix: Bug in MIPS linker scripts
by Robert Deliën 11 Apr '07

11 Apr '07

Hi, This patch fixes the possible alignment error between _gp and __got_start in the linker scripts of all MIPS targets. This problem has been previously reported under the title '_gp and __got_start alignment problem in u-boot.lds. Thanks for your comment Andrew! With kind regards, Robert.

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[U-Boot-Users] [GIT PULL] AVR32 relocation
by Haavard Skinnemoen 02 Mar '07

02 Mar '07

Hi Wolfgang, Please pull from the 'for-upstream' branch of git://www.atmel.no/~hskinnemoen/u-boot/avr32 for-upstream to receive the following updates: Haavard Skinnemoen (6): AVR32: Split start_u_boot into board_init_f and board_init_r AVR32: Use avr32-linux- cross-compilation prefix by default AVR32: Build position-independent u-boot AVR32: Clean up memory-map.h for at32ap7000 AVR32: Resource management rewrite AVR32: Relocate u-boot to SDRAM Makefile | 2 +- avr32_config.mk | 2 +- board/atmel/atstk1000/atstk1000.c | 13 + board/atmel/atstk1000/flash.c | 2 +- board/atmel/atstk1000/u-boot.lds | 21 +- cpu/at32ap/Makefile | 2 +- cpu/at32ap/at32ap7000/Makefile | 2 +- cpu/at32ap/at32ap7000/devices.c | 448 ------------------------ cpu/at32ap/at32ap7000/gpio.c | 77 ++++ cpu/at32ap/at32ap7000/hebi.c | 38 -- cpu/at32ap/cpu.c | 64 +++- cpu/at32ap/device.c | 126 ------- cpu/at32ap/entry.S | 3 +- cpu/at32ap/exception.c | 7 +- cpu/at32ap/hsdramc.c | 43 +-- cpu/at32ap/hsdramc1.h | 8 +- cpu/at32ap/hsmc3.h | 8 +- cpu/at32ap/interrupts.c | 14 +- cpu/at32ap/pio.c | 90 ++---- cpu/at32ap/pio2.h | 8 +- cpu/at32ap/pm.c | 127 +------- cpu/at32ap/sm.h | 8 +- cpu/at32ap/start.S | 113 +++++-- drivers/atmel_usart.c | 48 ++- drivers/atmel_usart.h | 8 +- include/asm-avr32/arch-at32ap7000/clk.h | 58 +++ include/asm-avr32/arch-at32ap7000/gpio.h | 210 +++++++++++ include/asm-avr32/arch-at32ap7000/hmatrix2.h | 8 +- include/asm-avr32/arch-at32ap7000/memory-map.h | 81 +++-- include/asm-avr32/arch-at32ap7000/platform.h | 146 -------- include/asm-avr32/global_data.h | 3 +- include/configs/atstk1002.h | 17 +- lib_avr32/avr32_linux.c | 4 +- lib_avr32/board.c | 139 +++++++- 34 files changed, 796 insertions(+), 1152 deletions(-) delete mode 100644 cpu/at32ap/at32ap7000/devices.c create mode 100644 cpu/at32ap/at32ap7000/gpio.c delete mode 100644 cpu/at32ap/at32ap7000/hebi.c delete mode 100644 cpu/at32ap/device.c create mode 100644 include/asm-avr32/arch-at32ap7000/clk.h create mode 100644 include/asm-avr32/arch-at32ap7000/gpio.h delete mode 100644 include/asm-avr32/arch-at32ap7000/platform.h After this, the avr32 port will relocate itself to the end of DRAM like the ppc port does. Attached is a combined diff with all the changes, for your reference (too big to include inline.) Quite a large number of files were touched. This is mostly early init code which assumed the .data and .bss sections were available. Now, I would like to use the cfi driver with the AT49BV6416 chip on atstk1000 instead of the custom driver, but unfortunately, it doesn't work. I'll have a closer look at it later (I think it's a combination of the geometry reversal issue and a special non-intel unlocking algorithm.) Thanks, Haavard

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[U-Boot-Users] fixup section problem.
by Txema Lopez 12 Feb '07

12 Feb '07

Hi, We are working in a MPC5200B based custom board and we are developping a tool to relocate a U-Boot (1.1.4 version) binary file to a different address in flash that it was linked. So, we have to change the GOT and FIXUP entries in the original file to point at the new address. Doing this work, we have found that, surprisingly, the FIXUP section in U-Boot is empty. When U-Boot is relocated from flash to sdram these lines in the file start.S have no effect: /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ 2: li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 addi r3,r3,-4 beq 4f 3: lwzu r4,4(r3) lwzux r0,r4,r11 add r0,r0,r11 stw r10,0(r3) stw r0,0(r4) bdnz 3b 4: Looking into the sources we have found some places where the fixup elements seem to be relocated manually, i.e.: void malloc_bin_reloc (void) { DECLARE_GLOBAL_DATA_PTR; unsigned long *p = (unsigned long *)(&av_[2]); int i; for (i=2; i<(sizeof(av_)/sizeof(mbinptr)); ++i) { *p++ += gd->reloc_off; } } Is there any reason to leave the FIXUP section empty in U-Boot? Is it a bug?. Checking the u-boot.lds file for the IceCube board we have found that fhe fixup section is included in the TEXT section and in the RELOC section, but the linker generate code only for the TEXT section. If we put it only in the RELOC section the FIXUP is not empty, the pointers adjustement in the start.S seems to work properly and the malloc_bin_reloc() function would be not necessary. Does anynone know if I'am missing something? Any clue will be welcomed. Best regards,

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[U-Boot-Users] [PATCH] Fixed cfi flash read uchar bug.
by wei.zhang＠freescale.com 11 Feb '07

11 Feb '07

From: Zhang Wei <wei.zhang(a)freescale.com> For the flash of port width more than 8bit, a completetly read must be performed. For example, 16bit port width flash must perform a ushort read. Otherwise, some flashes will get error data. Signed-off-by: Zhang Wei <wei.zhang(a)freescale.com> --- drivers/cfi_flash.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index 9b10220..f02b047 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -250,9 +250,9 @@ #endif */ inline uchar flash_read_uchar (flash_info_t * info, uint offset) { - uchar *cp; + uchar cp[FLASH_CFI_64BIT]; - cp = flash_make_addr (info, 0, offset); + memcpy(cp, flash_make_addr (info, 0, offset), info->portwidth); #if defined(__LITTLE_ENDIAN) return (cp[0]); #else -- 1.4.0

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[U-Boot-Users] builtin OF tree dtb gone
by Joakim Tjernlund 22 Jan '07

22 Jan '07

While trying out the latest u-boot from my board I noticed that support for using a prebuilt OF tree compiled int u-boot is gone. The oftree_dtb symbol is gone and I can't find a replacement. Why was it removed and is there a replacement? If there isn't a replacement I request that one is added. Jocke

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[U-Boot-Users] [PATCH] Fix PCI I/O space mapping on Freescale MPC85x0ADS
by Sergei Shtylyov 13 Jan '07

13 Jan '07

The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's describing the local address window used for the PCI I/O space accesses -- fix this and carry over the necessary changes into the MPC8560ADS code since the PCI I/O space mapping was also broken for this board (by the earlier commit 087454609e47295443af793a282cddcd91a5f49c). Add the comments clarifying how the PCI I/O space must be mapped to all the MPC85xx board config. headers. Signed-off-by: Sergei Shtylyov <sshtylyov(a)ru.mvista.com> board/mpc8540ads/init.S | 4 ++-- board/mpc8560ads/init.S | 4 ++-- include/configs/MPC8540ADS.h | 5 ++--- include/configs/MPC8541CDS.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8560ADS.h | 8 ++++---- 6 files changed, 12 insertions(+), 13 deletions(-) Index: u-boot/board/mpc8540ads/init.S =================================================================== --- u-boot.orig/board/mpc8540ads/init.S +++ u-boot/board/mpc8540ads/init.S @@ -260,8 +260,8 @@ tlb1_entry: #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* * Rapid IO at 0xc000_0000 for 512 M Index: u-boot/board/mpc8560ads/init.S =================================================================== --- u-boot.orig/board/mpc8560ads/init.S +++ u-boot/board/mpc8560ads/init.S @@ -260,8 +260,8 @@ tlb1_entry: #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* * Rapid IO at 0xc000_0000 for 512 M Index: u-boot/include/configs/MPC8540ADS.h =================================================================== --- u-boot.orig/include/configs/MPC8540ADS.h +++ u-boot/include/configs/MPC8540ADS.h @@ -330,13 +330,12 @@ /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ - -#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ Index: u-boot/include/configs/MPC8541CDS.h =================================================================== --- u-boot.orig/include/configs/MPC8541CDS.h +++ u-boot/include/configs/MPC8541CDS.h @@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE Index: u-boot/include/configs/MPC8548CDS.h =================================================================== --- u-boot.orig/include/configs/MPC8548CDS.h +++ u-boot/include/configs/MPC8548CDS.h @@ -340,7 +340,7 @@ extern unsigned long get_clock_freq(void /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE Index: u-boot/include/configs/MPC8560ADS.h =================================================================== --- u-boot.orig/include/configs/MPC8560ADS.h +++ u-boot/include/configs/MPC8560ADS.h @@ -320,14 +320,14 @@ /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI)

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