December 2006 - U-Boot

[U-Boot-Users] [PATCH] Infineon ADM5120 support
by Robert Deliën 11 Dec '06

11 Dec '06

Hi, The patch attached adds support for the Infineon ADM5120 (formerly ADMtek ADM5120) SoC to U-Boot. This SoC can be found in countless low-end router products. See http://www.linux-mips.org/wiki/Adm5120#Products_based_on_the_ADM5120 for a list of devices using the ADM5120. This patch applies cleanly if my previous patches have been applied: 1. pnx8550support.diff 2. nxp_i2c.diff 3. mips_timer2.diff 4. nxp_pci.diff 5. serial_pl010.patch (required) This U-Boot port for ADM5120 is a private project of mine. With kind regards, Robert.

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[U-Boot-Users] (no subject)
by Robert Deliën 11 Dec '06

11 Dec '06

Hi, The patch attached adds support for the Infineon ADM5120 (formerly ADMtek ADM5120) SoC to U-Boot. This SoC can be found in countless low-end router products. See http://www.linux-mips.org/wiki/Adm5120#Products_based_on_the_ADM5120 for a list of devices using the ADM5120. This patch applies cleanly if my previous patches have been applied: 1. pnx8550support.diff 2. nxp_i2c.diff 3. mips_timer2.diff 4. nxp_pci.diff 5. serial_pl010.patch (required) This U-Boot port for ADM5120 is a private project of mine. With kind regards, Robert.

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[U-Boot-Users] [PATCH] NXP Semiconductors PCI IP block driver
by Robert Deliën 11 Dec '06

11 Dec '06

Hi, The patch attached contains a driver for the NXP Semiconductors A051 PCI IP block as present on the PNX8550, PNX8535 and PNX8536. The configuration for the SilverBox development target has been updated for PCI support. This patch applies cleanly if my previous patches have been applied: 1. pnx8550support.diff 2. nxp_i2c.diff 3. mips_timer2.diff 4. nxp_pci.diff Either the driver drivers/pci_indirect.c is not processor endianness independent or the IO functionality for MIPS is a bit outdated. In order to satisfy the need of drivers/pci_indirect.c for prototypes of out_le32 etc, I have added externals for those in include/asm-mips/io.h. With kind regards, Robert.

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[U-Boot-Users] Porting U-Boot to AMCC 440 Spe
by William Oppermann 11 Dec '06

11 Dec '06

Has anybody ported U-Boot to the AMCC 440-Spe processor at PVR version 53421891. 1. We have an AMCC Yucca board using a processor with PVR 53421890 (revA silicon), the start.s code runs fine. 2. When running this same code on our board with PVR version 53421891 (revB silicon) we always have an ESR set to 0x8000000, as soon as we enable the MSR[ME] Bit is set we of course get a machine check. 3. We have tried a Denx patch to write all three words of the TLB table (to make sure no parity errors are occuring) however we still have the problem. 4. We have applied a Denx patch to write the TLB table depending on whether its revA or revB silicon. Neither patch has cured the problem? Has anybody seen this issue ? William Oppermann -- No virus found in this outgoing message. Checked by AVG Free Edition. Version: 7.1.409 / Virus Database: 268.15.15/581 - Release Date: 09/12/2006

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[U-Boot-Users] U-boot - Access to files
by Ram 11 Dec '06

11 Dec '06

Hi, Im trying to provide something like an audio interface to the bootloader. I want to play some audio - (It could be name of the command or simply "Downloading the kernel") - something like that. Basically, What i want is access to some sound data in flash, i have an small audio driver in place in the boot loader, All i want is to download the audio data file sitting somewhere in the flash and access it. It could be a file or it could be some data flashed at some predetermined location in the flash. Does u-boot provide any facility to do that or has anyone tried that in u-boot?. I know this is some kinda of a wired requirement. Please Advice, Regards, sriram

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Re: [U-Boot-Users] [PATCH] MIPS time.c fix
by Robert Deliën 11 Dec '06

11 Dec '06

> The above is not true for all MIPS. A lot (almost all) of older MIPS > parts run the cpu CP0 counter at half the core clock rate. Thanks for your feedback; I wasn't aware of this. I've encountered a couple of /2 constructions in some configurations, but I though that was just a quick fix that degrades the granularity of the timer by half in order to prevent overflows in net.c. > I would suggest changing CPU_CLOCK_RATE to CPU_CP0_COUNT_RATE since > they are not always the same. I have changed it to CFG_CP0_COUNT_RATE, if you don't mind. The IncaIP and Purple platform seem to have cores with half-speed COUNT registers so those have been fixed too. Behold the new patch ;-)

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Re: [U-Boot-Users] location independence
by TXEMA LOPEZ 11 Dec '06

11 Dec '06

Is the part of the U-Boot code that is executed from flash "location independent"? By "location independent" I mean code that can be executed from any address range (in flash) without any modification. The target is MPC85xx. I don't know the details of the MPC85xx architecture, I'm only familiar with the MPC5200 architecture but I think both cases could be familiar. The U-Boot code running from flash is linker address dependent, so you can not, by example, put an image of U-Boot in a different address that it was linked and jump to it from a smaller boot. It is because you must reassign the GOT and the FIXUP sections in a similar way It's done when U-Boot is relocated in RAM.

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Re: [U-Boot-Users] new gatherin
by Korbin Mascarenas 10 Dec '06

10 Dec '06

VfAGRA from $3. 30 and other goods. http://www.zaseruijintunhfeunhans.com through that school of his. So watch out for the Durmstrang champion as well. Okay, said Harry slowly. But... are you saying Karkaroff put my name

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[U-Boot-Users] BDI2000 CFG file for 8560
by Dig Dis 10 Dec '06

10 Dec '06

Hello, Got U-boot programmed on a custom board with the MPC8560 CPU (the board is actually derived from the sbc8560 EVB). I'm tryin to debug it with BDI2000, but I'm facing some startup problems. Before diving in, I'd like to make sure I have the proper configuration file for the BDI. Browsed the denx ftp site, but it only holds some PQ2 based files. Can anyone post a proper 8560 (preferably sbc8560 or ads8560 compatible) cfg file? If there is one, I'd kindly ask to update the ftp as well. Regards, D.

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[U-Boot-Users] AM29LV160DB flash + cfi-driver
by Andre Puschmann 10 Dec '06

10 Dec '06

Hey Folks, we got a custom PPC-based board with a 2MB AM29LV160DB flash chip. I am trying to use U-Boots CFI driver but it seems that there are still some problems with this configuration, reading e.g. the wrong vendor id. This is my output if I boot the board: 0.01> U-Boot 1.1.6-ge4bbd8da-dirty (Dec 8 2006 - 12:25:48) 0.01> 0.01> CPU: MPC5200 v1.2, Core v1.1 at 396 MHz 0.03> Bus 132 MHz, IPB 132 MHz, PCI 33 MHz 0.03> Board: MPC5200 ECU 0.03> I2C: 85 kHz, ready 0.03> DRAM: 8 MB 0.03> Top of RAM usable for U-Boot at: 00800000 0.03> Reserving 164k for U-Boot at: 007d6000 0.04> Reserving 129k for malloc() at: 007b5c00 0.04> Reserving 68 Bytes for Board Info at: 007b5bbc 0.04> Reserving 56 Bytes for Global Data at: 007b5b84 0.04> Stack Pointer at: 007b5b68 0.06> New Stack Pointer is: 007b5b68 0.10> Now running in RAM - U-Boot at: 007d6000 0.10> FLASH: flash detect cfi 0.12> fwc addr ffe00000 cmd 0 0 8bit x 8 bit 0.12> fwc addr ffe00055 cmd 98 98 8bit x 8 bit 0.12> is= cmd 51(Q) addr ffe00010 is= ff 51 0.12> fwc addr ffe00000 cmd 0 0000 16bit x 8 bit 0.14> fwc addr ffe000aa cmd 98 9898 16bit x 8 bit 0.14> is= cmd 51(Q) addr ffe00020 is= ffff 5151 0.14> fwc addr ffe00000 cmd 0 0000 16bit x 16 bit 0.14> fwc addr ffe000aa cmd 98 0098 16bit x 16 bit 0.15> is= cmd 51(Q) addr ffe00020 is= ffff 0051 0.15> fwc addr ffe00000 cmd 0 00000000 32bit x 8 bit 0.15> fwc addr ffe00154 cmd 98 98989898 32bit x 8 bit 0.15> is= cmd 51(Q) addr ffe00040 is= ffffffff 51515151 0.17> fwc addr ffe00000 cmd 0 00000000 32bit x 16 bit 0.17> fwc addr ffe00154 cmd 98 00980098 32bit x 16 bit 0.17> is= cmd 51(Q) addr ffe00040 is= ffffffff 00510051 0.18> fwc addr ffe00000 cmd 0 00000000 32bit x 32 bit 0.18> fwc addr ffe00154 cmd 98 00000098 32bit x 32 bit 0.18> is= cmd 51(Q) addr ffe00040 is= ffffffff 00000051 0.18> fwrite addr ffe00000 cmd 0 0000000000000000 64 bit x 8 bit 0.20> fwrite addr ffe002a8 cmd 98 9898989898989898 64 bit x 8 bit 0.20> is= cmd 51(Q) addr ffe00080 is= ffffffffffffffff 5151515151515151 0.21> fwrite addr ffe00000 cmd 0 0000000000000000 64 bit x 16 bit 0.21> fwrite addr ffe002a8 cmd 98 0098009800980098 64 bit x 16 bit 0.21> is= cmd 51(Q) addr ffe00080 is= ffffffffffffffff 0051005100510051 0.23> fwrite addr ffe00000 cmd 0 0000000000000000 64 bit x 32 bit 0.23> fwrite addr ffe002a8 cmd 98 0000009800000098 64 bit x 32 bit 0.23> is= cmd 51(Q) addr ffe00080 is= ffffffffffffffff 0000005100000051 0.25> fwrite addr ffe00000 cmd 0 0000000000000000 64 bit x 64 bit 0.25> fwrite addr ffe002a8 cmd 98 0000000000000098 64 bit x 64 bit 0.25> is= cmd 51(Q) addr ffe00080 is= ffffffffffffffff 0000000000000051 0.26> not found 0.26> ## Unknown FLASH on Bank 0 - Size = 0x00000000 = 0 MB 0.26> flash_protect ON: from 0xFFF00000 to 0xFFF23FFF 0.26> flash_protect ON: from 0xFFE0FA00 to 0xFFE0FDFF 0.26> *** failed *** 0.28> ### ERROR ### Please RESET the board ### There already was a discussion about this flash chip and u-boot but this thread doesn't came to an end. http://www.nabble.com/Help%3A-flash-driver-for-CFI-complient-flash-t893564.… Any hints? Best regards, Andre

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Re: [U-Boot-Users] [DNX#2006120942000014] new morticia
by U-Boot patch tracking system 09 Dec '06

09 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006120942000014]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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[U-Boot-Users] [PATCH] 83xx: Put the version (and magic) after the HRCW.
by Jerry Van Baren 08 Dec '06

08 Dec '06

Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren <vanbaren(a)cideas.com> Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren <vanbaren(a)cideas.com> --- cpu/mpc83xx/start.S | 28 ++++++++++++++++------------ 1 files changed, 16 insertions(+), 12 deletions(-) diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 0f27bb6..6ee9ec9 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -77,19 +77,11 @@ END_GOT /* - * Version string - must be in data segment because MPC83xx uses the - * first 256 bytes for the Hard Reset Configuration Word table (see - * below). Similarly, can't have the U-Boot Magic Number as the first - * thing in the image - don't know how this will affect the image tools, - * but I guess I'll find out soon. + * The Hard Reset Configuration Word (HRCW) table is in the first 64 + * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 + * times so the processor can fetch it out of flash whether the flash + * is 8, 16, 32, or 64 bits wide (hardware trickery). */ - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii " ", CONFIG_IDENT_STRING, "\0" - .text #define _HRCW_TABLE_ENTRY(w) \ .fill 8,1,(((w)>>24)&0xff); \ @@ -100,6 +92,18 @@ version_string: _HRCW_TABLE_ENTRY(CFG_HRCW_LOW) _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH) +/* + * Magic number and version string - put it after the HRCW since it + * cannot be first in flash like it is in many other processors. + */ + .long 0x27051956 /* U-Boot Magic Number */ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii " ", CONFIG_IDENT_STRING, "\0" + #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined -- 1.4.3.3

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[U-Boot-Users] [PATCH] MIPS time.c fix
by Robert Deliën 08 Dec '06

08 Dec '06

Hi, The patch attached makes the MIPS timer function get_timer return time in CFG_HZ ticks, where CFG_HZ is set to 1000 per default. The functions get_ticks and get_tbclk still work using the actual number of COUNT register increments per second, which is equal to the cpu clock frequency for MIPS processors. With kind regards, Robert.

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[U-Boot-Users] (no subject)
by s.maiti＠tcs.com 08 Dec '06

08 Dec '06

Hi All, I am using linux-2.4.25 kernel and ELDK3.1 toolchain for my Custom PPC(MPC8260) board. I am using the ramdisk image which is come along with the ELDK. With this board is coming up. Now I wanted to upgrade my busybox-0.65 to busybox-1.1.3 So I installed the new busy box and copied the bin sbin and usr directories to the filesytem . When i tried to do tftp it is giving following errors. Looking up port of RPC 100005/1 on 172.18.18.59 VFS: Mounted root (nfs filesystem). Freeing unused kernel memory: 56k init kmod: runaway modprobe loop assumed and stopped kmod: runaway modprobe loop assumed and stopped kmod: failed to exec /sbin/modprobe -s -k binfmt-4c46, errno = 8 (endless loop) With the old busybox it is working fine. Please kindly help me in this regard. Thanks and regards, Souvik Maiti Tata Consultancy Services Mailto: s.maiti(a)tcs.com Website: http://www.tcs.com =====-----=====-----===== Notice: The information contained in this e-mail message and/or attachments to it may contain confidential or privileged information. If you are not the intended recipient, any dissemination, use, review, distribution, printing or copying of the information contained in this e-mail message and/or attachments to it are strictly prohibited. If you have received this communication in error, please notify us by reply e-mail or telephone and immediately and permanently delete the message and any attachments. Thank you

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[U-Boot-Users] get_timer versus get_ticks
by Robert Deliën 08 Dec '06

08 Dec '06

Hello, I am currently straightening out lib-mips/time.c to make its granularity defined by CFG_HZ (=1000) instead of the processors frequency at which MIPS counters normally run. Can somebody explain me what the difference between get_timer and get_ticks is? Get_timer returns the current value of the timer in 1/CFG_HZ units, as I would expect. I would expect get_ticks to return the raw counter value, but that value would useless because theres no way to tell what speed its running at: get_tbclk is returning CFG_HZ and not the actual counter incremental frequency. In common/main.c get_ticks is used in conjuction with get_tbclk as if it were get_timer. This indicates either get_tbclk should be returning the actual counter incremental frequency, or get_ticks to return the same value as get_timer(0). I have looked at the PPC implementation, but that wasnt of much help because there a hardware time base is used so that solution always correct. Thanks in advance! With kind regards, Robert.

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Re: [U-Boot-Users] [DNX#2006120842000016] frontwis VIAttGRA
by DENX Support System 08 Dec '06

08 Dec '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006120842000016] was created: <snip> > Hi, your V / AGRA from $ 3, 30 http://www.plontunhandfenhadesin.com > - > Floyd, said Floyd. </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006120842000016] frontwis VIAttGRA
by U-Boot patch tracking system 08 Dec '06

08 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006120842000016]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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[U-Boot-Users] usbtty windows driver
by Chris Boger 08 Dec '06

08 Dec '06

Hello all, I *think* that I have properly ported the usbtty functionality to my XScale-based board, but I'm having some issues using it via a Windows host. I started off thinking that once implemented, this would be recognized by Windows (using the proper INF file) and use the built-in usbser.sys driver on my Windows XP host. But, I've been having a heck of a time getting that to work. My device is enumerates and passes the USB-IF chapter 9 compliance tools just fine. It shows up in the Device Manager under the Ports section as a COM port with a yellow slash over it. After digging deeper into the code and the USB documentation, I see that u-boot's usbtty doesn't seem follow the Serial Emulation Abstract Control Model (section 3.6.2.1 of the CDC spec) like I thought it did. In fact, USBTTY_INTERFACE_CLASS is defined as 0xFF (vendor specific) and not 0x02 (communication class). I also noticed that we don't use the interrupt IN endpoint at all. So, am I totally wrong here or does our usbtty require a custom Windows device driver? Best Regards, Crhis

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Re: [U-Boot-Users] MPC83xx SPI driver
by Ben Warren 08 Dec '06

08 Dec '06

On Thu, 2006-12-07 at 23:49 +0100, Joakim Tjernlund wrote: > > Didn't find any other SPI driver. Looked at the docs > for SPI in CPU mode for 832x and I don't get the command register > where one is supposed to set a bit if the char one is about to TX is > the last one in a frame. Should I just set that bit at driver > init and be done with it? > > Jocke Maybe somebody from Freescale can weigh in on this one. The 83xx driver that's in the Linux kernel doesn't touch this bit (LTS). The 834x manual says that if LTS is set before the last character is written, an LT event will occur after physical transmission is complete. In my experience LT never fires regardless of LTS state. With the 834x the LTS scheme seems a bit pointless since there's only one transmit buffer. I'm guessing the LTS isn't really implemented and the documentation was cut'n'pasted from another chip. On CPM-based chips like yours, it might be useful to queue a bunch of buffers, start them off and then be interrupted when transmission's complete, just as you would with Ethernet, HDLC or whatever. I guess it depends how big your messages are. If they're short and fit in a single buffer, you could probably just ignore LTS, mask off the LT interrupt and move on. regards, Ben

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Re: [U-Boot-Users] MPC83xx SPI driver
by Ben Warren 07 Dec '06

07 Dec '06

On Thu, 2006-12-07 at 23:31 +0100, Joakim Tjernlund wrote: > > Doubtful, since the 834x and 8313 don't have QUICC engines. While the > > control registers appear to be common among all 83xx chips, on these > > ones transmit and receive are handled by dedicated 32-bit registers > > rather than the RAM-based descriptor types found in CPMs. > > Ahh, that's probably why the 83xx spi driver in linux won't work > on 8321 either. Could you comment on that? Yes, that's correct. I don't know for sure, but it looks to me that the SPI engine on the 8321/8360 chips has more in common with the traditional PowerQUICC chips like 8xx and 82xx. Maybe there's a Linux driver for them that you could tweak? regards, Ben

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[U-Boot-Users] MPC83xx SPI driver
by Ben Warren 07 Dec '06

07 Dec '06

Hello, I'm ready to re-submit a hard SPI driver for some members of the MPC83xx family of CPUs, but am unsure where to put it. While designed for the MPC834x chips, it should also work with the upcoming MPC8313, if the online datasheet is accurate. The other 83xx chips handle SPI with a CPM, so this driver won't work there. Should I put it in cpu/mpc83xx/, drivers/, or somewhere else? And given the unusual chip compatibilities, what should the file be called? Suggestions? regards, Ben

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[U-Boot-Users] possible ELDK4 gcc compiler bug
by Matthias Fuchs 07 Dec '06

07 Dec '06

Hi, I noticed some strange behavior when using the ELDK4 gcc for compiling U-Boot for a (new) 405 target based on the current PMC405 board. The code needs to read-modify-write a memory mapped FPGA internal register. But the FPGA access does not appear in the object and therefore it is never done. Here are some code snippets: 1) my 'fifo' BSP command: int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { struct pmc405v2_fpga_s *fpga = (struct pmc405v2_fpga_s *)FPGA_BA; int i; int n = 0; u32 ctrl, data, f; char str[] = "\\|/-"; int abort = 0; int count = 0; int count2 = 0; switch(argc) { case 2: /* completely read out fifo 'n' */ if (!strcmp(argv[1],"read")) { printf(" # fifo level data\n"); printf("__________________________________\n"); for (i=0; i<FIFO_COUNT; i++) { dump_fifo(fpga, i, &n); } } else if (!strcmp(argv[1],"wait")) { got_fifoirq = 0; irq_install_handler (FPGA_IRQ, (interrupt_handler_t *)fpga_interrupt, (void*)fpga); printf(" # fifo level data\n"); printf("__________________________________\n"); fpga->ctrl |= CTRL_FIFO_IE; for (i=0; i<FIFO_COUNT; i++) { /* enable interrupts from all fifos */ printf("DEBUG1: %p:%08x\n", &(fpga->fifo[i].ctrl), fpga->fifo[i].ctrl); --> These RMW-ops do not appear in the object and is never done! --> fpga->fifo[i].ctrl |= 0x8000; printf("DEBUG2: %p:%08x\n", &(fpga->fifo[i].ctrl), fpga->fifo[i].ctrl); } while (1) { /* wait loop */ while(!got_fifoirq) { ... 2) Here are the used structs for the fpga variable: struct pmc405v2_fifo_s { volatile u32 data; volatile u32 ctrl; }; /* fifo ctrl register */ #define FIFO_OVERFLOW 0x00000400 #define FIFO_EMPTY 0x00000200 #define FIFO_FULL 0x00000100 #define FIFO_IE 0x00008000 #define FIFO_LEVEL_MASK 0x000000ff #define FIFO_COUNT 4 struct pmc405v2_fpga_s { volatile u32 ctrl; volatile u32 status; volatile u32 test1; volatile u32 test2; u32 pad1[0x60 / sizeof(u32) - 4]; volatile u32 hostctrl; /* 0x0060 */ u32 pad2[0x20 / sizeof(u32) - 1]; struct pmc405v2_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */ }; 3) Here are some lines from the objectdump. I do not find anything from the RMW-op to the FPGA register (fpga->fifo[i].ctrl |= 0x8000;). /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:556 dd8: 48 00 00 01 bl dd8 <do_fifo+0x178> dd8: R_PPC_PLTREL24 printf /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:558 ddc: 3d 20 ef 00 lis r9,-4352 de0: 80 09 00 00 lwz r0,0(r9) de4: 3b 40 00 00 li r26,0 de8: 60 00 02 00 ori r0,r0,512 dec: 90 09 00 00 stw r0,0(r9) df0: 7f 7f db 78 mr r31,r27 /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:561 for (i=0; i<FIFO_COUNT; i++) { /* enable interrupts from all fifos */ printf("DEBUG1: %p:%08x\n", df4: 83 9b 00 00 lwz r28,0(r27) df8: 80 7e 80 cc lwz r3,-32564(r30) dfc: 7f e4 fb 78 mr r4,r31 e00: 7f 85 e3 78 mr r5,r28 e04: 48 00 00 01 bl e04 <do_fifo+0x1a4> e04: R_PPC_PLTREL24 printf /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:564 &(fpga->fifo[i].ctrl), fpga->fifo[i].ctrl); fpga->fifo[i].ctrl |= 0x8000; printf("DEBUG2: %p:%08x\n", e08: 80 7e 80 d0 lwz r3,-32560(r30) e0c: 7f e4 fb 78 mr r4,r31 e10: 7f 85 e3 78 mr r5,r28 e14: 48 00 00 01 bl e14 <do_fifo+0x1b4> e14: R_PPC_PLTREL24 printf /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:559 e18: 2f 9a 00 03 cmpwi cr7,r26,3 e1c: 3b ff 00 08 addi r31,r31,8 e20: 3b 7b 00 08 addi r27,r27,8 e24: 3b 5a 00 01 addi r26,r26,1 e28: 40 9e ff cc bne+ cr7,df4 <do_fifo+0x194> e2c: 3b e0 00 00 li r31,0 e30: 48 00 00 6c b e9c <do_fifo+0x23c> /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:571 &(fpga->fifo[i].ctrl), fpga->fifo[i].ctrl); } while (1) { /* wait loop */ while(!got_fifoirq) { count++; e34: 3b ff 00 01 addi r31,r31,1 /data/home/matthias/projects/pmc405/V2_u-boot.git/board/esd/pmc405v2/cmd_pmc405v2.c:572 4) This is how the compiler is called for the code file: ppc_4xx-gcc -g -Os -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -D__KERNEL__ -DTEXT_BASE=0xFFF80000 -I/data/home/matthias/projects/pmc405/V2_u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/eldk_400/usr/bin/../lib/gcc/powerpc-linux/4.0.0/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m405 -mcpu=405 -msoft-float -Wall -Wstrict-prototypes -c -o cmd_pmc405v2.o cmd_pmc405v2.c Any idea about what I am doing wrong? BTW: Using -O0 instead of -Os makes everything fine - at least for the code above. Matthias -- ----------------------------------------------------------------------- Dipl.-Ing. Matthias Fuchs esd electronic system design gmbh http://www.esd-electronics.com Vahrenwalder Str. 207 phone: +49-511-37298-0, fax: -68 30165 Hannover, Germany -----------------------------------------------------------------------

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Re: [U-Boot-Users] [PATCH] 83xx: Put the version (and magic) after the HRCW.
by Joakim Tjernlund 07 Dec '06

07 Dec '06

> -----Original Message----- > From: u-boot-users-bounces(a)lists.sourceforge.net > [mailto:u-boot-users-bounces@lists.sourceforge.net] On Behalf > Of Jerry Van Baren > Sent: 07 December 2006 14:23 > To: Joakim Tjernlund > Cc: u-boot-users(a)lists.sourceforge.net > Subject: Re: [U-Boot-Users] [PATCH] 83xx: Put the version > (and magic) after the HRCW. > > Joakim Tjernlund wrote: > >> Sam Song wrote: > >>> Jerry Van Baren <gerald.vanbaren(a)comcast.net> wrote: > >>>> Put the version (and magic) after the HRCW. This > >>>> puts it in a fixed location in flash, not at the > >>> start > >>>> of flash but as close as we can get. > >>> Nice effort. Space saving and better version check. > >>> > >>> I guess the same change could apply for MPC8260/47/8. > >>> > >>> Thanks, > >>> > >>> Sam > >> Yes. Most boards have the version in the first bytes of > >> flash, but this > >> was not possible on the 82xx because of the HRCW, so it was put in > >> .data. This set up was copied for the 83xx (which also has a > >> HRCW). My > >> change moves it back to .text just after the HRCW. I put also the > >> u-boot magic number back in in honor of Wolfgang. ;-) > >> > >> If you change the file names in the patch, it probably would > >> apply. :-) > >> I intend to do this (perhaps literally), but ran out of > >> ambition tonight. > >> > > > > Looks almost the same as the patch I sent the other day. I am good > > with either version. > > > > Jocke > > Hi Jocke, > > Yes, your patch, and my objection to its removal of the HRCW, was the > genesis of this one. The two differences are (a) I kept the HRCW and > (b) I put the "u-boot magic number" in (no known reason to do > this, but > it Just Seemed Right[tm]). The result of (b) is that the > version starts > at flash offset 0x44 rather than 0x40. Should be NBD. (a) yeah, I don't really need this either, I just added that to give others a choice. (b) uh, I want the "u-boot magic number". If I didn't have it in my patch then it was a typo. Thanks Jocke

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Re: [U-Boot-Users] [DNX#2006120742000027] [PATCH] Add support for 8641 Rev 2 silicon.
by DENX Support System 07 Dec '06

07 Dec '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006120742000027] was created: <snip> > From: Ed Swarthout <ed.swarthout(a)freescale.com> > > Without this patch, I am unable to get to the prompt on rev 2 silicon. > Only set ddrioovcr for rev1. > > Signed-off-by: Ed Swarthout<ed.swarthout(a)freescale.com> > Signed-off-by: Jon Loeliger <jdl(a)freescale.com> > --- > cpu/mpc86xx/spd_sdram.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c > index b18e822..ac9ff81 100644 > --- a/cpu/mpc86xx/spd_sdram.c > +++ b/cpu/mpc86xx/spd_sdram.c > @@ -284,9 +284,9 @@ #endif > } > > /* > - * Adjust DDR II IO voltage biasing. It just makes it work. > + * Adjust DDR II IO voltage biasing. Rev1 only > */ > - if (spd.mem_type == SPD_MEMTYPE_DDR2) { > + if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == > SPD_MEMTYPE_DDR2)) { > gur->ddrioovcr = (0 > | 0x80000000 /* Enable */ > | 0x10000000 /* VSEL to 1.8V */ > -- > 1.4.2.3 </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006120742000036] [PATCH] Set Rev 2.x 86xx PIC in mixed mode.
by DENX Support System 07 Dec '06

07 Dec '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006120742000036] was created: <snip> > From: Haiying Wang <haiying.wang(a)freescale.com> > > Prevent false interrupt from hanging Linux as MSR[EE] is set > to enable interrupts by changing the PIC out of the default > pass through mode into mixed mode. > > Signed-off-by: Haiying Wang <haiying.wang(a)freescale.com> > Signed-off-by: Jon Loeliger <jdl(a)freescale.com> > --- > cpu/mpc86xx/interrupts.c | 20 ++++++++++++++++++++ > include/asm-ppc/immap_86xx.h | 2 ++ > 2 files changed, 22 insertions(+), 0 deletions(-) > > diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c > index 1df6cdc..49820bb 100644 > --- a/cpu/mpc86xx/interrupts.c > +++ b/cpu/mpc86xx/interrupts.c > @@ -80,6 +80,26 @@ int interrupt_init(void) > { > int ret; > > + /* > + * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to > + * implement PEX10 errata. As INT is active high, it > + * will cause core to take 0x500 interrupt. > + * > + * Due to the PIC's default pass through mode, as soon > + * as interrupts are enabled (MSR[EE] = 1), an interrupt > + * will be taken and u-boot will hang. This is due to a > + * hardware change (per an errata fix) on new revisions > + * of the board with Rev 2.x parts. > + * > + * Setting the PIC to mixed mode prevents the hang. > + */ > + if ((get_svr() & 0xf0) == 0x20) { > + volatile immap_t *immr = (immap_t *)CFG_IMMR; > + immr->im_pic.gcr = MPC86xx_PICGCR_RST; > + while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); > + immr->im_pic.gcr = MPC86xx_PICGCR_MODE; > + } > + > /* call cpu specific function from $(CPU)/interrupts.c */ > ret = interrupt_init_cpu(&decrementer_count); > > diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h > index a5552c4..0e3fc34 100644 > --- a/include/asm-ppc/immap_86xx.h > +++ b/include/asm-ppc/immap_86xx.h > @@ -721,6 +721,8 @@ typedef struct ccsr_pic { > uint frr; /* 0x41000 - Feature Reporting Register */ > char res10[28]; > uint gcr; /* 0x41020 - Global Configuration Register */ > +#define MPC86xx_PICGCR_RST 0x80000000 > +#define MPC86xx_PICGCR_MODE 0x20000000 > char res11[92]; > uint vir; /* 0x41080 - Vendor Identification Register */ > char res12[12]; > -- > 1.4.2.3 </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006120742000027] [PATCH] Add support for 8641 Rev 2 silicon.
by U-Boot patch tracking system 07 Dec '06

07 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006120742000027]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006120742000036] [PATCH] Set Rev 2.x 86xx PIC in mixed mode.
by U-Boot patch tracking system 07 Dec '06

07 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006120742000036]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006120742000018] [PATCH] Add flash cmd function to 8641HPCN ramboot
by U-Boot patch tracking system 07 Dec '06

07 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006120742000018]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006120742000018] [PATCH] Add flash cmd function to 8641HPCN ramboot [...]
by DENX Support System 07 Dec '06

07 Dec '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006120742000018] was created: <snip> > From: Jason Jin <jason.jin(a)freescale.com> > > Also fixes some commmand for 8641 HPCN ramboot case. > > Signed-off-by: Jason Jin <jason.jin(a)freescale.com> > Signed-off-by: Jon Loeliger <jdl(a)freescale.com> > --- > include/configs/MPC8641HPCN.h | 16 +++------------- > 1 files changed, 3 insertions(+), 13 deletions(-) > > diff --git a/include/configs/MPC8641HPCN.h > b/include/configs/MPC8641HPCN.h > index 4a313af..0e42fa0 100644 > --- a/include/configs/MPC8641HPCN.h > +++ b/include/configs/MPC8641HPCN.h > @@ -212,7 +212,6 @@ #undef CFG_RAMBOOT > #endif > > #if defined(CFG_RAMBOOT) > -#undef CFG_FLASH_CFI_DRIVER > #undef CONFIG_SPD_EEPROM > #define CFG_SDRAM_SIZE 256 > #endif > @@ -468,7 +467,6 @@ #ifndef CFG_RAMBOOT > #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ > #define CFG_ENV_SIZE 0x2000 > #else > - #define CFG_NO_FLASH 1 /* Flash is not usable now */ > #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ > #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) > #define CFG_ENV_SIZE 0x2000 > @@ -486,21 +484,13 @@ #if defined(CFG_RAMBOOT) > | CFG_CMD_SCSI \ > | CFG_CMD_EXT2) \ > & \ > - ~(CFG_CMD_ENV \ > - | CFG_CMD_IMLS \ > - | CFG_CMD_FLASH \ > - | CFG_CMD_LOADS)) > + ~(CFG_CMD_ENV)) > #else > #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ > | CFG_CMD_PING \ > - | CFG_CMD_I2C \ > - | CFG_CMD_SCSI \ > - | CGF_CMD_EXT2) \ > + | CFG_CMD_I2C) \ > & \ > - ~(CFG_CMD_ENV \ > - | CFG_CMD_IMLS \ > - | CFG_CMD_FLASH \ > - | CFG_CMD_LOADS)) > + ~(CFG_CMD_ENV)) > #endif > #else > #if defined(CONFIG_PCI) > -- > 1.4.2.3 </snip> Your U-Boot support team

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[U-Boot-Users] [PATCH] Set Rev 2.x 86xx PIC in mixed mode.
by Jon Loeliger 07 Dec '06

07 Dec '06

From: Haiying Wang <haiying.wang(a)freescale.com> Prevent false interrupt from hanging Linux as MSR[EE] is set to enable interrupts by changing the PIC out of the default pass through mode into mixed mode. Signed-off-by: Haiying Wang <haiying.wang(a)freescale.com> Signed-off-by: Jon Loeliger <jdl(a)freescale.com> --- cpu/mpc86xx/interrupts.c | 20 ++++++++++++++++++++ include/asm-ppc/immap_86xx.h | 2 ++ 2 files changed, 22 insertions(+), 0 deletions(-) diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 1df6cdc..49820bb 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -80,6 +80,26 @@ int interrupt_init(void) { int ret; + /* + * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to + * implement PEX10 errata. As INT is active high, it + * will cause core to take 0x500 interrupt. + * + * Due to the PIC's default pass through mode, as soon + * as interrupts are enabled (MSR[EE] = 1), an interrupt + * will be taken and u-boot will hang. This is due to a + * hardware change (per an errata fix) on new revisions + * of the board with Rev 2.x parts. + * + * Setting the PIC to mixed mode prevents the hang. + */ + if ((get_svr() & 0xf0) == 0x20) { + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_pic.gcr = MPC86xx_PICGCR_RST; + while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); + immr->im_pic.gcr = MPC86xx_PICGCR_MODE; + } + /* call cpu specific function from $(CPU)/interrupts.c */ ret = interrupt_init_cpu(&decrementer_count); diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index a5552c4..0e3fc34 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -721,6 +721,8 @@ typedef struct ccsr_pic { uint frr; /* 0x41000 - Feature Reporting Register */ char res10[28]; uint gcr; /* 0x41020 - Global Configuration Register */ +#define MPC86xx_PICGCR_RST 0x80000000 +#define MPC86xx_PICGCR_MODE 0x20000000 char res11[92]; uint vir; /* 0x41080 - Vendor Identification Register */ char res12[12]; -- 1.4.2.3

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[U-Boot-Users] [PATCH] Add support for 8641 Rev 2 silicon.
by Jon Loeliger 07 Dec '06

07 Dec '06

From: Ed Swarthout <ed.swarthout(a)freescale.com> Without this patch, I am unable to get to the prompt on rev 2 silicon. Only set ddrioovcr for rev1. Signed-off-by: Ed Swarthout<ed.swarthout(a)freescale.com> Signed-off-by: Jon Loeliger <jdl(a)freescale.com> --- cpu/mpc86xx/spd_sdram.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index b18e822..ac9ff81 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -284,9 +284,9 @@ #endif } /* - * Adjust DDR II IO voltage biasing. It just makes it work. + * Adjust DDR II IO voltage biasing. Rev1 only */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { gur->ddrioovcr = (0 | 0x80000000 /* Enable */ | 0x10000000 /* VSEL to 1.8V */ -- 1.4.2.3

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[U-Boot-Users] [PATCH] Add flash cmd function to 8641HPCN ramboot
by Jon Loeliger 07 Dec '06

07 Dec '06

From: Jason Jin <jason.jin(a)freescale.com> Also fixes some commmand for 8641 HPCN ramboot case. Signed-off-by: Jason Jin <jason.jin(a)freescale.com> Signed-off-by: Jon Loeliger <jdl(a)freescale.com> --- include/configs/MPC8641HPCN.h | 16 +++------------- 1 files changed, 3 insertions(+), 13 deletions(-) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 4a313af..0e42fa0 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -212,7 +212,6 @@ #undef CFG_RAMBOOT #endif #if defined(CFG_RAMBOOT) -#undef CFG_FLASH_CFI_DRIVER #undef CONFIG_SPD_EEPROM #define CFG_SDRAM_SIZE 256 #endif @@ -468,7 +467,6 @@ #ifndef CFG_RAMBOOT #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) #define CFG_ENV_SIZE 0x2000 @@ -486,21 +484,13 @@ #if defined(CFG_RAMBOOT) | CFG_CMD_SCSI \ | CFG_CMD_EXT2) \ & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_IMLS \ - | CFG_CMD_FLASH \ - | CFG_CMD_LOADS)) + ~(CFG_CMD_ENV)) #else #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_SCSI \ - | CGF_CMD_EXT2) \ + | CFG_CMD_I2C) \ & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_IMLS \ - | CFG_CMD_FLASH \ - | CFG_CMD_LOADS)) + ~(CFG_CMD_ENV)) #endif #else #if defined(CONFIG_PCI) -- 1.4.2.3

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Re: [U-Boot-Users] [PATCH] 83xx: Put the version (and magic) after the HRCW.
by Joakim Tjernlund 07 Dec '06

07 Dec '06

> > Sam Song wrote: > > Jerry Van Baren <gerald.vanbaren(a)comcast.net> wrote: > >> Put the version (and magic) after the HRCW. This > >> puts it in a fixed location in flash, not at the > > start > >> of flash but as close as we can get. > > > > Nice effort. Space saving and better version check. > > > > I guess the same change could apply for MPC8260/47/8. > > > > Thanks, > > > > Sam > > Yes. Most boards have the version in the first bytes of > flash, but this > was not possible on the 82xx because of the HRCW, so it was put in > .data. This set up was copied for the 83xx (which also has a > HRCW). My > change moves it back to .text just after the HRCW. I put also the > u-boot magic number back in in honor of Wolfgang. ;-) > > If you change the file names in the patch, it probably would > apply. :-) > I intend to do this (perhaps literally), but ran out of > ambition tonight. > Looks almost the same as the patch I sent the other day. I am good with either version. Jocke

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[U-Boot-Users] location independence
by cam＠sysgo.com 07 Dec '06

07 Dec '06

Hello, I have to evaluate if U-Boot fulfills an special requirement, and for that I have to answer the following: Is the part of the U-Boot code that is executed from flash "location independent"? By "location independent" I mean code that can be executed from any address range (in flash) without any modification. The target is MPC85xx. (The bootpage is obviously out of question). Best regards, Carlos Mitidieri

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[U-Boot-Users] reg usb commands
by mahendra varman 07 Dec '06

07 Dec '06

Hi Iam using U-boot 1.1.6 for a board under cmd_usb.c i can find commands for usb reset command usb start command usb device info command usb read command but I COULD NOT FIND A COMMAND FOR USB WRITE any idea?

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[U-Boot-Users] 85xx sync to msync necessary?
by Sam Song 07 Dec '06

07 Dec '06

Hi, I found that there was an unclear assembly usage on 'sync' for 85xx in current tree. On P202 of E500CORERM.pdf, it says that 'sync' has replaced by 'msync' in BOOK-E and E500. But there are still some 'sync' for 85xx at cpu/mpc85xx folder and other files like drivers/ tsec.c. I changed all 'sync' as 'msync' on my customized 8548 boards. Seems no obvious difference. Both OK. So I wonder whether we should fix it. Thoughts? Thanks, Sam ___________________________________________________________ 抢注雅虎免费邮箱-3.5G容量，20M附件！ http://cn.mail.yahoo.com

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[U-Boot-Users] [PATCH] Write YAFFS filesystem images to NAND (Updated)
by Frank Mandarino 06 Dec '06

06 Dec '06

The attached patch updates my previous patch of Sept 9th, 2006 for the latest versions of U-Boot and YAFFS. It adds two sub-commands, "write.yaffs" and "write.yaffs1", to the nand command set, which write YAFFS filesystem images generated by mkyaffs2image and mkyaffsimage from RAM to NAND flash. YAFFS images cannot be written using the normal nand write command because they contain data which must be written to the NAND OOB area. The "write.yaffs" command writes images generated by mkyaffs2image for 2048+64 NAND chips. I do not have access to this type of chip, so it has not been tested (any takers?). The "write.yaffs1" command writes images generated by mkyaffsimage for 512+16 NAND. It writes the older yaffs1 OOB format used by Linux kernels before 2.6.18, or, by defining a CFG parameter, it writes the newer OOB format used by Linux 2.6.18 and up. This patch is much simpler than the previous version because the new nand_util.c code contains most of the required functionality. It uses two CFG parameters: CFG_NAND_WRITE_YAFFS - enables the YAFFS writing code. CFG_NAND_WRITE_YAFFS1_NEW_OOB_LAYOUT - writes the OOB data in the format used by Linux 2.6.18 and up. I find it VERY convenient to write YAFFS filesystems in U-Boot, especially the Linux root filesystem. Without this patch, I need to maintain a separate non-YAFFS root filesystem in NAND so that I can boot Linux in order to update my YAFFS root filesystem. This wastes valuable NAND space and is more time-consuming. Signed-off-by: Frank Mandarino <fmandarino(a)endrelia.com> Regards, ../fam -- Frank Mandarino fmandarino(a)endrelia.com Endrelia Technologies Inc. Toronto, Ontario, Canada

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[U-Boot-Users] Access ErrorHeadline functionality has been disabled from your intranet.
by Wade Pauline 06 Dec '06

06 Dec '06

Liberal MP Paul Szabo, one of the Liberals who voted against same sex marriage last year, called Harper's motion "hollow" and said he'll vote against it. He wants to focus on bringing another Grey Cup home to Saskatchewan, he said. If you are the system administrator, please click here. Disaster recovery is preparing for the worst. And Harper has said if the House votes against changing the law to allow same-sex marriages, the matter would be settled. If you use a combination of normal and differential backups, you must have the last normal backup media set and the last differential backup sets to restore your data. Access ErrorHeadline functionality has been disabled from your intranet. If you have questions, please visit our forum. Access ErrorHeadline functionality has been disabled from your intranet. If you are the system administrator, please click here. West Vancouver police spokesman Sgt. Copying is a useful temporary method to back up files between normal and incremental backups; it does not affect other backup operations. This could be used for internet backup, disk backup, hard drive or file backups. Care should be taken to label them. If you are the system administrator, please click here. If you are the system administrator, please click here. "If we have a party vote, he'll say that I muzzled my MPs and that if I had let them vote freely the motion would have passed," Dion said of Harper. If you are the system administrator, please click here. Access ErrorHeadline functionality has been disabled from your intranet. If the backup does not fit onto one or a few CDs, it is easy to use many discs with sequential labels. Please contact your system administrator to report this fault. Link to this Article! With people, one generation is older than the following generation. File-by-file backup is far more efficient.

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[U-Boot-Users] [PATCH] Add support for AT91RM9200 NAND (Smartmedia) controller
by Frank Mandarino 06 Dec '06

06 Dec '06

The attached patch adds support for the AT91RM9200 NAND (Smartmedia) controller, allowing use of the U-Boot NAND commands on AT91RM9200-based boards which use NAND flash. It uses four CFG parameters: CFG_NAND_BASE - address of Smartmedia chip select (normally 0x40000000) CFG_NAND_AT91_CLE_BIT - address bit number used to set CLE signal CFG_NAND_AT91_ALE_BIT - address bit number used to set ALE signal CFG_NAND_CHIP_DELAY - command delay time in microseconds I have been using this code for almost a year with no problems on our custom AT91RM9200 board. I believe it would be useful for others as the popularity of NAND flash increases. Regards, ../fam -- Frank Mandarino fmandarino(a)endrelia.com Endrelia Technologies Inc. Toronto, Ontario, Canada

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Re: [U-Boot-Users] [PATCH] use CFI-Flash and board depended driver together
by Yotam Admon 06 Dec '06

06 Dec '06

Hi, The callback function which obtains the portwidth, chipwidth is the prefer option for a more generic solution. The driver will then support the none CFI devices as well. Call for a board specific function to setup the flash_info_t for that bank will cause a code duplication for auto detect of none CFI devices. Thanks, Yotam -----Original Message----- From: Tolunay Orkun [mailto:listmember@orkun.us] Sent: Tuesday, December 05, 2006 2:56 AM To: U-Boot Cc: Stefan Roese; Jens Scharsig; Andrew Dyer; Rui Sousa; Timur Tabi; Yotam Admon; matvejchikov(a)gmail.com Subject: Re: [U-Boot-Users] [PATCH] use CFI-Flash and board depended driver together Tolunay Orkun wrote: > Jens Scharsig wrote: >> Hello, >> >> i need to use cfi and board flash driver together. This Patch contains a >> simple way to do this with a minimun changes at cfi_flash.c. All changes >> will only enable if CFG_FLASH_BOARD_DRIVER defined. >> >> >> CHANGELOG >> >> * Rename flash_print_info, flash_erase, write_buff and >> flash_real_protect to cfi_xxxx, if CFG_FLASH_BOARD_DRIVER is >> defined. This will allow use cfi driver together with board a >> dependent flash driver (see README.board-dependent-flash for >> an example) > > I have to object to this patch. I will be providing a testing patch > tonight or tomorrow that will address this issue properly which is > teaching cfi_flash driver to deal with non-cfi flash. There is no need > to have two flash drivers... I've started with this patch but ran into some roadblocks so it did not happen last Friday as promised. I have been thinking better solutions that avoids two sets of flash drivers. Basically, I was trying to detect the port and chip width by using a technique similar to flash_detect_cfi() but instead of checking for combinations of Q R Y etc., I was trying to see there was a change in the first 16 bytes of flash. Well that seemed workable until I actually tried the modified code :( The probe this way failed miserably with Intel flash responding to 0x90 in either in upper or lower byte even in 16-bit mode! Thus, if the flash is not detected by CFI method the portwidth and chipwidth will have to be set manually for even jedec ids to be read properly. If the jedec probe worked, the jedec ids could be used to lookup a static list for proper configuration of info structure. I have not given up yet. I would like to start over and take a simpler approach. Here is the idea: The CFI driver will do CFI probe. If the probe is not successful and board configuration has defined a macro, CFI driver will call a board specific function to setup the flash_info_t for that bank. I will pass the bank number to the function as argument. If the function returns non-zero, I will assume that board has setup the info structure successfully (hopefully) and move on. This still avoids driver code duplication by only passing the responsibility of setting up the info structure to the board. A variation of this could be the callback function obtains the portwidth, chipwidth (and possibly the command set) for the specific bank and do flash_read_jedec_ids to get the ids and lookup the values from a statically compiled list like I originally intended. This list would be compiled in compiled only if this feature is enabled, say CFG_FLASH_CFI_JEDEC. Instead of a callback we could use the flash_base address list and augment the array to an array of structures which include base, portwidth and chipwidth but that would require a change in all boards that uses CFI driver. A callback to the board supplied function is the least invasive way in my opinion. In either method, to cut the compiled image size a bit if there is definitely no cfi compliant flash on any bank we can omit the cfi detection and other cfi related setup code using a macro like CFG_FLASH_CFI_DISABLE (or something like that). I would like to hear opinions regarding which choices looks more attractive... Tolunay

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[U-Boot-Users] [PATCH] NXP Semiconductors I2C IP block drivers
by Robert Deliën 06 Dec '06

06 Dec '06

Hi, The patch attached adds drivers for the NXP Semiconductors (former Philips Semiconductors) Nexperia I2C IP blocks as found onboard the PNX8550, PNX8535 and PNX8536. The configuration of the SilverBox development platform has been altered to include these new drivers. This patch depends on the PNX8550 on SilverBox support patch I have submitted at 04-12-2006 13:43. With kind regards, Robert.

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[U-Boot-Users] Memory Maps
by Matias Sundman (AS/EAB) 06 Dec '06

06 Dec '06

Hello, In the PowerPC architecture and specifically a Freescale 8270 the HRCW word decides if U-boot is going to be booted from regions: HIMEM 0xFE00_0000-0xFFFF_FFFF or LOMEM 0x0000_0000-0x01FF_FFFF. The CIP field decides the exception vectors; physical address 0xFFFn_nnnn or physical address 0x000n_nnnn. Now, in my current board range I have TEXT_BASE as 0xFFF0'0000 and CFG_FLASH_BASE as 0XFE00'0000. ( 32M ) I my world that makes sense since the flash is mapped in the same range as the bootloader. The start.S file says that things will be fine as longs as we configure BR0 with the same boot ROM link address. Isn't TEXT_BASE the boot ROM link address? In one of the TQM boards ( 8260 ) I see that TEXT_BASE is 0x4000'0000 and the FLASH_BASE is 0xFF80'0000. Here the TEXT_BASE is mapped to a totally different address than HIMEM/LOMEM, the exception vectors and the FLASH_BASE - How is that possible? In other words - Could someone explain what the relationship is actually between TEXT_BASE, FLASH_BASE and the BR0 register settings are? Thx // Matias

2 1

[U-Boot-Users] Problems with an E1000 driver
by Marc Lawrence 06 Dec '06

06 Dec '06

Dear All This is my first post - so a quick background. In my spare time I am working on the Qnap Turbostation series of NAS devices; which uses an extended version of U-Boot 1.2. (the modified code - only sandpoint8245.c can be obtained from Qnap). Further board specifications and info can be found at http://scratchpad.wikia.com/wiki/Open_Turbostation:TS101 A colleague is looking at porting the existing U-Boot to version 1.6 - and trying to enable network support (the Qnap version is based on sandpoint 8245). There are two board variants - one with an RTL 8139 ethernet driver (which seems to work no problems); and mine which has an Intel 8250 OEM. Currently my version of the boot code fails; and generates program exceptions. Working backwards we have identified that the failure is occurring in e1000.c between lines 2580 and 2625 - within the e1000_sw_init function. In particular I suspect the code problem is with reading the E1000_STATUS register. <<<>>> if (hw->mac_type >= e1000_82543) { uint32_t status = E1000_READ_REG(hw, STATUS); <<<>>> I had a quick look on the tracker list; and google but was not able to find anything specific. (perhaps im just blind ;-) Currently we daisy chain to the new U-Boot version (as JTAG access is somewhat unreliable at the moment). Thus we download the new version to RAM; then copy it to spare flash; and issue the 'go' command from the U-Boot prompt. I know this is not the recommended path - and therefore wonder if this might also be the associated with the problem. A program trace is attached. I would be grateful if someone could provide some pointers about what might be going wrong. I do know (from debug messages) that the code point never reaches the end of the function - i.e. return E1000_SUCCESS; Many thanks, Marc Ps Please note: to aid initial debugging I had issued extra printf statements - showing "Marc:...".

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[U-Boot-Users] U-boot patches for Malta board
by Sathesh Babu Edara 06 Dec '06

06 Dec '06

Hi, Can some one give pointers on where can i get u-bootloader patches for Malta board?. Regards, Sathesh

1 0

[U-Boot-Users] U-boot for Malta board and MIPS24KE
by Sathesh Babu Edara 06 Dec '06

06 Dec '06

Hi , Could you please tell me U-boot implentation for Malta board?. Does u-boot have support for MIPS24KE. Thanks in advance. Regards, Sathesh

1 0

[U-Boot-Users] Breakage of board ports on new features.
by Pantelis Antoniou 05 Dec '06

05 Dec '06

Hi there, So I'm cleaning my new 834x board in the time period of just two days. There's a commit with a bunch of 834x related fixes which totally broke the board port. I understand that the main code is volatile, but it seems there's a blatant disregard of keeping up a minimum of backwards compatibility. If someone changes code that's supporting a bunch of board ports, please put in some default macros to ensure past behaviour is preserved. I.e. in this case the CONFIG_MPC8349 & CFG_FLASH_SIZE could have easily been defined with the defaults values for the non updated board ports to continue working. Please don't make our lives harder than they are. /me steps down the soapbox. Regards Pantelis

5 22

Re: [U-Boot-Users] LAN9118 ethernet controller (William Feng)
by Tim Braun 05 Dec '06

05 Dec '06

> Date: Fri, 01 Dec 2006 17:50:45 -0800 > From: William Feng <wfeng(a)mysourcecommunications.com> > I have an ARM board which has a LAN9118 ethernet controller (SMSC) > instead of a LAN91C111 which is supported in u-boot. Is there any > existing patch or ongoing work to support it? Here's a patch I've got on the shelf against 1.1.3 which should provide a driver for you. It uses CONFIG_NET_MULTI, CONFIG_DRIVER_LAN911X, and CONFIG_LAN911x_BASE to configure. Tim Braun, Sr. Des. Eng. LibreStream Technologies 200-55 Rothwell Rd. Winnipeg R3P 2M5

2 1

[U-Boot-Users] Flat device tree, blob for Icecube board
by Wolfgang Grandegger 05 Dec '06

05 Dec '06

Hello, does anyone have a flat device tree blob for the Icecube eval board? Or what is the recipe to make one? TIA. Wolfgang.

1 0

[U-Boot-Users] u-boot won't start on its own anymore...
by mitsy 05 Dec '06

05 Dec '06

My u-boot was running fine until I added some commands. What's happening is that it runs just fine if I have BDI attached or run "reset" command from u-boot itself. However, if I physically power cycle without BDI, it won't start anymore on its own. The functions I have added have nothing to do with the boot-up, and the bdi config file has been always the same so I don't believe it's some initialization issue. I assume something went wrong when the code size changed... Has anyone seen this issue? Any suggestion on what should I look for to fix this? Thank you so much for your advice! Mitsy

1 0

[U-Boot-Users] Boot Linux kernel from external HDD, connected to PCI interface.
by Leonid 05 Dec '06

05 Dec '06

Hi: I have AMCC PPC440EP card with Silicon Image 680 PCI-IDE chip, external HDD is connected to it as IDE1 - see snapshot from Linux booting log: SiI680: IDE controller at PCI slot 0000:01:06.0 SiI680: chipset revision 2 SiI680: BASE CLOCK == 133 SiI680: 100% native mode on irq 25 ide0: MMIO-DMA , BIOS settings: hda:pio, hdb:pio ide1: MMIO-DMA , BIOS settings: hdc:pio, hdd:pio hdc: Maxtor 6L100P0, ATA DISK drive ide1 at 0xd105cfc0-0xd105cfc7,0xd105cfca on irq 25 hdc: max request size: 64KiB hdc: 195813072 sectors (100256 MB) w/8192KiB Cache, CHS=65535/16/63, UDMA(133) hdc: cache flushes supported hdc: hdc1 hdc2 hdc3 However this HDD is visible only because Linux kernel happened to have drivers for Silicon Image chip. I boot Linux kernel either from the flash or from RAM. The question is does u-boot itself support Silicon Image or, by other words, can I boot kernel from some partition on HDD (behind this PCI-IDE chip) and if yes - how? Thanks, Leonid.

4 10

[U-Boot-Users] [PATCH] Proposed change to PL010 serial driver
by Robert Deliën 05 Dec '06

05 Dec '06

Hi, I am currently cleaning up my patch that provides ADM5120 support in U-Boot. But before submitting it I'd like to propose a change to the PL010 serial port driver. As far as I know, the PL010 uart is mostly used in ARM based SoCs. It's currently implemented for big endian only. The ADM5120 is MIPS based and has two PL010 serial ports on board. Most of the targets using the ADM5120 are configured for little endian mode. The patch below replaces the IO_READ and IO_WRITE macros with the readl and writel functions from asm/io.h, the designated functions for reading from and writing to IO, swapping endianness if necessary. It also replaces the various bitrate macros with one macro containing a unified bitrate calculation formula, using the newly introduced CFG_UART_PL010_CLOCK macro. The only other target using this serial port driver is intergratorap.h. I have backward calculated the uart clock for this target and added it to its configuration. With kind regards, Robert.

1 0

[U-Boot-Users] dwarf hypothetically
by Clayton 05 Dec '06

05 Dec '06

's Virtual Server must recognise and support the new APIs associated with NPIV . The goods are then released to the importer. Since that time there have been six different revisions and updates to the Incoterms. The Mac cost is higher than for Linux, other Unix, or Windows users. This tutorial will show you how to create a Windows application that plays WAV audio files in a separate thread or in the UI thread. tttt HOT STOCK ALERT! EXCITING NEW ISSUE ARSS, GET IN NOW! IT'S JUST BEGINNING OF 1 WEEK PROMOTION!!! Trade Date: Tuesday, December 05, 2006 Company: AMEROSSI EC INC (ARSS.PK) Symbol: ARSS Category: Oil and Gas Industry Region: United States, Europe and Russia Current Price: $0.50 Short Term Target: $2.50 - $4.00 Long Term Target: $10 or more You may not be aware of AMEROSSI EC INC (ARSS.PK), but you should be, because this company represents a terrific profit opportunity for early investors! Sick of hedge funds and flippers getting all the great new issues? Most stock brokers give out their new issues to their largest commission paying clients - and if you trade through an online broker or discount broker - good luck ever getting 1 share of a new issue. WELL ALL THAT IS CHANGING - IF YOU ARE RECEIVING THIS EMAIL, YOU ARE AMONG THE FIRST PUBLIC INVESTORS TO KNOW ABOUT ARSS !!! $$$ GET IN NOW!!! You know the old saying, buy the rumor and sell on the news. Once the news is out it is time to get ready for next rally... JUST DO YOURSELF A FAVOR AND WATCH ARSS START TRADING TUESDAY MORNING, and DON'T SAY WE DIDN'T TELL YOU! tttt This handling fee is not charged on packages sent through military mail channels. is required to post a bond or its cash equivalent. CBP Acting Commissioner Deborah J. It is usually pronounced like the English X but softer, often. com Spanish Language GuideSite. After all, you have a lot to learn,. Some commodities are also subject to an import quota or a restraint under bilateral trade agreements and arrangements. To expedite this process, Customs entry papers may be presented before the merchandise arrives, but entry will not take place until the merchandise arrives within the port limits. Any corporation, company or individual who wishes to import goods into the U. Customs bonds are issued by surety companies. com - Cabe destacar quienes tuvimos la oportunidad de asistir al taller pasado aprendimos aspectos fundamentales que debemos tener en cuenta al alimentarnos. com - Queremos sensibilizar a nuestros lectores acerca de estos desordenes. And if you already know the word, chances are there's a word in the. NET Framework you can use the Windows Color Picker control in your application thanks to the ColorPicker object. You can separate words using white space and tabs. In this tutorial we're going to build a color picker application and we will be getting the hex value of the selected color. For instance, OSes like AIX, HP-UX, Linux, Solaris, VMware and Microsoft Corp. Novell's UK office has started . Some commodities are also subject to an import quota or a restraint under bilateral trade agreements and arrangements. If you heard about WoW's banning of Cedega users, then you can imagine how . This tutorial will show you how to create a Windows application that plays WAV audio files in a separate thread or in the UI thread. In this tutorial we're going to build a color picker application and we will be getting the hex value of the selected color. This tutorial will show you how to create a Windows application that plays WAV audio files in a separate thread or in the UI thread. had the guts to give Microsoft Corp. For the first time, U. For instance, OSes like AIX, HP-UX, Linux, Solaris, VMware and Microsoft Corp. The verb endings are placed at the end of the infinitive, so there are. Atencion, el contenido es explicito. But by most definitions, Spanish has fewer words. Among improvements to the previous code, we are adding the code that allows the user to pause and resume a download. First Central American Nation to Target and Pre-Screen Cargo to U. For the first time, U. The verb endings are placed at the end of the infinitive, so there are. In other shipments, sample packages of the merchandise may be retained by Customs for appraisal or classification purposes and the remainder of the shipment released. " That is certainly the verb's most common meaning, and while I. In this tutorial we're going to build a color picker application and we will be getting the hex value of the selected color. This tutorial will show you how to create a Windows application that plays WAV audio files in a separate thread or in the UI thread. In this tutorial we're going to build a color picker application and we will be getting the hex value of the selected color. You will also see how to clear the content of the clipboard.

1 0

[U-Boot-Users] [PATCH] AS352X SOC02:Part03 for U-boot1.1.6
by thomas.luo 05 Dec '06

05 Dec '06

U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525… Part 3: Br Signed-off-by: Thomas Luothomas.luo(a)austriamicrosystems.com -------------------------------------------------------------------------------------------------- diff -upBNr u-boot-1.1.6.org/include/as352x.h u-boot-1.1.6/include/as352x.h --- u-boot-1.1.6.org/include/as352x.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/as352x.h 2006-12-05 09:50:51.000000000 +0800 @@ -0,0 +1,492 @@ +/* +* (C) Copyright 2006 +* Copyright (C) 2006 Austriamicrosystems, by thomas.luo +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ +#ifndef __AS352X_H__ +#define __AS352X_H__ + +#define AS352X_UART_CHANNELS 1 + +/* AS352X only supports 512 Byte HW ECC */ +#define AS352X_ECCSIZE 512 +#define AS352X_ECCBYTES 3 + + +/* AS352X device base addresses */ + + +/* ----------------------------------------------------------------- +* AS352X Registers +* ------------------------------------------------------------------ +* +*/ + + +/* AHB */ +#define AS352X_USB_BASE 0xC6000000 +#define AS352X_VIC_BASE 0xC6010000 +#define AS352X_DMAC_BASE 0xC6020000 +#define AS352X_MPMC_BASE 0xC6030000 +#define AS352X_MEMSTICK_BASE 0xC6040000 +#define AS352X_CF_IDE_BASE 0xC6050000 + +/* APB */ +#define AS352X_NAND_FLASH_BASE 0xC8000000 +#define AS352X_BIST_MANAGER_BASE 0xC8010000 +#define AS352X_SD_MCI_BASE 0xC8020000 +#define AS352X_TIMER_BASE 0xC8040000 +#define AS352X_WDT_BASE 0xC8050000 +#define AS352X_I2C_MS_BASE 0xC8060000 +#define AS352X_I2C_AUDIO_BASE 0xC8070000 +#define AS352X_SSP_BASE 0xC8080000 +#define AS352X_I2SIN_BASE 0xC8090000 +#define AS352X_I2SOUT_BASE 0xC80A0000 +#define AS352X_GPIO1_BASE 0xC80B0000 +#define AS352X_GPIO2_BASE 0xC80C0000 +#define AS352X_GPIO3_BASE 0xC80D0000 +#define AS352X_GPIO4_BASE 0xC80E0000 +#define AS352X_CGU_BASE 0xC80F0000 +#define AS352X_CCU_BASE 0xC8100000 +#define AS352X_UART0_BASE 0xC8110000 +#define AS352X_DBOP_BASE 0xC8120000 + + + +/* ------------------------------------------------------------------------ +* AS352X control registers +* ------------------------------------------------------------------------ +*/ + +#define CCU_SRC ( (AS352X_CCU_BASE) + 0x00) +#define CCU_SRL ( (AS352X_CCU_BASE) + 0x04) +#define CCU_MEMMAP ( (AS352X_CCU_BASE) + 0x08) +#define CCU_IO ( (AS352X_CCU_BASE) + 0x0C) +#define CCU_SCON ( (AS352X_CCU_BASE) + 0x10) +#define CCU_VERS ( (AS352X_CCU_BASE) + 0x14) + + +/** +* Reset Control Lines in CCU_SRC register +**/ +#define CCU_SRC_DBOP_EN ( 1 << 24 ) +#define CCU_SRC_SPDIF_EN ( 1 << 22 ) +#define CCU_SRC_TIMER_EN ( 1 << 21 ) +#define CCU_SRC_SSP_EN ( 1 << 20 ) +#define CCU_SRC_WDO_EN ( 1 << 19 ) +#define CCU_SRC_IDE_EN ( 1 << 18 ) +#define CCU_SRC_IDE_AHB_EN ( 1 << 17 ) +#define CCU_SRC_UART0 ( 1 << 16 ) +#define CCU_SRC_NAF_EN ( 1 << 15 ) +#define CCU_SRC_SDMCI_EN ( 1 << 14 ) +#define CCU_SRC_GPIO_EN ( 1 << 13 ) +#define CCU_SRC_I2C_AUDIO_EN ( 1 << 12 ) +#define CCU_SRC_I2C_EN ( 1 << 11 ) +#define CCU_SRC_MST_EN ( 1 << 10 ) +#define CCU_SRC_I2SIN ( 1 << 9 ) +#define CCU_SRC_I2SOUT ( 1 << 8 ) +#define CCU_SRC_USB_AHB_EN ( 1 << 7 ) +#define CCU_SRC_USB_PHY_EN ( 1 << 6 ) +#define CCU_SRC_DMAC_EN ( 1 << 5 ) +#define CCU_SRC_VIC_EN ( 1 << 4 ) + +/** +* Magic number for CCU_SRL for reset. +**/ +#define CCU_SRL_MAGIC_NUMBER 0x1A720212 + +/** +* Chip select lines for NAF. Use these constants to +*select/deselct the CE lines for NAND flashes in Register CCU_IO. +**/ +#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 ) +#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 ) +#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 ) +#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 ) + +/* CCU IO Select/Deselect IDE */ +#define CCU_IO_IDE ( 1 << 5 ) + +/* CCU IO Select/desect I2C */ +#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 ) + +/* CCU IO Select/desect UART */ +#define CCU_IO_UART0 ( 1 << 0 ) + + +#define CCU_RESET_ALL_BUT_MEMORY \ + ( CCU_SRC_DBOP_EN \ + | CCU_SRC_SPDIF_EN \ + | CCU_SRC_TIMER_EN \ + | CCU_SRC_SSP_EN \ + | CCU_SRC_WDO_EN \ + | CCU_SRC_IDE_EN \ + | CCU_SRC_IDE_AHB_EN \ + | CCU_SRC_UART0 \ + | CCU_SRC_NAF_EN \ + | CCU_SRC_SDMCI_EN \ + | CCU_SRC_GPIO_EN \ + | CCU_SRC_I2C_AUDIO_EN \ + | CCU_SRC_I2C_EN \ + | CCU_SRC_MST_EN \ + | CCU_SRC_I2SIN \ + | CCU_SRC_I2SOUT \ + | CCU_SRC_USB_AHB_EN \ + | CCU_SRC_USB_PHY_EN \ + | CCU_SRC_DMAC_EN \ + | CCU_SRC_VIC_EN \ + ) + +/** +* Magic number for CCU_SRL for reset. +**/ +#define CCU_SRL_MAGIC_NUMBER 0x1A720212 + +/** +* Chip select lines for NAF. Use these constants to select/deselct +* the CE lines for NAND flashes in Register CCU_IO. +**/ +#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 ) +#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 ) +#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 ) +#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 ) + +/* CCU IO Select/Deselect IDE */ +#define CCU_IO_IDE ( 1 << 5 ) + +/* CCU IO Select/desect I2C */ +#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 ) + +/* CCU IO Select/desect UART */ +#define CCU_IO_UART ( 1 << 0 ) + + +#define CCU_COUNT_MIN_10_MICROSEC 640 + +/* ------------------------------------------------------------------------ +* AS352X clock control registers +* ------------------------------------------------------------------------ +*/ + +#define CGU_REG_PLLA ( (AS352X_CGU_BASE) + 0x00 ) +#define CGU_REG_PLLB ( (AS352X_CGU_BASE) + 0x04 ) +#define CGU_REG_PLLASUP ( (AS352X_CGU_BASE) + 0x08 ) +#define CGU_REG_PLLBSUP ( (AS352X_CGU_BASE) + 0x0C ) +#define CGU_REG_PROC ( (AS352X_CGU_BASE) + 0x10 ) +#define CGU_REG_PERI ( (AS352X_CGU_BASE) + 0x14 ) +#define CGU_REG_AUDIO ( (AS352X_CGU_BASE) + 0x18 ) +#define CGU_REG_USB ( (AS352X_CGU_BASE) + 0x1C ) +#define CGU_REG_INTCTRL ( (AS352X_CGU_BASE) + 0x20 ) +#define CGU_REG_IRQ ( (AS352X_CGU_BASE) + 0x24 ) +#define CGU_REG_COUNTA ( (AS352X_CGU_BASE) + 0x28 ) +#define CGU_REG_COUNTB ( (AS352X_CGU_BASE) + 0x2C ) +#define CGU_REG_IDE ( (AS352X_CGU_BASE) + 0x30 ) +#define CGU_REG_MEMSTICK ( (AS352X_CGU_BASE) + 0x34 ) +#define CGU_REG_DBOP ( (AS352X_CGU_BASE) + 0x38 ) + + +/* --- are disabled after reset --- */ +/* dma */ +#define CGU_DMA_CLOCK_ENABLE ( 1 << 22 ) +/* usb */ +#define CGU_USB_CLOCK_ENABLE ( 1 << 21 ) +/* i2sout */ +#define CGU_I2SOUT_APB_CLOCK_ENABLE ( 1 << 20 ) +/* i2sin */ +#define CGU_I2SIN_APB_CLOCK_ENABLE ( 1 << 19 ) +/* i2c master/slave */ +#define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE ( 1 << 18 ) +/* i2c audio master */ +#define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE ( 1 << 17 ) +/* gpio */ +#define CGU_GPIO_CLOCK_ENABLE ( 1 << 16 ) +/* mmc + sd */ +#define CGU_MCI_CLOCK_ENABLE ( 1 << 15 ) +/* naf */ +#define CGU_NAF_CLOCK_ENABLE ( 1 << 14 ) + /* uart */ +#define CGU_UART_APB_CLOCK_ENABLE ( 1 << 13 ) +/* watchdog counter */ +#define CGU_WDOCNT_CLOCK_ENABLE ( 1 << 12 ) + /* watchdog timer module */ +#define CGU_WDOIF_CLOCK_ENABLE ( 1 << 11 ) +/* ssp */ +#define CGU_SSP_CLOCK_ENABLE ( 1 << 10 ) +/* timer 1 */ +#define CGU_TIMER1_CLOCK_ENABLE ( 1 << 9 ) +/* timer 2 */ +#define CGU_TIMER2_CLOCK_ENABLE ( 1 << 8 ) +/* timer interface */ +#define CGU_TIMERIF_CLOCK_ENABLE ( 1 << 7 ) + +/** ------------------------------------------------------------------ +* Number of cycles to wait before cgu is safely locked. +**/ +#define CGU_LOCK_CNT 0xFF + +/* FIFO depth is 16 for tx and rx fifo */ +#define UART_FIFO_DEPTH 16 + +/* ------------------- UART Line Control Register bit fields ------------- */ + +#define UART_LNCTL_DLSEN (1 << 7) /* Device latch select bit */ + + +/* -------------- UART Interrupt Control Register bit fields ---------- */ + +#define UART_INTR_RXDRDY 0x1 /* Data ready interrupt */ +#define UART_INTR_TXEMT 0x2 /* Transmit data empty interrupt */ +#define UART_INTR_RXLINESTATUS 0x4 /* Receive line status interrupt */ + +/* ------------------- UART Line Status Register bit fields ------------- */ + +#define UART_ERRORBITS 0x1E +#define UART_RX_DATA_READY (1 << 0) +#define UART_TX_HOLD_REG_EMPTY (1 << 5) + +/* ------------------- FIFO CNTL Register contants --------------*/ + +#define UART_FIFO_EN (1 << 0) /* Enable the UART FIFO */ +#define UART_TX_FIFO_RST (1 << 1) /* Enable the UART FIFO */ +#define UART_RX_FIFO_RST (1 << 2) +#define UART_RXFIFO_TRIGLVL_1 (0 << 4) /* RX FIFO TRIGGER_LEVEL 1 */ +#define UART_RXFIFO_TRIGLVL_4 0x08 /* RX FIFO TRIGGER_LEVEL 4 */ +#define UART_RXFIFO_TRIGLVL_8 0x10 /* RX FIFO TRIGGER_LEVEL 8 */ +#define UART_RXFIFO_TRIGLVL_14 0x18 /* RX FIFO TRIGGER_LEVEL 14 */ + + +/* ------------------- FIFO status Register contants -----------*/ +#define UART_TX_FIFO_FULL (1 << 0) +#define UART_RX_FIFO_FULL (1 << 1) +#define UART_TX_FIFO_EMPTY (1 << 2) +#define UART_RX_FIFO_EMPTY (1 << 3) + + +/* ----------------------- defines -------------------------------------- */ +/* Data register */ +#define UART_DATA_REG ( (AS352X_UART0_BASE) + 0x00 ) +/* Clock divider(lower byte) register */ +#define UART_DLO_REG ( (AS352X_UART0_BASE) + 0x00 ) +/* Clock divider(higher byte) register */ +#define UART_DHI_REG ( (AS352X_UART0_BASE) + 0x04 ) +/* Interrupt enable register */ +#define UART_INTEN_REG ( (AS352X_UART0_BASE) + 0x04 ) +/* Interrupt status register */ +#define UART_INTSTATUS_REG ( (AS352X_UART0_BASE) + 0x08 ) +/* Fifo control register */ +#define UART_FCTL_REG ( (AS352X_UART0_BASE) + 0x0C ) +/* Fifo status register */ +#define UART_FSTATUS_REG ( (AS352X_UART0_BASE) + 0x0C ) +/* Line control register */ +#define UART_LNCTL_REG ( (AS352X_UART0_BASE) + 0x10 ) +/* Line status register */ +#define UART_LNSTATUS_REG ( (AS352X_UART0_BASE) + 0x14 ) + +/* 32-bit width */ +#define TIMER_LOAD ( (AS352X_TIMER_BASE) + 0x00 ) +/* 32 bit width */ +#define TIMER_VALUE ( (AS352X_TIMER_BASE) + 0x04 ) +/* 8 bit width */ +#define TIMER_CONTROL ( (AS352X_TIMER_BASE) + 0x08 ) +/* clears ir by write access */ +#define TIMER_INTCLR ( (AS352X_TIMER_BASE) + 0x0C ) +/* 1 bit width */ +#define TIMER_RIS ( (AS352X_TIMER_BASE) + 0x10 ) + /* 1 bit width */ +#define TIMER_MIS ( (AS352X_TIMER_BASE) + 0x14 ) + +/** +* Counter/Timer control register bits +**/ +#define TIMER_ENABLE 0x80 +#define TIMER_PERIODIC 0x40 +#define TIMER_INT_ENABLE 0x20 +#define TIMER_32_BIT 0x02 +#define TIMER_ONE_SHOT 0x01 +#define TIMER_PRESCALE_1 0x00 +#define TIMER_PRESCALE_16 0x04 +#define TIMER_PRESCALE_256 0x08 + + + +#define NAF_CONFIG ( (AS352X_NAND_FLASH_BASE) + 0x00 ) +#define NAF_CONTROL ( (AS352X_NAND_FLASH_BASE) + 0x04 ) +#define NAF_ECC ( (AS352X_NAND_FLASH_BASE) + 0x08 ) +#define NAF_DATA ( (AS352X_NAND_FLASH_BASE) + 0x0C ) +#define NAF_MODE ( (AS352X_NAND_FLASH_BASE) + 0x10 ) +#define NAF_STATUS ( (AS352X_NAND_FLASH_BASE) + 0x14 ) +#define NAF_MASK ( (AS352X_NAND_FLASH_BASE) + 0x18 ) +#define NAF_FIFODATA ( (AS352X_NAND_FLASH_BASE) + 0x1C ) +#define NAF_WORDS ( (AS352X_NAND_FLASH_BASE) + 0x20 ) +#define NAF_CLEAR ( (AS352X_NAND_FLASH_BASE) + 0x24 ) +#define NAF_TEST ( (AS352X_NAND_FLASH_BASE) + 0x28 ) + +/* Macro introduced to compensate for no support for floating +point division operation in the processor. So to get the correct value, +roundup is peformed to provide accurate results for certain conditions. */ + +#define DIVIDE_AND_ROUND_UP(dividend,divisor) \ + ( ( (dividend) + (divisor) - 1 ) / (divisor) ) + +/* For sake of completness and for easier exchanging of +round-up and round-down divisions provide also a round-down macro */ + +#define DIVIDE_AND_ROUND_DOWN( a , b ) ((a)/(b)) + +/* Macro which evaluates to the absolute value of an integer value*/ +#define ABS(A) (((A)>0)?(A):(-(A))) + + +/* ------------------------defines for Dynamic Mem ----------------- */ +#define AS352X_SDRAM_BASE_ADDR(offset) (0xc6030000 + offset) + +#define AS352X_MPMC_CONTROL AS352X_SDRAM_BASE_ADDR( 0x00 ) +#define AS352X_MPMC_CONFIG AS352X_SDRAM_BASE_ADDR( 0x08 ) +#define AS352X_MPMC_DYRDCFG AS352X_SDRAM_BASE_ADDR( 0x28 ) +#define AS352X_MPMC_DYTRP AS352X_SDRAM_BASE_ADDR( 0x30 ) +#define AS352X_MPMC_DYTRAS AS352X_SDRAM_BASE_ADDR( 0x34 ) +#define AS352X_MPMC_DYTSREX AS352X_SDRAM_BASE_ADDR( 0x38 ) +#define AS352X_MPMC_DYTAPR AS352X_SDRAM_BASE_ADDR( 0x3C ) +#define AS352X_MPMC_DYTDAL AS352X_SDRAM_BASE_ADDR( 0x40 ) +#define AS352X_MPMC_DYTWR AS352X_SDRAM_BASE_ADDR( 0x44 ) +#define AS352X_MPMC_DYTRC AS352X_SDRAM_BASE_ADDR( 0x48 ) +#define AS352X_MPMC_DYTRFC AS352X_SDRAM_BASE_ADDR( 0x4C ) +#define AS352X_MPMC_DYTXSR AS352X_SDRAM_BASE_ADDR( 0x50 ) +#define AS352X_MPMC_DYTRRD AS352X_SDRAM_BASE_ADDR( 0x54 ) +#define AS352X_MPMC_DYTMRD AS352X_SDRAM_BASE_ADDR( 0x58 ) +#define AS352X_MPMC_DYRASCAS0 AS352X_SDRAM_BASE_ADDR( 0x104 ) +#define AS352X_MPMC_DYCONFIG0 AS352X_SDRAM_BASE_ADDR( 0x100 ) +#define AS352X_MPMC_DYCNTL AS352X_SDRAM_BASE_ADDR( 0x20 ) +#define AS352X_MPMC_DYREF AS352X_SDRAM_BASE_ADDR( 0x24 ) + +/* --- MT48LC4M16A2 SDRAM & MT48LC32M16A2 SDRAM ----------------- */ +#define MPMC_DY_TRP_IN_NS 20 +#define MPMC_CLK_IN_MHZ_MIN 20 +#define MPMC_1_CLKCYCLE_IN_NS_MIN 50 + +#define MPMC_CLK_IN_MHZ 66 +#if MPMC_CLK_IN_MHZ == 24 +#define MPMC_1_CLKCYCLE_IN_NS 42 +#elif MPMC_CLK_IN_MHZ == 66 +#define MPMC_1_CLKCYCLE_IN_NS 16 +#else +#define MPMC_1_CLKCYCLE_IN_NS 16 +#endif +#define MPMC_SDRAM_TCK_IN_NS 10 + +#define MPMC_DY_TRAS_MIN_IN_NS 50 +#define MPMC_DY_TRAS_IN_NS MPMC_DY_TRAS_MIN_IN_NS + +/* tAPR not available for micron MT48LC4M16A2 SDRAM */ +#define MPMC_DY_TAPR_INNS 0 + +#define MPMC_DY_TDAL_IN_NS (5 * (MPMC_SDRAM_TCK_IN_NS)) + +/* tWR can be minimum 15ns or 1CLK * 7ns */ +#define MPMC_DY_TWR_IN_NS (MPMC_1_CLKCYCLE_IN_NS + 8) +#define MPMC_DY_TRC_IN_NS 70 + +#define MPMC_DY_TRFC_INNS 70 + +#define MPMC_DY_TXSR_IN_NS 80 + +#define MPMC_DY_TRRD_IN_NS 20 +#define MPMC_DY_TMRD_IN_NS (2 * (MPMC_SDRAM_TCK_IN_NS)) + +#define MPMC_SDRAM_CAS 0x2 +#define MPMC_SDRAM_RAS 0x2 /* hha??? */ + +/* Low Power device bit settings */ +/* Device Type for APP Board 2.0 and 1.0 */ +/* MT48LC32M16A2 - 512Mbit and MT48LC4M16 - 64Mbit -both NOT Low Power */ +#define MPMC_SDRAM_DEVICE_TYPE (0 << 3) + +/*ROW and COLUMN size mapping for mpmc SoC device */ + +/* Addr Mapping for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +#define MPMC_SDRAM_ADDR_MAPPING (0x11 << 7) + +#define MPMC_SDRAM_32BIT_EXTBUS (0 <<14) +#define MPMC_SDRAM_BUFFER_DISABLE (0 <<19) +#define MPMC_SDRAM_BUFFER_ENABLE (1 <<19) +#define MPMC_SDRAM_WP_ENABLE (0 <<20) + +#define MPMC_SDRAM_DYN_CONFIG ((MPMC_SDRAM_DEVICE_TYPE) | \ + (MPMC_SDRAM_ADDR_MAPPING) | \ + (MPMC_SDRAM_32BIT_EXTBUS) | \ + (MPMC_SDRAM_BUFFER_DISABLE) | \ + (MPMC_SDRAM_WP_ENABLE)) + +#define MPMC_SDRAM_START_2_REF_CYCLES 2 +/* TREF for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +/*64ms divided by 8192 */ +#define MPMC_SDRAM_tREF_inNs 7812 + + +#define MPMC_SDRAM_DYNAMIC_REF ((MPMC_SDRAM_tREF_inNs) \ + / (MPMC_1_CLKCYCLE_IN_NS_MIN)) + +/* CAS Latency for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +#if MPMC_SDRAM_CAS == 2 +#define MPMC_SDRAM_MODEVALUE (0x23 << 13) +#else +#define MPMC_SDRAM_MODEVALUE (0x33 << 13) +#endif +/* Quarter Strength*/ +#define MPMC_SDRAM_EXMODEVALUE ((0x40 << 12) | (0x1 << 11)) + +#define set_reg_bits32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) |= ( (u32)(value) ) ) + + +#define clr_reg_bits32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) &= ( ~( (u32)(value) ) ) ) + +#define read_reg32( registerAddress ) \ + ( *( ( const volatile u32 * )( registerAddress ) ) ) + +#define write_reg32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) = ( (u32)(value) ) ) + + + +#define read_reg16( registerAddress ) \ + ( *( ( const volatile u16 * )( registerAddress ) ) ) + +#define write_reg16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) = ( (u16)(value) ) ) + +#define set_reg_bits16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) |= ( (u16)(value) ) ) + +#define clr_reg_bits16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) &= ( ~( (u16)(value) ) ) ) + + +#define read_reg8( registerAddress ) \ + ( *( ( const volatile u8 * )( registerAddress ) ) ) + +#define write_reg8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) = ( (u8)(value) ) ) + +#define set_reg_bits8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) |= ( (u8)(value) ) ) + +#define clr_reg_bits8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) &= ( ~( (u8)(value) ) ) ) +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#endif /*__AS352X_H__*/ diff -upBNr u-boot-1.1.6.org/include/asm-arm/mach-types.h u-boot-1.1.6/include/asm-arm/mach-types.h --- u-boot-1.1.6.org/include/asm-arm/mach-types.h 2006-12-01 17:49:35.000000000 +0800 +++ u-boot-1.1.6/include/asm-arm/mach-types.h 2006-12-01 18:01:45.000000000 +0800 @@ -737,6 +737,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 #define MACH_TYPE_PDNB3 1002 +#define MACH_TYPE_AS352X 1166 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -6054,7 +6055,7 @@ extern unsigned int __machine_arch_type; # define machine_is_ess710() (0) #endif -#ifdef CONFIG_MACH_MX3ADS +#ifdef CONFIG_MACH_MX31ADS # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type @@ -9401,6 +9402,18 @@ extern unsigned int __machine_arch_type; #else # define machine_is_mp2usb() (0) #endif +#ifdef CONFIG_MACH_AS352X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS352X +# endif +# define machine_is_as352x() (machine_arch_type == MACH_TYPE_AS352X) +#else +# define machine_is_as352x() (0) +#endif + /* * These have not yet been registered diff -upBNr u-boot-1.1.6.org/include/configs/as352xpb.h u-boot-1.1.6/include/configs/as352xpb.h --- u-boot-1.1.6.org/include/configs/as352xpb.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/configs/as352xpb.h 2006-12-05 16:06:36.000000000 +0800 @@ -0,0 +1,232 @@ +/* +* (C) Copyright 2006 +* Copyright (C) 2006 Austriamicrosystems, by thomas.luo +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* +* High Level Configuration Options +* (easy to change) +*/ +#define CONFIG_ARM922T 1 /* This is an ARM922T Core */ +#define CONFIG_AS352X 1 /* in a AS352X SoC */ +#define CONFIG_AS352XPB 1 /* on a AS352XPB Board */ +#define CFG_NO_FLASH 1 + +/* input clock of PLL */ +/* the AS352XPB has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + + +#define USE_922T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* +* Size of malloc() pool +*/ +#define CFG_MALLOC_LEN (((CFG_ENV_SIZE + 128*1024 + 0x4000-1) \ + /0x4000)*0x4000) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 128 + +/* +* Hardware drivers +*/ + +/* +* select serial console configuration +*/ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on AS352XPB */ + +/************************************************************ +* RTC +************************************************************/ +#define CONFIG_RTC_AS352X 0 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +/*********************************************************** +* Command definition +***********************************************************/ +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + /* CFG_CMD_CACHE |*/ \ + CFG_CMD_NAND | \ + /*CFG_CMD_EEPROM |*/ \ + /*CFG_CMD_I2C |*/ \ + /*CFG_CMD_USB |*/ \ + CFG_CMD_REGINFO \ + /*CFG_CMD_ELF*/ )& ~(CFG_CMD_FLASH| \ + CFG_CMD_IMLS|CFG_CMD_NET|CFG_CMD_XIMG)) +/*this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTARGS "root=/dev/ram0 rw init=/linuxrc console=ttyS0 mem=64M" +#define CONFIG_BOOTCOMMAND "nand read 0x30007FC0 0x80000 0x200000; \ +nand read 0x32000000 0x280000 0x420000;bootm 0x30007FC0 0x32000000" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "autoboot in %d seconds (stop with 's')...\n" +#define CONFIG_AUTOBOOT_STOP_STR "s" +/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ +/*#define CONFIG_NETMASK 255.255.255.0*/ +/*#define CONFIG_IPADDR 10.0.0.110*/ +/*#define CONFIG_SERVERIP 10.0.0.1*/ +/*#define CONFIG_BOOTFILE "" */ +/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +/* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 +/* what's this ? it's not used anywhere */ +/* which serial port to use */ +#define CONFIG_KGDB_SER_INDEX 1 +#endif + +#undef CFG_ENV_IS_IN_FLASH +/* +* Miscellaneous configurable options +*/ +#define CFG_LONGHELP 1 /* undef to save memory*/ +/* Monitor Command Prompt */ +#define CFG_PROMPT "AS352X # " +#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 8 /* max number of command args*/ +/* Boot Argument Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE + +#define CFG_MEMTEST_START 0x30000000 /* memtest works on*/ +#define CFG_MEMTEST_END 0x33F00000/* 63 MB in DRAM*/ +/* everything, incl board info, in Hz */ +#undef CFG_CLKS_IN_HZ +/* default load address */ +#define CFG_LOAD_ADDR 0x30008000 + +#define CFG_HZ 1500000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_ENV_IS_IN_NAND 1 + +#define CFG_ENV_NAND_ERASE_SIZE 0x20000 +/* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x800 +#if CFG_ENV_IS_IN_NAND +#define CFG_ENV_OFFSET 0x60000 + +#endif +/*------------------------------------------------------------------ +* Stack sizes +* +* The stack sizes are set up in start.S using the settings below +*/ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*------------------------------------------------------------------- +* Physical Memory Map +*/ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*------------------------------------------------------------------- +* FLASH and environment organization +*/ +/* uncomment this if you have a LV400 flash */ +#define CONFIG_AMD_LV400 0 +#if 0 +/* uncomment this if you have a LV800 flash */ +#define CONFIG_AMD_LV800 1 +#endif + +#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks*/ +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +/* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT (19) +/* addr of environment */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) +#endif +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +/* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT (11) +/* addr of environment */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) +#endif + + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices*/ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + + +#define NAND_DISABLE_CE(nand) do { } while(0) +#define NAND_ENABLE_CE(nand) do { } while(0) + +#define NAND_WAIT_READY(nand) + +#define WRITE_NAND_COMMAND(d, adr) do{ } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ } while(0) +#define WRITE_NAND(d, adr) do{} while(0) +#define READ_NAND(adr) () +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +/* timeout values are in ticks */ +/* Timeout for Flash Erase */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) +/* Timeout for Flash Write */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) + +#include <as352x.h> +#define CFG_NAND_BASE NAF_DATA +#include <cmd_confdefs.h> + +#define NAND_ALLOW_ERASE_ALL + + + +#endif /* __CONFIG_H */ diff -upBNr u-boot-1.1.6.org/MAINTAINERS u-boot-1.1.6/MAINTAINERS --- u-boot-1.1.6.org/MAINTAINERS 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/MAINTAINERS 2006-12-04 10:20:27.000000000 +0800 @@ -566,6 +566,17 @@ Zachary P. Landau <zachary.landau@labxte Haavard Skinnemoen <hskinnemoen(a)atmel.com> ATSTK1000 AT32AP7000 +######################################################################### +# AS352X Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Thomas Luo <thomas.luo(a)austriamicrosystems.com> + + AS352XPB AS352X + ######################################################################### # End of MAINTAINERS list # diff -upBNr u-boot-1.1.6.org/MAKEALL u-boot-1.1.6/MAKEALL --- u-boot-1.1.6.org/MAKEALL 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/MAKEALL 2006-12-04 10:20:27.000000000 +0800 @@ -189,13 +189,13 @@ LIST_ARM7=" \ LIST_ARM9=" \ at91rm9200dk cmc_pu2 \ ap920t ap922_XA10 ap926ejs ap946es \ - ap966 cp920t cp922_XA10 cp926ejs \ + ap966 cp920t cp922t cp922_XA10 cp926ejs \ cp946es cp966 lpd7a400 mp2usb \ mx1ads mx1fs2 netstar omap1510inn \ omap1610h2 omap1610inn omap730p2 sbc2410x \ scb9328 smdk2400 smdk2410 trab \ VCMA9 versatile versatileab versatilepb \ - voiceblue \ + voiceblue as3525pb \ " ######################################################################### diff -upBNr u-boot-1.1.6.org/Makefile u-boot-1.1.6/Makefile --- u-boot-1.1.6.org/Makefile 2006-12-01 17:49:33.000000000 +0800 +++ u-boot-1.1.6/Makefile 2006-12-04 10:20:27.000000000 +0800 @@ -2253,6 +2253,9 @@ atstk1002_config : unconfig @./mkconfig $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000 ######################################################################### +as352xpb_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm922t as352xpb NULL as352x + ######################################################################### #########################################################################

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[U-Boot-Users] [PATCH] AS352X SOC02:Part02 for U-boot1.1.6
by thomas.luo 05 Dec '06

05 Dec '06

U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525… Part 2: Br Signed-off-by: Thomas Luothomas.luo(a)austriamicrosystems.com -------------------------------------------------------------------------------------------------- diff -upBNr u-boot-1.1.6.org/cpu/arm922t/as352x/serial.c u-boot-1.1.6/cpu/arm922t/as352x/serial.c --- u-boot-1.1.6.org/cpu/arm922t/as352x/serial.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/serial.c 2006-12-04 10:30:49.000000000 +0800 @@ -0,0 +1,145 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#if defined(CONFIG_AS352X) +#include <as352x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* +* Initialise the serial port with the given baudrate. The settings +* are always 8 data bits, no parity, 1 stop bit, no start bits. +*/ +void serial_setbrg (void) +{ + u8 controlData; + set_reg_bits32(CCU_IO,CCU_IO_UART); + + /* reset the uart + */ + set_reg_bits32(CCU_SRC, CCU_SRC_UART0); + write_reg32(CCU_SRL, CCU_SRL_MAGIC_NUMBER); + clr_reg_bits32(CCU_SRC, CCU_SRC_UART0); + write_reg32(CCU_SRL, 0x0); + write_reg32(UART_FCTL_REG, 0); + write_reg32(UART_INTEN_REG, 0); + controlData = 3; + write_reg32(UART_LNCTL_REG,controlData| UART_LNCTL_DLSEN); + write_reg32(UART_DLO_REG,0x68); + write_reg32(UART_DHI_REG,0x0); + write_reg32(UART_LNCTL_REG,controlData& (~UART_LNCTL_DLSEN)); + +} +int serial_init (void) +{ + int i; + serial_setbrg(); + for (i = 0; i < 100; i++); + return (0); +} + +/* +* Read a single byte from the serial port. Returns 1 on success, 0 +* otherwise. When the function is succesfull, the character read is +* written into its argument c. +*/ +int serial_getc (void) +{ + u8 c; + + while (!(read_reg32(UART_LNSTATUS_REG) & UART_RX_DATA_READY)); + c = read_reg32(UART_DATA_REG); + return c&0xff; +} + +#ifdef CONFIG_HWFLOW +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ + switch(on) { + case 0: + default: + break; /* return current */ + case 1: + hwflow = 0; /* turn on */ + break; + case -1: + hwflow = 0; /* turn off */ + break; + } + return hwflow; +} +#endif + +#ifdef CONFIG_MODEM_SUPPORT +static int be_quiet = 0; +void disable_putc(void) +{ + be_quiet = 1; +} + +void enable_putc(void) +{ + be_quiet = 0; +} +#endif + + +/* +* Output a single byte to the serial port. +*/ +void serial_putc (const char c) +{ +#ifdef CONFIG_MODEM_SUPPORT + if (be_quiet) + return; +#endif + + /* wait for room in the tx FIFO */ + while (!(read_reg32(UART_LNSTATUS_REG) & UART_TX_HOLD_REG_EMPTY)); + write_reg32(UART_DATA_REG,c); + + + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* +* Test whether a character is in the RX buffer +*/ +int serial_tstc (void) +{ + return (read_reg32(UART_LNSTATUS_REG) & UART_RX_DATA_READY); +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#endif /* defined(CONFIG_AS352X)*/ diff -upBNr u-boot-1.1.6.org/cpu/arm922t/config.mk u-boot-1.1.6/cpu/arm922t/config.mk --- u-boot-1.1.6.org/cpu/arm922t/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/config.mk 2006-11-24 16:43:15.000000000 +0800 @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + + +PLATFORM_CPPFLAGS += -march=armv4 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff -upBNr u-boot-1.1.6.org/cpu/arm922t/cpu.c u-boot-1.1.6/cpu/arm922t/cpu.c --- u-boot-1.1.6.org/cpu/arm922t/cpu.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/cpu.c 2006-12-04 09:51:34.000000000 +0800 @@ -0,0 +1,194 @@ +/* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Marius Groeger <mgroeger(a)sysgo.de> +* +* (C) Copyright 2002 +* Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +/* +* CPU specific code +*/ + +#include <common.h> +#include <command.h> +#include <arm922t.h> + +#ifdef CONFIG_USE_IRQ +DECLARE_GLOBAL_DATA_PTR; +#endif + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + +#ifdef MMU_DEBUG + printf ("p15/c1 is = %08lx\n", value); +#endif + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ +#ifdef MMU_DEBUG + printf ("write %08lx to p15/c1\n", value); +#endif + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM922T Technical reference Manual */ +/* mmu off/on */ +#define C1_MMU (1<<0) +/* alignment faults off/on */ +#define C1_ALIGN (1<<1) +/* dcache off/on */ +#define C1_DC (1<<2) + +/* big endian off/on */ +#define C1_BIG_ENDIAN (1<<7) +/* system protection */ +#define C1_SYS_PROT (1<<8) +/* ROM protection */ +#define C1_ROM_PROT (1<<9) +/* icache off/on */ +#define C1_IC (1<<12) +/* location of vectors: low/high addresses */ +#define C1_HIGH_VECTORS (1<<13) + + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + IRQ_STACK_START = _armboot_start - + CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + /* get control reg. */ + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IC) != 0; +} + +#ifdef USE_922T_MMU +/* It makes no sense to use the dcache if the MMU is not enabled */ +void dcache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_DC); +} + +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + reg &= ~C1_DC; + write_p15_c1 (reg); +} + +int dcache_status (void) +{ + return (read_p15_c1 () & C1_DC) != 0; +} +#endif diff -upBNr u-boot-1.1.6.org/cpu/arm922t/interrupts.c u-boot-1.1.6/cpu/arm922t/interrupts.c --- u-boot-1.1.6.org/cpu/arm922t/interrupts.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/interrupts.c 2006-11-23 17:01:25.000000000 +0800 @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <arm920t.h> +#include <asm/proc-armv/ptrace.h> + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} diff -upBNr u-boot-1.1.6.org/cpu/arm922t/Makefile u-boot-1.1.6/cpu/arm922t/Makefile --- u-boot-1.1.6.org/cpu/arm922t/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/Makefile 2006-11-02 22:15:02.000000000 +0800 @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = cpu.o interrupts.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -upBNr u-boot-1.1.6.org/cpu/arm922t/start.S u-boot-1.1.6/cpu/arm922t/start.S --- u-boot-1.1.6.org/cpu/arm922t/start.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/start.S 2006-11-30 10:25:41.000000000 +0800 @@ -0,0 +1,353 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * relocate armboot to ram + * setup stack + * jump to second stage + * + ************************************************************************* + */ + +RAM_END: + .word 0x50000 + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word _end+200 + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word _end+400 +#endif + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + /* Set up the stack */ +stack_setup: + ldr r0, RAM_END /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + ldr r0,RAM_END + ldr r1,_bss_end + str r0,_armboot_start + add r1,r1,r0 + str r1,_bss_end + ldr r1,_bss_start + add r1,r1,r0 + str r1,_bss_start + ldr pc,_start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + mrc p15, 0, r0, c1, c0, 0 @ read CP15 register 1 into r0 + bic r0, r0, #0x0001 @ clear bit 0 MMU disable + bic r0, r0, #0x0004 @ clear bit 2 D-cache disable + bic r0, r0, #0x1000 @ clear bit 12 I-cache disable + bic r0, r0, #0xc0000000 @ clear bit 30,31 fast bus mode + mcr p15, 0, r0, c1, c0, 0 @ write value back + + @ invalidate all caches to have a clean startup + mov r2, #0 + mcr p15, 0, r2, c7, c7, 0 @ Invalidate D- and I-Cache + mcr p15, 0, r2, c8, c7, 0 @ invalidate all TLBs + + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + mov ip, lr + bl lowlevel_init + mov lr, ip + mov pc, lr +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get pc, cpsr + add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif diff -upBNr u-boot-1.1.6.org/CREDITS u-boot-1.1.6/CREDITS --- u-boot-1.1.6.org/CREDITS 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/CREDITS 2006-12-04 10:20:27.000000000 +0800 @@ -465,3 +465,8 @@ N: James MacAulay E: james.macaulay(a)amirix.com D: Suppport for Amirix AP1000 W: www.amirix.com + +N: Thomas Luo +E: thomas.luo(a)austriamicrosystems.com +D: Port to ARM base SOC AS352X. +W: www.austriamicrosystems.com diff -upBNr u-boot-1.1.6.org/include/arm922t.h u-boot-1.1.6/include/arm922t.h --- u-boot-1.1.6.org/include/arm922t.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/arm922t.h 2006-11-23 16:30:48.000000000 +0800 @@ -0,0 +1,12 @@ +/************************************************ + * NAME : arm922t.h + * Version : 30 April 2002 * + * + * empty for now + ************************************************/ + +#ifndef __ARM922T_H__ +#define __ARM922T_H__ + + +#endif /*__ARM922T_H__*/

1 0

[U-Boot-Users] [PATCH] AS352X SOC02:Part01 for U-boot1.1.6
by thomas.luo 05 Dec '06

05 Dec '06

U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525… Part 1: Br Signed-off-by: Thomas Luothomas.luo(a)austriamicrosystems.com -------------------------------------------------------------------------------------------------- diff -upBNr u-boot-1.1.6.org/board/as352xpb/as352xpb.c u-boot-1.1.6/board/as352xpb/as352xpb.c --- u-boot-1.1.6.org/board/as352xpb/as352xpb.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/as352xpb.c 2006-12-05 09:45:02.000000000 +0800 @@ -0,0 +1,212 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <as352x.h> + +DECLARE_GLOBAL_DATA_PTR; + + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} +void sdram_init(void ) +{ + volatile u32 temp; + *(volatile u32 *)AS352X_MPMC_CONTROL = 0x00000001; + *(volatile u32 *)(AS352X_MPMC_CONFIG) = 0x00000000; + *(volatile u32 *)(AS352X_MPMC_DYRDCFG) = 0x00000001; + /* MPMCDynamicRP setup */ + *(volatile u32 *)(AS352X_MPMC_DYTRP) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRP_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)) ; + /* MPMCDytRAS setup */ + *(volatile u32 *)(AS352X_MPMC_DYTRAS) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRAS_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamicSREX */ + *(volatile u32 *)(AS352X_MPMC_DYTSREX) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TXSR_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictAPR */ + *(volatile u32 *)(AS352X_MPMC_DYTAPR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TAPR_INNS), + (MPMC_1_CLKCYCLE_IN_NS)); + *(volatile u32 *)(AS352X_MPMC_DYTDAL) = + (1+(DIVIDE_AND_ROUND_UP((MPMC_DY_TDAL_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)))); + /* Setup MPMCDynamictWR */ + *(volatile u32 *)(AS352X_MPMC_DYTWR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TWR_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictRC */ + *(volatile u32 *)(AS352X_MPMC_DYTRC) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRC_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictRFC */ + *(volatile u32 *)(AS352X_MPMC_DYTRFC) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRFC_INNS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictXSR */ + *(volatile u32 *)(AS352X_MPMC_DYTXSR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TXSR_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictRRD */ + *(volatile u32 *)(AS352X_MPMC_DYTRRD) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRRD_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + /* Setup MPMCDynamictMRD */ + *(volatile u32 *)(AS352X_MPMC_DYTMRD) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TMRD_IN_NS), + (MPMC_1_CLKCYCLE_IN_NS)); + *(volatile u32 *)(AS352X_MPMC_DYRASCAS0) = + ((MPMC_SDRAM_CAS << 0x8) | (MPMC_SDRAM_RAS)); + *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) = MPMC_SDRAM_DYN_CONFIG; + + /*wait for 200uS by performing dummy + read operation which consumes two */ + /* clock cycles for each operation */ + delay(200); + + /* apply NOP */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000183; + delay(1); + /* write to MPMCDyCntl reg to start PRECHARGing: PRECHARGE ALL */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000103; + delay(100); + /* start two auto refresh */ + *(volatile u32 *)(AS352X_MPMC_DYREF) = + MPMC_SDRAM_START_2_REF_CYCLES ; + /*- wait for 64 clk cycles of HCLK-*/ + delay(128); + /* Program the operational value of the Refresh cycles, + depending upon the device specified period */ + *(volatile u32 *)(AS352X_MPMC_DYREF) = + MPMC_SDRAM_DYNAMIC_REF / 16; + + /* Send the Mode set command to SDRAM */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000083; + + /*------------------------------------------------------------*/ + + /* Read the SDRAM address with the mode value */ + temp = *(volatile u32 *) (0x30000000 + MPMC_SDRAM_MODEVALUE) ; + + /* Merged with S.U. */ +#ifdef SDRAM_MT48H8M16LF + /* (MT48H8M16LF - 128Mbit - Low Power) */ + temp = *(volatile u32 *) (0x30000000 + MPMC_SDRAM_EXMODEVALUE) ; +#endif /*SDRAM_MT48H8M16LF*/ + /*--------------------------------------*/ + /* Send the Normal mode set command to the SDRAM */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000003; + /* Enable the buffer for the SDRAM */ + temp = *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) ; + *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) = + temp | (MPMC_SDRAM_BUFFER_ENABLE); +} + +/*Miscellaneous platform dependent initialisations*/ +void ccu_reset_device +( u32 device_mask + ) +{ + int i; + /* reset devices */ + write_reg32( CCU_SRC, device_mask ); + write_reg32( CCU_SRL, CCU_SRL_MAGIC_NUMBER ); + /* hold the reset for at least 10 microseconds */ + for ( i = CCU_COUNT_MIN_10_MICROSEC; i > 0; i-- ){ + write_reg32( CCU_SRL, CCU_SRL_MAGIC_NUMBER ); + } + /* remove lock */ + write_reg32( CCU_SRL, 0 ); + write_reg32( CCU_SRC, 0 ); +} + +void clk_set_async_mode() +{ + unsigned long i; + /* read CP15 register 1 into r0*/ + asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i)); + /*enable asynchronous clocking mode*/ + asm("orr r0, %0, #(0x3 <<30) ": :"r"(i)); + /* write cp15 register 1*/ + asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i)); +} + +int board_init (void) +{ + ccu_reset_device( CCU_RESET_ALL_BUT_MEMORY ); + /*init cgu regs*/ + write_reg32(CGU_REG_PERI, 0x0F802000); + write_reg32(CGU_REG_PROC,0); + write_reg32(CGU_REG_AUDIO,0); + write_reg32(CGU_REG_USB,0); + write_reg32(CGU_REG_INTCTRL,0); + + write_reg32(CGU_REG_COUNTA,0); + write_reg32(CGU_REG_COUNTB,0); + write_reg32(CGU_REG_IDE,0); + write_reg32(CGU_REG_MEMSTICK,0); + write_reg32(CGU_REG_DBOP,0); + + + write_reg32(CGU_REG_PLLASUP,0x8); + write_reg32(CGU_REG_PLLBSUP,0x8); + + write_reg32(CGU_REG_PLLA,0); + write_reg32(CGU_REG_PLLB,0); + + clk_set_async_mode(); + /*set cpu and bus default clock + plla 384M, CPU 192M,mpmc 64M,pclk 64M */ + + write_reg32(CGU_REG_PLLA,0x2630); + write_reg32(CGU_REG_PLLASUP,0); + write_reg32(CGU_REG_COUNTA,CGU_LOCK_CNT); + while (!(read_reg32(CGU_REG_INTCTRL)&1)) ; + + write_reg32( CGU_REG_PROC, 0x011); + write_reg32(CGU_REG_PERI,0x0EF2E295); + + /* arch number of AS352X-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AS352X; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + sdram_init(); + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff -upBNr u-boot-1.1.6.org/board/as352xpb/config.mk u-boot-1.1.6/board/as352xpb/config.mk --- u-boot-1.1.6.org/board/as352xpb/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/config.mk 2006-12-04 09:48:37.000000000 +0800 @@ -0,0 +1,23 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> +# +# AMS AS352XPB board with AS352X (ARM922T) cpu +# +# see http://www.austriamicrosystems.com for more information +# +# +# AS352X has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3400'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# optionally with a ramdisk at 3080'0000 +# +# we load ourself to 0000'0000 +# +# download area is 3300'0000 +# + +TEXT_BASE = 0x00000000 diff -upBNr u-boot-1.1.6.org/board/as352xpb/lowlevel_init.S u-boot-1.1.6/board/as352xpb/lowlevel_init.S --- u-boot-1.1.6.org/board/as352xpb/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/lowlevel_init.S 2006-12-04 09:48:37.000000000 +0800 @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + +/* some parameters for the board */ + +/* + * + */ + + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ diff -upBNr u-boot-1.1.6.org/board/as352xpb/Makefile u-boot-1.1.6/board/as352xpb/Makefile --- u-boot-1.1.6.org/board/as352xpb/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/Makefile 2006-12-04 09:48:37.000000000 +0800 @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := as352xpb.o nandas.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -upBNr u-boot-1.1.6.org/board/as352xpb/nandas.c u-boot-1.1.6/board/as352xpb/nandas.c --- u-boot-1.1.6.org/board/as352xpb/nandas.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/nandas.c 2006-12-04 10:30:57.000000000 +0800 @@ -0,0 +1,410 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> +#include <asm/errno.h> +/* +* hardware specific access to control-lines +*/ + +#define NAF_X8_X16_CODE 0x03 /* only for big block nand */ + +/** +* Power bit in NAF mode register. +**/ +#define NAF_POWER_ON 0x0C +#define NAF_POWER_OFF 0x00 + +/** +* NAF Config register bits. +**/ +#define NAF_X16 0x00000001 +#define NAF_FIFO_ENABLE 0x00000004 +#define NAF_DMA_ON 0x00000008 + +/* read strobe high is 4 PLCK cycles */ +#define NAF_READ_STROBE_H 0x00000020 + +/* read strobe low is 5 PLCK cycles */ +#define NAF_READ_STROBE_L 0x00000400 + +/* write strobe high is 4 PCLK cycles */ +#define NAF_WRITE_STROBE_H 0x00003000 + +/* write strobe high is 4 PCLK cycles */ +#define NAF_WRITE_STROBE_L 0x00040000 + +#define NAF_STROBE_CONFIG \ + ( NAF_READ_STROBE_H | NAF_READ_STROBE_L \ + | NAF_WRITE_STROBE_H | NAF_WRITE_STROBE_L ) + + +/** +* NAF modi +**/ +#define NAF_MODE_CLE 1<<0 +#define NAF_MODE_ALE 1<<1 +#define NAF_MODE_NCE 1<<4 +#define NAF_MODE_WP 1<<7 + +#define NAF_MODE_DATA_READ_NO_ECC 0x14 +#define NAF_MODE_DATA_WRITE_ECC_RESET 0xF4 +#define NAF_MODE_DATA_WRITE_NO_ECC 0x94 +/* +* chip R/B detection +*/ +static int as352x_read_status; + +static int as352x_nand_ready(struct mtd_info *mtd) +{ + return ( ( read_reg16( NAF_STATUS ) & 0x0080 ) == 0x0080 ); + +} +static int as352x_nand_strobe() +{ + return ( ( read_reg16( NAF_STATUS ) & 0x0100 ) == 0x0100 ); +} +static int as352x_fifo_isfull() +{ + return ( ( read_reg16( NAF_STATUS ) & 0x01000 ) ); +} + +static int as352x_fifo_isempty() +{ + return ( ( read_reg16( NAF_STATUS ) & 0x0200 ) ); +} +/** +* nand_read_byte - [DEFAULT] read one byte from the chip +* @mtd: MTD device structure +* +* Default read function for 8bit buswith +*/ +static u_char as352x_nand_read_byte(struct mtd_info *mtd) +{ + u_char data; + write_reg8 ( NAF_CONTROL, 0x1 ); /* generate read strobe */ + while (!as352x_nand_strobe(mtd)); + data = read_reg16( NAF_DATA ); + if (as352x_read_status) + data |= 0x80; + return data; +} + +/** +* nand_write_byte - [DEFAULT] write one byte to the chip +* @mtd: MTD device structure +* @byte: pointer to data byte to write +* +* Default write function for 8it buswith +*/ +static void as352x_nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + + write_reg16( NAF_DATA, byte ); + while (!as352x_nand_strobe(mtd)); +} + +void as352x_nand_wait_fifo_empty( ) +{ + /* wait for got empty and ready */ + while ( ( read_reg16( NAF_STATUS ) & 0x0004 ) != 0x0004 ) ; +} + +/** +* nand_write_buf - [DEFAULT] write buffer to chip +* @mtd: MTD device structure +* @buf: data buffer +* @len: number of bytes to write +* +* Default write function for 8bit buswith +*/ +static void as352x_nand_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + int i; + u32 *p =(u32 *)buf; + struct nand_chip *this = mtd->priv; + len /=4; + write_reg8( NAF_CLEAR, 0x7f ); + write_reg32( NAF_WORDS, len ); + for (i=0; i<len; i++){ + while (as352x_fifo_isfull()); + write_reg32( NAF_FIFODATA, p[i] ); + } + as352x_nand_wait_fifo_empty(); +} + +/** +* nand_read_buf - [DEFAULT] read chip data into buffer +* @mtd: MTD device structure +* @buf: buffer to store date +* @len: number of bytes to read +* +* Default read function for 8bit buswith +*/ +static void as352x_nand_read_buf(struct mtd_info *mtd, + u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u32 *p =(u32 *)buf; + len /=4; + write_reg8( NAF_CLEAR, 0x7f ); + write_reg32( NAF_WORDS, len ); + for (i=0; i<len; i++){ + while (as352x_fifo_isempty()); + p[i] = read_reg32( NAF_FIFODATA ); + } + as352x_nand_wait_fifo_empty( ); +} +/** +* nand_verify_buf - [DEFAULT] Verify chip data against buffer +* @mtd: MTD device structure +* @buf: buffer containing the data to compare +* @len: number of bytes to compare +* +* Default verify function for 8bit buswith +*/ +static int nand_verify_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; i<len; i++) + if (buf[i] != as352x_nand_read_byte(mtd)) + return -EFAULT; + + return 0; +} + +static void as352x_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + + struct nand_chip *this = mtd->priv; + + switch (cmd) { + case NAND_CTL_SETCLE:{ + set_reg_bits16 ( NAF_MODE, NAF_MODE_CLE ); + } + break; + case NAND_CTL_CLRCLE: + clr_reg_bits16( NAF_MODE, NAF_MODE_CLE ); + break; + case NAND_CTL_SETALE:{ + set_reg_bits16 ( NAF_MODE, NAF_MODE_ALE ); + + } + break; + case NAND_CTL_CLRALE: + clr_reg_bits16( NAF_MODE, NAF_MODE_ALE ); + break; + case NAND_CTL_SETNCE: + set_reg_bits16 ( NAF_MODE, NAF_MODE_NCE ); + break; + case NAND_CTL_CLRNCE: + clr_reg_bits16( NAF_MODE, NAF_MODE_NCE ); + break; + case NAND_CTL_SETWP: + set_reg_bits16 ( NAF_MODE, NAF_MODE_WP ); + break; + case NAND_CTL_CLRWP: + clr_reg_bits16( NAF_MODE, NAF_MODE_WP ); + break; + + } +} +/** +* nand_command_lp - [DEFAULT] Send command to NAND large page device +* @mtd: MTD device structure +* @command: the command to be sent +* @column: the column address for this command, -1 if none +* @page_addr: the page address for this command, -1 if none +* +* Send command to NAND device. + This is the version for the new large page devices +* We dont have the seperate regions as we have in the small page devices. +* We must emulate NAND_CMD_READOOB to keep the code compatible. +* +*/ + +static void as352x_nand_command_lp (struct mtd_info *mtd, + unsigned command, int column, + int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + column += mtd->oobblock; + command = NAND_CMD_READ0; + } + + as352x_read_status =0; + switch (command) { + case NAND_CMD_SEQIN: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2:{ + write_reg8( NAF_MASK, 0xFF ); + write_reg8( NAF_CLEAR, 0x7f ); + } + case NAND_CMD_CACHEDPROG: + case NAND_CMD_PAGEPROG:{ + this->hwcontrol(mtd, NAND_CTL_SETWP); + } + break; + case NAND_CMD_READ0: + write_reg8( NAF_MASK, 0xFF ); + write_reg8( NAF_CLEAR, 0x7f ); + write_reg8( NAF_MODE,NAF_MODE_DATA_READ_NO_ECC); + default: + this->hwcontrol(mtd, NAND_CTL_CLRWP); + } + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the command to the device. */ + this->write_byte(mtd, command); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column & 0xff); + this->write_byte(mtd, column >> 8); + } + if (page_addr != -1) { + this->write_byte(mtd, + (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, + (unsigned char) + ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 128MiB */ + if (this->chipsize > (128 << 20)) + this->write_byte(mtd, + (unsigned char) ((page_addr >> 16) & 0xff)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + case NAND_CMD_SEQIN:{ + write_reg8( NAF_MODE, NAF_MODE_DATA_WRITE_ECC_RESET ); + break; + } + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + break; + case NAND_CMD_STATUS: + as352x_read_status =1; + break; + case NAND_CMD_CACHEDPROG: + + case NAND_CMD_PAGEPROG: + write_reg8( NAF_MODE, NAF_MODE_DATA_WRITE_NO_ECC ); + break; + + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + case NAND_CMD_READ0: + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the start read command */ + this->write_byte(mtd, NAND_CMD_READSTART); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + /* Fall through into ready check */ + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, + we apply the given command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (1000); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + + +void board_nand_init(struct nand_chip *nand) +{ + /* clear all NAF chip select bits*/ + clr_reg_bits32( CCU_IO , + ( CCU_IO_NAF_CE_LINE_0 | CCU_IO_NAF_CE_LINE_1 + | CCU_IO_NAF_CE_LINE_2 | CCU_IO_NAF_CE_LINE_3 ) ); + + set_reg_bits32( CCU_IO , CCU_IO_NAF_CE_LINE_0 ); + + /* configure NAF */ + write_reg8( NAF_MODE, NAF_POWER_ON ); /* turn power on */ + write_reg8( NAF_MASK, 0xFF ); + write_reg8( NAF_CLEAR, 0x7f ); /* clear any pending error indication */ + + /* configure fifo on but dma still off */ + write_reg32( NAF_CONFIG, NAF_FIFO_ENABLE | NAF_STROBE_CONFIG ); + + /* 2. change into read mode */ + write_reg8 ( NAF_MODE, NAF_MODE_DATA_READ_NO_ECC ); + + nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = as352x_nand_hwcontrol; + nand->dev_ready = as352x_nand_ready; + nand->chip_delay = 18; + nand->read_byte = as352x_nand_read_byte; + nand->write_byte = as352x_nand_write_byte; + nand->read_buf = as352x_nand_read_buf; + nand->write_buf = as352x_nand_write_buf; + nand->cmdfunc = as352x_nand_command_lp; +} +#endif diff -upBNr u-boot-1.1.6.org/board/as352xpb/u-boot.lds u-boot-1.1.6/board/as352xpb/u-boot.lds --- u-boot-1.1.6.org/board/as352xpb/u-boot.lds 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/u-boot.lds 2006-12-04 09:48:37.000000000 +0800 @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm922t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -upBNr u-boot-1.1.6.org/common/env_nand.c u-boot-1.1.6/common/env_nand.c --- u-boot-1.1.6.org/common/env_nand.c 2006-12-01 17:49:33.000000000 +0800 +++ u-boot-1.1.6/common/env_nand.c 2006-11-30 09:35:19.000000000 +0800 @@ -162,9 +162,13 @@ int saveenv(void) if(gd->env_valid == 1) { puts ("Erasing redundant Nand..."); - if (nand_erase(&nand_info[0], - CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) - return 1; +#ifdef CONFIG_AS352X + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET_REDUND, CFG_ENV_NAND_ERASE_SIZE)) + return 1; +#else + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) + return 1; +#endif puts ("Writing to redundant Nand... "); ret = nand_write(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, (u_char*) env_ptr); @@ -192,9 +196,13 @@ int saveenv(void) int ret = 0; puts ("Erasing Nand..."); +#ifdef CONFIG_AS352X + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_NAND_ERASE_SIZE)) + return 1; +#else if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE)) return 1; - +#endif puts ("Writing to Nand... "); total = CFG_ENV_SIZE; ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); diff -upBNr u-boot-1.1.6.org/cpu/arm922t/as352x/interrupts.c u-boot-1.1.6/cpu/arm922t/as352x/interrupts.c --- u-boot-1.1.6.org/cpu/arm922t/as352x/interrupts.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/interrupts.c 2006-12-04 10:30:50.000000000 +0800 @@ -0,0 +1,212 @@ +/* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Marius Groeger <mgroeger(a)sysgo.de> +* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Alex Zuepke <azu(a)sysgo.de> +* +* (C) Copyright 2002 +* Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <arm922t.h> +#include <as352x.h> + +#if defined(CONFIG_AS352X) +#define TIMER_LOAD_VAL 0xffffffff +static ulong timestamp; +static ulong lastdec; +#define CFG_TIMER_INTERVAL 1500000 +#define CFG_TIMER_RELOAD (CFG_TIMER_INTERVAL) + +int interrupt_init (void) +{ + u32 val = read_reg32(CGU_REG_PERI); + + write_reg32(val|CGU_TIMER1_CLOCK_ENABLE ,CGU_REG_PERI); + + /* + * Initialise to a known state (all timers off) + */ + write_reg32(TIMER_CONTROL,0); + write_reg32(TIMER_CONTROL,0); + + write_reg32(TIMER_INTCLR,1); + write_reg32(TIMER_INTCLR,1); + + write_reg32(TIMER_LOAD,CFG_TIMER_RELOAD ); + write_reg32(TIMER_VALUE,CFG_TIMER_RELOAD); + + write_reg32(TIMER_CONTROL,TIMER_PRESCALE_1 | TIMER_ENABLE |TIMER_32_BIT ); + + reset_timer_masked(); + return (0); +} + + + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if(usec >= 1000){ +/* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; +/* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; + /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; + /* finish normalize. */ + }else{ + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + /* get current timestamp */ + tmp = get_timer (0); + /* if setting this fordward will roll time stamp */ + if( (tmo + tmp + 1) < tmp ) + /* reset "advancing" timestamp to 0, set lastdec value */ + reset_timer_masked (); + else + /* else, set advancing stamp wake up time */ + tmo += tmp; + + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + + +void reset_timer_masked (void) +{ + /* reset time */ + /* capure current decrementer value time */ + lastdec = read_reg32(TIMER_VALUE); + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + /* current tick value */ + ulong now = read_reg32(TIMER_VALUE); + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + /* move stamp fordward with absoulte diff ticks */ + timestamp += lastdec - now; + } else { + /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"... + *it could also roll and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + /* if "big" number, spread normalization to seconds */ + if (usec >= 1000) { + /* start to normalize for usec to ticks per sec */ + tmo = usec / 1000; + /* find number of "ticks" to wait to achieve target */ + tmo *= CFG_HZ; + tmo /= 1000; /* finish normalize. */ + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* +* This function is derived from PowerPC code (read timebase as long long). +* On ARM it just returns the timer value. +*/ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* +* This function is derived from PowerPC code (timebase clock frequency). +* On ARM it returns the number of timer ticks per second. +*/ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} + + +/* +* reset the cpu by setting up the watchdog timer and let him time out +*/ +void reset_cpu (ulong ignored) +{ + + /* Disable watchdog */ + + /* Initialize watchdog timer count register */ + + /* Enable watchdog timer; assert reset at timer timeout */ + + while(1); /* loop forever and wait for reset to happen */ + + /*NOTREACHED*/ +} + +#endif /* defined(CONFIG_AS352X) */ diff -upBNr u-boot-1.1.6.org/cpu/arm922t/as352x/Makefile u-boot-1.1.6/cpu/arm922t/as352x/Makefile --- u-boot-1.1.6.org/cpu/arm922t/as352x/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/Makefile 2006-12-04 09:55:14.000000000 +0800 @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = interrupts.o serial.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################

1 0

[U-Boot-Users] usbtty .inf file
by Chris B 05 Dec '06

05 Dec '06

Does anybody have a sample Windows .INF file that would allow one to connect to u-boot's USBTTY...such as the one needed for the Siemen's SX1? Thanks, Chris ____________________________________________________________________________________ Want to start your own business? Learn how on Yahoo! Small Business. http://smallbusiness.yahoo.com/r-index

1 0

[U-Boot-Users] to check the board
by Nethra 05 Dec '06

05 Dec '06

hi, i am using 8248 custom board. Now i want check the board by toggling the led without using u-boot. Is it possible?If possible which one we have to use(flash,sdram)........... with regards Nethra -- View this message in context: http://www.nabble.com/to-check-the-board-tf2759113.html#a7692851 Sent from the Uboot - Users mailing list archive at Nabble.com.

3 2

[U-Boot-Users] [PATCH] use CFI-Flash and board depended driver together
by Jens Scharsig 05 Dec '06

05 Dec '06

Hello, i need to use cfi and board flash driver together. This Patch contains a simple way to do this with a minimun changes at cfi_flash.c. All changes will only enable if CFG_FLASH_BOARD_DRIVER defined. CHANGELOG * Rename flash_print_info, flash_erase, write_buff and flash_real_protect to cfi_xxxx, if CFG_FLASH_BOARD_DRIVER is defined. This will allow use cfi driver together with board a dependent flash driver (see README.board-dependent-flash for an example) diff --git a/doc/README.board-dependent-flash b/doc/README.board-dependent-flash new file mode 100644 index 0000000..d71cf49 --- /dev/null +++ b/doc/README.board-dependent-flash @@ -0,0 +1,145 @@ +How to use CFI-Flash and board depended driver together +========================================================= + +1. OVERVIEW +----------- +If CFG_FLASH_BOARD_DRIVER is defined, the following functions are renamed +in CFI_XXXX: flash_print_info + flash_erase + write_buff + flash_real_protect + +They can be called now by the board flash functions. + + +2. Target/Broard dependent Driver +--------------------------------- + +You can use the following functions as pattern for your own implementation: + + +/*---------------------------------------------------------------------------*/ +/* boardflash.c */ +/*---------------------------------------------------------------------------*/ + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*---------------------------------------------------------------------------*/ + +ulong board_flash_get_size (ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + + if (base == CFG_INT_FLASH_BASE) + { + debug("Use Board Flash-Init at %p\n",base); + /* put your on code here */ + } + else + { + debug("Use CFI Flash-Init at %p\n",base); + flash_get_size (base,banknum); + } + + return (info->size); +} + +/*---------------------------------------------------------------------------*/ + +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case <your vendor>: + /* put your on code here */ + break; + default: + cfi_flash_print_info (info); + return; + break; + } + + puts (" Size: "); + if ((info->size >> 20) > 0) + { + printf ("%ld MiB",info->size >> 20); + } + else + { + printf ("%ld KiB",info->size >> 10); + } + printf (" in %d Sectors\n", info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 4) == 0) { + printf ("\n "); + } + printf ("%02d: %08lX%s ", i,info->start[i], + info->protect[i] ? " P" : " "); + } + printf ("\n\n"); +} + +/*---------------------------------------------------------------------------*/ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int iflag, cflag; + int sector; + int rc; + + switch (info->flash_id & FLASH_VENDMASK) + { + case <your vendor>: + /* put your on code here */ + break; + default: + rc=cfi_flash_erase (info,s_first,s_last); + } + return rc; +} + +/*---------------------------------------------------------------------------*/ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + + switch (info->flash_id & FLASH_VENDMASK) + { + case (<your vendor>: + /* put your on code here */ + break; + default: + rc = cfi_write_buff (info,src,addr,cnt); + } + return rc; +} + +/*---------------------------------------------------------------------------*/ + +#ifdef CFG_FLASH_PROTECTION + +int flash_real_protect(flash_info_t * info,long sector,int prot) +{ + int rc; + + switch (info->flash_id & FLASH_VENDMASK) + { + case <your vendor>: + /* put your on code here */ + break; + default: + rc = cfi_flash_real_protect(info,sector,prot); + } + return rc; +} + +#endif +/*---------------------------------------------------------------------------*/ +/* end of boardflash.c */ +/*---------------------------------------------------------------------------*/ + + diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index fd0a186..9c05130 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -71,6 +71,13 @@ * Verify erase and program timeouts. */ +#ifdef CFG_FLASH_BOARD_DRIVER +#define flash_print_info cfi_flash_print_info +#define flash_erase cfi_flash_erase +#define write_buff cfi_write_buff +#define flash_real_protect cfi_flash_real_protect +#endif + #ifndef CFG_FLASH_BANKS_LIST #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #endif @@ -353,8 +360,13 @@ unsigned long flash_init (void) /* Init: no FLASHes known */ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; +#ifdef CFG_FLASH_BOARD_DRIVER + size += flash_info[i].size = board_flash_get_size (bank_base[i], i); +#else size += flash_info[i].size = flash_get_size (bank_base[i], i); +#endif if (flash_info[i].flash_id == FLASH_UNKNOWN) { #ifndef CFG_FLASH_QUIET_TEST printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", @@ -641,7 +653,7 @@ int write_buff (flash_info_t * info, uch i = cnt; if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) return rc; - i -= i & (info->portwidth - 1); + i -= (i % info->portwidth); wp += i; src += i; cnt -= i;

4 7

[U-Boot-Users] Problem with the ST Microlectronics M29W320B flash and the CFI driver.
by Txema Lopez 05 Dec '06

05 Dec '06

Hi all, We have a MPC5200B based custom board with a ST Microelectronics M29W320B (x8/x16 flash in x8 mode) as boot flash. We are able to program the flash using a BDI2000 and start up U-Boot. But U-Boot is unable to detect the boot flash using the CFI driver. With the same hardware (but other board) and a flash from other vendor (Spansion S29GL32A) the CFI driver works properly. Has anyone tested the CFI driver for the M29W320B flash? This is the BDI2000 output when we write a CFI Query command ffc00000 : 2000 5722 FFFF FFFF FFFF FFFF FFFF FFFF .W"............ ffc00010 : FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF ................ ffc00020 : 5100 5200 5900 0200 0000 4000 0000 0000 Q.R.Y.....@..... ffc00030 : 0000 0000 0000 2700 3600 b500 c500 0400 ......'.6....... ffc00040 : 0000 0a00 0000 0400 0000 0300 0000 1600 ................ ffc00050 : 0200 0000 0000 0000 0200 0700 0000 2000 .............. . ffc00060 : 0000 3e00 0000 0000 0100 0000 0000 8000 ..>............. ffc00070 : 0000 3e00 0000 0000 0100 FFFF FFFF FFFF ..>............. ffc00080 : 5000 5200 4900 3100 3000 0000 0200 0100 P.R.I.1.0....... ffc00090 : 0100 0400 0000 0000 0000 b500 c500 0200 ................ ffc000a0 : FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF ................ ffc000b0 : FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF ................ ffc000c0 : FFFF 6012 4e3b f07d 9b54 3500 2002 2003 ..`.N;.}.T5. . . ffc000d0 : 1200 2700 3a00 0100 0000 0000 0000 0000 ..'.:........... ffc000e0 : 0000 0f00 0700 0200 0000 0100 0100 0000 ................ ffc000f0 : 0000 0000 0000 0100 0000 0000 0000 0000 ................ AFAIK the CFI driver is waiting an output like this for a x8/x16 device in x8 mode: ffc00020 : 5151 5252 5959 QQRRYY Am I wrong? Best regards,

2 3

[U-Boot-Users] bus fault in calling eth_init()
by Tom Brown 05 Dec '06

05 Dec '06

Hi, I've compiled up 1.1.6 and loaded it onto our board. I can't load linux because I can't do a tftp. I get a bus fault every time I use the tftp command or the ping command. I put some printf's into u-boot to try to diagnose the problem. What I've come up with is the call to eth_init() is the problem. Not the code in eth_init(), but the actuall call. Any ideas on what the problem may be or what I need to be looking at? The output of the bootup and result of the ping command is given below. Thanks, Tom U-Boot 1.1.6.2 (Dec 4 2006 - 15:11:37)for the 195Eg CPU: AMCC PowerPC 405EP Rev. B at 250 MHz (PLB=62, OPB=31, EBC=31 MHz) I2C boot EEPROM disabled Internal PCI arbiter enabled 16 kB I-Cache 16 kB D-Cache I2C: ready DRAM: 16 MB Top of RAM usable for U-Boot at: 01000000 Reserving 263k for U-Boot at: 00fbe000 Reserving 256k for malloc() at: 00f7e000 Reserving 144 Bytes for Board Info at: 00f7df70 Reserving 48 Bytes for Global Data at: 00f7df40 Stack Pointer at: 00f7df28 New Stack Pointer is: 00f7df28 Now running in RAM - U-Boot at: 00fbe000 FLASH: manufact type value = 1f8b02 flash_protect ON: from 0xFFFC0000 to 0xFFFFFFFF protect on 67 protect on 68 protect on 69 protect on 70 4 MB In: serial Out: serial Err: serial U-Boot relocated to 00fbe000 ### main_loop entered: bootdelay=1 ### main_loop: bootcmd="bootm ffc20000" Hit any key to stop autoboot: 0 => ping 172.16.32.9 find_cmd BEGIN cmd == ping find_cmd full match END cmdtp == 0xff5ec808 do_ping call NetLoop NetLoop BEGIN Setup packet buffers, aligned correctly PktBuf[0] == 002 Fill NeRxPackets Setup NetArpWaitTxPacket eth_halt == 0xfc235408 call eth_halt() bd == 0xf7df7008 eth_init == 0xfc200c08 call eth_init() Bus Fault @ 0x00fc2018, fixup 0x00000000 Machine check in kernel mode. Caused by (from msr): regs 00f7d828 Unknown values in msr NIP: 00FC2018 XER: 00000000 LR: 00FC2018 REGS: 00f7d828 TRAP: 0200 DAR: 00F7DF40 MSR: 00001000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 00FC20FC 00F7D918 C017F8D0 00000000 00FC2080 00F7E1D8 00000000 00000000 GPR08: 00000002 600022E8 00200000 00FF6358 00000000 00000000 00FFBA00 00FFE000 GPR16: 00000000 00000001 FFFFFFFF 00F7DC48 00001000 00F7D978 00000000 00FC019C GPR24: 00000000 00000000 FFFFFFFF 600022E8 00000001 00F7DF40 00FFBA98 00200000 Call backtrace: machine check

1 1

[U-Boot-Users] MMC/SD support for AT91SAM9261EK-board
by Lutz Ballaschke 04 Dec '06

04 Dec '06

Hi there, has anyone tried this before? I just know this board being supported by the atmel-patch for u-boot-1.1.4 and there is no MMC/SD support included. Might it be possible to adapt any existing source code? (possibly the AT91RM9200dk sources)? Thanx, Lutz -- I2SE GmbH Office Leipzig Egelstrasse 4 04103 Leipzig Germany www.i2se.com lutz.ballaschke(a)i2se.com phone:(+49)341/23101942

3 2

[U-Boot-Users] Please pull u-boot.git 'mpc83xx' branch
by Kumar Gala 04 Dec '06

04 Dec '06

Please pull from 'mpc83xx' branch of git://git.kernel.org/pub/scm/boot/u-boot/galak/u-boot.git to receive the following updates: cpu/mpc83xx/cpu.c | 2 - cpu/mpc83xx/cpu_init.c | 12 +++---- cpu/mpc83xx/speed.c | 12 +++---- doc/README.mpc83xxads | 2 - include/asm-ppc/global_data.h | 4 +- include/asm-ppc/immap_83xx.h | 66 +++++++++++++++++++++--------------------- include/configs/MPC8349EMDS.h | 1 include/configs/MPC8349ITX.h | 1 include/configs/TQM834x.h | 1 include/mpc83xx.h | 10 +++--- 10 files changed, 54 insertions(+), 57 deletions(-) commit cd6447cfd69ace6fc748ff1964d42107bc93beab Author: Kumar Gala <galak(a)kernel.crashing.org> Date: Mon Dec 4 12:42:06 2006 -0600 Fix config of Arbiter, System Priority, and Clock Mode on MPC83xx The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Wasn't not being used when setting the appropriate register Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> commit 2b0c21e7a44172084a1194897693977d01083e3e Author: Kumar Gala <galak(a)kernel.crashing.org> Date: Mon Dec 4 12:41:37 2006 -0600 Remove CONFIG_MPC8349 and use CONFIG_MPC834X instead CONFIG_MPC8349 is redudant with CONFIG_MPC834X. Additionally CONFIG_MPC834X truly states the class of processors the code is applicable for. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 1b51078..7efe7c5 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -97,7 +97,7 @@ int checkcpu(void) return -1; /* Not sure what this is */ } -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock)); #else printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock)); diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index e5725fb..442937c 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -69,31 +69,31 @@ void cpu_init_f (volatile immap_t * im) #ifdef CFG_ACR_PIPE_DEP /* Arbiter pipeline depth */ - im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT); + im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); #endif #ifdef CFG_SPCR_TSEC1EP /* TSEC1 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT); + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); #endif #ifdef CFG_SPCR_TSEC2EP /* TSEC2 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT); + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); #endif #ifdef CFG_SCCR_TSEC1CM /* TSEC1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT); + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); #endif #ifdef CFG_SCCR_TSEC2CM /* TSEC2 & I2C1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT); + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); #endif #ifdef CFG_ACR_RPTCNT /* Arbiter repeat count */ - im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT)); + im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT)); #endif /* RSR - Reset Status Register - clear all status (4.6.1.3) */ diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 7e53b1e..d0fe34a 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -99,7 +99,7 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbmph_clk; @@ -144,7 +144,7 @@ #endif sccr = im->clk.sccr; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -249,7 +249,7 @@ #endif /* unkown SCCR_ENCCM value */ return -6; } -#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8360) lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); #else @@ -266,7 +266,7 @@ #endif /* unknown lcrr */ return -10; } -#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8360) ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; @@ -314,7 +314,7 @@ #if defined (CONFIG_MPC8360) #endif gd->csb_clk = csb_clk; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) gd->tsec1_clk = tsec1_clk; gd->tsec2_clk = tsec2_clk; gd->usbmph_clk = usbmph_clk; @@ -364,7 +364,7 @@ #endif printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000); printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000); printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000); diff --git a/doc/README.mpc83xxads b/doc/README.mpc83xxads index d456103..f5ba6a7 100644 --- a/doc/README.mpc83xxads +++ b/doc/README.mpc83xxads @@ -49,7 +49,7 @@ Freescale MPC83xx ADS Boards include/configs/MPC8349ADS.h CONFIG_MPC83xx MPC83xx family - CONFIG_MPC8349 MPC8349 specific + CONFIG_MPC834X MPC834x specific CONFIG_MPC8349ADS MPC8349ADS board specific CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 8bc61b6..c113b7e 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -52,12 +52,12 @@ #endif #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbmph_clk; u32 usbdr_clk; -#endif /* CONFIG_MPC8349 */ +#endif /* CONFIG_MPC834X */ u32 core_clk; u32 i2c1_clk; u32 i2c2_clk; diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 43cde5e..b6f5bc4 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -90,7 +90,7 @@ #define SPCR_TBEN 0x00400000 /* E300 #define SPCR_TBEN_SHIFT (31-9) #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ #define SPCR_COREPR_SHIFT (31-11) -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ #define SPCR_TSEC1DP_SHIFT (31-19) #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ @@ -110,7 +110,7 @@ #elif defined (CONFIG_MPC8360) #define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR) #endif u32 sicrl; /* System General Purpose Register Low */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SICRL_LDP_A 0x80000000 #define SICRL_USB1 0x40000000 #define SICRL_USB0 0x20000000 @@ -143,7 +143,7 @@ #define SICRL_RES ~(SICRL_LDP_A | SI #endif u32 sicrh; /* System General Purpose Register High */ #define SICRH_DDR 0x80000000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SICRH_TSEC1_A 0x10000000 #define SICRH_TSEC1_B 0x08000000 #define SICRH_TSEC1_C 0x04000000 @@ -314,7 +314,7 @@ #define SICVR_IVECX 0xfc000000 /* Inter #define SICVR_IVEC 0x0000007f /* Interrupt vector */ #define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ #define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ #define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ @@ -333,7 +333,7 @@ #define SIIH_UART2 0x00000040 /* UART #define SIIH_SEC 0x00000020 /* SEC interrupt */ #define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ #define SIIH_I2C2 0x00000002 /* I2C2 interrupt */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SIIH_SPI 0x00000001 /* SPI interrupt */ #define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \ @@ -349,7 +349,7 @@ #endif #define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ #define SIIL_PIT 0x40000000 /* PIT interrupt */ #define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ #endif #define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ @@ -358,7 +358,7 @@ #define SIIL_SBA 0x02000000 /* System #define SIIL_DMA 0x01000000 /* DMA interrupt */ #define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ #define SIIL_GTM8 0x00400000 /* GTM8 interrupt */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */ #define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ #endif @@ -376,7 +376,7 @@ #define SIIL_GTM7 0x00000400 /* GTM7 i #define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ #define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ #define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \ | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \ | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \ @@ -444,7 +444,7 @@ #define SECNR_RES ~( SECNR_MIXB0T | SECN #define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ #define SERR_WDT 0x40000000 /* WDT MCP request */ #define SERR_SBA 0x20000000 /* SBA MCP request */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SERR_DDR 0x10000000 /* DDR MCP request */ #define SERR_LBC 0x08000000 /* LBC MCP request */ #define SERR_PCI1 0x04000000 /* PCI1 MCP request */ @@ -457,7 +457,7 @@ #define SERR_PCI 0x04000000 /* PCI MCP #endif #define SERR_MU 0x01000000 /* MU MCP request */ #define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \ |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \ |SERR_RNC ) @@ -540,7 +540,7 @@ #define RCWL_LBIUCM 0x80000000 /* LBIUC #define RCWL_LBIUCM_SHIFT 31 #define RCWL_DDRCM 0x40000000 /* DDRCM */ #define RCWL_DDRCM_SHIFT 30 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define RCWL_SVCOD 0x30000000 /* SVCOD */ #endif #define RCWL_SPMF 0x0f000000 /* SPMF */ @@ -552,7 +552,7 @@ #define RCWL_CEPDF 0x00000020 /* CEPDF #define RCWL_CEPDF_SHIFT 5 #define RCWL_CEPMF 0x0000001F /* CEPMF */ #define RCWL_CEPMF_SHIFT 0 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) #elif defined (CONFIG_MPC8360) #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF) @@ -560,7 +560,7 @@ #endif u32 rcwh; /* RCHL Register */ #define RCWH_PCIHOST 0x80000000 /* PCIHOST */ #define RCWH_PCIHOST_SHIFT 31 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define RCWH_PCI64 0x40000000 /* PCI64 */ #define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ #define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ @@ -573,7 +573,7 @@ #define RCWH_BMS 0x04000000 /* BMS * #define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ #define RCWH_SWEN 0x00800000 /* SWEN */ #define RCWH_ROMLOC 0x00700000 /* ROMLOC */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ #define RCWH_TSEC2M 0x00003000 /* TSEC2M */ #define RCWH_TPR 0x00000100 /* TPR */ @@ -582,7 +582,7 @@ #define RCWH_SDDRIOE 0x00000010 /* Seco #endif #define RCWH_TLE 0x00000008 /* TLE */ #define RCWH_LALE 0x00000004 /* LALE */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \ | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \ | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \ @@ -637,7 +637,7 @@ typedef struct clk83xx { u32 spmr; /* system PLL mode Register */ #define SPMR_LBIUCM 0x80000000 /* LBIUCM */ #define SPMR_DDRCM 0x40000000 /* DDRCM */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SPMR_SVCOD 0x30000000 /* SVCOD */ #endif #define SPMR_SPMF 0x0F000000 /* SPMF */ @@ -647,7 +647,7 @@ #define SPMR_COREPLL 0x007F0000 /* COREP #define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ #define SPMR_CEPDF 0x00000020 /* CEPDF */ #define SPMR_CEPMF 0x0000001F /* CEPMF */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \ | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \ | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF) @@ -660,7 +660,7 @@ #endif #define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ #define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ #define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ #define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ #define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ @@ -670,7 +670,7 @@ #endif #define OCCR_PCICD0 0x00800000 /* PCICD0 */ #define OCCR_PCICD1 0x00400000 /* PCICD1 */ #define OCCR_PCICD2 0x00200000 /* PCICD2 */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define OCCR_PCICD3 0x00100000 /* PCICD3 */ #define OCCR_PCICD4 0x00080000 /* PCICD4 */ #define OCCR_PCICD5 0x00040000 /* PCICD5 */ @@ -691,7 +691,7 @@ #define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCI |OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR ) #endif u32 sccr; /* system clock control Register */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ @@ -699,14 +699,14 @@ #define SCCR_TSEC2CM_SHIFT 28 #endif #define SCCR_ENCCM 0x03000000 /* ENCCM */ #define SCCR_ENCCM_SHIFT 24 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */ #define SCCR_USBMPHCM_SHIFT 22 #define SCCR_USBDRCM 0x00300000 /* USBDRCM */ #define SCCR_USBDRCM_SHIFT 20 #endif #define SCCR_PCICM 0x00010000 /* PCICM */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \ | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM) #endif @@ -726,7 +726,7 @@ #define PMCCR_DLPEN 0x00000002 /* DDR SD #if defined (CONFIG_MPC8360) #define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */ #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN) -#elif defined (CONFIG_MPC8349) +#elif defined (CONFIG_MPC834X) #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) #endif u32 pmcer; /* PMC Event Register */ @@ -738,7 +738,7 @@ #define PMCMR_RES ~(PMCMR_PMCIE) u8 res0[0xF4]; } pmc83xx_t; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) /* * general purpose I/O module */ @@ -1173,7 +1173,7 @@ #define LCRR_CLKDIV_SHIFT 0 u8 res8[0xF00]; } lbus83xx_t; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) /* * Serial Peripheral Interface */ @@ -1403,18 +1403,18 @@ #define EATCR_ES_MASK 0x000f0000 /* err #define EATCR_ES_EM 0x00000000 /* external master */ #define EATCR_ES_DMA 0x00050000 #define EATCR_CMD_MASK 0x0000f000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */ #endif #define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define EATCR_HPB 0x00000004 /* high parity bit */ #endif #define EATCR_PB 0x00000002 /* parity bit */ #define EATCR_VI 0x00000001 /* error information valid */ u32 eacr; u32 eeacr; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u32 edlcr; u32 edhcr; #elif defined (CONFIG_MPC8360) @@ -1477,7 +1477,7 @@ #define PIWAR_IWS_1G 0x0000001D #define PIWAR_IWS_2G 0x0000001E } pcictrl83xx_t; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) /* * USB */ @@ -1988,7 +1988,7 @@ typedef struct immap { reset83xx_t reset; /* Reset Module */ clk83xx_t clk; /* System Clock Module */ pmc83xx_t pmc; /* Power Management Control Module */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) gpio83xx_t pgio[2]; /* general purpose I/O module */ #elif defined (CONFIG_MPC8360) qepi83xx_t qepi; /* QE Ports Interrupts Registers */ @@ -1999,7 +1999,7 @@ #if defined (CONFIG_MPC8360) #endif u8 DDL_DDR[0x100]; u8 DDL_LBIU[0x100]; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u8 res1[0xE00]; #elif defined (CONFIG_MPC8360) u8 res1[0x200]; @@ -2010,7 +2010,7 @@ #endif fsl_i2c_t i2c[2]; /* I2C Controllers */ u8 res2[0x1300]; duart83xx_t duart[2]; /* DUART */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u8 res3[0x900]; lbus83xx_t lbus; /* Local Bus Controller Registers */ u8 res4[0x1000]; @@ -2022,7 +2022,7 @@ #elif defined (CONFIG_MPC8360) u8 res4[0x2000]; #endif dma83xx_t dma; /* DMA */ -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ ios83xx_t ios; /* Sequencer */ pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 5bed2d0..400583c 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -37,7 +37,6 @@ #undef DEBUG #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC83XX 1 /* MPC83XX family */ #define CONFIG_MPC834X 1 /* MPC834X family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ #undef CONFIG_PCI diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index cbdbb29..5e64772 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -62,7 +62,6 @@ #undef DEBUG * High Level Configuration Options */ #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ -#define CONFIG_MPC8349 /* MPC8349 specific */ #define CONFIG_PCI diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 728083b..7903a48 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -37,7 +37,6 @@ #undef DEBUG #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC83XX 1 /* MPC83XX family */ #define CONFIG_MPC834X 1 /* MPC834X specific */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_TQM834X 1 /* TQM834X board specific */ /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 03dd0ca..005c043 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -140,7 +140,7 @@ #define BR_ATOM_SHIFT 2 #endif #define BR_V 0x00000001 #define BR_V_SHIFT 0 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) #elif defined (CONFIG_MPC8360) #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V) @@ -227,7 +227,7 @@ #define OR_SDRAM_EAD_SHIFT 0 #define HRCWH_PCI_AGENT 0x00000000 #define HRCWH_PCI_HOST 0x80000000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define HRCWH_32_BIT_PCI 0x00000000 #define HRCWH_64_BIT_PCI 0x40000000 #endif @@ -235,7 +235,7 @@ #endif #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 #elif defined (CONFIG_MPC8360) @@ -258,14 +258,14 @@ #define HRCWH_SW_WATCHDOG_ENABLE 0x0 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 #define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) #define HRCWH_TSEC1M_IN_RGMII 0x00000000 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 #define HRCWH_TSEC1M_IN_GMII 0x00008000

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[U-Boot-Users] [PATCH] NXP Semiconductors PNX8550/PNX8535/PNX8536 SoC support added
by Robert Deliën 04 Dec '06

04 Dec '06

Hi, The patch attached adds support for the NXP Semiconductors (former Philips Semiconductors) PNX8550 SoC to U-Boot. As a target, the SilverBox development target (config_silverbox) has been added. The PNX8550 SoC contains a PR4450 MIPS core, a Philips implementation of a MIPS32 processor. This patch will work on later - MIPS 4KEc based - SoCs such as the PNX8535 and PNX8836 too, but there's no specific configuration for those available yet. Serious rework of the MIPS lowlevel code is required for that. Therefore the PNX8550 and PNX8535 U-Boot does not run cached, but it does run in the cached memory segment. For proper MIPS32 cache support significant rework of start.S and cache.S is needed. We opted not to do this at this time as that may break existing MIPS based boards. It is our intention to submit MIPS32 architecture compliant versions of these when the PNX8550/PNX8535 board support is in U-Boot. This will also include proper MIPS exception handling, something sorely missing. The PNX8550 and PNX8535 are SoCs that are part of the NXP Semiconductors Nexperia product line. NXP sells over 6,000,000 of these SoCs annually. They are used in high-end TV sets, set-top boxes and PVRs. With kind regards, Robert Deliën.

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[U-Boot-Users] LAN9118 ethernet controller
by William Feng 04 Dec '06

04 Dec '06

Hi, I have an ARM board which has a LAN9118 ethernet controller (SMSC) instead of a LAN91C111 which is supported in u-boot. Is there any existing patch or ongoing work to support it? Thanks, -William

2 1

[U-Boot-Users] Colilo integration...
by Jeremy C. Andrus 04 Dec '06

04 Dec '06

Hello, A few years ago I contributed a port of colilo to the Motorola/Freescale MCF5249. Recently I downloaded the latest U-Boot ditribution for use in another project (colilo seems to have disappeared), and I noticed a few of my own comments in the following two files: cpu/mcf52x2/cpu_init.c cpu/mcf52x2/start.S It appears as though this project absorbed some of the colilo code (probably a while ago). I don't usually like to be this picky, but I was wondering if I could get my name added to the CREDITS file as such: N: Jeremy C. Andrus E: jeremy(a)jeremya.com D: MCF5249 initialization code Sorry to be pedantic... -Jeremy -- ----------------------- Jeremy C. Andrus http://www.jeremya.com/ -----------------------

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[U-Boot-Users] mpc74xx cpu clock measure issue
by Zang Roy-r61911 04 Dec '06

04 Dec '06

Hi, all I work to add mpc7448hpc2 board to u-boot. I checked the u-boot code cpu/74xx_74xx/speed.c and found the following issue: static const int hid1_multipliers_x_10[] = { 25, /* 0000 - 2.5x */ 75, /* 0001 - 7.5x */ 70, /* 0010 - 7x */ 10, /* 0011 - bypass */ 20, /* 0100 - 2x */ 65, /* 0101 - 6.5x */ 100, /* 0110 - 10x */ 45, /* 0111 - 4.5x */ 30, /* 1000 - 3x */ 55, /* 1001 - 5.5x */ 40, /* 1010 - 4x */ 50, /* 1011 - 5x */ 80, /* 1100 - 8x */ 60, /* 1101 - 6x */ 35, /* 1110 - 3.5x */ 0 /* 1111 - off */ }; int get_clocks (void) { ulong clock = 0; /* calculate the clock frequency based upon the CPU type */ switch (get_cpu_type()) { case CPU_7448: case CPU_7455: case CPU_7457: /* * It is assumed that the PLL_EXT line is zero. * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; break; Roy: Can the hid1_multipliers_x_10 table reflect the PLL configuration of 7448/7455/7457? There are five bit for 7455/7457 to configure the PLL. case CPU_750GX: case CPU_750FX: clock = CFG_BUS_CLK * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; break; case CPU_7450: Roy: Why does 7450 locates here? Its hid1 has the same behavior as 7455/7457. case CPU_740: case CPU_740P: case CPU_745: case CPU_750CX: case CPU_750: case CPU_750P: case CPU_755: case CPU_7400: case CPU_7410: /* * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[get_hid1 () >> 28]; Roy: hid1_multipliers_x_10 is suitable here :-). If this issue can be confirmed, I will add a patch in my mpc7448hpc2 git tree at http://opensource.freescale.com Thanks! Roy

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Re: [U-Boot-Users] [DNX#2006120442000014] bobtai empiricis
by DENX Support System 04 Dec '06

04 Dec '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006120442000014] was created: <snip> > others come, to more pressing business. Since I am now in the open, so > > of our cheering fans. We moved on through what appeared to be a > Shouting and cursing and lying and stinking > scientists were sorting the males out this way, our cultural engineers > shyster who is theoretically paid to uphold the law. Yet you stand by > You could see that? The difference is obvious I suppose, to someone > from them following the others. There was a creak and a thud from > little surprised when a voice behind me said, Yes. > I thought so. But the galaxys loss is our gain. We are pleased > I dont believe you! I snapped. </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006120442000014] bobtai empiricis
by U-Boot patch tracking system 04 Dec '06

04 Dec '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006120442000014]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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[U-Boot-Users] error: arm-linux-gcc:unrecognized option` -MQ'
by 李亮 03 Dec '06

03 Dec '06

Hi All, I have downloaded u-boot latest version 1.1.6 from the sourceforge.net I have installed cross compiler for arm. my board and cross compiler : board: sbc2410x cross compiler: 2.95.3 cpu: arm920t pc enviroment :red hat 9 u-boot: 1.1.6 1).i set the enviroment variable #vi /etc/profile --------/usr/local/arm/2.95.3/bin 2).I am using following procedure to compile:* make sbc2410x_config make all 3).I am getting an error indicates that *"arm-linux-gcc: unrecognized <BR>option `-MQ'"* the discrete information is the following : ~skip~ ~skip~ *make[1]: Leaving directory `/home/hcac/u-boot-1.1.6/post/cpu' make -C cpu/arm920t start.o make[1]: Entering directory `/home/hcac/u-boot-1.1.6/cpu/arm920t' arm-linux-gcc: start.o: No such file or directory arm-linux-gcc: unrecognized option `-MQ' arm-linux-gcc: cpu.o: No such file or directory arm-linux-gcc: unrecognized option `-MQ' arm-linux-gcc: interrupts.o: No such file or directory arm-linux-gcc: unrecognized option `-MQ' make[1]: *** [.depend] Error 1 make[1]: Leaving directory `/home/hcac/u-boot-1.1.6/cpu/arm920t' make: *** [cpu/arm920t/start.o] Error 2* * Thanks liliang -------

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[U-Boot-Users] [PATCH 1/8] Make autocomplete work with HUSH parser too.
by Pantelis Antoniou 02 Dec '06

02 Dec '06

Auto complete did not work when the HUSH parser was selected. Fix this obvious problem. --- Signed-off-by: Pantelis Antoniou <pantelis(a)embeddedalley.com> --- README | 4 ---- common/main.c | 25 +++++++++++++++++++++++-- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/README b/README index ecfd1f8..e28f935 100644 --- a/README +++ b/README @@ -1511,10 +1511,6 @@ The following options need to be configured: Enable auto completion of commands using TAB. - Note that this feature has NOT been implemented yet - for the "hush" shell. - - CFG_HUSH_PARSER Define this variable to enable the "hush" shell (from diff --git a/common/main.c b/common/main.c index cc4b50f..a8ae07c 100644 --- a/common/main.c +++ b/common/main.c @@ -718,10 +718,11 @@ static void cread_add_str(char *str, int strsize, int insert, unsigned long *num } } -static int cread_line(char *buf, unsigned int *len) +static int cread_line(const char *const prompt, char *buf, unsigned int *len) { unsigned long num = 0; unsigned long eol_num = 0; + int num2, col; unsigned long rlen; unsigned long wlen; char ichar; @@ -840,6 +841,7 @@ static int cread_line(char *buf, unsigned int *len) insert = !insert; break; case CTL_CH('x'): + case CTL_CH('u'): /* like that too */ BEGINNING_OF_LINE(); ERASE_TO_EOL(); break; @@ -889,6 +891,25 @@ static int cread_line(char *buf, unsigned int *len) REFRESH_TO_EOL(); continue; } +#ifdef CONFIG_AUTO_COMPLETE + case '\t': + + /* do not autocomplete when in the middle */ + if (num < eol_num) { + getcmd_cbeep(); + break; + } + + buf[num] = '\0'; + col = strlen(prompt) + eol_num; + num2 = num; + if (cmd_auto_complete(prompt, buf, &num2, &col)) { + col = num2 - num; + num += col; + eol_num += col; + } + break; +#endif default: cread_add_char(ichar, insert, &num, &eol_num, buf, *len); break; @@ -931,7 +952,7 @@ int readline (const char *const prompt) puts (prompt); - rc = cread_line(p, &len); + rc = cread_line(prompt, p, &len); return rc < 0 ? rc : len; #else char *p = console_buffer;

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[U-Boot-Users] [Patch01]AS352X:U-Boot1.1.6 patch 1 for AS352X SOC
by Luo Thomas 02 Dec '06

02 Dec '06

From:thomas.luo@austriamicrosystems. U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. Part 1: Br Signed-off-by: Thomas Luo ------------------------------------------------------------------------ ---- diff -urN u-boot-1.1.6.org/board/as352xpb/as352xpb.c u-boot-1.1.6/board/as352xpb/as352xpb.c --- u-boot-1.1.6.org/board/as352xpb/as352xpb.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/as352xpb.c 2006-12-01 17:44:42.000000000 +0800 @@ -0,0 +1,359 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <as352x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Macro introduced to compensate for no support for floating point +division operation in the processor. So to get the correct value, +roundup is peformed to provide accurate results for certain conditions. */ + +#define DIVIDE_AND_ROUND_UP(dividend,divisor) \ + ( ( (dividend) + (divisor) - 1 ) / (divisor) ) + +/* For sake of completness and for easier exchanging of round-up and round-down +divisions provide also a round-down macro */ + +#define DIVIDE_AND_ROUND_DOWN( a , b ) ((a)/(b)) + +/* Macro which evaluates to the absolute value of an integer value*/ +#define ABS(A) (((A)>0)?(A):(-(A))) + +/* ------------------------defines for Dynamic Mem --------------------------- */ +#define AS352X_SDRAM_BASE_ADDR(offset) (0xc6030000 + offset) + +#define AS352X_MPMC_CONTROL AS352X_SDRAM_BASE_ADDR( 0x00 ) +#define AS352X_MPMC_CONFIG AS352X_SDRAM_BASE_ADDR( 0x08 ) +#define AS352X_MPMC_DYRDCFG AS352X_SDRAM_BASE_ADDR( 0x28 ) +#define AS352X_MPMC_DYTRP AS352X_SDRAM_BASE_ADDR( 0x30 ) +#define AS352X_MPMC_DYTRAS AS352X_SDRAM_BASE_ADDR( 0x34 ) +#define AS352X_MPMC_DYTSREX AS352X_SDRAM_BASE_ADDR( 0x38 ) +#define AS352X_MPMC_DYTAPR AS352X_SDRAM_BASE_ADDR( 0x3C ) +#define AS352X_MPMC_DYTDAL AS352X_SDRAM_BASE_ADDR( 0x40 ) +#define AS352X_MPMC_DYTWR AS352X_SDRAM_BASE_ADDR( 0x44 ) +#define AS352X_MPMC_DYTRC AS352X_SDRAM_BASE_ADDR( 0x48 ) +#define AS352X_MPMC_DYTRFC AS352X_SDRAM_BASE_ADDR( 0x4C ) +#define AS352X_MPMC_DYTXSR AS352X_SDRAM_BASE_ADDR( 0x50 ) +#define AS352X_MPMC_DYTRRD AS352X_SDRAM_BASE_ADDR( 0x54 ) +#define AS352X_MPMC_DYTMRD AS352X_SDRAM_BASE_ADDR( 0x58 ) +#define AS352X_MPMC_DYRASCAS0 AS352X_SDRAM_BASE_ADDR( 0x104 ) +#define AS352X_MPMC_DYCONFIG0 AS352X_SDRAM_BASE_ADDR( 0x100 ) +#define AS352X_MPMC_DYCNTL AS352X_SDRAM_BASE_ADDR( 0x20 ) +#define AS352X_MPMC_DYREF AS352X_SDRAM_BASE_ADDR( 0x24 ) + +/* ------------------ MT48LC4M16A2 SDRAM & MT48LC32M16A2 SDRAM --------------------------- */ +#define MPMC_DY_TRP_IN_NS 20 +//#define MPMC_DY_TRP_IN_NS 10 + +#define MPMC_CLK_IN_MHZ_MIN 20 +#define MPMC_1_CLKCYCLE_IN_NS_MIN 50 + +#define MPMC_CLK_IN_MHZ 66 +//#define MPMC_CLK_IN_MHZ 24 +#if MPMC_CLK_IN_MHZ == 24 +#define MPMC_1_CLKCYCLE_IN_NS 42 +#elif MPMC_CLK_IN_MHZ == 66 +#define MPMC_1_CLKCYCLE_IN_NS 16 +#else +#define MPMC_1_CLKCYCLE_IN_NS 16 +#endif + +//#define MPMC_SDRAM_TCK_IN_NS 20 +#define MPMC_SDRAM_TCK_IN_NS 10 + +#define MPMC_DY_TRAS_MIN_IN_NS 50 +#define MPMC_DY_TRAS_IN_NS MPMC_DY_TRAS_MIN_IN_NS + +/* tAPR not available for micron MT48LC4M16A2 SDRAM */ +#define MPMC_DY_TAPR_INNS 0 + +#define MPMC_DY_TDAL_IN_NS (5 * (MPMC_SDRAM_TCK_IN_NS)) + +/* tWR can be minimum 15ns or 1CLK * 7ns */ +#define MPMC_DY_TWR_IN_NS (MPMC_1_CLKCYCLE_IN_NS + 8) +#define MPMC_DY_TRC_IN_NS 70 + +#define MPMC_DY_TRFC_INNS 70 + +#define MPMC_DY_TXSR_IN_NS 80 + +#define MPMC_DY_TRRD_IN_NS 20 +#define MPMC_DY_TMRD_IN_NS (2 * (MPMC_SDRAM_TCK_IN_NS)) + +#define MPMC_SDRAM_CAS 0x2 +#define MPMC_SDRAM_RAS 0x2 /* hha??? */ + +/* Low Power device bit settings */ +/* Device Type for APP Board 2.0 and 1.0 */ +/* MT48LC32M16A2 - 512Mbit and MT48LC4M16 - 64Mbit -both NOT Low Power */ +#define MPMC_SDRAM_DEVICE_TYPE (0 << 3) + +/*ROW and COLUMN size mapping for mpmc SoC device */ + +/* Addr Mapping for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +#define MPMC_SDRAM_ADDR_MAPPING (0x11 << 7) + +#define MPMC_SDRAM_32BIT_EXTBUS (0 <<14) +#define MPMC_SDRAM_BUFFER_DISABLE (0 <<19) +#define MPMC_SDRAM_BUFFER_ENABLE (1 <<19) +#define MPMC_SDRAM_WP_ENABLE (0 <<20) + +#define MPMC_SDRAM_DYN_CONFIG ((MPMC_SDRAM_DEVICE_TYPE) | \ + (MPMC_SDRAM_ADDR_MAPPING) | \ + (MPMC_SDRAM_32BIT_EXTBUS) | \ + (MPMC_SDRAM_BUFFER_DISABLE) | \ + (MPMC_SDRAM_WP_ENABLE)) + +#define MPMC_SDRAM_START_2_REF_CYCLES 2 +/* TREF for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +/*64ms divided by 8192 */ +#define MPMC_SDRAM_tREF_inNs 7812 + + +#define MPMC_SDRAM_DYNAMIC_REF ((MPMC_SDRAM_tREF_inNs) / (MPMC_1_CLKCYCLE_IN_NS_MIN)) + + + +/* CAS Latency for APP Board 2.0 (MT48LC32M16A2 - 512Mbit) */ +#if MPMC_SDRAM_CAS == 2 +#define MPMC_SDRAM_MODEVALUE (0x23 << 13) +#else +#define MPMC_SDRAM_MODEVALUE (0x33 << 13) +#endif + +/* ----------------------------------- functions --------------------------- */ + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} +void sdram_init(void ) +{ + volatile u32 Temp; + + + + *(volatile u32 *)AS352X_MPMC_CONTROL = 0x00000001; + + *(volatile u32 *)(AS352X_MPMC_CONFIG) = 0x00000000; + + *(volatile u32 *)(AS352X_MPMC_DYRDCFG) = 0x00000001; + + /* MPMCDynamicRP setup */ + *(volatile u32 *)(AS352X_MPMC_DYTRP) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRP_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)) ; + + /* MPMCDytRAS setup */ + *(volatile u32 *)(AS352X_MPMC_DYTRAS) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRAS_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamicSREX */ + *(volatile u32 *)(AS352X_MPMC_DYTSREX) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TXSR_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictAPR */ + *(volatile u32 *)(AS352X_MPMC_DYTAPR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TAPR_INNS),(MPMC_1_CLKCYCLE_IN_NS)); + + *(volatile u32 *)(AS352X_MPMC_DYTDAL) = + (1+(DIVIDE_AND_ROUND_UP((MPMC_DY_TDAL_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)))); + + /* Setup MPMCDynamictWR */ + *(volatile u32 *)(AS352X_MPMC_DYTWR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TWR_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictRC */ + *(volatile u32 *)(AS352X_MPMC_DYTRC) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRC_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictRFC */ + *(volatile u32 *)(AS352X_MPMC_DYTRFC) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRFC_INNS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictXSR */ + *(volatile u32 *)(AS352X_MPMC_DYTXSR) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TXSR_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictRRD */ + *(volatile u32 *)(AS352X_MPMC_DYTRRD) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TRRD_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + /* Setup MPMCDynamictMRD */ + *(volatile u32 *)(AS352X_MPMC_DYTMRD) = + DIVIDE_AND_ROUND_UP((MPMC_DY_TMRD_IN_NS),(MPMC_1_CLKCYCLE_IN_NS)); + + + *(volatile u32 *)(AS352X_MPMC_DYRASCAS0) = + ((MPMC_SDRAM_CAS << 0x8) | (MPMC_SDRAM_RAS)); + + + *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) = MPMC_SDRAM_DYN_CONFIG; + + /*wait for 200uS by performing dummy read operation which consumes two */ + /* clock cycles for each operation */ + delay(50); + + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000183; /* apply NOP */ + + delay(1); + + /* write to MPMCDyCntl reg to start PRECHARGing: PRECHARGE ALL */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000103; + + delay(100); + + /* start two auto refresh */ + *(volatile u32 *)(AS352X_MPMC_DYREF) = MPMC_SDRAM_START_2_REF_CYCLES ; + + /*- wait for 64 clk cycles of HCLK-*/ + delay(128); + + /* Program the operational value of the Refresh cycles, depending upon the + device specified period */ + *(volatile u32 *)(AS352X_MPMC_DYREF) = MPMC_SDRAM_DYNAMIC_REF / 16; + + /* Send the Mode set command to SDRAM */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000083; + + /*---------------------------------------------------------------------- */ + + /* Read the SDRAM address with the mode value, such that SDRAM will be + selected and the mode value will go as row address in HADDR [23:12] */ + Temp = *(volatile u32 *) (0x30000000 + MPMC_SDRAM_MODEVALUE) ; + + /* Merged with S.U. */ +#ifdef SDRAM_MT48H8M16LF + /* Device Type for APP Board 2.0 (MT48H8M16LF - 128Mbit - Low Power) */ + /* Read the SDRAM address with the mode value, such that SDRAM will be + selected and the mode value will go as row address in HADDR [23:12] */ + Temp = *(volatile u32 *) (0x30000000 + MPMC_SDRAM_EXMODEVALUE) ; +#endif /*SDRAM_MT48H8M16LF*/ + + /*---------------------------------------------------------------------- */ + /* Send the Normal mode set command to the SDRAM */ + *(volatile u32 *)(AS352X_MPMC_DYCNTL) = 0x00000003; + + /* Enable the buffer for the SDRAM */ + Temp = *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) ; + *(volatile u32 *)(AS352X_MPMC_DYCONFIG0) = + Temp | (MPMC_SDRAM_BUFFER_ENABLE); + +} +#define CCU_COUNT_MIN_10_MICROSEC 640 +/* +* Miscellaneous platform dependent initialisations +*/ + +void ccu_reset_device +( u32 deviceMask + ) +{ + int i; + + /* reset devices */ + wreg32( CCU_SRC, deviceMask ); + wreg32( CCU_SRL, CCU_SRL_MAGIC_NUMBER ); + + /* hold the reset for at least 10 microseconds */ + for ( i = CCU_COUNT_MIN_10_MICROSEC; i > 0; i-- ) + { + wreg32( CCU_SRL, CCU_SRL_MAGIC_NUMBER ); + } + + /* remove lock */ + wreg32( CCU_SRL, 0 ); + wreg32( CCU_SRC, 0 ); +} + +void clk_set_async_mode() +{ + unsigned long i; + /* read CP15 register 1 into r0*/ + asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i)); + /*enable asynchronous clocking mode*/ + asm("orr r0, %0, #(0x3 <<30) ": :"r"(i)); + /* write cp15 register 1*/ + asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i)); +} + + +int board_init (void) +{ + ccu_reset_device( CCU_RESET_ALL_BUT_MEMORY ); + + wreg32(CGU_REG_PERI, 0x0F802000); + wreg32(CGU_REG_PROC,0); + wreg32(CGU_REG_AUDIO,0); + wreg32(CGU_REG_USB,0); + wreg32(CGU_REG_INTCTRL,0); + + wreg32(CGU_REG_COUNTA,0); + wreg32(CGU_REG_COUNTB,0); + wreg32(CGU_REG_IDE,0); + wreg32(CGU_REG_MEMSTICK,0); + wreg32(CGU_REG_DBOP,0); + + + wreg32(CGU_REG_PLLASUP,0x8); + wreg32(CGU_REG_PLLBSUP,0x8); + + wreg32(CGU_REG_PLLA,0); + wreg32(CGU_REG_PLLB,0); + + clk_set_async_mode(); + //set cpu and bus default clock + //plla 384M, CPU 192M,mpmc 64M,pclk 64M + + wreg32(CGU_REG_PLLA,0x2630); + wreg32(CGU_REG_PLLASUP,0); + wreg32(CGU_REG_COUNTA,CGU_LOCK_CNT); + while (!(rreg32(CGU_REG_INTCTRL)&1)) ; + + wreg32( CGU_REG_PROC, 0x011); + wreg32(CGU_REG_PERI,0x0EF2E295); + + + + //ccuResetDevice( CCU_RESET_ALL_BUT_MEMORY ); + + /* arch number of AS352X-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AS352X; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + sdram_init(); + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff -urN u-boot-1.1.6.org/board/as352xpb/config.mk u-boot-1.1.6/board/as352xpb/config.mk --- u-boot-1.1.6.org/board/as352xpb/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/config.mk 2006-11-24 10:08:10.000000000 +0800 @@ -0,0 +1,23 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> +# +# AMS AS352XPB board with AS352X (ARM922T) cpu +# +# see http://www.austriamicrosystems.com for more information +# +# +# AS352X has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3400'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# optionally with a ramdisk at 3080'0000 +# +# we load ourself to 0000'0000 +# +# download area is 3300'0000 +# + +TEXT_BASE = 0x00000000 diff -urN u-boot-1.1.6.org/board/as352xpb/lowlevel_init.S u-boot-1.1.6/board/as352xpb/lowlevel_init.S --- u-boot-1.1.6.org/board/as352xpb/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/lowlevel_init.S 2006-11-30 10:24:49.000000000 +0800 @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + +/* some parameters for the board */ + +/* + * + */ + + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ diff -urN u-boot-1.1.6.org/board/as352xpb/Makefile u-boot-1.1.6/board/as352xpb/Makefile --- u-boot-1.1.6.org/board/as352xpb/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/Makefile 2006-11-29 16:02:27.000000000 +0800 @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := as352xpb.o nandas.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +####################################################################### ## + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +####################################################################### ## diff -urN u-boot-1.1.6.org/board/as352xpb/nandas.c u-boot-1.1.6/board/as352xpb/nandas.c --- u-boot-1.1.6.org/board/as352xpb/nandas.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/nandas.c 2006-12-01 17:47:46.000000000 +0800 @@ -0,0 +1,400 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> +#include <asm/errno.h> +/* + * hardware specific access to control-lines + */ + +#define NAF_X8_X16_CODE 0x03 /* only for big block nand */ + +/** + * Power bit in NAF mode register. + **/ +#define NAF_POWER_ON 0x0C +#define NAF_POWER_OFF 0x00 + +/** + * NAF Config register bits. + **/ +#define NAF_X16 0x00000001 +#define NAF_FIFO_ENABLE 0x00000004 +#define NAF_DMA_ON 0x00000008 + +#define NAF_READ_STROBE_H 0x00000020 /* read strobe high is 4 PLCK cycles */ +#define NAF_READ_STROBE_L 0x00000400 /* read strobe low is 5 PLCK cycles */ +#define NAF_WRITE_STROBE_H 0x00003000 /* write strobe high is 4 PCLK cycles */ +#define NAF_WRITE_STROBE_L 0x00040000 /* write strobe high is 4 PCLK cycles */ + +#define NAF_STROBE_CONFIG \ + ( NAF_READ_STROBE_H | NAF_READ_STROBE_L | NAF_WRITE_STROBE_H | NAF_WRITE_STROBE_L ) + + +/** + * NAF modi + **/ +#define NAF_MODE_CLE 1<<0 +#define NAF_MODE_ALE 1<<1 +#define NAF_MODE_NCE 1<<4 +#define NAF_MODE_WP 1<<7 + +#define NAF_MODE_DATA_READ_NO_ECC 0x14 +#define NAF_MODE_DATA_WRITE_ECC_RESET 0xF4 +#define NAF_MODE_DATA_WRITE_NO_ECC 0x94 +/* + * chip R/B detection + */ +static int as352x_read_status; + +static int as352x_nand_ready(struct mtd_info *mtd) +{ + return ( ( rreg16( NAF_STATUS ) & 0x0080 ) == 0x0080 ); + +} +static int as352x_nand_strobe() +{ + return ( ( rreg16( NAF_STATUS ) & 0x0100 ) == 0x0100 ); +} +static int as352x_fifo_isfull() +{ + return ( ( rreg16( NAF_STATUS ) & 0x01000 ) ); +} + +static int as352x_fifo_isempty() +{ + return ( ( rreg16( NAF_STATUS ) & 0x0200 ) ); +} +/** + * nand_read_byte - [DEFAULT] read one byte from the chip + * @mtd: MTD device structure + * + * Default read function for 8bit buswith + */ +static u_char as352x_nand_read_byte(struct mtd_info *mtd) +{ + u_char data; + wreg8 ( NAF_CONTROL, 0x1 ); /* generate read strobe */ + while (!as352x_nand_strobe(mtd)); + data = rreg16( NAF_DATA ); + if (as352x_read_status) + data |= 0x80; + return data; +} + +/** + * nand_write_byte - [DEFAULT] write one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default write function for 8it buswith + */ +static void as352x_nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + + wreg16( NAF_DATA, byte ); + while (!as352x_nand_strobe(mtd)); +} + +void as352x_nand_wait_fifo_empty( ) +{ + while ( ( rreg16( NAF_STATUS ) & 0x0004 ) != 0x0004 ) ; /* wait for got empty and ready */ +} + +/** + * nand_write_buf - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 8bit buswith + */ +static void as352x_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + u32 *p =(u32 *)buf; + struct nand_chip *this = mtd->priv; + len /=4; + wreg8( NAF_CLEAR, 0x7f ); + wreg32( NAF_WORDS, len ); + for (i=0; i<len; i++) + { + while (as352x_fifo_isfull()); + wreg32( NAF_FIFODATA, p[i] ); + } + as352x_nand_wait_fifo_empty(); +} + +/** + * nand_read_buf - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 8bit buswith + */ +static void as352x_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u32 *p =(u32 *)buf; + len /=4; + wreg8( NAF_CLEAR, 0x7f ); + wreg32( NAF_WORDS, len ); + for (i=0; i<len; i++) + { + while (as352x_fifo_isempty()); + p[i] = rreg32( NAF_FIFODATA ); + } + as352x_nand_wait_fifo_empty( ); +} +/** + * nand_verify_buf - [DEFAULT] Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + * + * Default verify function for 8bit buswith + */ +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; i<len; i++) + if (buf[i] != as352x_nand_read_byte(mtd)) + return -EFAULT; + + return 0; +} + +static void as352x_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + + struct nand_chip *this = mtd->priv; +// ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + switch (cmd) + { + case NAND_CTL_SETCLE: + { + set_reg_bits16 ( NAF_MODE, NAF_MODE_CLE ); + } + break; + case NAND_CTL_CLRCLE: + clr_reg_bits16( NAF_MODE, NAF_MODE_CLE ); + break; + case NAND_CTL_SETALE: + { + set_reg_bits16 ( NAF_MODE, NAF_MODE_ALE ); + + } + break; + case NAND_CTL_CLRALE: + clr_reg_bits16( NAF_MODE, NAF_MODE_ALE ); + break; + case NAND_CTL_SETNCE: + set_reg_bits16 ( NAF_MODE, NAF_MODE_NCE ); + break; + case NAND_CTL_CLRNCE: + clr_reg_bits16( NAF_MODE, NAF_MODE_NCE ); + break; + case NAND_CTL_SETWP: + set_reg_bits16 ( NAF_MODE, NAF_MODE_WP ); + break; + case NAND_CTL_CLRWP: + clr_reg_bits16( NAF_MODE, NAF_MODE_WP ); + break; + + } +} +/** + * nand_command_lp - [DEFAULT] Send command to NAND large page device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + * + * Send command to NAND device. This is the version for the new large page devices + * We dont have the seperate regions as we have in the small page devices. + * We must emulate NAND_CMD_READOOB to keep the code compatible. + * + */ + +static void as352x_nand_command_lp (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + column += mtd->oobblock; + command = NAND_CMD_READ0; + } + + as352x_read_status =0; + switch (command) + { + case NAND_CMD_SEQIN: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + { + wreg8( NAF_MASK, 0xFF ); + wreg8( NAF_CLEAR, 0x7f ); + } + case NAND_CMD_CACHEDPROG: + case NAND_CMD_PAGEPROG: + { + this->hwcontrol(mtd, NAND_CTL_SETWP); + } + break; + case NAND_CMD_READ0: + wreg8( NAF_MASK, 0xFF ); + wreg8( NAF_CLEAR, 0x7f ); + wreg8( NAF_MODE,NAF_MODE_DATA_READ_NO_ECC); + default: + this->hwcontrol(mtd, NAND_CTL_CLRWP); + } + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the command to the device. */ + this->write_byte(mtd, command); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column & 0xff); + this->write_byte(mtd, column >> 8); + } + if (page_addr != -1) { + this->write_byte(mtd, (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 128MiB */ + if (this->chipsize > (128 << 20)) + this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0xff)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + case NAND_CMD_SEQIN: + { + wreg8( NAF_MODE, NAF_MODE_DATA_WRITE_ECC_RESET ); + break; + } + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + break; + case NAND_CMD_STATUS: + as352x_read_status =1; + break; + case NAND_CMD_CACHEDPROG: + + case NAND_CMD_PAGEPROG: + wreg8( NAF_MODE, NAF_MODE_DATA_WRITE_NO_ECC ); + break; + + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + case NAND_CMD_READ0: + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the start read command */ + this->write_byte(mtd, NAND_CMD_READSTART); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + /* Fall through into ready check */ + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (1000); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + + +void board_nand_init(struct nand_chip *nand) +{ + // clear all NAF chip select bits + clr_reg_bits32( CCU_IO , ( CCU_IO_NAF_CE_LINE_0 | CCU_IO_NAF_CE_LINE_1 + | CCU_IO_NAF_CE_LINE_2 | CCU_IO_NAF_CE_LINE_3 ) ); + set_reg_bits32( CCU_IO , CCU_IO_NAF_CE_LINE_0 ); + + /* configure NAF */ + wreg8( NAF_MODE, NAF_POWER_ON ); /* turn power on */ + wreg8( NAF_MASK, 0xFF ); + wreg8( NAF_CLEAR, 0x7f ); /* clear any pending error indication */ + + /* configure fifo on but dma still off */ + wreg32( NAF_CONFIG, NAF_FIFO_ENABLE | NAF_STROBE_CONFIG ); + + /* 2. change into read mode */ + wreg8 ( NAF_MODE, NAF_MODE_DATA_READ_NO_ECC ); + + nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = as352x_nand_hwcontrol; + nand->dev_ready = as352x_nand_ready; + nand->chip_delay = 18; + nand->read_byte = as352x_nand_read_byte; + nand->write_byte = as352x_nand_write_byte; + nand->read_buf = as352x_nand_read_buf; + nand->write_buf = as352x_nand_write_buf; + nand->cmdfunc = as352x_nand_command_lp; +} +#endif diff -urN u-boot-1.1.6.org/board/as352xpb/u-boot.lds u-boot-1.1.6/board/as352xpb/u-boot.lds --- u-boot-1.1.6.org/board/as352xpb/u-boot.lds 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/u-boot.lds 2006-11-23 16:27:49.000000000 +0800 @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm922t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -urN u-boot-1.1.6.org/common/env_nand.c u-boot-1.1.6/common/env_nand.c --- u-boot-1.1.6.org/common/env_nand.c 2006-12-01 17:49:33.000000000 +0800 +++ u-boot-1.1.6/common/env_nand.c 2006-11-30 09:35:19.000000000 +0800 @@ -162,9 +162,13 @@ if(gd->env_valid == 1) { puts ("Erasing redundant Nand..."); - if (nand_erase(&nand_info[0], - CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) - return 1; +#ifdef CONFIG_AS352X + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET_REDUND, CFG_ENV_NAND_ERASE_SIZE)) + return 1; +#else + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) + return 1; +#endif puts ("Writing to redundant Nand... "); ret = nand_write(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, (u_char*) env_ptr); @@ -192,9 +196,13 @@ int ret = 0; puts ("Erasing Nand..."); +#ifdef CONFIG_AS352X + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_NAND_ERASE_SIZE)) + return 1; +#else if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE)) return 1; - +#endif puts ("Writing to Nand... "); total = CFG_ENV_SIZE; ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); diff -urN u-boot-1.1.6.org/cpu/arm922t/as352x/interrupts.c u-boot-1.1.6/cpu/arm922t/as352x/interrupts.c --- u-boot-1.1.6.org/cpu/arm922t/as352x/interrupts.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/interrupts.c 2006-12-01 17:43:30.000000000 +0800 @@ -0,0 +1,196 @@ +/* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Marius Groeger <mgroeger(a)sysgo.de> +* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Alex Zuepke <azu(a)sysgo.de> +* +* (C) Copyright 2002 +* Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <arm922t.h> +#include <as352x.h> + +#if defined(CONFIG_AS352X) +#define TIMER_LOAD_VAL 0xffffffff +static ulong timestamp; +static ulong lastdec; +#define CFG_TIMER_INTERVAL 1500000 +#define CFG_TIMER_RELOAD (CFG_TIMER_INTERVAL) + +int interrupt_init (void) +{ + u32 val = rreg32(CGU_REG_PERI); + + wreg32(val|CGU_TIMER1_CLOCK_ENABLE ,CGU_REG_PERI); + + /* + * Initialise to a known state (all timers off) + */ + wreg32(TIMER_CONTROL,0); + wreg32(TIMER_CONTROL,0); + + wreg32(TIMER_INTCLR,1); + wreg32(TIMER_INTCLR,1); + + wreg32(TIMER_LOAD,CFG_TIMER_RELOAD ); + wreg32(TIMER_VALUE,CFG_TIMER_RELOAD); + + wreg32(TIMER_CONTROL,TIMER_PRESCALE_1 | TIMER_ENABLE |TIMER_32_BIT ); + + reset_timer_masked(); + return (0); +} + + + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + }else{ /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = rreg32(TIMER_VALUE); /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = rreg32(TIMER_VALUE); /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* +* This function is derived from PowerPC code (read timebase as long long). +* On ARM it just returns the timer value. +*/ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* +* This function is derived from PowerPC code (timebase clock frequency). +* On ARM it returns the number of timer ticks per second. +*/ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} + + +/* +* reset the cpu by setting up the watchdog timer and let him time out +*/ +void reset_cpu (ulong ignored) +{ + + /* Disable watchdog */ + + /* Initialize watchdog timer count register */ + + /* Enable watchdog timer; assert reset at timer timeout */ + + while(1); /* loop forever and wait for reset to happen */ + + /*NOTREACHED*/ +} + +#endif /* defined(CONFIG_AS352X) */

4 5

[U-Boot-Users] [Patch02.2]AS352X:U-Boot1.1.6 patch 1 for AS352X SOC(New)
by thomas 02 Dec '06

02 Dec '06

From:thomas.luo@ieee.org U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525… Part 2.2: Br Signed-off-by: Thomas Luothomas.luo(a)austriamicrosystems.com ------------------------------------------------------------------------------- diff -urN u-boot-1.1.6.org/cpu/arm922t/interrupts.c u-boot-1.1.6/cpu/arm922t/interrupts.c --- u-boot-1.1.6.org/cpu/arm922t/interrupts.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/interrupts.c 2006-11-23 17:01:25.000000000 +0800 @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <arm920t.h> +#include <asm/proc-armv/ptrace.h> + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} diff -urN u-boot-1.1.6.org/cpu/arm922t/Makefile u-boot-1.1.6/cpu/arm922t/Makefile --- u-boot-1.1.6.org/cpu/arm922t/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/Makefile 2006-11-02 22:15:02.000000000 +0800 @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = cpu.o interrupts.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -urN u-boot-1.1.6.org/cpu/arm922t/start.S u-boot-1.1.6/cpu/arm922t/start.S --- u-boot-1.1.6.org/cpu/arm922t/start.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/start.S 2006-11-30 10:25:41.000000000 +0800 @@ -0,0 +1,353 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * relocate armboot to ram + * setup stack + * jump to second stage + * + ************************************************************************* + */ + +RAM_END: + .word 0x50000 + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word _end+200 + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word _end+400 +#endif + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + /* Set up the stack */ +stack_setup: + ldr r0, RAM_END /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + ldr r0,RAM_END + ldr r1,_bss_end + str r0,_armboot_start + add r1,r1,r0 + str r1,_bss_end + ldr r1,_bss_start + add r1,r1,r0 + str r1,_bss_start + ldr pc,_start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + mrc p15, 0, r0, c1, c0, 0 @ read CP15 register 1 into r0 + bic r0, r0, #0x0001 @ clear bit 0 MMU disable + bic r0, r0, #0x0004 @ clear bit 2 D-cache disable + bic r0, r0, #0x1000 @ clear bit 12 I-cache disable + bic r0, r0, #0xc0000000 @ clear bit 30,31 fast bus mode + mcr p15, 0, r0, c1, c0, 0 @ write value back + + @ invalidate all caches to have a clean startup + mov r2, #0 + mcr p15, 0, r2, c7, c7, 0 @ Invalidate D- and I-Cache + mcr p15, 0, r2, c8, c7, 0 @ invalidate all TLBs + + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + mov ip, lr + bl lowlevel_init + mov lr, ip + mov pc, lr +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get pc, cpsr + add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif diff -urN u-boot-1.1.6.org/CREDITS u-boot-1.1.6/CREDITS --- u-boot-1.1.6.org/CREDITS 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/CREDITS 2006-11-30 10:30:13.000000000 +0800 @@ -465,3 +465,8 @@ E: james.macaulay(a)amirix.com D: Suppport for Amirix AP1000 W: www.amirix.com + +N: Thomas Luo +E: thomas.luo(a)austriamicrosystems.com +D: Port to ARM base SOC AS352X. +W: www.austriamicrosystems.com

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[U-Boot-Users] [Patch02.1]AS352X:U-Boot1.1.6 patch 1 for AS352X SOC(New)
by thomas 02 Dec '06

02 Dec '06

From:thomas.luo@ieee.org U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. please ref: http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525… Part 2.1: Br Signed-off-by: Thomas Luothomas.luo(a)austriamicrosystems.com ------------------------------------------------------------------------------- diff -urN u-boot-1.1.6.org/board/as352xpb/u-boot.lds u-boot-1.1.6/board/as352xpb/u-boot.lds --- u-boot-1.1.6.org/board/as352xpb/u-boot.lds 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/board/as352xpb/u-boot.lds 2006-11-23 16:27:49.000000000 +0800 @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm922t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -urN u-boot-1.1.6.org/common/env_nand.c u-boot-1.1.6/common/env_nand.c --- u-boot-1.1.6.org/common/env_nand.c 2006-12-01 17:49:33.000000000 +0800 +++ u-boot-1.1.6/common/env_nand.c 2006-11-30 09:35:19.000000000 +0800 @@ -162,9 +162,13 @@ if(gd->env_valid == 1) { puts ("Erasing redundant Nand..."); - if (nand_erase(&nand_info[0], - CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) - return 1; +#ifdef CONFIG_AS352X + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET_REDUND, CFG_ENV_NAND_ERASE_SIZE)) + return 1; +#else + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) + return 1; +#endif puts ("Writing to redundant Nand... "); ret = nand_write(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, (u_char*) env_ptr); @@ -192,9 +196,13 @@ int ret = 0; puts ("Erasing Nand..."); +#ifdef CONFIG_AS352X + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_NAND_ERASE_SIZE)) + return 1; +#else if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE)) return 1; - +#endif puts ("Writing to Nand... "); total = CFG_ENV_SIZE; ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); diff -urN u-boot-1.1.6.org/cpu/arm922t/as352x/interrupts.c u-boot-1.1.6/cpu/arm922t/as352x/interrupts.c --- u-boot-1.1.6.org/cpu/arm922t/as352x/interrupts.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/interrupts.c 2006-12-01 17:43:30.000000000 +0800 @@ -0,0 +1,196 @@ +/* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Marius Groeger <mgroeger(a)sysgo.de> +* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Alex Zuepke <azu(a)sysgo.de> +* +* (C) Copyright 2002 +* Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <arm922t.h> +#include <as352x.h> + +#if defined(CONFIG_AS352X) +#define TIMER_LOAD_VAL 0xffffffff +static ulong timestamp; +static ulong lastdec; +#define CFG_TIMER_INTERVAL 1500000 +#define CFG_TIMER_RELOAD (CFG_TIMER_INTERVAL) + +int interrupt_init (void) +{ + u32 val = rreg32(CGU_REG_PERI); + + wreg32(val|CGU_TIMER1_CLOCK_ENABLE ,CGU_REG_PERI); + + /* + * Initialise to a known state (all timers off) + */ + wreg32(TIMER_CONTROL,0); + wreg32(TIMER_CONTROL,0); + + wreg32(TIMER_INTCLR,1); + wreg32(TIMER_INTCLR,1); + + wreg32(TIMER_LOAD,CFG_TIMER_RELOAD ); + wreg32(TIMER_VALUE,CFG_TIMER_RELOAD); + + wreg32(TIMER_CONTROL,TIMER_PRESCALE_1 | TIMER_ENABLE |TIMER_32_BIT ); + + reset_timer_masked(); + return (0); +} + + + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + }else{ /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = rreg32(TIMER_VALUE); /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = rreg32(TIMER_VALUE); /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* +* This function is derived from PowerPC code (read timebase as long long). +* On ARM it just returns the timer value. +*/ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* +* This function is derived from PowerPC code (timebase clock frequency). +* On ARM it returns the number of timer ticks per second. +*/ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} + + +/* +* reset the cpu by setting up the watchdog timer and let him time out +*/ +void reset_cpu (ulong ignored) +{ + + /* Disable watchdog */ + + /* Initialize watchdog timer count register */ + + /* Enable watchdog timer; assert reset at timer timeout */ + + while(1); /* loop forever and wait for reset to happen */ + + /*NOTREACHED*/ +} + +#endif /* defined(CONFIG_AS352X) */ diff -urN u-boot-1.1.6.org/cpu/arm922t/as352x/Makefile u-boot-1.1.6/cpu/arm922t/as352x/Makefile --- u-boot-1.1.6.org/cpu/arm922t/as352x/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/Makefile 2006-11-29 17:29:07.000000000 +0800 @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = interrupts.o serial.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -urN u-boot-1.1.6.org/cpu/arm922t/as352x/serial.c u-boot-1.1.6/cpu/arm922t/as352x/serial.c --- u-boot-1.1.6.org/cpu/arm922t/as352x/serial.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/serial.c 2006-12-01 17:43:18.000000000 +0800 @@ -0,0 +1,145 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#if defined(CONFIG_AS352X) +#include <as352x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* +* Initialise the serial port with the given baudrate. The settings +* are always 8 data bits, no parity, 1 stop bit, no start bits. +*/ +void serial_setbrg (void) +{ + u8 controlData; + set_reg_bits32(CCU_IO,CCU_IO_UART); + + /* reset the uart + */ + set_reg_bits32(CCU_SRC, CCU_SRC_UART0); + wreg32(CCU_SRL, CCU_SRL_MAGIC_NUMBER); + clr_reg_bits32(CCU_SRC, CCU_SRC_UART0); + wreg32(CCU_SRL, 0x0); + wreg32(UART_FCTL_REG, 0); + wreg32(UART_INTEN_REG, 0); + controlData = 3; + wreg32(UART_LNCTL_REG,controlData| UART_LNCTL_DLSEN); + wreg32(UART_DLO_REG,0x68); + wreg32(UART_DHI_REG,0x0); + wreg32(UART_LNCTL_REG,controlData& (~UART_LNCTL_DLSEN)); + +} +int serial_init (void) +{ + int i; + serial_setbrg(); + for (i = 0; i < 100; i++); + return (0); +} + +/* +* Read a single byte from the serial port. Returns 1 on success, 0 +* otherwise. When the function is succesfull, the character read is +* written into its argument c. +*/ +int serial_getc (void) +{ + u8 c; + + while (!(rreg32(UART_LNSTATUS_REG) & UART_RX_DATA_READY)); + c = rreg32(UART_DATA_REG); + return c&0xff; +} + +#ifdef CONFIG_HWFLOW +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ + switch(on) { + case 0: + default: + break; /* return current */ + case 1: + hwflow = 0; /* turn on */ + break; + case -1: + hwflow = 0; /* turn off */ + break; + } + return hwflow; +} +#endif + +#ifdef CONFIG_MODEM_SUPPORT +static int be_quiet = 0; +void disable_putc(void) +{ + be_quiet = 1; +} + +void enable_putc(void) +{ + be_quiet = 0; +} +#endif + + +/* +* Output a single byte to the serial port. +*/ +void serial_putc (const char c) +{ +#ifdef CONFIG_MODEM_SUPPORT + if (be_quiet) + return; +#endif + + /* wait for room in the tx FIFO */ + while (!(rreg32(UART_LNSTATUS_REG) & UART_TX_HOLD_REG_EMPTY)); + wreg32(UART_DATA_REG,c); + + + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* +* Test whether a character is in the RX buffer +*/ +int serial_tstc (void) +{ + return (rreg32(UART_LNSTATUS_REG) & UART_RX_DATA_READY); +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#endif /* defined(CONFIG_AS352X)*/ diff -urN u-boot-1.1.6.org/cpu/arm922t/config.mk u-boot-1.1.6/cpu/arm922t/config.mk --- u-boot-1.1.6.org/cpu/arm922t/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/config.mk 2006-11-24 16:43:15.000000000 +0800 @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + + +PLATFORM_CPPFLAGS += -march=armv4 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff -urN u-boot-1.1.6.org/cpu/arm922t/cpu.c u-boot-1.1.6/cpu/arm922t/cpu.c --- u-boot-1.1.6.org/cpu/arm922t/cpu.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/cpu.c 2006-12-01 17:43:54.000000000 +0800 @@ -0,0 +1,185 @@ +/* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Marius Groeger <mgroeger(a)sysgo.de> +* +* (C) Copyright 2002 +* Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +/* +* CPU specific code +*/ + +#include <common.h> +#include <command.h> +#include <arm922t.h> + +#ifdef CONFIG_USE_IRQ +DECLARE_GLOBAL_DATA_PTR; +#endif + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + +#ifdef MMU_DEBUG + printf ("p15/c1 is = %08lx\n", value); +#endif + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ +#ifdef MMU_DEBUG + printf ("write %08lx to p15/c1\n", value); +#endif + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM920T Technical reference Manual */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ + +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ + + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); /* get control reg. */ + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IC) != 0; +} + +#ifdef USE_922T_MMU +/* It makes no sense to use the dcache if the MMU is not enabled */ +void dcache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_DC); +} + +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + reg &= ~C1_DC; + write_p15_c1 (reg); +} + +int dcache_status (void) +{ + return (read_p15_c1 () & C1_DC) != 0; +} +#endif

1 0

[U-Boot-Users] Please pull u-boot-83xx.git
by Kim Phillips 02 Dec '06

02 Dec '06

Please pull from 'master' branch of: http://opensource.freescale.com/pub/scm/u-boot-83xx.git to receive the following updates (essentially MPC8349mITX and MPC8360EMDS support): Ben Warren: Add support for multiple I2C buses Multi-bus I2C implementation of MPC834x Additional MPC8349 support for multibus i2c Dave Liu: mpc83xx: Changed to unified mpx83xx names and added common 83xx changes mpc83xx: Add 8360 specifics to 83xx immap mpc83xx: add the QUICC Engine (QE) immap file mpc83xx: Add MPC8360EMDS basic board support mpc83xx: add QE ethernet support mpc83xx: add the README.mpc8360emds mpc83xx: Fix the incorrect dcbz operation Kim Phillips: mpc83xx: change ft code to modify local-mac-address property mpc83xx: add OF_FLAT_TREE bits to 83xx boards mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c Nick Spence: Added RGMII support to the TSECs and Marvell 881111 Phy NAND Flash verify across block boundaries Tanya Jiang: mpc83xx: Removed unused file resetvec.S for mpc83xx cpu mpc83xx: Fix missing build for mpc8349emds pci.c mpc83xx: Unified TQM834x variable names with 83xx and consolidated macros Timur Tabi: mpc83xx: Add support for variable flash memory sizes on 83xx systems mpc83xx: fix TQM build by defining a CFG_FLASH_SIZE for it mpc83xx: Add support for Errata DDR6 on MPC 834x systems mpc83xx: Add support for the MPC8349E-mITX mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITX mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and MPC8360EMDS mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR mpc83xx: Update 83xx to use fsl_i2c.c CREDITS | 5 MAINTAINERS | 4 MAKEALL | 2 Makefile | 36 + README | 61 + board/mpc8349emds/Makefile | 2 board/mpc8349emds/mpc8349emds.c | 40 + board/mpc8349emds/pci.c | 53 + board/mpc8349itx/Makefile | 48 + board/mpc8349itx/config.mk | 33 + board/mpc8349itx/mpc8349itx.c | 477 +++++++++ board/mpc8349itx/pci.c | 357 +++++++ board/mpc8349itx/u-boot.lds | 120 ++ board/mpc8360emds/Makefile | 50 + board/mpc8360emds/config.mk | 28 + board/mpc8360emds/mpc8360emds.c | 657 ++++++++++++ board/mpc8360emds/pci.c | 313 ++++++ board/mpc8360emds/u-boot.lds | 123 ++ board/tqm834x/pci.c | 18 board/tqm834x/tqm834x.c | 4 common/cmd_i2c.c | 159 +++ cpu/mpc83xx/Makefile | 4 cpu/mpc83xx/cpu.c | 155 ++- cpu/mpc83xx/cpu_init.c | 71 + cpu/mpc83xx/i2c.c | 253 ----- cpu/mpc83xx/interrupts.c | 2 cpu/mpc83xx/qe_io.c | 85 ++ cpu/mpc83xx/resetvec.S | 6 cpu/mpc83xx/spd_sdram.c | 557 ++++++---- cpu/mpc83xx/speed.c | 312 +++--- cpu/mpc83xx/start.S | 57 + doc/README.mpc8360emds | 126 ++ drivers/fsl_i2c.c | 113 +- drivers/nand/nand_base.c | 1 drivers/qe/Makefile | 43 + drivers/qe/qe.c | 254 +++++ drivers/qe/qe.h | 237 ++++ drivers/qe/uccf.c | 404 +++++++ drivers/qe/uccf.h | 130 ++ drivers/qe/uec.c | 1266 +++++++++++++++++++++++ drivers/qe/uec.h | 716 +++++++++++++ drivers/qe/uec_phy.c | 604 +++++++++++ drivers/qe/uec_phy.h | 256 +++++ drivers/tsec.c | 12 drivers/tsec.h | 2 include/asm-ppc/e300.h | 2 include/asm-ppc/global_data.h | 16 include/asm-ppc/i2c.h | 103 -- include/asm-ppc/immap_83xx.h | 2130 ++++++++++++++++++++++++++++----------- include/asm-ppc/immap_qe.h | 550 ++++++++++ include/common.h | 5 include/configs/MPC8349EMDS.h | 70 + include/configs/MPC8349ITX.h | 804 +++++++++++++++ include/configs/MPC8360EMDS.h | 635 ++++++++++++ include/configs/TQM834x.h | 28 - include/i2c.h | 45 + include/ioports.h | 11 include/mpc83xx.h | 138 ++- lib_ppc/board.c | 2 net/eth.c | 7 60 files changed, 11286 insertions(+), 1516 deletions(-) create mode 100644 board/mpc8349itx/Makefile create mode 100644 board/mpc8349itx/config.mk create mode 100644 board/mpc8349itx/mpc8349itx.c create mode 100644 board/mpc8349itx/pci.c create mode 100644 board/mpc8349itx/u-boot.lds create mode 100644 board/mpc8360emds/Makefile create mode 100644 board/mpc8360emds/config.mk create mode 100644 board/mpc8360emds/mpc8360emds.c create mode 100644 board/mpc8360emds/pci.c create mode 100644 board/mpc8360emds/u-boot.lds delete mode 100644 cpu/mpc83xx/i2c.c create mode 100644 cpu/mpc83xx/qe_io.c delete mode 100644 cpu/mpc83xx/resetvec.S create mode 100644 doc/README.mpc8360emds create mode 100644 drivers/qe/Makefile create mode 100644 drivers/qe/qe.c create mode 100644 drivers/qe/qe.h create mode 100644 drivers/qe/uccf.c create mode 100644 drivers/qe/uccf.h create mode 100644 drivers/qe/uec.c create mode 100644 drivers/qe/uec.h create mode 100644 drivers/qe/uec_phy.c create mode 100644 drivers/qe/uec_phy.h delete mode 100644 include/asm-ppc/i2c.h create mode 100644 include/asm-ppc/immap_qe.h create mode 100644 include/configs/MPC8349ITX.h create mode 100644 include/configs/MPC8360EMDS.h For the resulting (cumulative) diff, please reference: http://opensource.freescale.com/pub/mpc83xx-origin-master.diff Thanks, Kim

8 27

[U-Boot-Users] u-boot hangs after relocating itself to ram
by Andre Puschmann 02 Dec '06

02 Dec '06

Hey folkes, I have ported u-boot to a custom board based on a freescale mpc5200. I can successfully copy u-boot into flash using the connected bdi2000 and we get some output on the debug port. It seems that the board crashes right after relocation to ram (see output). I already read the regarding faq entry but I'm not sure if this problem has something to do with faulty sdram initialization. this is the output than comes up on the console: 20030.56> U-Boot 1.1.6-ge4bbd8da-dirty (Nov 27 2006 - 18:46:24) 20030.56> 20030.56> CPU: MPC5200 v1.2, Core v1.1 at 396 MHz 20030.56> Bus 132 MHz, IPB 66 MHz, PCI 33 MHz 20030.57> Board: MPC5200 ECU 20030.57> I2C: 85 kHz, ready 20030.57> DRAM: 8 MB 20030.57> FLASH: I'm using eldk 4.0 + insight to debug the problem. I can single-step through the code up to the point where it branches to sdram. After relocation I loaded a new symbol file width offset 0x7d8000, since this is the dest-address for relocate_code(). If I continue running from that point on the board crashes at 0x7dc314 which is in function loadtask(). In assembler the code looks like this: "0x7dc314 <loadtask+48>: lwz r11,-32768(r30)" Can this be a sdram related problem or what might cause this behavior? Any comments and suggestions are more than welcome. Best regards, André Puschmann

3 6

[U-Boot-Users] SMC91111 driver
by Wang, Qingjun 01 Dec '06

01 Dec '06

Hi, I am developing a new board which uses LAN91C1111. I wrote the commands in board.h file as: #define CONFIG_DRIVER_SMC91111 #define CONFIG_SMC91111_BASE 0x2A000000 #undef CONFIG_SMC91111_EXT_PHY #undef CONFIG_SMC_USE_32_BITS After I got prompt in SuperTerm, and typed "dhcp" to get ip address: I got an error of "Memory allocation failed". Can you help me with this problem? I found SMC91111.c driver is updated in 2003. Do you a new one? Thanks in advance Qingjun

1 0

[U-Boot-Users] [PATCH] MPC8641HPCN u-boot.lds problem with ELDK 4.0
by Chris Fester 01 Dec '06

01 Dec '06

Hi all, I recently have been attempting to get u-boot working on my MPC8641HPCN evaulation board (AKA the Argo Navis platform). I faced a problem compiling the latest git source with the ELDK 4.0 and getting it to work on the board. The processor would run off into the weeds when doing the command table relocation step in lib_ppc/board.c:633. After debugging with a BDI, some head scratching, and a few google searches, it came down to an issue with the linker, which seems to have been a common problem in the past for this mail list. Please see the thread at: http://sourceware.org/ml/binutils/2005-08/msg00412.html. The information from that link is what I used to compose the patch below. (Synopsis of the above web link - the newer linker needs to be told more specifically where to put the __u_boot_cmd_start symbol, otherwise it decides to put other misc symbols between __u_boot_cmd_start and __u_boot_cmd_end, causing all sorts of funk when iterating through the command array.) After I apply this patch the u-boot is hunky-dory and happy. Happy holidays! :) Chris Fester CHANGELOG * Fix to linker script for mpc8641hpcn platform to enable a correct symbol table with ELDK 4.0 linker. diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index b34de8e..c2f6727 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -120,7 +120,7 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; + __u_boot_cmd_start = ADDR(.u_boot_cmd); .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .;

3 3

[U-Boot-Users] cannot read flash manufact. id on 405EP with u-boot-1.1.6
by Tom Brown 01 Dec '06

01 Dec '06

Hi, We currently use u-boot-1.0.0 successfully on our 405EP SBC. Last year, we upgraded our toolchain from gcc-3.2.2-uClibc-0.9.20-binutils-2.13.2.1-linux-2.4.21-powerpc to gcc-3.4.3-uClibc-0.9.27-binutils-2.15.91.0.2-linux-2.4.27-powerpc When we made the upgrade we couldn't get u-boot-1.0.0 to compile with the new toolchain. Now, we'd like to upgrade u-boot so it compiles with the same toolchain as our firmware image. I am able to get u-boot-1.1.6 to compile with the new toolchain. However, it will not get past recognizing the flash during boot. The output is given below. As you can see, it is reading a value of 0x1f8b08 for the manufacturer type when it should be reading 0x0001 for AMD. We get the same problem when we try to use u-boot-1.1.0. Any ideas on what we need to look at? Thanks, Tom U-Boot 1.1.6.1 for the 195Eg CPU: AMCC PowerPC 405EP Rev. B at 250 MHz (PLB=125, OPB=62, EBC=31 MHz) I2C boot EEPROM disabled Internal PCI arbiter enabled 16 kB I-Cache 16 kB D-Cache I2C: ready DRAM: 16 MB Top of RAM usable for U-Boot at: 01000000 Reserving 251k for U-Boot at: 00fc1000 Reserving 256k for malloc() at: 00f81000 Reserving 140 Bytes for Board Info at: 00f80f74 Reserving 48 Bytes for Global Data at: 00f80f44 Stack Pointer at: 00f80f28 New Stack Pointer is: 00f80f28 Now running in RAM - U-Boot at: 00fc1000 FLASH: flash_get_size begin manufact type value == 1f8b08 flash_id == FLASH_UNKOWN flash_get_size end ## Unknown FLASH on Bank 0 - Size = 0x00000000 = 0 MB flash_protect ON: from 0xFFFC0000 to 0xFFFFFFFF

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[U-Boot-Users] [Patch02]AS352X:U-Boot1.1.6 patch 2 for AS352X SOC
by Luo Thomas 01 Dec '06

01 Dec '06

From:thomas.luo@austriamicrosystems. U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. Part 2: Br Signed-off-by: Thomas Luo ------------------------------------------------------------------------ ---- diff -urN u-boot-1.1.6.org/cpu/arm922t/as352x/Makefile u-boot-1.1.6/cpu/arm922t/as352x/Makefile --- u-boot-1.1.6.org/cpu/arm922t/as352x/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/Makefile 2006-11-29 17:29:07.000000000 +0800 @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = interrupts.o serial.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +####################################################################### ## + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +####################################################################### ## diff -urN u-boot-1.1.6.org/cpu/arm922t/as352x/serial.c u-boot-1.1.6/cpu/arm922t/as352x/serial.c --- u-boot-1.1.6.org/cpu/arm922t/as352x/serial.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/as352x/serial.c 2006-12-01 17:43:18.000000000 +0800 @@ -0,0 +1,145 @@ +/* +* Copyright (C) 2006 Austriamicrosystems Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#if defined(CONFIG_AS352X) +#include <as352x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* +* Initialise the serial port with the given baudrate. The settings +* are always 8 data bits, no parity, 1 stop bit, no start bits. +*/ +void serial_setbrg (void) +{ + u8 controlData; + set_reg_bits32(CCU_IO,CCU_IO_UART); + + /* reset the uart + */ + set_reg_bits32(CCU_SRC, CCU_SRC_UART0); + wreg32(CCU_SRL, CCU_SRL_MAGIC_NUMBER); + clr_reg_bits32(CCU_SRC, CCU_SRC_UART0); + wreg32(CCU_SRL, 0x0); + wreg32(UART_FCTL_REG, 0); + wreg32(UART_INTEN_REG, 0); + controlData = 3; + wreg32(UART_LNCTL_REG,controlData| UART_LNCTL_DLSEN); + wreg32(UART_DLO_REG,0x68); + wreg32(UART_DHI_REG,0x0); + wreg32(UART_LNCTL_REG,controlData& (~UART_LNCTL_DLSEN)); + +} +int serial_init (void) +{ + int i; + serial_setbrg(); + for (i = 0; i < 100; i++); + return (0); +} + +/* +* Read a single byte from the serial port. Returns 1 on success, 0 +* otherwise. When the function is succesfull, the character read is +* written into its argument c. +*/ +int serial_getc (void) +{ + u8 c; + + while (!(rreg32(UART_LNSTATUS_REG) & UART_RX_DATA_READY)); + c = rreg32(UART_DATA_REG); + return c&0xff; +} + +#ifdef CONFIG_HWFLOW +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ + switch(on) { + case 0: + default: + break; /* return current */ + case 1: + hwflow = 0; /* turn on */ + break; + case -1: + hwflow = 0; /* turn off */ + break; + } + return hwflow; +} +#endif + +#ifdef CONFIG_MODEM_SUPPORT +static int be_quiet = 0; +void disable_putc(void) +{ + be_quiet = 1; +} + +void enable_putc(void) +{ + be_quiet = 0; +} +#endif + + +/* +* Output a single byte to the serial port. +*/ +void serial_putc (const char c) +{ +#ifdef CONFIG_MODEM_SUPPORT + if (be_quiet) + return; +#endif + + /* wait for room in the tx FIFO */ + while (!(rreg32(UART_LNSTATUS_REG) & UART_TX_HOLD_REG_EMPTY)); + wreg32(UART_DATA_REG,c); + + + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* +* Test whether a character is in the RX buffer +*/ +int serial_tstc (void) +{ + return (rreg32(UART_LNSTATUS_REG) & UART_RX_DATA_READY); +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#endif /* defined(CONFIG_AS352X)*/ diff -urN u-boot-1.1.6.org/cpu/arm922t/config.mk u-boot-1.1.6/cpu/arm922t/config.mk --- u-boot-1.1.6.org/cpu/arm922t/config.mk 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/config.mk 2006-11-24 16:43:15.000000000 +0800 @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + + +PLATFORM_CPPFLAGS += -march=armv4 +# ======================================================================== = +# +# Supply options according to compiler version +# +# ======================================================================== = +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff -urN u-boot-1.1.6.org/cpu/arm922t/cpu.c u-boot-1.1.6/cpu/arm922t/cpu.c --- u-boot-1.1.6.org/cpu/arm922t/cpu.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/cpu.c 2006-12-01 17:43:54.000000000 +0800 @@ -0,0 +1,185 @@ +/* +* (C) Copyright 2002 +* Sysgo Real-Time Solutions, GmbH <www.elinos.com> +* Marius Groeger <mgroeger(a)sysgo.de> +* +* (C) Copyright 2002 +* Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +/* +* CPU specific code +*/ + +#include <common.h> +#include <command.h> +#include <arm922t.h> + +#ifdef CONFIG_USE_IRQ +DECLARE_GLOBAL_DATA_PTR; +#endif + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + +#ifdef MMU_DEBUG + printf ("p15/c1 is = %08lx\n", value); +#endif + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ +#ifdef MMU_DEBUG + printf ("write %08lx to p15/c1\n", value); +#endif + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM920T Technical reference Manual */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ + +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ + + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); /* get control reg. */ + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IC) != 0; +} + +#ifdef USE_922T_MMU +/* It makes no sense to use the dcache if the MMU is not enabled */ +void dcache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_DC); +} + +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + reg &= ~C1_DC; + write_p15_c1 (reg); +} + +int dcache_status (void) +{ + return (read_p15_c1 () & C1_DC) != 0; +} +#endif diff -urN u-boot-1.1.6.org/cpu/arm922t/interrupts.c u-boot-1.1.6/cpu/arm922t/interrupts.c --- u-boot-1.1.6.org/cpu/arm922t/interrupts.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/interrupts.c 2006-11-23 17:01:25.000000000 +0800 @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <arm920t.h> +#include <asm/proc-armv/ptrace.h> + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} diff -urN u-boot-1.1.6.org/cpu/arm922t/Makefile u-boot-1.1.6/cpu/arm922t/Makefile --- u-boot-1.1.6.org/cpu/arm922t/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/Makefile 2006-11-02 22:15:02.000000000 +0800 @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = cpu.o interrupts.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +####################################################################### ## + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +####################################################################### ## diff -urN u-boot-1.1.6.org/cpu/arm922t/start.S u-boot-1.1.6/cpu/arm922t/start.S --- u-boot-1.1.6.org/cpu/arm922t/start.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/cpu/arm922t/start.S 2006-11-30 10:25:41.000000000 +0800 @@ -0,0 +1,353 @@ +/* + * Copyright (C) 2006 Austriamicrosystems Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + + +/* + ************************************************************************ * + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************ * + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************ * + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * relocate armboot to ram + * setup stack + * jump to second stage + * + ************************************************************************ * + */ + +RAM_END: + .word 0x50000 + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word _end+200 + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word _end+400 +#endif + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + /* Set up the stack */ +stack_setup: + ldr r0, RAM_END /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + ldr r0,RAM_END + ldr r1,_bss_end + str r0,_armboot_start + add r1,r1,r0 + str r1,_bss_end + ldr r1,_bss_start + add r1,r1,r0 + str r1,_bss_start + ldr pc,_start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************ * + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************ * + */ + + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + mrc p15, 0, r0, c1, c0, 0 @ read CP15 register 1 into r0 + bic r0, r0, #0x0001 @ clear bit 0 MMU disable + bic r0, r0, #0x0004 @ clear bit 2 D-cache disable + bic r0, r0, #0x1000 @ clear bit 12 I-cache disable + bic r0, r0, #0xc0000000 @ clear bit 30,31 fast bus mode + mcr p15, 0, r0, c1, c0, 0 @ write value back + + @ invalidate all caches to have a clean startup + mov r2, #0 + mcr p15, 0, r2, c7, c7, 0 @ Invalidate D- and I-Cache + mcr p15, 0, r2, c8, c7, 0 @ invalidate all TLBs + + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + mov ip, lr + bl lowlevel_init + mov lr, ip + mov pc, lr +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + ************************************************************************ * + * + * Interrupt handling + * + ************************************************************************ * + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get pc, cpsr + add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif diff -urN u-boot-1.1.6.org/CREDITS u-boot-1.1.6/CREDITS --- u-boot-1.1.6.org/CREDITS 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/CREDITS 2006-11-30 10:30:13.000000000 +0800 @@ -465,3 +465,8 @@ E: james.macaulay(a)amirix.com D: Suppport for Amirix AP1000 W: www.amirix.com + +N: Thomas Luo +E: thomas.luo(a)austriamicrosystems.com +D: Port to ARM base SOC AS352X. +W: www.austriamicrosystems.com diff -urN u-boot-1.1.6.org/include/arm922t.h u-boot-1.1.6/include/arm922t.h --- u-boot-1.1.6.org/include/arm922t.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/arm922t.h 2006-11-23 16:30:48.000000000 +0800 @@ -0,0 +1,12 @@ +/************************************************ + * NAME : arm922t.h + * Version : 30 April 2002 * + * + * empty for now + ************************************************/ + +#ifndef __ARM922T_H__ +#define __ARM922T_H__ + + +#endif /*__ARM922T_H__*/

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[U-Boot-Users] [Patch03]AS352X:U-Boot1.1.6 patch 3 for AS352X SOC
by Luo Thomas 01 Dec '06

01 Dec '06

From:thomas.luo@austriamicrosystems. U-Boot1.1.6 for AS352X Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot. Part 3: Br Signed-off-by: Thomas Luo ------------------------------------------------------------------------ ---- diff -urN u-boot-1.1.6.org/include/as352x.h u-boot-1.1.6/include/as352x.h --- u-boot-1.1.6.org/include/as352x.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/as352x.h 2006-12-01 17:42:16.000000000 +0800 @@ -0,0 +1,352 @@ +/* +* (C) Copyright 2006 +* Copyright (C) 2006 Austriamicrosystems, by thomas.luo +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ +#ifndef __AS352X_H__ +#define __AS352X_H__ + +#define AS352X_UART_CHANNELS 1 + +/* AS352X only supports 512 Byte HW ECC */ +#define AS352X_ECCSIZE 512 +#define AS352X_ECCBYTES 3 + + +/* AS352X device base addresses */ + + +/* ------------------------------------------------------------------------ +* AS352X Registers +* ------------------------------------------------------------------------ +* +*/ + + +/* AHB */ +#define AS352X_USB_BASE 0xC6000000 +#define AS352X_VIC_BASE 0xC6010000 +#define AS352X_DMAC_BASE 0xC6020000 +#define AS352X_MPMC_BASE 0xC6030000 +#define AS352X_MEMSTICK_BASE 0xC6040000 +#define AS352X_CF_IDE_BASE 0xC6050000 + +/* APB */ +#define AS352X_NAND_FLASH_BASE 0xC8000000 +#define AS352X_BIST_MANAGER_BASE 0xC8010000 +#define AS352X_SD_MCI_BASE 0xC8020000 +#define AS352X_TIMER_BASE 0xC8040000 +#define AS352X_WDT_BASE 0xC8050000 +#define AS352X_I2C_MS_BASE 0xC8060000 +#define AS352X_I2C_AUDIO_BASE 0xC8070000 +#define AS352X_SSP_BASE 0xC8080000 +#define AS352X_I2SIN_BASE 0xC8090000 +#define AS352X_I2SOUT_BASE 0xC80A0000 +#define AS352X_GPIO1_BASE 0xC80B0000 +#define AS352X_GPIO2_BASE 0xC80C0000 +#define AS352X_GPIO3_BASE 0xC80D0000 +#define AS352X_GPIO4_BASE 0xC80E0000 +#define AS352X_CGU_BASE 0xC80F0000 +#define AS352X_CCU_BASE 0xC8100000 +#define AS352X_UART0_BASE 0xC8110000 +#define AS352X_DBOP_BASE 0xC8120000 + + + + + + + + +/* ------------------------------------------------------------------------ +* AS352X control registers +* ------------------------------------------------------------------------ +*/ + +#define CCU_SRC ( (AS352X_CCU_BASE) + 0x00) +#define CCU_SRL ( (AS352X_CCU_BASE) + 0x04) +#define CCU_MEMMAP ( (AS352X_CCU_BASE) + 0x08) +#define CCU_IO ( (AS352X_CCU_BASE) + 0x0C) +#define CCU_SCON ( (AS352X_CCU_BASE) + 0x10) +#define CCU_VERS ( (AS352X_CCU_BASE) + 0x14) + + +/** +* Reset Control Lines in CCU_SRC register +**/ +#define CCU_SRC_DBOP_EN ( 1 << 24 ) +#define CCU_SRC_SPDIF_EN ( 1 << 22 ) +#define CCU_SRC_TIMER_EN ( 1 << 21 ) +#define CCU_SRC_SSP_EN ( 1 << 20 ) +#define CCU_SRC_WDO_EN ( 1 << 19 ) +#define CCU_SRC_IDE_EN ( 1 << 18 ) +#define CCU_SRC_IDE_AHB_EN ( 1 << 17 ) +#define CCU_SRC_UART0 ( 1 << 16 ) +#define CCU_SRC_NAF_EN ( 1 << 15 ) +#define CCU_SRC_SDMCI_EN ( 1 << 14 ) +#define CCU_SRC_GPIO_EN ( 1 << 13 ) +#define CCU_SRC_I2C_AUDIO_EN ( 1 << 12 ) +#define CCU_SRC_I2C_EN ( 1 << 11 ) +#define CCU_SRC_MST_EN ( 1 << 10 ) +#define CCU_SRC_I2SIN ( 1 << 9 ) +#define CCU_SRC_I2SOUT ( 1 << 8 ) +#define CCU_SRC_USB_AHB_EN ( 1 << 7 ) +#define CCU_SRC_USB_PHY_EN ( 1 << 6 ) +#define CCU_SRC_DMAC_EN ( 1 << 5 ) +#define CCU_SRC_VIC_EN ( 1 << 4 ) + +/** +* Magic number for CCU_SRL for reset. +**/ +#define CCU_SRL_MAGIC_NUMBER 0x1A720212 + +/** +* Chip select lines for NAF. Use these constants to select/deselct the CE lines +* for NAND flashes in Register CCU_IO. +**/ +#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 ) +#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 ) +#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 ) +#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 ) + +/* CCU IO Select/Deselect IDE */ +#define CCU_IO_IDE ( 1 << 5 ) + +/* CCU IO Select/desect I2C */ +#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 ) + +/* CCU IO Select/desect UART */ +#define CCU_IO_UART0 ( 1 << 0 ) + + +#define CCU_RESET_ALL_BUT_MEMORY \ + ( CCU_SRC_DBOP_EN \ + | CCU_SRC_SPDIF_EN \ + | CCU_SRC_TIMER_EN \ + | CCU_SRC_SSP_EN \ + | CCU_SRC_WDO_EN \ + | CCU_SRC_IDE_EN \ + | CCU_SRC_IDE_AHB_EN \ + | CCU_SRC_UART0 \ + | CCU_SRC_NAF_EN \ + | CCU_SRC_SDMCI_EN \ + | CCU_SRC_GPIO_EN \ + | CCU_SRC_I2C_AUDIO_EN \ + | CCU_SRC_I2C_EN \ + | CCU_SRC_MST_EN \ + | CCU_SRC_I2SIN \ + | CCU_SRC_I2SOUT \ + | CCU_SRC_USB_AHB_EN \ + | CCU_SRC_USB_PHY_EN \ + | CCU_SRC_DMAC_EN \ + | CCU_SRC_VIC_EN \ + ) + +/** +* Magic number for CCU_SRL for reset. +**/ +#define CCU_SRL_MAGIC_NUMBER 0x1A720212 + +/** +* Chip select lines for NAF. Use these constants to select/deselct the CE lines +* for NAND flashes in Register CCU_IO. +**/ +#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 ) +#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 ) +#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 ) +#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 ) + +/* CCU IO Select/Deselect IDE */ +#define CCU_IO_IDE ( 1 << 5 ) + +/* CCU IO Select/desect I2C */ +#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 ) + +/* CCU IO Select/desect UART */ +#define CCU_IO_UART ( 1 << 0 ) +/* ------------------------------------------------------------------------ +* AS352X clock control registers +* ------------------------------------------------------------------------ +*/ + +#define CGU_REG_PLLA ( (AS352X_CGU_BASE) + 0x00 ) +#define CGU_REG_PLLB ( (AS352X_CGU_BASE) + 0x04 ) +#define CGU_REG_PLLASUP ( (AS352X_CGU_BASE) + 0x08 ) +#define CGU_REG_PLLBSUP ( (AS352X_CGU_BASE) + 0x0C ) +#define CGU_REG_PROC ( (AS352X_CGU_BASE) + 0x10 ) +#define CGU_REG_PERI ( (AS352X_CGU_BASE) + 0x14 ) +#define CGU_REG_AUDIO ( (AS352X_CGU_BASE) + 0x18 ) +#define CGU_REG_USB ( (AS352X_CGU_BASE) + 0x1C ) +#define CGU_REG_INTCTRL ( (AS352X_CGU_BASE) + 0x20 ) +#define CGU_REG_IRQ ( (AS352X_CGU_BASE) + 0x24 ) +#define CGU_REG_COUNTA ( (AS352X_CGU_BASE) + 0x28 ) +#define CGU_REG_COUNTB ( (AS352X_CGU_BASE) + 0x2C ) +#define CGU_REG_IDE ( (AS352X_CGU_BASE) + 0x30 ) +#define CGU_REG_MEMSTICK ( (AS352X_CGU_BASE) + 0x34 ) +#define CGU_REG_DBOP ( (AS352X_CGU_BASE) + 0x38 ) + + +/* --- are disabled after reset --- */ +#define CGU_DMA_CLOCK_ENABLE ( 1 << 22 ) /* dma */ +#define CGU_USB_CLOCK_ENABLE ( 1 << 21 ) /* usb */ +#define CGU_I2SOUT_APB_CLOCK_ENABLE ( 1 << 20 ) /* i2sout */ +#define CGU_I2SIN_APB_CLOCK_ENABLE ( 1 << 19 ) /* i2sin */ +#define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE ( 1 << 18 ) /* i2c master/slave */ +#define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE ( 1 << 17 ) /* i2c audio master */ +#define CGU_GPIO_CLOCK_ENABLE ( 1 << 16 ) /* gpio */ +#define CGU_MCI_CLOCK_ENABLE ( 1 << 15 ) /* mmc + sd */ +#define CGU_NAF_CLOCK_ENABLE ( 1 << 14 ) /* naf */ +#define CGU_UART_APB_CLOCK_ENABLE ( 1 << 13 ) /* uart */ +#define CGU_WDOCNT_CLOCK_ENABLE ( 1 << 12 ) /* watchdog counter */ +#define CGU_WDOIF_CLOCK_ENABLE ( 1 << 11 ) /* watchdog timer module */ +#define CGU_SSP_CLOCK_ENABLE ( 1 << 10 ) /* ssp */ +#define CGU_TIMER1_CLOCK_ENABLE ( 1 << 9 ) /* timer 1 */ +#define CGU_TIMER2_CLOCK_ENABLE ( 1 << 8 ) /* timer 2 */ +#define CGU_TIMERIF_CLOCK_ENABLE ( 1 << 7 ) /* timer interface */ + +/** ------------------------------------------------------------------ +* Number of cycles to wait before cgu is safely locked. +**/ +#define CGU_LOCK_CNT 0xFF + +/* FIFO depth is 16 for tx and rx fifo */ +#define UART_FIFO_DEPTH 16 + +/* ------------------- UART Line Control Register bit fields -------------------- */ + +#define UART_LNCTL_DLSEN (1 << 7) /* Device latch select bit */ + + +/* -------------- UART Interrupt Control Register bit fields --------------- */ + +#define UART_INTR_RXDRDY 0x1 /* Data ready interrupt */ +#define UART_INTR_TXEMT 0x2 /* Transmit data empty interrupt */ +#define UART_INTR_RXLINESTATUS 0x4 /* Receive line status interrupt */ + +/* ------------------- UART Line Status Register bit fields -------------------- */ + +#define UART_ERRORBITS 0x1E +#define UART_RX_DATA_READY (1 << 0) +#define UART_TX_HOLD_REG_EMPTY (1 << 5) + +/* ------------------- FIFO CNTL Register contants -------------------*/ + +#define UART_FIFO_EN (1 << 0) /* Enable the UART FIFO */ +#define UART_TX_FIFO_RST (1 << 1) /* Enable the UART FIFO */ +#define UART_RX_FIFO_RST (1 << 2) +#define UART_RXFIFO_TRIGLVL_1 (0 << 4) /* RX FIFO TRIGGER_LEVEL 1 */ +#define UART_RXFIFO_TRIGLVL_4 0x08 /* RX FIFO TRIGGER_LEVEL 4 */ +#define UART_RXFIFO_TRIGLVL_8 0x10 /* RX FIFO TRIGGER_LEVEL 8 */ +#define UART_RXFIFO_TRIGLVL_14 0x18 /* RX FIFO TRIGGER_LEVEL 14 */ + + +/* ------------------- FIFO status Register contants ------------------*/ +#define UART_TX_FIFO_FULL (1 << 0) +#define UART_RX_FIFO_FULL (1 << 1) +#define UART_TX_FIFO_EMPTY (1 << 2) +#define UART_RX_FIFO_EMPTY (1 << 3) + + +/* ----------------------- defines ---------------------------------------- */ + +#define UART_DATA_REG ( (AS352X_UART0_BASE) + 0x00 ) /* Data register */ +#define UART_DLO_REG ( (AS352X_UART0_BASE) + 0x00 ) /* Clock divider(lower byte) register */ +#define UART_DHI_REG ( (AS352X_UART0_BASE) + 0x04 ) /* Clock divider(higher byte) register */ +#define UART_INTEN_REG ( (AS352X_UART0_BASE) + 0x04 ) /* Interrupt enable register */ +#define UART_INTSTATUS_REG ( (AS352X_UART0_BASE) + 0x08 ) /* Interrupt status register */ +#define UART_FCTL_REG ( (AS352X_UART0_BASE) + 0x0C ) /* Fifo control register */ +#define UART_FSTATUS_REG ( (AS352X_UART0_BASE) + 0x0C ) /* Fifo status register */ +#define UART_LNCTL_REG ( (AS352X_UART0_BASE) + 0x10 ) /* Line control register */ +#define UART_LNSTATUS_REG ( (AS352X_UART0_BASE) + 0x14 ) /* Line status register */ + + +#define TIMER_LOAD ( (AS352X_TIMER_BASE) + 0x00 ) /* 32-bit width */ +#define TIMER_VALUE ( (AS352X_TIMER_BASE) + 0x04 ) /* 32 bit width */ +#define TIMER_CONTROL ( (AS352X_TIMER_BASE) + 0x08 ) /* 8 bit width */ +#define TIMER_INTCLR ( (AS352X_TIMER_BASE) + 0x0C ) /* clears ir by write access */ +#define TIMER_RIS ( (AS352X_TIMER_BASE) + 0x10 ) /* 1 bit width */ +#define TIMER_MIS ( (AS352X_TIMER_BASE) + 0x14 ) /* 1 bit width */ + +/** +* Counter/Timer control register bits +**/ +#define TIMER_ENABLE 0x80 +#define TIMER_PERIODIC 0x40 +#define TIMER_INT_ENABLE 0x20 +#define TIMER_32_BIT 0x02 +#define TIMER_ONE_SHOT 0x01 +#define TIMER_PRESCALE_1 0x00 +#define TIMER_PRESCALE_16 0x04 +#define TIMER_PRESCALE_256 0x08 + + + +#define NAF_CONFIG ( (AS352X_NAND_FLASH_BASE) + 0x00 ) +#define NAF_CONTROL ( (AS352X_NAND_FLASH_BASE) + 0x04 ) +#define NAF_ECC ( (AS352X_NAND_FLASH_BASE) + 0x08 ) +#define NAF_DATA ( (AS352X_NAND_FLASH_BASE) + 0x0C ) +#define NAF_MODE ( (AS352X_NAND_FLASH_BASE) + 0x10 ) +#define NAF_STATUS ( (AS352X_NAND_FLASH_BASE) + 0x14 ) +#define NAF_MASK ( (AS352X_NAND_FLASH_BASE) + 0x18 ) +#define NAF_FIFODATA ( (AS352X_NAND_FLASH_BASE) + 0x1C ) +#define NAF_WORDS ( (AS352X_NAND_FLASH_BASE) + 0x20 ) +#define NAF_CLEAR ( (AS352X_NAND_FLASH_BASE) + 0x24 ) +#define NAF_TEST ( (AS352X_NAND_FLASH_BASE) + 0x28 ) + + + +#define set_reg_bits32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) |= ( (u32)(value) ) ) + + +#define clr_reg_bits32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) &= ( ~( (u32)(value) ) ) ) + +#define rreg32( registerAddress ) \ + ( *( ( const volatile u32 * )( registerAddress ) ) ) + +#define wreg32( registerAddress, value ) \ + ( *( (volatile u32 *)(registerAddress) ) = ( (u32)(value) ) ) + + + +#define rreg16( registerAddress ) \ + ( *( ( const volatile u16 * )( registerAddress ) ) ) + +#define wreg16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) = ( (u16)(value) ) ) + +#define set_reg_bits16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) |= ( (u16)(value) ) ) + +#define clr_reg_bits16( registerAddress, value ) \ + ( *( (volatile u16 *)(registerAddress) ) &= ( ~( (u16)(value) ) ) ) + + +#define rreg8( registerAddress ) \ + ( *( ( const volatile u8 * )( registerAddress ) ) ) + +#define wreg8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) = ( (u8)(value) ) ) + +#define set_reg_bits8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) |= ( (u8)(value) ) ) + +#define clr_reg_bits8( registerAddress, value ) \ + ( *( (volatile u8 *)(registerAddress) ) &= ( ~( (u8)(value) ) ) ) +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#endif /*__AS352X_H__*/ diff -urN u-boot-1.1.6.org/include/asm-arm/mach-types.h u-boot-1.1.6/include/asm-arm/mach-types.h --- u-boot-1.1.6.org/include/asm-arm/mach-types.h 2006-12-01 17:49:35.000000000 +0800 +++ u-boot-1.1.6/include/asm-arm/mach-types.h 2006-12-01 18:01:45.000000000 +0800 @@ -737,6 +737,7 @@ #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 #define MACH_TYPE_PDNB3 1002 +#define MACH_TYPE_AS352X 1166 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -6054,7 +6055,7 @@ # define machine_is_ess710() (0) #endif -#ifdef CONFIG_MACH_MX3ADS +#ifdef CONFIG_MACH_MX31ADS # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type @@ -9401,6 +9402,18 @@ #else # define machine_is_mp2usb() (0) #endif +#ifdef CONFIG_MACH_AS352X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS352X +# endif +# define machine_is_as352x() (machine_arch_type == MACH_TYPE_AS352X) +#else +# define machine_is_as352x() (0) +#endif + /* * These have not yet been registered diff -urN u-boot-1.1.6.org/include/configs/as352xpb.h u-boot-1.1.6/include/configs/as352xpb.h --- u-boot-1.1.6.org/include/configs/as352xpb.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-1.1.6/include/configs/as352xpb.h 2006-12-01 17:42:50.000000000 +0800 @@ -0,0 +1,218 @@ +/* +* (C) Copyright 2006 +* Copyright (C) 2006 Austriamicrosystems, by thomas.luo +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* +* High Level Configuration Options +* (easy to change) +*/ +#define CONFIG_ARM922T 1 /* This is an ARM922T Core */ +#define CONFIG_AS352X 1 /* in a AS352X SoC */ +#define CONFIG_AS352XPB 1 /* on a AS352XPB Board */ +#define CFG_NO_FLASH 1 + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 24000000/* the AS352XPB has 24MHz input clock */ + + +#define USE_922T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* +* Size of malloc() pool +*/ +#define CFG_MALLOC_LEN (((CFG_ENV_SIZE + 128*1024 + 0x4000-1) /0x4000)*0x4000) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* +* Hardware drivers +*/ + +/* +* select serial console configuration +*/ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on AS352XPB */ + +/************************************************************ +* RTC +************************************************************/ +#define CONFIG_RTC_AS352X 0 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +/*********************************************************** +* Command definition +***********************************************************/ +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + /* CFG_CMD_CACHE |*/ \ + CFG_CMD_NAND | \ + /*CFG_CMD_EEPROM |*/ \ + /*CFG_CMD_I2C |*/ \ + /*CFG_CMD_USB |*/ \ + CFG_CMD_REGINFO \ + /*CFG_CMD_ELF*/ )& ~(CFG_CMD_FLASH|CFG_CMD_IMLS|CFG_CMD_NET|CFG_CMD_XIMG)) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTARGS "root=/dev/ram0 rw init=/linuxrc console=ttyS0 mem=64M" +#define CONFIG_BOOTCOMMAND "nand read 0x30007FC0 0x80000 0x200000; nand read 0x32000000 0x280000 0x200000;bootm 0x30007FC0 0x32000000" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n" +#define CONFIG_AUTOBOOT_STOP_STR "s" +/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ +/*#define CONFIG_NETMASK 255.255.255.0*/ +/*#define CONFIG_IPADDR 10.0.0.110*/ +/*#define CONFIG_SERVERIP 10.0.0.1*/ +/*#define CONFIG_BOOTFILE "" */ +/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +#undef CFG_ENV_IS_IN_FLASH +/* +* Miscellaneous configurable options +*/ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "AS352X # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 8 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x30008000 /* default load address */ + +#define CFG_HZ 1500000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_ENV_IS_IN_NAND 1 + +#define CFG_ENV_NAND_ERASE_SIZE 0x20000 +#define CFG_ENV_SIZE 0x800 /* Total Size of Environment Sector */ +#if CFG_ENV_IS_IN_NAND +#define CFG_ENV_OFFSET 0x60000 + +#endif +/*--------------------------------------------------------------------- -- +* Stack sizes +* +* The stack sizes are set up in start.S using the settings below +*/ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*--------------------------------------------------------------------- -- +* Physical Memory Map +*/ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*--------------------------------------------------------------------- -- +* FLASH and environment organization +*/ + +#define CONFIG_AMD_LV400 0 /* uncomment this if you have a LV400 flash */ +#if 0 +#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ +#endif + +#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks */ +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ +#endif +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ +#endif + + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + + +#define NAND_DISABLE_CE(nand) do { } while(0) +#define NAND_ENABLE_CE(nand) do { } while(0) + +#define NAND_WAIT_READY(nand) + +#define WRITE_NAND_COMMAND(d, adr) do{ } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ } while(0) +#define WRITE_NAND(d, adr) do{} while(0) +#define READ_NAND(adr) () +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + + + + + + +#include <as352x.h> +#define CFG_NAND_BASE NAF_DATA +#include <cmd_confdefs.h> + +#define NAND_ALLOW_ERASE_ALL + + + +#endif /* __CONFIG_H */ diff -urN u-boot-1.1.6.org/MAINTAINERS u-boot-1.1.6/MAINTAINERS --- u-boot-1.1.6.org/MAINTAINERS 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/MAINTAINERS 2006-11-30 09:40:51.000000000 +0800 @@ -566,6 +566,17 @@ Haavard Skinnemoen <hskinnemoen(a)atmel.com> ATSTK1000 AT32AP7000 +####################################################################### ## +# AS352X Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +####################################################################### ## + +Thomas Luo <thomas.luo(a)austriamicrosystems.com> + + AS352XPB AS352X + ######################################################################## # # End of MAINTAINERS list # diff -urN u-boot-1.1.6.org/MAKEALL u-boot-1.1.6/MAKEALL --- u-boot-1.1.6.org/MAKEALL 2006-12-01 17:49:32.000000000 +0800 +++ u-boot-1.1.6/MAKEALL 2006-11-30 09:33:22.000000000 +0800 @@ -189,13 +189,13 @@ LIST_ARM9=" \ at91rm9200dk cmc_pu2 \ ap920t ap922_XA10 ap926ejs ap946es \ - ap966 cp920t cp922_XA10 cp926ejs \ + ap966 cp920t cp922t cp922_XA10 cp926ejs \ cp946es cp966 lpd7a400 mp2usb \ mx1ads mx1fs2 netstar omap1510inn \ omap1610h2 omap1610inn omap730p2 sbc2410x \ scb9328 smdk2400 smdk2410 trab \ VCMA9 versatile versatileab versatilepb \ - voiceblue \ + voiceblue as3525pb \ " ######################################################################## # diff -urN u-boot-1.1.6.org/Makefile u-boot-1.1.6/Makefile --- u-boot-1.1.6.org/Makefile 2006-12-01 17:49:33.000000000 +0800 +++ u-boot-1.1.6/Makefile 2006-11-30 09:38:22.000000000 +0800 @@ -2253,6 +2253,9 @@ @./mkconfig $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000 ######################################################################## # +as352xpb_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm922t as352xpb NULL as352x + ######################################################################## # ######################################################################## #

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[U-Boot-Users] [PATCH] MPC8360EMDS lowboot option
by Jerry Van Baren 01 Dec '06

01 Dec '06

Hi Dave Liu, The following patch adds a configuration to do "low boot" (HRCW.BMS = 0) as well as "high boot" (HRCW.BMS = 1). Many people, myself included :o) prefer to boot out of low memory. It has an added benefit that, if you screw up the image of of u-boot in low memory, you can switch SW9.3 FCFG and boot using the BCSR, which "high boots" (assuming you smart enough to keep a valid u-boot image at 0xFFF00000). The patch is against the top of the denx.de repository (thanks, Wolfgang, for pulling the fsl patches). gvb Add a configuration option to "low boot" (boot memory space 0x00000000) as well as the default "high boot" (0xFFF00000). Signed-off-by: Jerry Van Baren <vanbaren(a)cideas.com> --- Makefile | 18 +++++++++++++----- board/mpc8360emds/config.mk | 7 ++++++- include/configs/MPC8360EMDS.h | 14 ++++++++++++-- 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index d2534ab..684b862 100644 --- a/Makefile +++ b/Makefile @@ -1595,27 +1595,35 @@ MPC8349EMDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds MPC8360EMDS_config \ +MPC8360EMDS_lowboot_config \ MPC8360EMDS_HOST_33_config \ +MPC8360EMDS_HOST_33_lowboot_config \ MPC8360EMDS_HOST_66_config \ +MPC8360EMDS_HOST_66_lowboot_config \ +MPC8360EMDS_SLAVE_lowboot_config \ MPC8360EMDS_SLAVE_config: unconfig @echo "" >include/config.h ; \ if [ "$(findstring _HOST_,$@)" ] ; then \ - echo -n "... PCI HOST " ; \ + echo -n "...PCI HOST" ; \ echo "#define CONFIG_PCI" >>include/config.h ; \ fi ; \ if [ "$(findstring _SLAVE_,$@)" ] ; then \ - echo "...PCI SLAVE 66M" ; \ + echo "...PCI SLAVE 66M..." ; \ echo "#define CONFIG_PCI" >>include/config.h ; \ echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ fi ; \ if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "...33M ..." ; \ + echo -n " 33M..." ; \ echo "#define PCI_33M" >>include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ - echo -n "...66M..." ; \ + echo -n " 66M..." ; \ echo "#define PCI_66M" >>include/config.h ; \ - fi ; + fi ; \ + if [ "$(findstring lowboot_,$@)" ] ; then \ + echo -n " (lowboot) " ; \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8360emds/config.tmp ; \ + fi @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds MPC8349ITX_config: unconfig diff --git a/board/mpc8360emds/config.mk b/board/mpc8360emds/config.mk index 9ace886..dd560cc 100644 --- a/board/mpc8360emds/config.mk +++ b/board/mpc8360emds/config.mk @@ -25,4 +25,9 @@ # MPC8360EMDS # -TEXT_BASE = 0xFE000000 +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Default: boot high +TEXT_BASE = 0xFFF00000 +endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 8ad6551..c4fff07 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -47,6 +47,16 @@ #endif /* + * Figure out if we are booting low or high. Flash and I2C can boot either + * low or high, the BCSR is hardwired to boot high. + */ +#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ +# define BOOT_MEMORY_SPACE HRCWH_FROM_0X00000100 +#else +# define BOOT_MEMORY_SPACE HRCWH_FROM_0XFFF00100 +#endif + +/* * Hardware Reset Configuration Word */ #define CFG_HRCW_LOW (\ @@ -65,7 +75,7 @@ HRCWH_PCI1_ARBITER_DISABLE |\ HRCWH_PCICKDRV_DISABLE |\ HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ + BOOT_MEMORY_SPACE |\ HRCWH_BOOTSEQ_DISABLE |\ HRCWH_SW_WATCHDOG_DISABLE |\ HRCWH_ROM_LOC_LOCAL_16BIT) @@ -75,7 +85,7 @@ HRCWH_PCI1_ARBITER_ENABLE |\ HRCWH_PCICKDRV_ENABLE |\ HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ + BOOT_MEMORY_SPACE |\ HRCWH_BOOTSEQ_DISABLE |\ HRCWH_SW_WATCHDOG_DISABLE |\ HRCWH_ROM_LOC_LOCAL_16BIT) -- 1.4.3.3

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[U-Boot-Users] [PATCH]Fix the UEC driver bug of QE
by Dave Liu 01 Dec '06

01 Dec '06

Hello, The patch prevents the GCC tool chain from striping useful code for optimization. It will make UEC ethernet driver workable, Otherwise the UEC will fail in tx when you are using gcc4.x. but the driver can work when using gcc3.4.3. Wolfgang and Stefan, I am really sorry for that. I used gcc3.4.3 when I developed it, so I didn't find it. please apply it, TIA. CHANGELOG *Prevent the GCC from striping code for optimization, Otherwise the UEC will tx failed when you are using gcc4.x. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index f640c81..c44a5be 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1122,7 +1122,7 @@ static int uec_send(struct eth_device* d uec_private_t *uec; ucc_fast_private_t *uccf; volatile qe_bd_t *bd; - volatile u16 status; + u16 status; int i; int result = 0; @@ -1131,7 +1131,7 @@ static int uec_send(struct eth_device* d bd = uec->txBd; /* Find an empty TxBD */ - for (i = 0; BD_STATUS(bd) & TxBD_READY; i++) { + for (i = 0; bd->status & TxBD_READY; i++) { if (i > 0x100000) { printf("%s: tx buffer not ready\n", dev->name); return result; @@ -1150,13 +1150,11 @@ static int uec_send(struct eth_device* d ucc_fast_transmit_on_demand(uccf); /* Wait for buffer to be transmitted */ - status = BD_STATUS(bd); - for (i = 0; status & TxBD_READY; i++) { + for (i = 0; bd->status & TxBD_READY; i++) { if (i > 0x100000) { printf("%s: tx error\n", dev->name); return result; } - status = BD_STATUS(bd); } /* Ok, the buffer be transimitted */ @@ -1171,12 +1169,12 @@ static int uec_recv(struct eth_device* d { uec_private_t *uec = dev->priv; volatile qe_bd_t *bd; - volatile u16 status; + u16 status; u16 len; u8 *data; bd = uec->rxBd; - status = BD_STATUS(bd); + status = bd->status; while (!(status & RxBD_EMPTY)) { if (!(status & RxBD_ERROR)) { @@ -1190,7 +1188,7 @@ static int uec_recv(struct eth_device* d BD_LENGTH_SET(bd, 0); BD_STATUS_SET(bd, status | RxBD_EMPTY); BD_ADVANCE(bd, status, uec->p_rx_bd_ring); - status = BD_STATUS(bd); + status = bd->status; } uec->rxBd = bd;

1 0