November 2006 - U-Boot

Re: [U-Boot-Users] [PATCH] CFI driver AMD Command Set Top boot geometry reversal, etc.
by Timur Tabi 09 Nov '06

09 Nov '06

Stefan Roese wrote: > Yes, I second Timurs opinion. So Tolunay, please send your updated patch to > also correctly display the ID's and we'll try to get this in pretty soon. Actually, what I meant to say is the Tolunay's patch, as it is *now*, is good enough for now. But again, that's just my opinion. -- Timur Tabi Linux Kernel Developer @ Freescale

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[U-Boot-Users] [PATCH] CFI driver AMD Command Set Top boot geometry reversal, etc.
by Tolunay Orkun 09 Nov '06

09 Nov '06

This patch: * Adds support for AMD command set Top Boot flash geometry reversal * Adds support for displaying command set, manufacturer id and device ids (flinfo) * Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO defined * Removes outdated change history (refer to git log instead) Signed-off-by: Tolunay Orkun <listmember(a)orkun.us> --- drivers/cfi_flash.c | 153 +++++++++++++++++++++++++++++++++------------------ include/flash.h | 7 ++ 2 files changed, 105 insertions(+), 55 deletions(-)

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[U-Boot-Users] mpc83xx watchdog
by David Updegraff 09 Nov '06

09 Nov '06

Hi. Watchdog could work with this. -dbu

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[U-Boot-Users] : Not able to compile u-boot 1.1.5 for the at91rm9200dk
by Rajucm 09 Nov '06

09 Nov '06

Hi All, I have downloaded u-boot latest version 1.1.5 from the sourceforge.net I have installed cross compiler for arm. *I am using following procedure to compile:* make clobber make clean make at91rm9200dk_config make dep make all *But,* I am getting an error indicates that *"arm-linux-gcc: unrecognized option `-MQ'"* please Let me know me, if I have left with any more configuration. * Here is a log please some body can look into it. *make[1]: Leaving directory `/home/hcac/u-boot-1.1.5/post/cpu' make -C cpu/arm920t start.o make[1]: Entering directory `/home/hcac/u-boot-1.1.5/cpu/arm920t' arm-linux-gcc: start.o: No such file or directory arm-linux-gcc: unrecognized option `-MQ' arm-linux-gcc: cpu.o: No such file or directory arm-linux-gcc: unrecognized option `-MQ' arm-linux-gcc: interrupts.o: No such file or directory arm-linux-gcc: unrecognized option `-MQ' make[1]: *** [.depend] Error 1 make[1]: Leaving directory `/home/hcac/u-boot-1.1.5/cpu/arm920t' make: *** [cpu/arm920t/start.o] Error 2* * Thanks RajuCm

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[U-Boot-Users] ixdp465
by Michael Trimarchi 09 Nov '06

09 Nov '06

Hi, I have a full patch for ixdp465 with ethernet support and flash support. I don't have time to spend to clean my patch. Someone can help me? Regards Michael

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[U-Boot-Users] hello, everyone, I have a problem with u-boot-1.1.4 version
by 谭航 09 Nov '06

09 Nov '06

hi, Now I want to port u-boot-1.1.4 to the lpc22xx mcu,but I found this version couldn't support this cpu ,so I feel very frustrated! whether you intend to add this cpu to u-boot? if you just have a patch ,could I get from you? Thanks! best wishes to you! tanhang china 2006-11-10 _________________________________________________________________ 享用世界上最大的电子邮件系统― MSN Hotmail。 http://www.hotmail.com

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Re: [U-Boot-Users] [DNX#2006110942000034] new
by DENX Support System 09 Nov '06

09 Nov '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006110942000034] was created: <snip> > Hi, > > Approved PHrrARMACY http://www.aserunkiondfeunhas.com > > > > worked up a cover story. It goes this way, something close to the </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006110942000034] new
by U-Boot patch tracking system 09 Nov '06

09 Nov '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006110942000034]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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[U-Boot-Users] U-boot for imx31
by mukul bhardwaj 09 Nov '06

09 Nov '06

Hi, I wanted to gather some help from u-boot community. I am curretnly working on IMX31 , arm1136EJ-S . and trying to port u-boot on this board. Being new to the bootloader porting i neede some assistance. Workingon u-boot1.1.4 , able to compile it for target. > The initial code that i need to modify for the board , besides memory mapping in header file. Like First few things u-boot should be doing is Initilisation of RAM , init of Vectors , copying bootloader in RAM , setting up of Stack and jumping to the C starting code in RAM. Can someone help me in understanding the modification and sequence to be done. Can i get some standard code that i can use it for this board. Thanks. -- regards, Mukul Bhardwaj

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Re: [U-Boot-Users] [DNX#2006110942000016] [PATCH] CFI driver AMD Command Set Top boot geometry reversa [...]
by U-Boot patch tracking system 09 Nov '06

09 Nov '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006110942000016]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006110942000016] [PATCH] CFI driver AMD Command Set Top boot geomet [...]
by DENX Support System 09 Nov '06

09 Nov '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006110942000016] was created: <snip> > This patch: > > * Adds support for AMD command set Top Boot flash geometry reversal > * Adds support for displaying command set, manufacturer id and > device ids (flinfo) > * Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO > defined > * Removes outdated change history (refer to git log instead) > > Signed-off-by: Tolunay Orkun <listmember(a)orkun.us> > --- > > drivers/cfi_flash.c | 153 > +++++++++++++++++++++++++++++++++------------------ > include/flash.h | 7 ++ > 2 files changed, 105 insertions(+), 55 deletions(-) </snip> Your U-Boot support team

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Re: [U-Boot-Users] ethernet on FCC
by Lei Sun 08 Nov '06

08 Nov '06

Hi; Please ignore my first question regarding proff_enet, I wasn't too careful, it was inialized when defining the array. But still, can't explain why its not receiving any packets though.

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[U-Boot-Users] ethernet on FCC
by Lei Sun 08 Nov '06

08 Nov '06

Hi: While tring to bring up my mpc8270 based board, I found out the u-boot is not receiving packets (It's sending correct packet when i use ethereal for sniffing). When trying "ping", it generated an ARP packet first, the other host replied with , but the board never seems to receive it. When digging into the code, in cpu/mpc8260/ether_fcc.c file, it tries to initialize the parameter ram by : pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]); However, I can't seems to find where the info->proff_enet got initialized. I am using u-boot-1.1.4, but the 1.1.6 code does the same thing. The ether_scc.c file seems doing the right thing, because it defined PROFF_ENET as a macro. A bug ? Another thing, I loaded the uImage into memory using JTAG, but the "bootm" command failed when it tries to uncompressing the kernel, error message is "inflate() returned -3". I am running u-boot in ram directly , not from the flash, I have found some posts which saids if u-boot is running from RAM, it can't uncompressing the kernel, but without any explaination on why. Thanks lei

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[U-Boot-Users] why need disable icache
by Jackson 08 Nov '06

08 Nov '06

Hi, all I have been confused by cache recently. 1. why need we disable icache and dcache at the beginning of the u-boot code? 2. when can we enable them ? Thank you for the help. Best regards Jackson

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[U-Boot-Users] [PATCH] Where does U-Boot's CFI driver check for top/bottom boot?
by timur＠freescale.com 08 Nov '06

08 Nov '06

From: Timur Tabi <timur(a)freescale.com> This patch adds support for the reversed geometry data in some AMD flash chips. I'm not proud of this patch, so I'm posting it for review only. I know it works on the my board that was the problem, but I have no idea if it will break any other board. I'm sure this code could be improved a lot. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- drivers/cfi_flash.c | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index fd0a186..8cc8d60 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -1120,6 +1120,7 @@ ulong flash_get_size (ulong base, int ba uchar num_erase_regions; int erase_region_size; int erase_region_count; + int geometry_reversed = 0; #ifdef CFG_FLASH_PROTECTION int ext_addr; info->legacy_unlock = 0; @@ -1148,6 +1149,8 @@ #endif case CFI_CMDSET_AMD_STANDARD: case CFI_CMDSET_AMD_EXTENDED: info->cmd_reset = AMD_CMD_RESET; + if (flash_read_uchar(info, FLASH_OFFSET_CFI_RESP + (0x7E / info->portwidth)) == 3) + geometry_reversed = 1; break; } @@ -1171,8 +1174,13 @@ #endif num_erase_regions, NUM_ERASE_REGIONS); break; } - tmp = flash_read_long (info, 0, + if (geometry_reversed) + tmp = flash_read_long (info, 0, FLASH_OFFSET_ERASE_REGIONS + + (num_erase_regions - 1 - i) * 4); + else + tmp = flash_read_long (info, 0, + FLASH_OFFSET_ERASE_REGIONS + i * 4); erase_region_size = (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; -- 1.4.2.1

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[U-Boot-Users] u-boot as second monitor
by Francisco Afonso 07 Nov '06

07 Nov '06

Hi, I have a TQM823L board that comes with the Mon8xx monitor. I have read about how to install uboot over Mon8xx, but I would like to know if it is possible to generate u-boot for a different flash address and call it after the Mon8xx boot. If so what should I change in the uboot code? Thanks, Francisco

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[U-Boot-Users] mtest boundaries
by Rodolfo Giometti 07 Nov '06

07 Nov '06

Hello, how I can detect where u-boot puts itself into RAM in such a way the "mtest" command doesn't destroy it during memory tests? In this manner it could be possible to auto-exclude u-boot code during the test... Thanks, Rodolfo -- GNU/Linux Solutions e-mail: giometti(a)enneenne.com Linux Device Driver giometti(a)gnudd.com Embedded Systems giometti(a)linux.it UNIX programming phone: +39 349 2432127

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[U-Boot-Users] Compiling u-boot for coldfire
by Aitor Calderón 07 Nov '06

07 Nov '06

Hi there. I am trying to build u-boot for coldfire mcf52x2 CPU. I have run "make M5282EVB_config" and "make all" but I get this error: make[1]: Entering directory `/tmp/u-boot-1.1.6/cpu/mcf52x2' m68k-elf-gcc -D__ASSEMBLY__ -g -Os -ffixed-d7 -msep-data -D__KERNEL__ -DTEXT_BASE=0x20000 -I/tmp/u-boot-1.1.6/include -fno-builtin -ffreestanding -nostdinc -isystem /usr/local/lib/gcc/m68k-uclinux/4.1.1/include -pipe -DCONFIG_M68K -D__M68K__ -m5307 -c -o start.o start.S start.S: Mensajes del ensamblador: start.S:442: Error fatal: Se intentó convertir una ramificación condicional relativa al PC a un salto absoluto make[1]: *** [start.o] Error 1 make[1]: Leaving directory `/tmp/u-boot-1.1.6/cpu/mcf52x2' make: *** [cpu/mcf52x2/start.o] Error 2 the start.S message translated: start.S: Assembler messages: start.S:442: Fatal error: attempted to convert a conditional tree relative to PC into an absolut jump I was not sure about which compiler to use, so I am using m68k-elf-gcc 4.1.1 from last m68k-uclinux-tools. Should I use other? I am using u-boot 1.1.6 Thanks, Aitor.

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[U-Boot-Users] [PATCH 02/07 v2]: mpc7448hpc2 platform support (part 1/4 header file)
by Zang Roy-r61911 07 Nov '06

07 Nov '06

Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The original one is too big and divided into 4 parts for review. the board support header file. Signed-off-by: Alexandre Bounine <alexandreb(a)tundra.com> Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- include/configs/mpc7448hpc2.h | 440 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 440 insertions(+), 0 deletions(-) diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h new file mode 100644 index 0000000..5a1b8e2 --- /dev/null +++ b/include/configs/mpc7448hpc2.h @@ -0,0 +1,440 @@ +/* + * Copyright (c) 2005 Freescale Semiconductor, Inc. + * + * (C) Copyright 2006 + * Alex Bounine , Tundra Semiconductor Corp. + * Roy Zang , Freescale Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************** + * + * board specific configuration options for Freescale + * MPC7448HPC2 (High-Performance Computing II) (Taiga) board + * + ****************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* Board Configuration Definitions */ +/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */ + +#define CONFIG_MPC7448HPC2 + +#define CONFIG_74xx +#define CONFIG_750FX /* this option to enable init of extended BATs */ +#define CONFIG_ALTIVEC /* undef to disable */ + +#define CFG_BOARD_NAME "MPC7448 HPC II" +#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" + +#define CFG_OCN_CLK 133000000 /* 133 MHz */ +#define CFG_CONFIG_BUS_CLK 133000000 + +#define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ + +#undef CONFIG_ECC /* disable ECC support */ + +/* Board-specific Initialization Functions to be called */ +#define CFG_BOARD_ASM_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +/* Default MAC Addresses for on-chip GIGE Controller */ + +#define CONFIG_ETHADDR 00:06:D2:00:00:01 + +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:06:D2:00:00:02 + +#define CONFIG_ENV_OVERWRITE + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ + +/*#define CFG_HUSH_PARSER */ +#undef CFG_HUSH_PARSER + +#define CFG_PROMPT_HUSH_PS2 "> " + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * what to do: + * If you have hacked a serial cable onto the second DUART channel, change the CFG_DUART port from 1 + * to 0 below. + * + */ + +#define CONFIG_CONS_INDEX 1 +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK CFG_OCN_CLK * 8 + +#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808) +#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08) +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#undef CONFIG_BOOTARGS +/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ + +#if (CONFIG_BOOTDELAY >= 0) +#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ + setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ + ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " + +#define CONFIG_BOOTARGS "console=ttyS0,115200" +#endif + +#undef CONFIG_EXTRA_ENV_SETTINGS + +#define CONFIG_SERIAL "No. 1" + +/* Networking Configuration */ + +#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ + +#define CONFIG_TSI108_ETH +#define CONFIG_TSI108_ETH_NUM_PORTS 2 + +#define CONFIG_NET_MULTI + +#define CONFIG_IPADDR 172.27.234.48 +#define CONFIG_SERVERIP 172.27.234.10 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_GATEWAYIP 172.27.255.254 + +#define CONFIG_BOOTFILE zImage.initrd.elf +#define CONFIG_LOADADDR 0x400000 + +#define CONFIG_TESTDRAMDATA y +#define CONFIG_TESTDRAMADDRESS n +#define CONFIG_TESETDRAMWALK n + +/*--------------------------------------------------------------------- ----- */ + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +/* Flash banks JFFS2 should use */ +#define CFG_JFFS2_FIRST_BANK 1 +#define CFG_JFFS2_NUM_BANKS 1 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_CACHE \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C \ + | CFG_CMD_SDRAM \ + | CFG_CMD_EEPROM \ + | CFG_CMD_NET \ + | CFG_CMD_FLASH \ + | CFG_CMD_ENV \ + | CFG_CMD_BSP \ + | CFG_CMD_DHCP \ + | CFG_CMD_PING \ + | CFG_CMD_DATE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/*set date in u-boot*/ +#define CONFIG_RTC_M48T35A +#define CFG_NVRAM_BASE_ADDR 0xfc000000 +#define CFG_NVRAM_SIZE 0x8000 +/* + * Miscellaneous configurable options + */ +#define CONFIG_VERSION_VARIABLE 1 + +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* +#define CFG_DRAM_TEST + * DRAM tests + * CFG_DRAM_TEST - enables the following tests. + * + * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines + * Environment variable 'test_dram_data' must be + * set to 'y'. + * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely + * addressable. Environment variable + * 'test_dram_address' must be set to 'y'. + * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. + */ +#define CFG_DRAM_TEST +#if defined(CFG_DRAM_TEST) +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CFG_DRAM_TEST_DATA +#define CFG_DRAM_TEST_ADDRESS +#define CFG_DRAM_TEST_WALK +#endif /* CFG_DRAM_TEST */ + +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*--------------------------------------------------------------------- -- + * Definitions for initial stack pointer and data area + */ + +/* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized +*/ +#undef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ +#define CFG_INIT_RAM_END 0x4000 /* larger space - we have SDRAM initialized */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/*--------------------------------------------------------------------- -- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ + +#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ +#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ + +#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ +#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ + +#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ + +#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ + +#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ + +#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */ +#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ + +#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ + +#define PCI0_IO_BASE_BOOTM 0xfd000000 + +#define CFG_RESET_ADDRESS 0x3fffff00 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ + +/* Peripheral Device section */ + +/******************************************************* + * Resources on the Tsi108 + *******************************************************/ + +#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ +#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ + +#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ + +#undef DISABLE_PBM + +/*--------------------------------------------------------------------- -- + * PCI stuff + *----------------------------------------------------------------------- + */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_TSI108_PCI /* include tsi108 pci support */ + +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +/* PCI MEMORY MAP section */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +/* PCI Memory Space */ +#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) +#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) //CFG_PCI_MEM32_BASE = 0xE0000000 +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ + +/* PCI I/O Space */ +#define CFG_PCI_IO_BUS 0x00000000 +#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ + +#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */ + +#define _IO_BASE 0x00000000 /* points to PCI I/O space */ + +/* PCI Config Space mapping */ +#define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ +#define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */ + +#define CFG_IBAT0U 0xFE0003FF +#define CFG_IBAT0L 0xFE000002 + +#define CFG_IBAT1U 0x00007FFF +#define CFG_IBAT1L 0x00000012 + +#define CFG_IBAT2U 0x80007FFF +#define CFG_IBAT2L 0x80000022 + +#define CFG_IBAT3U 0x00000000 +#define CFG_IBAT3L 0x00000000 + +#define CFG_IBAT4U 0x00000000 +#define CFG_IBAT4L 0x00000000 + +#define CFG_IBAT5U 0x00000000 +#define CFG_IBAT5L 0x00000000 + +#define CFG_IBAT6U 0x00000000 +#define CFG_IBAT6L 0x00000000 + +#define CFG_IBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 + +#define CFG_DBAT0U 0xE0003FFF +#define CFG_DBAT0L 0xE000002A + +#define CFG_DBAT1U 0x00007FFF +#define CFG_DBAT1L 0x00000012 + +#define CFG_DBAT2U 0x00000000 +#define CFG_DBAT2L 0x00000000 + +#define CFG_DBAT3U 0xC0000003 +#define CFG_DBAT3L 0xC000002A + +#define CFG_DBAT4U 0x00000000 +#define CFG_DBAT4L 0x00000000 + +#define CFG_DBAT5U 0x00000000 +#define CFG_DBAT5L 0x00000000 + +#define CFG_DBAT6U 0x00000000 +#define CFG_DBAT6L 0x00000000 + +#define CFG_DBAT7U 0x00000000 +#define CFG_DBAT7L 0x00000000 + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x51 +#define DIMM1_I2C_ADDR 0x52 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +/*--------------------------------------------------------------------- -- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_SWAP + +#define PHYS_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_SECT (128) + +#define CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_ADDR 0xFC000000 + +#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ + +/*--------------------------------------------------------------------- -- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*--------------------------------------------------------------------- -- + * L2CR setup -- make sure this is right for your board! + * look in include/mpc74xx.h for the defines used here + */ +#undef CFG_L2 + +#define L2_INIT 0 +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CFG_EXCEPTION_AFTER_RELOCATE +#define CFG_SERIAL_HANG_IN_EXCEPTION +#endif /* __CONFIG_H */ -- 1.4.0

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[U-Boot-Users] MPC8270/MPC8250 Ethernet Problem
by Aaron Sells 07 Nov '06

07 Nov '06

I am having trouble getting Ethernet to work correctly on our Embedded Planet EP82xxM board. Specifically, pings and TFTP transfers fail when the board is populated with an MPC8250 or an MPC8270. However, when the board is populated with an MPC8280 processor, Ethernet works. Any suggestions of things to try out to resolve this would be greatly appreciated. FCC2/3 port pins appear to be correctly configured. PHY registers are able to be accessed and seem to show the correct configuration. No packets are appearing on the wire when sniffed with Ethereal. With ET_DEBUG turned on, pinging results in the following output: ep82xxm=> ping 10.0.0.26 Using FCC3 ETHERNET device sending ARP for 0a00001a ARP broadcast 1 packet received packet received Receive from protocol 0x0 packet received packet received Receive from protocol 0x0 . . . ARP broadcast 2 packet received packet received Receive from protocol 0x0 packet received packet received Receive from protocol 0x0 . . . ping failed; host 10.0.0.26 is not alive MII info and dump result in the following output: ep82xxm=> mii info PHY 0x00: OUI = 0x04DE, Model = 0x0E, Rev = 0x02, 100baseT, FDX PHY 0x01: OUI = 0x04DE, Model = 0x0E, Rev = 0x02, 10baseT, HDX ep82xxm=> mii dump 0 0-5 0. (3100) -- PHY control register -- (8000:0000) 0.15 = 0 reset (4000:0000) 0.14 = 0 loopback (2040:2000) 0. 6,13 = b01 speed selection = 100 Mbps (1000:1000) 0.12 = 1 A/N enable (0800:0000) 0.11 = 0 power-down (0400:0000) 0.10 = 0 isolate (0200:0000) 0. 9 = 0 restart A/N (0100:0100) 0. 8 = 1 duplex = full (0080:0000) 0. 7 = 0 collision test enable (003f:0000) 0. 5- 0 = 0 (reserved) 1. (782d) -- PHY status register -- (8000:0000) 1.15 = 0 100BASE-T4 able (4000:4000) 1.14 = 1 100BASE-X full duplex able (2000:2000) 1.13 = 1 100BASE-X half duplex able (1000:1000) 1.12 = 1 10 Mbps full duplex able (0800:0800) 1.11 = 1 10 Mbps half duplex able (0400:0000) 1.10 = 0 100BASE-T2 full duplex able (0200:0000) 1. 9 = 0 100BASE-T2 half duplex able (0100:0000) 1. 8 = 0 extended status (0080:0000) 1. 7 = 0 (reserved) (0040:0000) 1. 6 = 0 MF preamble suppression (0020:0020) 1. 5 = 1 A/N complete (0010:0000) 1. 4 = 0 remote fault (0008:0008) 1. 3 = 1 A/N able (0004:0004) 1. 2 = 1 link status (0002:0000) 1. 1 = 0 jabber detect (0001:0001) 1. 0 = 1 extended capabilities 2. (0013) -- PHY ID 1 register -- (ffff:0013) 2.15- 0 = 19 OUI portion 3. (78e2) -- PHY ID 2 register -- (fc00:7800) 3.15-10 = 30 OUI portion (03f0:00e0) 3. 9- 4 = 14 manufacturer part number (000f:0002) 3. 3- 0 = 2 manufacturer rev. number 4. (01e1) -- Autonegotiation advertisement register -- (8000:0000) 4.15 = 0 next page able (4000:0000) 4.14 = 0 reserved (2000:0000) 4.13 = 0 remote fault (1000:0000) 4.12 = 0 reserved (0800:0000) 4.11 = 0 asymmetric pause (0400:0000) 4.10 = 0 pause enable (0200:0000) 4. 9 = 0 100BASE-T4 able (0100:0100) 4. 8 = 1 100BASE-TX full duplex able (0080:0080) 4. 7 = 1 100BASE-TX able (0040:0040) 4. 6 = 1 10BASE-T full duplex able (0020:0020) 4. 5 = 1 10BASE-T able (001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3 5. (45e1) -- Autonegotiation partner abilities register -- (8000:0000) 5.15 = 0 next page able (4000:4000) 5.14 = 1 acknowledge (2000:0000) 5.13 = 0 remote fault (1000:0000) 5.12 = 0 (reserved) (0800:0000) 5.11 = 0 asymmetric pause able (0400:0400) 5.10 = 1 pause able (0200:0000) 5. 9 = 0 100BASE-T4 able (0100:0100) 5. 8 = 1 100BASE-X full duplex able (0080:0080) 5. 7 = 1 100BASE-TX able (0040:0040) 5. 6 = 1 10BASE-T full duplex able (0020:0020) 5. 5 = 1 10BASE-T able (001f:0001) 5. 4- 0 = 1 selector = IEEE 802.3 My environment settings are as follows: ep82xxm=> printenv bootdelay=5 baudrate=115200 ethaddr=00:10:EC:00:88:66 eth1addr=00:10:EC:80:88:66 ipaddr=10.0.0.245 serverip=10.0.0.26 gatewayip=10.0.0.1 netmask=255.255.255.0 hostname=EP82xxM ethprime=FCC3 ETHERNET stdin=serial stdout=serial stderr=serial ethact=FCC3 ETHERNET Thanks for your help!

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Re: [U-Boot-Users] Where does U-Boot's CFI driver check for top/bottom boot?
by Yogi 06 Nov '06

06 Nov '06

Early on AMD (now SPANSION), had typo in there data sheet for this MODEL# 3 and 4. Later on they corrected the data sheet. Yes, this field can be used to verify the sector layout to see if it is bottom boot or topboot. Thanks Yogi ----- Original Message ---- From: Timur Tabi <timur(a)freescale.com> To: Tolunay Orkun <listmember(a)orkun.us> Cc: u-boot-users(a)lists.sourceforge.net Sent: Monday, November 6, 2006 2:00:12 PM Subject: Re: [U-Boot-Users] Where does U-Boot's CFI driver check for top/bottom boot? Tolunay Orkun wrote: > I just looked at the datasheet of your flash part as well as datasheet > of a couple of intel flash parts as well as the current code. As I > suspected for your particular part, it looks like they are using the > same values for "Erase Bank Area 1" and "Erase Bank Area 2" irrespective > of top boot or bottom boot flash. I think, this is fundamentally wrong > and non-compliant with the general CFI standard. Using the PDF you specified, I see that my chip has a value of 03h for the "Top/Bottom Boot Sector Flag", at offset (P+F)h. That indicates a top-boot, which is correct (smaller sectors at the end of memory). Why can't we just check this byte if we're on an AMD part, and adjust accordingly? -- Timur Tabi Linux Kernel Developer @ Freescale ------------------------------------------------------------------------- Using Tomcat but need to do more? Need to support web services, security? Get stuff done quickly with pre-integrated technology to make your job easier Download IBM WebSphere Application Server v.1.0.1 based on Apache Geronimo http://sel.as-us.falkag.net/sel?cmd=lnk&kid=120709&bid=263057&dat=121642 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] Where does U-Boot's CFI driver check for top/bottom boot?
by Timur Tabi 06 Nov '06

06 Nov '06

Can someone point me to the code where the CFI driver checks if the flash is top-boot or bottom boot? The spec says that that information is in offset 1E of the Primary Vendor-Specific Extension Query Table, but I don't see any code that references that. Do I need to add an entry into flash.h for my part (29LV640BT)? -- Timur Tabi Linux Kernel Developer @ Freescale

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[U-Boot-Users] Why are some global vars part of the image, and some not?
by Timur Tabi 06 Nov '06

06 Nov '06

I have the following code in one of my files: #ifdef CFG_SPD_BUS_NUM static volatile unsigned int i2c_bus_num = CFG_SPD_BUS_NUM; #else static volatile unsigned int i2c_bus_num = 0; #endif static volatile struct fsl_i2c *i2c_dev[2] = { (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), #ifdef CFG_I2C2_OFFSET (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET) #endif }; As you can see, I defined two static volatile global vars: i2c_bus_num and i2c_dev. My U-Boot image is 0x294E0 bytes in size, and it's located at address 0xFE000000. When I run U-Boot, the address of i2c_bus_num is 0xfe02a114, and the address of i2c_dev[] is 0xfe028124. In other words, i2c_dev[] is part of the actual U-Boot image, but i2c_bus_num, which is defined right next to it, isn't. This means that i2c_dev[] is properly initialized, but i2c_bus_num is set to 0xFFFFFFFF (the value that erased flash has). How is this possible? How can two adjacent global variables be located is completely different memory segments? -- Timur Tabi Linux Kernel Developer @ Freescale

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Re: [U-Boot-Users] [DNX#2006110642000012] new 414
by U-Boot patch tracking system 06 Nov '06

06 Nov '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006110642000012]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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[U-Boot-Users] [help] suggest me u-boot version for my at91rm9200dk
by Rajucm 06 Nov '06

06 Nov '06

Hi all, I started working with at91rm9200dk board. U-BOOT-0.3.2 is up and running in my Atemel DK. Please suggest me one best version (Recent one) to start my work with the DK board that should be a very good starting point for my work. Thank's, RajuCm

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