October 2006 - U-Boot

[U-Boot-Users] 1 Nand - u-boot support
by Ram 06 Oct '06

06 Oct '06

Hi, Does u-boot has 1 nand support. Want u-boot to run from 1 nand flash. Regards, sriram

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Re: [U-Boot-Users] Can I write to flash using mw command
by Ben Warren 06 Oct '06

06 Oct '06

On Thu, 2006-10-05 at 14:03 -0700, bilahari akkiraju wrote: > Hi Ben, > > Stuff works fine using U-boot's cfi. I can protect > and erase using appropriate commands (protect and > erase ) provided by the u-boot. I do not know if > there is a u-boot command to write to flash. > > My flinfo command shows this : > > bank # 1: CFI conformant FLASH (32 x 16) Size: 16 MB > in 128 Sectors > Erase timeout 16384 ms, write timeout 0 ms, buffer > write timeout 4096 ms, buffe2 > Sector Start Addresses: > > FF000000 FF020000 FF040000 FF060000 > FF080000 > FF0A0000 FF0C0000 FF0E0000 FF100000 > FF120000 This is odd. The GL064 is either 32x8 or 16x16, and has either 128x64kB or 127x64kB + 8x8kB sector layout. Yours appears to have 128 uniform sectors of 128kB each. Either you're not using the part you think you are or my documentation is out of date. > I am trying low level access because I am writing my > own flash utilities which are independent of U-boot > and hence have to directly deal with right command > sequences. > If your utilities are independent of U-boot then your request is off-topic. Since the CFI driver is working, you're missing something in the sequence of commands being written to flash. I've done it before manually via BDI-2000, and although the Spansion documentation is cryptic, it's technically correct. Sorry I can't help more right now but work beckons... Also, please copy the U-boot mailing list when corresponding. regards, Ben

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Re: [U-Boot-Users] [DNX#2006100542000034] [PATCH] Fix PCI, USB, bootargs for MPC8349E-mITX
by U-Boot patch tracking system 05 Oct '06

05 Oct '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006100542000034]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006100542000034] [PATCH] Fix PCI, USB, bootargs for MPC8349E-mITX
by DENX Support System 05 Oct '06

05 Oct '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006100542000034] was created: <snip> > From: Timur Tabi <timur(a)freescale.com> > > PREREQUISITE PATCHES: > > * This patch can only be applied after the following patches have been > applied: > > 1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2" > 2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2" > > CHANGELOG: > > * For the 8349E-mITX, fix some size values in pci_init_board(), enable > the clock for the 2nd USB board (Linux kernel will hang otherwise), > and fix the CONFIG_BOOTARGS macro. > > Signed-off-by: Timur Tabi <timur(a)freescale.com> > --- > board/mpc8349itx/pci.c | 14 +++++++------- > include/configs/MPC8349ITX.h | 19 +++++++++++-------- > 2 files changed, 18 insertions(+), 15 deletions(-) > > diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c > index 22ab736..c90ccc0 100644 > --- a/board/mpc8349itx/pci.c > +++ b/board/mpc8349itx/pci.c > @@ -153,7 +153,7 @@ #endif > pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; > > pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; > - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; > + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; > > /* > * Configure PCI Outbound Translation Windows > @@ -162,17 +162,17 @@ #endif > /* PCI1 mem space - prefetch */ > pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; > pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; > - pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & > POCMR_CM_MASK); > + pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M; > > /* PCI1 IO space */ > pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; > pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; > - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & > POCMR_CM_MASK); > + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; > > /* PCI1 mmio - non-prefetch mem space */ > pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; > pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; > - pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); > + pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; > > /* > * Configure PCI Inbound Translation Windows > @@ -259,17 +259,17 @@ #ifdef CONFIG_MPC83XX_PCI2 > /* PCI2 mem space - prefetch */ > pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; > pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; > - pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | > (POCMR_CM_256M & POCMR_CM_MASK); > + pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | > POCMR_CM_256M; > > /* PCI2 IO space */ > pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; > pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; > - pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & > POCMR_CM_MASK); > + pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M; > > /* PCI2 mmio - non-prefetch mem space */ > pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; > pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; > - pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & > POCMR_CM_MASK); > + pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M; > > /* > * Configure PCI Inbound Translation Windows > diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h > index aed350f..20f3c6d 100644 > --- a/include/configs/MPC8349ITX.h > +++ b/include/configs/MPC8349ITX.h > @@ -604,7 +604,7 @@ #define CFG_ACR_RPTCNT 3 /* Arbiter rep > > /* System IO Config */ > #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 > */ > -#define CFG_SICRL SICRL_LDP_A > +#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) > > #define CFG_HID0_INIT 0x000000000 > > @@ -701,7 +701,7 @@ #define CONFIG_IPADDR 10.82.19.159 > #define CONFIG_SERVERIP 10.82.48.106 > #define CONFIG_GATEWAYIP 10.82.19.254 </snip> Your U-Boot support team

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[U-Boot-Users] What the right procedure should be when write a new driver for U-boot?
by Lyoo 05 Oct '06

05 Oct '06

Hi maintainer There is some confusion about what the right procedure should be, when someone want to add some drivers to U-boot. When I read U-boot's code, I found the devices initialize function devices_init() (called in /u-boot-x.x.x/lib_xxx/board.c), It creates a device list, then dev_xxx_init() register the devices such as LCD, USB, Serial, Keyboard in the list. But, some SOC have their own drivers, for example s3c24x0 have their own driver of USB, Serial,(/cpu/arm920t/s3c24x0/usb_ohci.c) they don't care about the device list, they do it their way. Is there any 'official' policy on it?

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[U-Boot-Users] U-boot AMCC yosemite board 440EP
by Föll, Tobias 05 Oct '06

05 Oct '06

Hi, i have a hardware which is very near to the yosemite board called JC-670. The yosemite board has 4 DDR chips and my hardware has only two chips (2*Micron 64V16M16 has 256Mbit...), because i need only 256MBit*2Chips=512MBit=64Mbyte. It seem that i have problems with the DDR interface. I downloaded the u-boot bin file from the AMCC -> denx page, and programmed it into the flash on my hardware called JC-670. On the serial output i saw that the system starts up. But then it hangs... Here is the first output hardware JC-670: =========================================== U-Boot 1.1.4-ga2c95a72 (Jul 28 2006 - 19:32:28) CPU: AMCC PowerPC 440EP Rev. B at 666.666 MHz (PLB=266, OPB=133, EBC=133 MHz) I2C boot EEPROM enabled Internal PCI arbiter disabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: Yosemite - AMCC PPC440EP Evaluation Board I2C: ready DRAM: Software has not detected the DRAM ! Here is the second output hardware JC-670: ========================================== U-Boot 1.1.4-ga2c95a72 (Jul 28 2006 - 19:32:28) CPU: AMCC PowerPC 440EP Rev. B at 666.666 MHz (PLB=266, OPB=133, EBC=133 MHz) I2C boot EEPROM enabled Internal PCI arbiter disabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: Yosemite - AMCC PPC440EP Evaluation Board I2C: ready DRAM: 256 MB U-boot software has detected the DRAM's. I can try this several times the difference is that sometimes i got the DRAM size(like first output) and somtimes not (like second output). Thats all. Must i change the u-boot code if i only use two DDR Chips ? On the moment i can not generate a new u-boot bin , because it will not work with cygwin under windows.I tried it. And i'am not a linux expert, because of this i can not do this work under linux on the moment. Has anybody an idea why sometimes the "256 MB" text will not come ? For me it looks like the sdram_init() function in yosemite.c sometimes hangs. Regards Tobias

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Re: [U-Boot-Users] [DNX#2006100542000025] Hi
by U-Boot patch tracking system 05 Oct '06

05 Oct '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006100542000025]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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Re: [U-Boot-Users] [DNX#2006100542000025] Hi
by DENX Support System 05 Oct '06

05 Oct '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006100542000025] was created: <snip> > Hi, > > ClAhLIS > > AMBhlEN > > VALhlUM > > VlAhGRA > > Save 60 % with http://www.shideonketunhertionde.com > > _____ > > > They sure bred them dumb in the future. Or without imagination or > room with what I recognized as being a state of the art communication > Sit, he commanded. Behind us was a clank and rattle, a hiss of </snip> Your U-Boot support team

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[U-Boot-Users] Help me, Ethernet does not work in Linux+Ramdisk system!
by kiennd 05 Oct '06

05 Oct '06

Hi everybody! My board use chip at91rm9200 ( my board as same as ARM9 SBC board http://www.ime.usp.br/~fr/sbc/ ) , and I use u-boot as a boot loader for my system. I built linux image 2.6 ( 2.6.16, 2.6.17, 2.6.18 ) with patch from http://maxim.org.za/AT91RM9200/2.6/ and a small root filesystem and use u-boot to load them. Everything is ok. My system had a sh shell. ################################################# # ls bin ftp linuxrc sbin var dev home lost+found tmp etc lib proc usr ################################################# And here is a part of dmesg log: ################################################# NET: Registered protocol family 16 Generic PHY: Registered new driver NET: Registered protocol family 2 IP route cache hash table entries: 256 (order: -2, 1024 bytes) TCP established hash table entries: 1024 (order: 0, 4096 bytes) TCP bind hash table entries: 512 (order: -1, 2048 bytes) TCP: Hash tables configured (established 1024 bind 512) TCP reno registered NetWinder Floating Point Emulator V0.97 (double precision) at91_spi: Baud rate set to 5990400 AT91 SPI driver loaded AT91 Watchdog Timer enabled (5 seconds, nowayout) at91_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL at91_usart.1: ttyS1 at MMIO 0xfffc4000 (irq = 7) is a AT91_SERIAL RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize LXT970: Registered new driver LXT971: Registered new driver eth0: Link now 100-FullDuplex eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (de:ad:be:ef:01:01) eth0: Intel LXT971A PHY ################################################################################# Ethernet card is seem to work. ################################################################################ # ifconfig lo up # ifconfig eth0 up eth0: Link now 100-FullDuplex # ifconfig eth0 192.168.0.1 netmask 255.255.255.0 # ping -c 1 localhost PING localhost.localdomain (127.0.0.1): 56 data bytes 64 bytes from 127.0.0.1: icmp_seq=0 ttl=64 time=1.6 ms --- localhost.localdomain ping statistics --- 1 packets transmitted, 1 packets received, 0% packet loss round-trip min/avg/max = 1.6/1.6/1.6 ms # ping -c 1 192.168.0.1 PING 192.168.0.1 (192.168.0.1): 56 data bytes 64 bytes from 192.168.0.1: icmp_seq=0 ttl=64 time=1.4 ms --- 192.168.0.1 ping statistics --- 1 packets transmitted, 1 packets received, 0% packet loss round-trip min/avg/max = 1.4/1.4/1.4 ms # ping -c 1 192.168.0.222 PING 192.168.0.222 (192.168.0.222): 56 data bytes --- 192.168.0.222 ping statistics --- 1 packets transmitted, 0 packets received, 100% packet loss # ################################################################################ But really, it can't connect to outside. ping localhost and it's ip address are ok, but ping a host in LAN ==> false! - Network configuration is Ok. - Network card is OK. In u-boot env, i use tftp to load kernel image and ramdisk image ==> network card is ok - In kernel with patched, i think kernel image had driver for network card ( eth0: Intel LXT971A PHY ). Can you give me some suggestion. Thanks!!!

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[U-Boot-Users] Can I write to flash using mw command
by bilahari akkiraju 05 Oct '06

05 Oct '06

Hello, -> On my target board I have a spansion GL064M flash device. -> The flash base address is 0xff000000. -> I have read the data sheet for the device and noted down the erase and write command sequences for the device. -> I cannot erase, write to flash by implementing the appropriate command sequences with mw (memory write ) command provided by u-boot that came with my sdk (u-boot 1.1.4). For example For erasing sector 0xff000000 I typed the following sector erase command sequence (as per data sheet) at u-boot prompt mw.b 0xff000555 0xAA mw.b 0xff0002AA 0x55 mw.b 0xff000555 0x80 mw.b 0xff000555 0xAA mw.b 0xff0002AA 0x55 mw.b 0xff000000 0x30 For writing to address 0xff000000 I typed the following write command sequence (as per data sheet) at the u-boot prompt. mw.b 0xff000555 0xAA mw.b 0xff0002AA 0x55 mw.b 0xff000555 0xA0 mw.b 0xff000000 0x12 ; value 0x12 mw.b 0xff000001 0x34 ; value 0x34 mw.b 0xff000000 0xF0 ; reset (I do it as u-boot driver cfi_flash.c does it ) -> After doing all this , when I do a memory dump using md.b 0xff000000 , to my frustration I see that nothing at all has happend to the flash. I am sure I am missing something small or may be I am doing a completely wrong thing. I am more of a computer science guy and new to chip programming. Any suggestions, ideas or comments would be very helpful. Thanks you all Bilahari __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

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