October 2006 - U-Boot

Re: [U-Boot-Users] [DNX#2006102442000016] VIEAGRA
by U-Boot patch tracking system 24 Oct '06

24 Oct '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006102442000016]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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[U-Boot-Users] For my partner only
by Dolores Louis 24 Oct '06

24 Oct '06

The first thing to do in tuesday is to get in on EQTD. It will SOAR up next week. There will be at least 100% appreciation within the first few hours, so do it fast . With oil markets retreating, big traders are turning to gold, driving it to levels never before seen. EQTD has made an advertisement of staggering proportions related to a recent survey on one of their gold ownership. The internal scoop is that we will be looking at a quadrupling of market rate once the public takes notice: CHICAGO, ILLINOIS-(MARKETWIRE)-Oct 23, 2006 - Equal trading is pleased to announce announcement results which have far exceeded expectations. The results from our British Columbia property show 58,000 ounce potential. Plans are already underway for urgent development. We look forward to this remarkable discovery bringing value to our stockholder. At 600$ an ounce this finding is worth 34.8 mil$. With 865mil shares outstanding, this would give us a book value of 0.04 (last price is under 1 cent). Don't miss this one. The value and the opportunity are there. This days is the lowest price it can be. It's high time to buy in! The profitable time to invest! Real promotion will help you to sell it with higher price later.

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[U-Boot-Users] bootm command and flushing cache
by warren.l.dodge＠exgate.tek.com 23 Oct '06

23 Oct '06

I was tring to get a bootm command to work and had a problem until I called the fluch_cache routine to force the results of the data move into ram. This way the execution of the image used the code I had moved into ram rather then whatever was sitting there. I see a reference to another user who had this problem but didn't see any resolution.. It seems like a rather serious thing and should be fixed. Email Archive: u-boot-users <http://sourceforge.net/mailarchive/forum.php?forum_id=12898> (read-only) Re: do_bootm() and flush_cache() From: Scott McNutt <smcnutt@ps...> - 2005-03-23 18:56 >>But after reviewing do_bootm(), I don"t see where the >>caches are flushed. A call to flush_cache() after >>moving/decompressing the image seems appropriate, but > > > Why? After the move/decompression, the data cache must be flushed to main memory ... otherwise an instruction cache miss (after jumping into the kernel) may read in a (potentially) stale line. (Neither cache can be disabled.) Regards, --Scott

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[U-Boot-Users] cpu_init_f - OR0/BRO PRELIM
by Rahul Kulkarni 23 Oct '06

23 Oct '06

I am trying to port uboot on our own board running mpc8541E processor. Have all the board specfic stuff created and compiled in, did face a few issues early on, but right now it seem like it goes all the way till board_init_f and hangs. Bactracking through the startup code I see that my LBC register have not been initialized. I have the following settings in my board.config file #define CFG_BR0_PRELIM 0xFE001801 #define CFG_OR0_PRELIM 0xFE006F35 2 * 16MB interleaved flashes configured on CS0 CCSRBAR config: #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ It does go through cpu_init_f with no exections etc but If I set a breakpoint or stop it at some later point and look at the OR0/BRO registes I do not see the above values being set. I am not quite sure how the CCSRBAR reloacation code in start.S seems to handle the relocation I do see that we go through this part in the the debugger. #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) /* Special sequence needed to update CCSRBAR itself */ lis r4, CFG_CCSRBAR_DEFAULT@h ori r4, r4, CFG_CCSRBAR_DEFAULT@l lis r5, CFG_CCSRBAR@h ori r5, r5, CFG_CCSRBAR@l srwi r6,r5,12 stw r6, 0(r4) isync lis r5, 0xffff ori r5,r5,0xf000 lwz r5, 0(r5) isync lis r3, CFG_CCSRBAR@h lwz r5, CFG_CCSRBAR@l(r3) isync #endif I was wondering if these two variables are being set properly volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; since the statment below in cpu_init_f does not seem to take effect. memctl->br0 = CFG_BR0_PRELIM; memctl->or0 = CFG_OR0_PRELIM; I'd really appreciate any replies or suggestions. thanks much, Rahul TLB config below: /* * TLB0 and TLB1 Entries * * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. * However, CCSRBAR is then relocated to CFG_CCSRBAR right after * these TLB entries are established. * * MAS0: tlbsel, esel, nv * MAS1: valid, iprot, tid, ts, tsize * MAS2: epn, sharen, x0, x1, w, i, m, g, e * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr */ #define entry_start \ mflr r1 ; \ bl 0f ; #define entry_end \ 0: mflr r0 ; \ mtlr r1 ; \ blr ; .section .bootpg, "ax" .globl tlb1_entry tlb1_entry: entry_start /* * Number of TLB0 and TLB1 entries in the following table */ .long 13 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) /* * TLB0 4K Non-cacheable, guarded * 0xff700000 4K Initial CCSRBAR mapping * * This ends up at a TLB0 Index==0 entry, and must not collide * with other TLB0 Entries. */ .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) #else #error("Update the number of table entries in tlb1_entry") #endif /* * TLB0 16K Cacheable, non-guarded * 0xd001_0000 16K Temporary Global data for initialization * * Use four 4K TLB0 entries. These entries must be cacheable * as they provide the bootstrap memory before the memory * controler and real memory have been configured. * * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, * and must not collide with other TLB0 entries. */ .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), 0,0,0,0,0,1,0,1,0,1) /* * TLB 0, 1: 32M Non-cacheable, guarded * 0xfe000000 32FLASH * Out of reset this entry is only 4K. */ .long TLB1_MAS0(1, 2, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(1, 1, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1) /* * TLB 3: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ .long TLB1_MAS0(1, 3, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* * TLB 4: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ .long TLB1_MAS0(1, 4, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), 0,0,0,0,0,1,0,1,0,1) /* * TLB 5: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* * TLB 6: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ .long TLB1_MAS0(1, 6, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), 0,0,0,0,0,1,0,1,0,1) /* * TLB 7: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ .long TLB1_MAS0(1, 7, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) /* * TLB 8: 256M DDR, cache disabled (needed for memory test) * 0x00000000 256M DDR System memory * Without SPD EEPROM configured DDR, this must be setup manually. * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ .long TLB1_MAS0(1, 8, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) entry_end /* * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G * 0xe000_0000 0xe000_ffff CCSR 1M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. */ #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) #define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) /* * Rapid IO at 0xc000_0000 for 512 M */ #define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) .section .bootpg, "ax" .globl law_entry law_entry: entry_start .long 0x05 .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 .long LAWBAR4,LAWAR4 entry_end

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Re: [U-Boot-Users] VlbAGRA
by Mariette Kriz 23 Oct '06

23 Oct '06

Hi, GREAT VlbAGRA http://www.pisadesinjionkadesun.com Do I look as bad as you do? Floyd said in a hoarse voice, his new- in their correct place. Great respect is given to the scientist. Veldi

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[U-Boot-Users] ixdp465 ethernet driver
by Michael Trimarchi 23 Oct '06

23 Oct '06

Hi all, I'm working on intel ethernet driver porting from linux. If somebody is working on the same topic, please contact me by email Regards Michael

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Re: [U-Boot-Users] NAND access via custom interface
by Jack Hab 23 Oct '06

23 Oct '06

Yes I have all the defines related to the NAND. I understand the stuff in cmd_nand.c is not called directly from U-Boot code, so what's the mechanism which includes this file in the link stage? On 10/23/06, Stefan Roese <sr(a)denx.de> wrote: > > Hi Jack, > > On Monday 23 October 2006 13:43, you wrote: > > I've implemented the NAND interface with functions registerd in > nand_chip > > struct. All compiles fine but somehow the cmd_nand.c is not getting > linked. > > I get the U-Boot image with all my nand flash functions inside but since > > cmd_nand.c is not linked, U_BOOT_CMD does not register the nand > commands. > > I have > > > > #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NAND > > > > in my boardconfig.h > > > > Is there anything else needed? > > Do you have something like: > > /* > * NAND-FLASH stuff > */ > #define CFG_MAX_NAND_DEVICE 1 > #define NAND_MAX_CHIPS 1 > #define CFG_NAND_BASE 0x51000000 /* NAND FLASH Base Address > */ > > in your config file? And please make sure that you don't > have "CFG_NAND_LEGACY" defined. > > BTW: Please keep send those kind of messages to the list and not _only_ to > me. > Thanks. > > Best regards, > Stefan >

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[U-Boot-Users] staffing totem pole
by William Pena 23 Oct '06

23 Oct '06

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[U-Boot-Users] [PATCH] NAND feature update
by Ladislav Michl 23 Oct '06

23 Oct '06

Wolfgang, this patch implements functionaly I found useful to have and hopefuly others can benefit from it too. Please drop all my previous NAND related, not yet applied patches. Once (if) applied I will rediff the rest. Now you can do: # mtdparts [snip] device nand0 <omapnand.0>, # parts = 5 #: name size offset mask_flags 0: kernel0 0x00400000 0x00000000 0 1: rootfs0 0x02800000 0x00400000 0 2: kernel1 0x00400000 0x02c00000 0 3: rootfs1 0x02800000 0x03000000 0 4: data 0x02800000 0x05800000 0 # nand write 10400000 kernel1 100000 NAND write: device 0 offset 0x2c00000, size 0x100000 1048576 bytes written: OK # nboot kernel0 Loading from NAND 128MiB 3,3V 8-bit, offset 0x0 ... # nand era kernel1 NAND erase: device 0 offset 0x2c00000, size 0x400000 OK or # nand era nand0,2 NAND erase: device 0 offset 0x2c00000, size 0x400000 OK # chpart rootfs1 partition changed to nand0,3 # fsload /boot/uImage ### JFFS2 loading '/boot/uImage' to 0x10400000 ... etc... Best regards, ladis Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> CHANGELOG * Patch by Ladislav Michl, 18 Aug 2006: chpart, nboot and NAND subsystem related commands now accept also partition name to specify offset. diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index 201c3c1..90b2930 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -1300,7 +1303,7 @@ static void list_partitions(void) * Given partition identifier in form of <dev_type><dev_num>,<part_num> find * corresponding device and verify partition number. * - * @param id string describing device and partition + * @param id string describing device and partition or partition name * @param dev pointer to the requested device (output) * @param part_num verified partition number (output) * @param part pointer to requested partition (output) @@ -1309,11 +1312,23 @@ static void list_partitions(void) int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part) { + struct list_head *dentry, *pentry; u8 type, dnum, pnum; const char *p; DEBUGF("--- find_dev_and_part ---\nid = %s\n", id); + list_for_each(dentry, &devices) { + *part_num = 0; + *dev = list_entry(dentry, struct mtd_device, link); + list_for_each(pentry, &(*dev)->parts) { + *part = list_entry(pentry, struct part_info, link); + if (strcmp((*part)->name, id) == 0) + return 0; + (*part_num)++; + } + } + p = id; *dev = NULL; *part = NULL; diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 21adb1b..2c9268c 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -36,6 +36,15 @@ #endif #include <jffs2/jffs2.h> #include <nand.h> +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + +/* parition handling routines */ +int mtdparts_init(void); +int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num); +int find_dev_and_part(const char *id, struct mtd_device **dev, + u8 *part_num, struct part_info **part); +#endif + extern nand_info_t nand_info[]; /* info for NAND chips */ static int nand_dump_oob(nand_info_t *nand, ulong off) @@ -83,50 +92,66 @@ static int nand_dump(nand_info_t *nand, /* ------------------------------------------------------------------------- */ -static void -arg_off_size(int argc, char *argv[], ulong *off, ulong *size, ulong totsize) +static int str2long(char *p, ulong *num) { - *off = 0; - *size = 0; - -#if defined(CONFIG_JFFS2_NAND) && defined(CFG_JFFS_CUSTOM_PART) - if (argc >= 1 && strcmp(argv[0], "partition") == 0) { - int part_num; - struct part_info *part; - const char *partstr; + char *endptr; - if (argc >= 2) - partstr = argv[1]; - else - partstr = getenv("partition"); - - if (partstr) - part_num = (int)simple_strtoul(partstr, NULL, 10); - else - part_num = 0; + *num = simple_strtoul(p, &endptr, 16); + return (*p != '\0' && *endptr == '\0') ? 1 : 0; +} - part = jffs2_part_info(part_num); - if (part == NULL) { - printf("\nInvalid partition %d\n", part_num); - return; +static int +arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size) +{ + int idx = nand_curr_device; +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + struct mtd_device *dev; + struct part_info *part; + u8 pnum; + + if (argc >= 1 && !(str2long(argv[0], off))) { + if ((mtdparts_init() == 0) && + (find_dev_and_part(argv[0], &dev, &pnum, &part) == 0)) { + if (dev->id->type != MTD_DEV_TYPE_NAND) { + puts("not a NAND device\n"); + return 1; + } + *off = part->offset; + if (argc >= 2) { + if (!(str2long(argv[1], size))) { + printf("'%s' is not a number\n", argv[1]); + return 1; + } + if (*size > part->size) + *size = part->size; + } else + *size = part->size; + idx = dev->id->num; + *nand = nand_info[idx]; + goto out; } - *size = part->size; - *off = (ulong)part->offset; - } else + } #endif - { - if (argc >= 1) - *off = (ulong)simple_strtoul(argv[0], NULL, 16); - else - *off = 0; - if (argc >= 2) - *size = (ulong)simple_strtoul(argv[1], NULL, 16); - else - *size = totsize - *off; + if (argc >= 1) { + if (!(str2long(argv[0], off))) { + printf("'%s' is not a number\n", argv[0]); + return 1; + } + } else + *off = 0; - } + if (argc >= 2) { + if (!(str2long(argv[1], size))) { + printf("'%s' is not a number\n", argv[1]); + return 1; + } + } else + *size = nand->size - *off; +out: + printf("device %d offset 0x%x, size 0x%x ", idx, *off, *size); + return 0; } int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) @@ -176,7 +201,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, return 0; } - if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 && + if (strcmp(cmd, "bad") != 0 && strncmp(cmd, "erase", 3) != 0 && strncmp(cmd, "dump", 4) != 0 && strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0) goto usage; @@ -197,13 +222,23 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, return 0; } - if (strcmp(cmd, "erase") == 0) { - arg_off_size(argc - 2, argv + 2, &off, &size, nand->size); - if (off == 0 && size == 0) + /* + * Syntax is: + * 0 1 2 3 4 + * nand erase [clean] [off size] + */ + if (strncmp(cmd, "erase", 3) == 0) { + /* "clean" at index 2 means request to erase OOB */ + int clean = (argc > 2 && strcmp(argv[2], "clean") == 0) ? 1 : 0; + int o = clean ? 3 : 2; + puts("\nNAND erase: "); + /* skip first two or three arguments, look for offset and size */ + if (arg_off_size(argc - o, argv + o, nand, &off, &size) != 0) return 1; - - printf("\nNAND erase: device %d offset 0x%x, size 0x%x ", - nand_curr_device, off, size); + if (clean) { /* TODO */ + puts("'clean' not implemented yet\n"); + return 1; + } ret = nand_erase(nand, off, size); printf("%s\n", ret ? "ERROR" : "OK"); @@ -241,13 +276,10 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, */ addr = (ulong)simple_strtoul(argv[2], NULL, 16); - arg_off_size(argc - 3, argv + 3, &off, &size, nand->size); - if (off == 0 && size == 0) - return 1; - i = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ - printf("\nNAND %s: device %d offset %u, size %u ... ", - i ? "read" : "write", nand_curr_device, off, size); + printf("\nNAND %s: ", i ? "read" : "write"); + if (arg_off_size(argc - 3, argv + 3, nand, &off, &size) != 0) + return 1; if (i) ret = nand_read(nand, off, &size, (u_char *)addr); @@ -268,8 +300,8 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand - NAND sub-system\n", "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" - "nand read[.jffs2] - addr off size\n" - "nand write[.jffs2] - addr off size - read/write `size' bytes starting\n" + "nand read[.jffs2] - addr off|partition size\n" + "nand write[.jffs2] - addr off|partiton size - read/write `size' bytes starting\n" " at offset `off' to/from memory address `addr'\n" "nand erase [clean] [off size] - erase `size' bytes from\n" " offset `off' (entire device if not specified)\n" @@ -279,62 +311,20 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand markbad off - mark bad block at offset (UNSAFE)\n" "nand biterr off - make a bit error at offset (UNSAFE)\n"); -int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, + ulong offset, ulong addr, char *cmd) { - char *boot_device = NULL; - char *ep; - int dev; int r; - ulong addr, cnt, offset = 0; + char *ep; + ulong cnt; image_header_t *hdr; - nand_info_t *nand; - switch (argc) { - case 1: - addr = CFG_LOAD_ADDR; - boot_device = getenv("bootdevice"); - break; - case 2: - addr = simple_strtoul(argv[1], NULL, 16); - boot_device = getenv("bootdevice"); - break; - case 3: - addr = simple_strtoul(argv[1], NULL, 16); - boot_device = argv[2]; - break; - case 4: - addr = simple_strtoul(argv[1], NULL, 16); - boot_device = argv[2]; - offset = simple_strtoul(argv[3], NULL, 16); - break; - default: - printf("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS(-1); - return 1; - } - - if (!boot_device) { - puts("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS(-1); - return 1; - } - - dev = simple_strtoul(boot_device, &ep, 16); - - if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) { - printf("\n** Device %d not available\n", dev); - SHOW_BOOT_PROGRESS(-1); - return 1; - } - - nand = &nand_info[dev]; - printf("\nLoading from device %d: %s (offset 0x%lx)\n", - dev, nand->name, offset); + printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset); cnt = nand->oobblock; r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { - printf("** Read error on %d\n", dev); + puts("** Read error\n"); SHOW_BOOT_PROGRESS(-1); return 1; } @@ -353,7 +343,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int f r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { - printf("** Read error on %d\n", dev); + puts("** Read error\n"); SHOW_BOOT_PROGRESS(-1); return 1; } @@ -367,7 +357,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int f char *local_args[2]; extern int do_bootm(cmd_tbl_t *, int, int, char *[]); - local_args[0] = argv[0]; + local_args[0] = cmd; local_args[1] = NULL; printf("Automatic boot of image at addr 0x%08lx ...\n", addr); @@ -378,9 +368,81 @@ int do_nandboot(cmd_tbl_t * cmdtp, int f return 0; } -U_BOOT_CMD(nboot, 4, 1, do_nandboot, - "nboot - boot from NAND device\n", "loadAddr dev\n"); +int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char *boot_device = NULL; + int idx; + ulong addr, offset = 0; +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + struct mtd_device *dev; + struct part_info *part; + u8 pnum; + + if (argc >= 2) { + char *p = (argc == 2) ? argv[1] : argv[2]; + if (!(str2long(p, &addr)) && (mtdparts_init() == 0) && + (find_dev_and_part(p, &dev, &pnum, &part) == 0)) { + if (dev->id->type != MTD_DEV_TYPE_NAND) { + puts("Not a NAND device\n"); + return 1; + } + if (argc > 3) + goto usage; + if (argc == 3) + addr = simple_strtoul(argv[2], NULL, 16); + else + addr = CFG_LOAD_ADDR; + return nand_load_image(cmdtp, &nand_info[dev->id->num], + part->offset, addr, argv[0]); + } + } +#endif + + switch (argc) { + case 1: + addr = CFG_LOAD_ADDR; + boot_device = getenv("bootdevice"); + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = getenv("bootdevice"); + break; + case 3: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + break; + case 4: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + offset = simple_strtoul(argv[3], NULL, 16); + break; + default: +usage: + printf("Usage:\n%s\n", cmdtp->usage); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + if (!boot_device) { + puts("\n** No boot device **\n"); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + idx = simple_strtoul(boot_device, NULL, 16); + + if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) { + printf("\n** Device %d not available\n", idx); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]); +} + +U_BOOT_CMD(nboot, 4, 1, do_nandboot, + "nboot - boot from NAND device\n", + "[partition] | [[[loadAddr] dev] offset]\n"); #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/doc/README.nand b/doc/README.nand index f2d6a5b..a2d10db 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -36,14 +36,19 @@ Commands: nand device num Make device `num' the current device and print information about it. - nand erase off size - nand erase clean [off size] - Erase `size' bytes starting at offset `off'. Only complete erase - blocks can be erased. + nand erase off|partition size + nand erase clean [off|partition size] + Erase `size' bytes starting at offset `off'. Alternatively partition + name can be specified, in this case size will be eventually limited + to not exceed partition size (this behaviour applies also to read + and write commands). Only complete erase blocks can be erased. + + If `erase' is specified without an offset or size, the entire flash + is erased. If `erase' is specified with partition but without an + size, the entire partition is erased. If `clean' is specified, a JFFS2-style clean marker is written to - each block after it is erased. If `clean' is specified without an - offset or size, the entire flash is erased. + each block after it is erased. This command will not erase blocks that are marked bad. There is a debug option in cmd_nand.c to allow bad blocks to be erased. @@ -53,28 +58,28 @@ Commands: nand info Print information about all of the NAND devices found. - nand read addr ofs size + nand read addr ofs|partition size Read `size' bytes from `ofs' in NAND flash to `addr'. If a page cannot be read because it is marked bad or an uncorrectable data error is found the command stops with an error. - nand read.jffs2 addr ofs size + nand read.jffs2 addr ofs|partition size Like `read', but the data for blocks that are marked bad is read as 0xff. This gives a readable JFFS2 image that can be processed by the JFFS2 commands such as ls and fsload. - nand read.oob addr ofs size + nand read.oob addr ofs|partition size Read `size' bytes from the out-of-band data area corresponding to `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of data for one 512-byte page or 2 256-byte pages. There is no check for bad blocks or ECC errors. - nand write addr ofs size + nand write addr ofs|partition size Write `size' bytes from `addr' to `ofs' in NAND flash. If a page cannot be written because it is marked bad or the write fails the command stops with an error. - nand write.jffs2 addr ofs size + nand write.jffs2 addr ofs|partition size Like `write', but blocks that are marked bad are skipped and the is written to the next block instead. This allows writing writing a JFFS2 image, as long as the image is short enough to fit even @@ -82,7 +87,7 @@ Commands: produced by mkfs.jffs2 should work well, but loading an image copied from another flash is going to be trouble if there are any bad blocks. - nand write.oob addr ofs size + nand write.oob addr ofs|partition size Write `size' bytes from `addr' to the out-of-band data area corresponding to `ofs' in NAND flash. This is limited to the 16 bytes of data for one 512-byte page or 2 256-byte pages. There is no check

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Re: [U-Boot-Users] ixdp 465
by Wolfgang Denk 23 Oct '06

23 Oct '06

Dear Michael, in message <453877C8.10103(a)evidence.eu.com> you wrote: > > > >Ummm... which patch are you referring to? Areghhh. Please NEVER send patches to my address. Always send these through the mailing list only, so others can comment on these, too. > diff -raN u-boot-1.1.4.orig/Makefile u-boot-1.1.4/Makefile > 1614a1615,1617 > > ixdp465_config : unconfig > > @./mkconfig $(@:_config=) arm ixp ixdp465 > > Such a plain diff output is not a patch, it cannot be applied. Please make sure to read the README, section Submitting Patches. You MUST use the correct options when creating the patch. Also mind the size limitations on the mailing list. And make sure to stick to the required coding style, your code contains lots of problems (indentation by spaces instead of TABs, C++ comments, trailing white space, etc.). Also never add change log entires to any files. We use git for this purpose. Make sure your code does not contain dead code (#if 0 etc.). Please cleanup and resubmit. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de I'm a programmer: I don't buy software, I write it. -- Tom Christiansen

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