September 2005 - U-Boot

[U-Boot-Users] [PATCH] cramfs support for m68k
by Zachary Landau 25 Sep '05

25 Sep '05

Hello, The attached patch provides a couple simple changes necessary to get CRAMFS support working on the M68K. -- Zachary P. Landau <kapheine(a)gmail.com>

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[U-Boot-Users] [PATCH]: Fix EP8260 H2 flash timeouts
by Jeff Angielski 25 Sep '05

25 Sep '05

Very small patch to ep8260.h to fix the flash timeouts and to improve the clock accuracy for faster UARTs by reducing the BRG divisor in the SCCR. CHANGELOG: * Patch by Jeff Angielski 21 Feb 2005 Fix flash write/erase timeouts. Improve clock resolution for faster UARTs. Jeff Angielski

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[U-Boot-Users] [patch] MIPS: AMD Alchemy au1x00 ethernet initialization in cpu/mips/au1x00_eth.c
by Joseph Chiu 25 Sep '05

25 Sep '05

Hi, On u-boot bootloader 1.1.2 on AMD Alchemy Au1x00: The au1x00_mac.c assumes that ethernet transmit always starts with transmit buffer 0. This is not necessarily true (in the event of a warm reboot). This little patch fixes that and prevents (reduces?) transmit timeouts that you might see when you're repeatedly warm-rebooting your board during development. Cheers, Joseph Chiu www.omnilux.net LC_ALL=C TZ=UTC0 diff -Naur u-boot-1.1.2.orig/cpu/mips/au1x00_eth.c u-boot-1.1.2.new/cpu/mips/au1x00_eth.c --- u-boot-1.1.2.orig/cpu/mips/au1x00_eth.c Fri Jan 2 15:01:32 2004 +++ u-boot-1.1.2.new/cpu/mips/au1x00_eth.c Wed Feb 16 02:10:27 2005 @@ -167,9 +167,6 @@ (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); int i; - next_tx = 0; - next_rx = 0; - /* We have to enable clocks before releasing reset */ *macen = MAC_EN_CLOCK_ENABLE; udelay(10); @@ -186,6 +183,9 @@ fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE; } + next_tx = (fifo_tx[0].addr & 0x0c )>>2; + next_rx = (fifo_rx[0].addr & 0x0c )>>2; + /* Put mac addr in little endian */ #define ea eth_get_dev()->enetaddr *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;

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[U-Boot-Users] [patch] au1x00_serial.c fix baud rate computation
by Andrew Dyer 25 Sep '05

25 Sep '05

CHANGELOG: * Patch by Andrew Dyer, 15 February 2005: fix au1x00_serial to remove hardcoded cpu clock divisor and use register instead. change baud rate calculation to round up instead of truncate in cases where fractional part would have been > 0.5 -- Hardware, n.: The parts of a computer system that can be kicked.

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[U-Boot-Users] [PATCH] Spartan3 family support
by Kurt Stremerch 25 Sep '05

25 Sep '05

Hi all. This small patch, against current cvs, adds Xilinx Spartan3 support. Only the bitstream size differs from the Spartan2 family, the configuration method stays the same. Regards Kurt CHANGELOG: * Patch by Kurt Stremerch, 14 February 2005: Add Xilinx Spartan3 family fpga support

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[U-Boot-Users] [PATCH] Use info->reset_cmd instead of FLASH_CMD_RESET
by Zachary Landau 25 Sep '05

25 Sep '05

Hello, This patch makes cfi_flash.c use info->cmd_reset. It was being set by flash_get_size() but not being used, which kept the Flash on my board from properly being reset. It looks like there are a lot of switch cases for different flash types that could probably probably be removed by setting up some function pointers, but that is a project for another time. -- Zachary P. Landau <kapheine(a)gmail.com>

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[U-Boot-Users] [Patch] MPC8272ADS PCI bridge support
by Vitaly Bordug 25 Sep '05

25 Sep '05

Hi, Attached a patch which adds support of the MPC8272ADS PCI bridge. This stuff is based on mpc8266ads, and has been tested with a Freescale MPC8272ADS board. Also attached a patch to README file which describes CFG_PCI_INT config entry (used in the 8266 but not documented yet). Patch made against CVS checkout of Feb 9 2005 CHANGELOG: * Patch by Vitaly Bordug, Feb 9 2005 Added support for PCI bridge on MPC8272ADS -- Sincerely, Vitaly

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[U-Boot-Users] [Patch] ARM Integrator/AP multicore patch
by jean-paul.saman＠philips.com 25 Sep '05

25 Sep '05

The patch is created against the multicore patch from Peter Pearse 02-02-2005 CHANGELOG: * Patch by Jean-Paul Saman, 8 Feb 2005 - Patch based on multicore patch from Peter Pearse 02-02-2005 - multicore CM9XX support for ARM Integrator AP defining CONFIG_CM_INIT and CONFIG_CM_REMAP allows to booting u-boot directly from flash Kind greetings, Jean-Paul Saman Philips Semiconductors CTO/RTG Philips HighTech Campus, building WDB 3.29 Professor van den Holstlaan 4 5655 AA Eindhoven tel: +31 (0)40 27 45131

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[U-Boot-Users] [patch] fix lib_generic version of strswab()
by Andrew Dyer 25 Sep '05

25 Sep '05

This patch changes the behavior of strswab() to end the byte swapping when either of the two candidate bytes is null. The old behavior was to only abort when the second byte was null. It looks like this is only used for little endian machines running with CONFIG_IDE. I noticed this because the ide serial number was not printing out - the reason was strswab() was running past the end of the previous string in memory and swapping a null into the first byte of my serial number string. -- Hardware, n.: The parts of a computer system that can be kicked.

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[U-Boot-Users] Patch: Typos in include/ppc440.h
by Andrew E Mileski 25 Sep '05

25 Sep '05

This is in CVS as well as u-boot-1.1.2.tar.bz2 and as far back as at least u-boot-0.2.0.tar.bz2 File: include/ppc440.h Line:235 Context: #define pbear 0x20 /* periph bus error addr reg */ #define pbesr 0x21 /* periph bus error status reg */ #define xbcfg 0x23 /* external bus configuration reg */ #define xbcid 0x23 /* external bus core id reg */ ^^^^ According to the 440GX user manual (mine's dated Nov 21, 2003) table 4-13 on page 186, EBC0_CID the "EBCO Peripheral Core ID Register" is located at offset 0x24. This register is not currently referenced by any code in the u-boot-1.1.2.tar.bz2 release, which explains why it has survied so long. Also note that the header comment for this section has a typo, which is also corrected in the attached patch. -- Andrew E. Mileski diff -urN include/ppc440.h.orig include/ppc440.h --- include/ppc440.h.orig 2005-02-04 15:55:53.000000000 -0500 +++ include/ppc440.h 2005-02-04 16:13:20.000000000 -0500 @@ -207,7 +207,7 @@ #define mem_eccesr 0x0098 /* ECC error status */ /*----------------------------------------------------------------------------- - | Extrnal Bus Controller + | External Bus Controller +----------------------------------------------------------------------------*/ #define EBC_DCR_BASE 0x12 #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ @@ -232,7 +232,7 @@ #define pbear 0x20 /* periph bus error addr reg */ #define pbesr 0x21 /* periph bus error status reg */ #define xbcfg 0x23 /* external bus configuration reg */ -#define xbcid 0x23 /* external bus core id reg */ +#define xbcid 0x24 /* external bus core id reg */ /*----------------------------------------------------------------------------- | Internal SRAM

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