February 2005 - U-Boot

[U-Boot-Users] PATCH: m68k/mcf5282 udelay support
by Mathias Küster 04 Apr '05

04 Apr '05

Hello, this patch add udelay support for the mcf5282 cpu. Best Regards, Mathias --- time.c.orig 2004-06-09 17:24:19.000000000 +0200 +++ time.c 2004-11-07 09:51:07.000000000 +0100 @@ -126,6 +126,28 @@ void udelay(unsigned long usec) { + volatile unsigned short *timerp; + uint tmp; + + timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3); + + while (usec > 0) { + if (usec > 65000) + tmp = 65000; + else + tmp = usec; + usec = usec - tmp; + + /* Set up TIMER 3 as timebase clock */ + timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW; + timerp[MCFTIMER_PMR] = 0; + /* set period to 1 us */ + timerp[MCFTIMER_PCSR] = + (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; + + timerp[MCFTIMER_PMR] = tmp; + while (timerp[MCFTIMER_PCNTR] > 0); + } } void timer_init (void)

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[U-Boot-Users] PATCH: CSB472 board incorrect CPLD base address
by Tolunay Orkun 04 Apr '05

04 Apr '05

This patch fixes the incorrect chip select base address programming for on board Xilinx CPLD due to incorrect value documented in Table 7 of Cogent CSB472 H/W Reference Manual - 4/8/03. The value was in conflict with references in Table 1 and Table 2 in the very same manual. CHANGELOG: * Patch by Tolunay Orkun, 16 November 2004 - fix incorrect onboard Xilinx CPLD base address

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[U-Boot-Users] Patch: Add support for A&M Rattler boards
by Yuli Barcohen 04 Apr '05

04 Apr '05

The attached patch adds support for Analogue & Micro Rattler boards. It was tested on Rattler8248. CHANGELOG: Add support for Analogue & Micro Rattler boards. Tested on Rattler8248. -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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[U-Boot-Users] common/lcd.c patch
by Andre Renaud 04 Apr '05

04 Apr '05

There is a minor bug in common/lcd.c: if you do not define CONFIG_MPC823, it does not include watchdog.h, but WATCHDOG_RESET is used several times in the code outside of #ifdef blocks. Moving the #include statement out of the #ifdef block fixes it. I've attached what I think it the appropriate patch. Andre Renaud

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[U-Boot-Users] [PATCH] MPC8245 vs XPC8245
by Marc Leeman 04 Apr '05

04 Apr '05

-- ash nazg durbatulûk, ash nazg gimbatul, ash nazg thrakatulûk agh burzum-ishi krimpatul

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[U-Boot-Users] [PATCH] 16-bit NAND support
by Zhang, Jian 03 Apr '05

03 Apr '05

Hi, This is a patch to add 16-bit NAND support to u-boot. It doesn't change any existing 8-bit NAND code so it shouldn't affect any existing boards that have 8-bit chips. I tested it in 2 TI OMAP boards, one using software to access chip, the other one using hardware NAND controller. Regards, Jian

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[U-Boot-Users] PATCH: Nios imi and mkimage
by Scott McNutt 03 Apr '05

03 Apr '05

Fixes: -imi "Unknown architecture" for Nios/Nios-II -mkimage unrecognized architecture. Regards, --Scott diff -Naurbx CVS u-boot-2004-10-20/common/cmd_bootm.c u-boot-work/common/cmd_bootm.c --- u-boot-2004-10-20/common/cmd_bootm.c 2004-10-10 17:27:32.000000000 -0400 +++ u-boot-work/common/cmd_bootm.c 2004-11-01 19:14:59.000000000 -0500 @@ -1189,7 +1189,9 @@ case IH_CPU_SPARC: arch = "SPARC"; break; case IH_CPU_SPARC64: arch = "SPARC 64 Bit"; break; case IH_CPU_M68K: arch = "M68K"; break; + case IH_CPU_NIOS: arch = "Nios"; break; case IH_CPU_MICROBLAZE: arch = "Microblaze"; break; + case IH_CPU_NIOS2: arch = "Nios-II"; break; default: arch = "Unknown Architecture"; break; } diff -Naurbx CVS u-boot-2004-10-20/tools/mkimage.c u-boot-work/tools/mkimage.c --- u-boot-2004-10-20/tools/mkimage.c 2004-07-10 18:36:01.000000000 -0400 +++ u-boot-work/tools/mkimage.c 2004-11-01 19:18:06.000000000 -0500 @@ -86,6 +86,8 @@ { IH_CPU_MICROBLAZE, "microblaze", "MicroBlaze", }, { IH_CPU_MIPS, "mips", "MIPS", }, { IH_CPU_MIPS64, "mips64", "MIPS 64 Bit", }, + { IH_CPU_NIOS, "nios", "Nios", }, + { IH_CPU_NIOS2, "nios2", "Nios-II", }, { IH_CPU_PPC, "ppc", "PowerPC", }, { IH_CPU_S390, "s390", "IBM S390", }, { IH_CPU_SH, "sh", "SuperH", },

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[U-Boot-Users] Re: u-boot error message
by Detlev Zundel 03 Apr '05

03 Apr '05

Hello Bruce, > I used u-boot-1.1.1 to boot linux.My target board is ALTERA DK1C20 and cpu is > nios.I used tools/mkimage to encapsulate a linux kernel image with header > information.But it display some error messages,it like that: > > > > [root@a901 u-boot-20040316cvs]# tools/mkimage -n 'linux kernel' \ > >> -A nios -O linux -T kernel -C none -a 1010000 -e 1010000 \ > >> -d /opt/cdk4nios/src/u-boot-20040316cvs/linux.bin uimage > > > > Invalid CPU Type - valid names are: alpha, arm, x86, ia64, mips, mips64, ppc, > s3 90, sh, sparc, sparc64, m68k > > > > Because my cpu is nios,so my linux kernel can't boot.Can you tell me what can i > do? > > Ps:my name is Bruce Hm, I haven't worked with a NIOS system, but obviously the port forgot to include support in the mkimage tool. cmd_bootm.c tests for those values so that might be your problem. Try the attached patch and maybe some NIOS people on this mailing list can speak up. Cheers Detlev PS: Mail F'up-to set to u-boot-users(a)lists.sourceforge.net -- (define Y (lambda (f) ((lambda (g) (f (lambda (x) ((g g) x)))) (lambda (g) (f (lambda (x) ((g g) x)))))))

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[U-Boot-Users] Missing 440GX SDRAM Controller reset?
by David Adair 03 Apr '05

03 Apr '05

I have this same problem described a few months ago and corrected by adding the SDRAM controller reset present in the PIBS code but missing in rev 1.1.1 of u-boot e.g: mtsdr(sdr_srst, 0x00200000); mtsdr(sdr_srst, 0x00000000); Was this left out on purpose? It seems like if the BDI configuration can cause a hang then a warm-reboot is going to be problematic too?? > Re: problems with BDI2000 / u-boot / Linux on IBM 440GX Ocotea reference board > > The first problem is if I try to run u-boot from flash with a BDI2000 > > connected (i.e. do "reset" and "go" commands), then u-boot starts > > running but hangs in the SDRAM init. Specifically, it hangs waiting > > for the MRS Command Complete status bit to be set. > > IIRC I ran into the same thing, all I needed to do was remove the sdram > configuration from the config for the BDI.

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[U-Boot-Users] PATCH: Removing all these "extern void reset_cpu()"
by Steven Scholz 03 Apr '05

03 Apr '05

Hi there, please consider the patch attached. CHANGELOG: * Patch by Steven Scholz, 25 Oct 2004: - Replace all "extern void reset_cpu()" with one occurence of "void reset_cpu (ulong addr)" in include/common.h -- Steven Scholz Index: cpu/arm720t/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm720t/cpu.c,v retrieving revision 1.6 diff -p -u -r1.6 cpu.c --- cpu/arm720t/cpu.c 1 Aug 2004 22:48:19 -0000 1.6 +++ cpu/arm720t/cpu.c 25 Oct 2004 14:03:13 -0000 @@ -84,8 +84,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm720t/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm720t/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/arm720t/interrupts.c 11 Jul 2004 22:19:27 -0000 1.6 +++ cpu/arm720t/interrupts.c 25 Oct 2004 14:03:13 -0000 @@ -31,8 +31,6 @@ #include <asm/proc-armv/ptrace.h> #include <asm/hardware.h> -extern void reset_cpu(ulong addr); - #ifndef CONFIG_NETARM /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff Index: cpu/arm920t/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/arm920t/cpu.c 8 Feb 2004 19:38:43 -0000 1.3 +++ cpu/arm920t/cpu.c 25 Oct 2004 14:03:13 -0000 @@ -124,8 +124,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm920t/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/arm920t/interrupts.c 1 Aug 2004 22:48:19 -0000 1.6 +++ cpu/arm920t/interrupts.c 25 Oct 2004 14:03:13 -0000 @@ -34,8 +34,6 @@ #include <arm920t.h> #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ interrupts */ void enable_interrupts (void) Index: cpu/arm920t/s3c24x0/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/s3c24x0/interrupts.c,v retrieving revision 1.1 diff -p -u -r1.1 interrupts.c --- cpu/arm920t/s3c24x0/interrupts.c 9 Oct 2004 22:21:30 -0000 1.1 +++ cpu/arm920t/s3c24x0/interrupts.c 25 Oct 2004 14:03:13 -0000 @@ -39,7 +39,6 @@ #include <s3c2410.h> #endif -extern void reset_cpu(ulong addr); int timer_load_val = 0; /* macro to read the 16 bit timer */ Index: cpu/arm925t/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm925t/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/arm925t/cpu.c 8 Feb 2004 19:38:43 -0000 1.3 +++ cpu/arm925t/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -125,8 +125,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm925t/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm925t/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/arm925t/interrupts.c 25 Apr 2004 14:37:30 -0000 1.6 +++ cpu/arm925t/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -38,7 +38,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ Index: cpu/arm926ejs/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm926ejs/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/arm926ejs/cpu.c 8 Feb 2004 19:38:43 -0000 1.3 +++ cpu/arm926ejs/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -125,8 +125,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm926ejs/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm926ejs/interrupts.c,v retrieving revision 1.7 diff -p -u -r1.7 interrupts.c --- cpu/arm926ejs/interrupts.c 23 Mar 2004 21:43:08 -0000 1.7 +++ cpu/arm926ejs/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -40,7 +40,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ Index: cpu/at91rm9200/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/at91rm9200/cpu.c,v retrieving revision 1.9 diff -p -u -r1.9 cpu.c --- cpu/at91rm9200/cpu.c 10 Oct 2004 20:23:59 -0000 1.9 +++ cpu/at91rm9200/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -115,8 +115,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag { #ifdef CFG_SOFT_RESET - extern void reset_cpu(ulong addr); - disable_interrupts(); reset_cpu(0); #else Index: cpu/at91rm9200/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/at91rm9200/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/at91rm9200/interrupts.c 11 Oct 2004 22:25:50 -0000 1.6 +++ cpu/at91rm9200/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -35,8 +35,6 @@ #include <asm/arch/hardware.h> #include <asm/proc/ptrace.h> -extern void reset_cpu(ulong addr); - /* the number of clocks per CFG_HZ */ #define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ) Index: cpu/i386/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/i386/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/i386/cpu.c 27 Jun 2003 21:32:33 -0000 1.3 +++ cpu/i386/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -50,8 +50,6 @@ int cpu_init(void) int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu(ulong addr); - printf ("resetting ...\n"); udelay(50000); /* wait 50 ms */ disable_interrupts(); Index: cpu/ixp/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/ixp/cpu.c,v retrieving revision 1.2 diff -p -u -r1.2 cpu.c --- cpu/ixp/cpu.c 8 Feb 2004 19:38:44 -0000 1.2 +++ cpu/ixp/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -76,8 +76,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - printf ("resetting ...\n"); udelay (50000); /* wait 50 ms */ Index: cpu/ixp/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/ixp/interrupts.c,v retrieving revision 1.2 diff -p -u -r1.2 interrupts.c --- cpu/ixp/interrupts.c 15 Oct 2003 23:53:51 -0000 1.2 +++ cpu/ixp/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -30,8 +30,6 @@ #include <common.h> #include <asm/arch/ixp425.h> -extern void reset_cpu (ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ void enable_interrupts (void) Index: cpu/lh7a40x/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/lh7a40x/cpu.c,v retrieving revision 1.1 diff -p -u -r1.1 cpu.c --- cpu/lh7a40x/cpu.c 9 Jun 2004 13:37:53 -0000 1.1 +++ cpu/lh7a40x/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -124,8 +124,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/lh7a40x/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/lh7a40x/interrupts.c,v retrieving revision 1.2 diff -p -u -r1.2 interrupts.c --- cpu/lh7a40x/interrupts.c 10 Jun 2004 21:55:34 -0000 1.2 +++ cpu/lh7a40x/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -35,7 +35,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); static ulong timer_load_val = 0; /* macro to read the 16 bit timer */ Index: cpu/pxa/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/pxa/cpu.c,v retrieving revision 1.5 diff -p -u -r1.5 cpu.c --- cpu/pxa/cpu.c 8 Feb 2004 19:38:44 -0000 1.5 +++ cpu/pxa/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -74,8 +74,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - printf ("resetting ...\n"); udelay (50000); /* wait 50 ms */ Index: cpu/pxa/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/pxa/interrupts.c,v retrieving revision 1.4 diff -p -u -r1.4 interrupts.c --- cpu/pxa/interrupts.c 9 Jun 2004 13:37:53 -0000 1.4 +++ cpu/pxa/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -29,8 +29,6 @@ #include <common.h> #include <asm/arch/pxa-regs.h> -extern void reset_cpu (ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ void enable_interrupts (void) Index: cpu/s3c44b0/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/s3c44b0/cpu.c,v retrieving revision 1.2 diff -p -u -r1.2 cpu.c --- cpu/s3c44b0/cpu.c 17 Oct 2004 21:12:11 -0000 1.2 +++ cpu/s3c44b0/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -86,8 +86,6 @@ void reset_cpu (ulong addr) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); Index: cpu/s3c44b0/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/s3c44b0/interrupts.c,v retrieving revision 1.1 diff -p -u -r1.1 interrupts.c --- cpu/s3c44b0/interrupts.c 24 Feb 2004 00:16:44 -0000 1.1 +++ cpu/s3c44b0/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -29,8 +29,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); - /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff Index: cpu/sa1100/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/sa1100/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/sa1100/cpu.c 8 Feb 2004 19:38:44 -0000 1.3 +++ cpu/sa1100/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -73,8 +73,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - printf ("resetting ...\n"); udelay (50000); /* wait 50 ms */ Index: cpu/sa1100/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/sa1100/interrupts.c,v retrieving revision 1.3 diff -p -u -r1.3 interrupts.c --- cpu/sa1100/interrupts.c 14 Mar 2004 15:20:56 -0000 1.3 +++ cpu/sa1100/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -31,8 +31,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu (ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ void enable_interrupts (void) Index: include/common.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/common.h,v retrieving revision 1.46 diff -p -u -r1.46 common.h --- include/common.h 10 Oct 2004 18:41:14 -0000 1.46 +++ include/common.h 25 Oct 2004 14:03:15 -0000 @@ -378,6 +378,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); +void reset_cpu (ulong addr); /* $(CPU)/serial.c */ int serial_init (void);

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