October 2005 - U-Boot

[U-Boot-Users] cfi_flash.c patch
by richard＠uclinux.net 28 Feb '06

28 Feb '06

Afternoon... Adding 2 spaces in cfi_flash.c makes the output of "flinfo" much more readable if there are protected and unprotected sectors: rick ---------------------------------------------------------------------------- CHANGELOG: * Patch by Richard Klingler, 09 Apr 2005: correct column layout of flinfo output. --- u-boot.orig/drivers/cfi_flash.c 2005-01-09 19:12:33.000000000 +0200 +++ u-boot/drivers/cfi_flash.c 2005-04-09 16:35:04.000000000 +0300 @@ -483,7 +483,7 @@ void flash_print_info (flash_info_t * in if ((i % 5) == 0) printf ("\n "); printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO) " : " "); + info->start[i], info->protect[i] ? " (RO) " : " "); #endif } putc ('\n');

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[U-Boot-Users] PATCH: minor bugs fix in cfi_driver.c
by Pierre AUBERT 28 Feb '06

28 Feb '06

Please find attached a little patch against current CVS. CHANGELOG: * Patch by Pierre Aubert 09 Dec 2004 - Fix flash information strings alignement in cfi_driver.c - Fix monitor size for flash protection in cfi_driver.c Best regards diff -pur u-boot/drivers/cfi_flash.c u-boot-paub/drivers/cfi_flash.c --- u-boot/drivers/cfi_flash.c 2004-10-11 01:27:35.000000000 +0200 +++ u-boot-paub/drivers/cfi_flash.c 2004-12-09 10:11:31.000000000 +0100 @@ -334,7 +334,7 @@ unsigned long flash_init (void) #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif @@ -477,7 +477,7 @@ void flash_print_info (flash_info_t * in if ((i % 5) == 0) printf ("\n "); printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO) " : " "); + info->start[i], info->protect[i] ? " (RO)" : " "); #endif } putc ('\n');

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[U-Boot-Users] [PATCH] Two System ACE CF fixes
by Peter Ryser 25 Jan '06

25 Jan '06

Attached a patch that adds support for the 16-bit wide bus of System ACE CF besides the existing support for the 8-bit wide bus. The patch also sets the FORCECFGMODE bit in the control register when the System ACE CF configuration controller is reset before reading a sector. Without this bit set System ACE CF reconfigures an FPGA if the CFGMODE pin is active whenever a sector is read. The third hunk fixes a typo. - Peter --- u-boot.orig/common/cmd_ace.c 2005-09-22 23:53:00.000000000 -0700 +++ u-boot/common/cmd_ace.c 2005-09-26 07:40:41.000000000 -0700 @@ -22,8 +22,9 @@ /* * The Xilinx SystemACE chip support is activated by defining * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE - * to set the base address of the device. This code currently - * assumes that the chip is connected via a byte-wide bus. + * to set the base address of the device. CFG_SYSTEMACE_WIDTH + * selects the bus width the chip is connected with. Valid + * settings are 8 or 16. * * The CONFIG_SYSTEMACE also adds to fat support the device class * "ace" that allows the user to execute "fatls ace 0" and the @@ -137,6 +138,11 @@ block_dev_desc_t * systemace_get_dev(in systemace_dev.removable = 1; systemace_dev.block_read = systemace_read; + if(CFG_SYSTEMACE_WIDTH == 8) + ace_writew(0, 0); + else + ace_writew(1, 0); + init_part(&systemace_dev); } @@ -227,7 +233,7 @@ static unsigned long systemace_read(int /* Reset the configruation controller */ val = ace_readw(0x18); - val|=0x0080; + val|=0x0088; ace_writew(val, 0x18); retry = trans * 16; @@ -249,7 +255,7 @@ static unsigned long systemace_read(int retry -= 1; } - /* Clear the configruation controller reset */ + /* Clear the configuration controller reset */ val = ace_readw(0x18); val&=~0x0080; ace_writew(val, 0x18); * Add System ACE CF support for 16-bit bus width Add fix to ignore CFGMODE pin when resetting the System ACE CF configuration controller to avoid reconfiguration of FPGAs when reading sectors. Patch by Peter Ryser, 26 Sep 2005

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[U-Boot-Users] EP852 : Kernel not booting ( Hangs after uncompressing)
by gautam borad 20 Jan '06

20 Jan '06

Hi, I'm trying to port u-boot-1.1.3 to EP852 board with mpc852T processor.The kernel im using is linuxppc 2.4.21. The board is working fine with u-boot , the problem is that kernel is not starting. I've made sure that the bd_info structure is same in kernel and u-boot. The clocks_in_mhz variable is not set and the IMMR value in kernel and u-boot matches. I run the test_burst program in u-boot and it worked fine.( so no prob with RAM) What else am i doing wrong?? The dump is : U-Boot 1.1.3 (Oct 28 2005 - 12:54:07) EP852 CPU: MPC852TxxZPnn at 50 MHz [25.0...125.0 MHz] 4 kB I-Cache 4 kB D-Cache FEC present Board: EP852 (Rev. e4). CPLD Rev: 00 DIP Switch: 1111 DRAM: 16 MB Top of RAM usable for U-Boot at: 01000000 Reserving 354k for U-Boot at: 00fa7000 Reserving 128k for malloc() at: 00f87000 Reserving 60 Bytes for Board Info at: 00f86fc4 Reserving 56 Bytes for Global Data at: 00f86f8c Stack Pointer at: 00f86f68 New Stack Pointer is: 00f86f68 Now running in RAM - U-Boot at: 00fa7000 FLASH: Flash addr:ff800000 AMD_ID_LV320B selected. before print_size 8 MB In: serial Out: serial Err: serial U-Boot relocated to 00fa7000 Net: FEC ETHERNET ### main_loop entered: bootdelay=8 ### main_loop: bootcmd="<UNDEFINED>" => printenv bootargs bootargs=console=ttyS0,9600 root=/dev/ram => tftp 0x00200000 pImage Using FEC ETHERNET device TFTP from server 10.129.87.5; our IP address is 10.129.87.250 Filename 'pImage'. Load address: 0x200000 Loading: ################################################################# ########################################################### done Bytes transferred = 631143 (9a167 hex) => bootm 0x00200000 ## Booting image at 00200000 ... Image Name: Linux-2.4.21 Created: 2005-10-27 13:15:01 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 631079 Bytes = 616.3 kB Load Address: 00100000 Entry Point: 00100000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK before do_bootm_linux() argv = 16722772 addr = 16282928 ## Current stack ends at 0x00F86CA8 => set upper limit to 0x00800000 ## cmdline at 0x007FFF00 ... 0x007FFF20 No initrd ## Transferring control to Linux (at address 00100000) ... bi_memstart = 0 bi_memsize = 16777216 bi_flashstart = 4286578688 bi_flashsize = 8388608 bi_flashoffset = 343040 bi_sramstart = 0 bi_sramsize = 0 bi_immr_base = 4196401152 bi_bootflags = 1 bi_ip_addr = 176248826 bi_enetaddr[6] = bi_ethspeed = 114 bi_intfreq = 50000000 bi_busfreq = 50000000 bi_baudrate = 38400 // see the problem below The image was created with the following in arc/ppc/boot/Makefile : $(MKIMAGE) -A ppc -O linux -T kernel -C gzip -a 0x00100000 -e 0x00100000 \ -n 'Linux-$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)' \ -d $< images/vmlinux.PPCBoot ln -sf vmlinux.PPCBoot images/pImage The same kernel was working fine before with the epbootloader. the partitions i made in kernel MTD are: ff80_0000 ------- ff82_0000 -> boot ff82_0000 ------- ff8c_0000 -> zImage ff8c_0000 ------- ff2c_0000 -> ramdisk ff2c_0000 ------- ffff_ffff -> UserFS (JFFS2) Some of the #defines in EP852 configs are : #define CFG_SDRAM_SIZE (16 * MB) #define CFG_FLASH_BASE 0xFF800000 #define CFG_FLASH_SIZE (8 * MB) #define CFG_BSCR_BASE 0xFA400000 #define CFG_IMMR 0xFA200000 #define CFG_JFFS2_FIRST_SECTOR 56 what should i give here? #define CFG_PRELIM_OR_AM 0xFF800000 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_BR0_PRELIM 0xFF800001 #define CFG_OR1_PRELIM 0xFF000600 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V ) #define CFG_BR3_PRELIM 0xFA400001 /* BCSR */ #define CFG_OR3_PRELIM 0xFF7F8970 #define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ #define CFG_OR4_PRELIM 0xFFF80970 There is other minor(??) problem. When i set the value of CFG_SCCR to SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | SCCR_DFALCD00 u-boot works at CONFIG_BAUDRATE / 4 speed i.e if CONFIG_BAUDRATE = 9600 i've to set minicom/kermit to 2400 . Now when i set CFG_SCCR to 0x03020800 ( the value given by embedded planet config file) the baud rate works fine but the FEC doesnt work properly. It works __VERY__ slowly, i get errors in fec_recv() ( enabling ET_DEBUG) How do I make both ( FEC and baudrate ) work fine and also is this related to kernel not booting? Thanks in advance. ----------- We would change the world..... But GOD wont give the source code.

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[U-Boot-Users] [PATCH]Fix cc-option macro in config.mk
by Paolo Broggini 21 Dec '05

21 Dec '05

The following patch fix the compilation problem discussed in thread "Problem building U-Boot for ARM target" Best regards -P.Broggini Signed-off-by: Paolo Broggini <pbroggini(a)softool.ch> CHANGELOG: Fix cc-option macro in config.mk, $(CFLAGS) dropped. Patch by Paolo Broggini, 12 Oct 2005 diff --git a/config.mk b/config.mk --- a/config.mk +++ b/config.mk @@ -90,7 +90,7 @@ HOSTSTRIP = strip # Option checker (courtesy linux kernel) to ensure # only supported compiler options are used # -cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \ +cc-option = $(shell if $(CC) $(1) -S -o /dev/null -xc /dev/null \ > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;) #

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[U-Boot-Users] 83xx TSEC
by David Updegraff 02 Dec '05

02 Dec '05

Hi. Anyone know of any registers to look at in the TSEC stuff that might tell a guy why a frame is not moving? Our PHY looks fine; 'mii dump' is fine, link up, etc. but in tsec_send() the buffer of a ping is loaded up, and simply never goes anywhere. ->tstat remains clear (no halt bit), but rtx.txbd[txIdx].status never changes from assigned value. Stats claim no frames; which is correct. I need some help in understanding why TSEC feels it cannot feed anything out the inerface. Thanx. -dbu.

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[U-Boot-Users] MIPS LE build patch
by Matej Kupljen 17 Nov '05

17 Nov '05

Hi Wolfgang, You did not say anything about the new config.mk for the MIPS target which supports building BE and LE u-boot. This is the message: http://sourceforge.net/mailarchive/message.php?msg_id=12736269 What about the patch that can resolve problems with the binutils, so there is no need to patch the binutils. See: http://sourceforge.net/mailarchive/message.php?msg_id=10690757 BR, Matej

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[U-Boot-Users] [PATCH] Command history and Command buffer editing
by J Mac 17 Nov '05

17 Nov '05

I made this patch using 'diff' on two source trees; I got the original copies of the files from the gitweb interface at source.denx.net. I used the 'diff -purN OLD NEW' command as described in README to generate the patch. All code changes are local to common/main.c Define CONFIG_COMMAND_HISTORY and/or CONFIG_COMMAND_EDIT to enable the behaviour(s). Please let me know if there is something I need to do to make the patch acceptable. * Patch by James MacAulay Sept 27, 2005 - Add a configuration option CONFIG_COMMAND_HISTORY to implement command history. Uses up and down arrow keys to scroll through history. Other options are described in README. - Add a configuration option CONFIG_COMMAND_EDIT to implement command buffer editing. Uses ^A, ^E, left and right arrow keys to move through command buffer. Other options are described in README.

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[U-Boot-Users] NAND flash support
by Terence Soh 02 Nov '05

02 Nov '05

Hi, Correct me if I'm wrong but u-boot only support 512 byte page size nand flash components. Is there going to be any nand flash driver support for 2048 bytes (8-bit data bus) page size components? Thanks, Terence.

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[U-Boot-Users] [PATCH] Add RealView Emulation BaseBoard support.
by Peter Pearse 31 Oct '05

31 Oct '05

The attached gzipped patch was made against the U-Boot GIT head of Oct 31 2005. It is my patch number 013. The patch is independent of patches 009 & 010, but dependent on patch 011 & 012 The patch adds support for the new RealView Emulation BaseBoard series of boards. CHANGELOG: Add RealView Emulation BaseBoard. Patch by Peter Pearse, 31st Oct 2005

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[U-Boot-Users] [PATCH] Use Versatile base board facilities.
by Peter Pearse 31 Oct '05

31 Oct '05

The attached gzipped patch was made against the U-Boot GIT head of Oct 31 2005. It is my patch number 011. The patch is independent of patches 009 & 010. The patch updates the Versatile board code to use the base board facilities, rather than the 926EJ-S core, for timing & board reset. CHANGELOG: Use Versatile base board facilities. Patch by Peter Pearse, 31st Oct 2005

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[U-Boot-Users] [PATCH] Document new Integrator/CP targets
by Peter Pearse 31 Oct '05

31 Oct '05

The attached gzipped patch was made against the U-Boot GIT head of Oct 31 2005. It is my patch number 010. The patch updates the README-integrator to document the target names, changed in my patch 009. CHANGELOG: Update README-integrator with new target names. Patch by Peter Pearse, 31st Oct 2005

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[U-Boot-Users] has someone run u-boot in mipssim?
by zhuzhenhua 29 Oct '05

29 Oct '05

because our soc is not available now, i want to run u-boot in mipssim to verify my modification on cpu/start.S and board/xxx/lowlevel_init.S. but the u-boot compiled by eldk seems to run not correctly in mipssim.and if i modify the CROSS_COMPILE as sde-, it shows error as "can't find mips-linux-as". so i wonder is there someone has run u-boot in mipssim and with which toolchain?

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[U-Boot-Users] re[18]
by Bart Dillon 28 Oct '05

28 Oct '05

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[U-Boot-Users] where to get the patch file mentioned in mail list
by zhuzhenhua 28 Oct '05

28 Oct '05

i search the mail list archive in u-boot sorceforge project, and i find some usefull patch, i wonder where to get these patch? thanks for hints

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[U-Boot-Users] Help on mpc8260ads flash u-boot
by batsayan.das＠tcs.com 27 Oct '05

27 Oct '05

Hello, We have a working RAM version of U-Boot for MPC8260ADS type customs board. We load the "u-boot.serc" by the TRACE tool and when run from the trace tool it gives the U-Boot prompt. I am giving a snap of the CMM file which actually loads the u-boot.serc to the memory. Our HRCW is "80 52 72 45". As per my understanding this values are stored in the flash. The flash is adress starts from 0x0. **********Snap of CMM file************ sys.mode down sys.option base 0x0F000000 system.cpu mpc8260 ... data.set 0x0f0101A8 %l 0x0f000000 ;IMMR data.set 0x0f010000 %l 0x8524C000 ;SIUMCR data.set 0x0f010004 %l 0xFFFFFF01 ;0xffffff81 ;SYPCR data.set 0x0f010024 %l 0x00000000 ;BCR data.set 0x0f010104 %l 0xFFF00660 ;OR0(Boot flash) data.set 0x0f010100 %l 0x00001001 ;BR0 ;UPMA initialization ;read region ;write region ;SDRAM initilization data.load c:\u-boot.srec *****************Snap End************** My question is. What the places we need to look into to convert this RAM version of U-Boot to ROM/Flash version of U-boot. The objective is when power on the u-boot binaries stored into the flash/ROM should be executed and give us the boot prompt. I think I need to change the HRCW. and the job done by the above CMM file should be done by the u-boot binary, so some part of the RAM version u-boot need to be modified to do this. Is there any specific place in the u-boot tree where we need to make change which does the job of the CMM file? Any help in this regard will be helpful. Thanks, Batsayan Das Tata Consultancy Services Limited Mailto: batsayan.das(a)tcs.com Website: http://www.tcs.com Notice: The information contained in this e-mail message and/or attachments to it may contain confidential or privileged information. If you are not the intended recipient, any dissemination, use, review, distribution, printing or copying of the information contained in this e-mail message and/or attachments to it are strictly prohibited. If you have received this communication in error, please notify us by reply e-mail or telephone and immediately and permanently delete the message and any attachments. Thank you

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[U-Boot-Users] skyeye and u-boot
by Richard Plana 27 Oct '05

27 Oct '05

Hi, I'm trying to build u-boot-1.1.3 for use with skyeye-1.0.0 (an ARM simulator) and was hoping to get tips and help building it from people who've done it before or know how. I'm building my own toolchain using the buildchain script written by Chip Coldwell <http://frank.harvard.edu/~coldwell/toolchain/> (gcc-2.4.4, glibc-2.3.5, linux-2.6.10). Unfortunately, I end up with a gcc compiler with a libgcc.a that's compiled to use hardware FP. Could someone tell me how to rebuild gcc to avoid that problem with u-boot? Is there an elegant way of keeping two versions of gcc (one that uses hardware FP and one that uses software FP) for when I need to build code for the actual board? Thanks for any help. -- Richard Plana Zi Corporation

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[U-Boot-Users] liuhuitian1997@gmail.com
by 刘会田 27 Oct '05

27 Oct '05

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[U-Boot-Users] u-boot-1.1.3 build error
by Li Weichen 26 Oct '05

26 Oct '05

Hi all: I am trying to build u-boot-1.1.3 for TI OMAP 5912 OSK. My system is Debian amd64 Sarge 3.1. First I encounter errors with option `short-load-bytes'and 'apcs-32'. When I delete this option in cpu/arm926ejs/config.mk, I encountered the second error: undefined CFG_GBL_DATA_SIZE. I found it is not defined in include/configs/omap5912osk.h and other related .h files. I tried to append a line in omap5912osk.h then a new error appeared. net.c: In function 'NetStartAgain': net.c:579: warning: pointer targets in passing argument 1 of 'getenv' differ in signedness net.c: In function 'NetCksum': net.c:1580: error: invalid lvalue in increment net.c: In function 'getenv_IPaddr': net.c:1742: warning: pointer targets in passing argument 1 of 'getenv' differ in signedness net.c: In function 'getenv_VLAN': net.c:1747: warning: pointer targets in passing argument 1 of 'getenv' differ in signedness make[1]: *** [net.o] Error 1 make: *** [net/libnet.a] Error 2 What should I do now? There is also a strange thing that if I built u-boot-1.1.3 with another PC ( Redhat FC3 ), the building process seems successful without any changes. Something wrong with configuration or else? Thank you for your advice and I am eager to receive your kind reply. Best regards! Li Weichen 2005-10-26

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[U-Boot-Users] 1.1.3 build error
by Li Weichen 26 Oct '05

26 Oct '05

Hi all: I am trying to build u-boot-1.1.3 for TI OMAP 5912 OSK. My system is Debian amd64 Sarge 3.1. First I encounter errors with option `short-load-bytes'and 'apcs-32'. When I delete this option in cpu/arm926ejs/config.mk, I encountered the second error: undefined CFG_GBL_DATA_SIZE. I found it is not defined in include/configs/omap5912osk.h and other related .h files. I tried to append a line in omap5912osk.h then a new error appeared. net.c: In function 'NetStartAgain': net.c:579: warning: pointer targets in passing argument 1 of 'getenv' differ in signedness net.c: In function 'NetCksum': net.c:1580: error: invalid lvalue in increment net.c: In function 'getenv_IPaddr': net.c:1742: warning: pointer targets in passing argument 1 of 'getenv' differ in signedness net.c: In function 'getenv_VLAN': net.c:1747: warning: pointer targets in passing argument 1 of 'getenv' differ in signedness make[1]: *** [net.o] Error 1 make: *** [net/libnet.a] Error 2 What should I do now? There is also a strange thing that if I built u-boot-1.1.3 with another PC ( Redhat FC3 ), the building process seems successful without any changes. Something wrong with configuration or else? Thank you for your advice and I am eager to receive your kind reply. Best regards! Li Weichen 2005-10-26

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[U-Boot-Users] [PATCH] support for mainstone development board
by Frank Agius 26 Oct '05

26 Oct '05

Attached are files to add support for the Mainstone development board (PXA270 CPU). This work was based on the Lubbock module. CHANGELOG: * Add support for the Mainstone development board Patch by Frank Agius, 26 Oct 2005 ________________________________________ Frank Agius SAMSys Technologies, Inc. Index: MAKEALL =================================================================== RCS file: /cvsroot/u-boot/u-boot/MAKEALL,v retrieving revision 1.128 diff -p -u -r1.128 MAKEALL --- MAKEALL 21 Oct 2005 20:39:10 -0000 1.128 +++ MAKEALL 26 Oct 2005 13:57:35 -0000 @@ -202,8 +202,8 @@ LIST_ARM11=" \ LIST_pxa=" \ adsvix cerf250 cradle csb226 \ - innokom lubbock pxa255_idp wepep250 \ - xaeniax xm250 xsengine \ + innokom lubbock mainstone pxa255_idp \ + wepep250 xaeniax xm250 xsengine \ " LIST_ixp="ixdp425" Index: Makefile =================================================================== RCS file: /cvsroot/u-boot/u-boot/Makefile,v retrieving revision 1.212 diff -p -u -r1.212 Makefile --- Makefile 15 Oct 2005 17:08:09 -0000 1.212 +++ Makefile 26 Oct 2005 13:57:36 -0000 @@ -1601,6 +1601,9 @@ lubbock_config : unconfig logodl_config : unconfig @./mkconfig $(@:_config=) arm pxa logodl +mainstone_config: unconfig + @./mkconfig $(@:_config=) arm pxa mainstone + pxa255_idp_config: unconfig @./mkconfig $(@:_config=) arm pxa pxa255_idp Index: README =================================================================== RCS file: /cvsroot/u-boot/u-boot/README,v retrieving revision 1.138 diff -p -u -r1.138 README --- README 12 Oct 2005 23:47:18 -0000 1.138 +++ README 26 Oct 2005 13:57:37 -0000 @@ -308,9 +308,9 @@ The following options need to be configu CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400, CONFIG_LUBBOCK, - CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, CONFIG_SHANNON, - CONFIG_P2_OMAP730, CONFIG_SMDK2400, CONFIG_SMDK2410, - CONFIG_TRAB, CONFIG_VCMA9 + CONFIG_MAINSTONE, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, + CONFIG_SHANNON, CONFIG_P2_OMAP730, CONFIG_SMDK2400, + CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9 MicroBlaze based boards: ------------------------ Index: drivers/smc91111.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/drivers/smc91111.c,v retrieving revision 1.19 diff -p -u -r1.19 smc91111.c --- drivers/smc91111.c 22 Nov 2004 22:20:09 -0000 1.19 +++ drivers/smc91111.c 26 Oct 2005 13:57:40 -0000 @@ -495,7 +495,15 @@ static void smc_enable() SMC_SELECT_BANK( 0 ); /* see the header file for options in TCR/RCR DEFAULT*/ SMC_outw( TCR_DEFAULT, TCR_REG ); +#ifdef CONFIG_SMC_PXA270 + /* The promiscuous bit set because I could not receive ARP reply + * packets from the server when I send a ARP request. It only works + * when I set the promiscuous bit + */ + SMC_outw( RCR_DEFAULT | RCR_PRMS, RCR_REG ); +#else SMC_outw( RCR_DEFAULT, RCR_REG ); +#endif /* clear MII_DIS */ /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ @@ -529,7 +537,6 @@ static void smc_shutdown() SMC_outb( TCR_CLEAR, TCR_REG ); } - /* . Function: smc_hardware_send_packet(struct net_device * ) . Purpose: @@ -640,7 +647,7 @@ again: } /* we have a packet address, so tell the card to use it */ -#ifndef CONFIG_XAENIAX +#ifndef SMC_WRITE_32 SMC_outb (packet_no, PN_REG); #else /* On Xaeniax board, we can't use SMC_outb here because that way @@ -654,7 +661,11 @@ again: printf ("Write data fifo not empty!\n"); /* point to the beginning of the packet */ +#ifndef CONFIG_SMC_PXA270 SMC_outw (PTR_AUTOINC, PTR_REG); +#else + SMC_outl (PTR_AUTOINC <<16, PTR_REG-2); +#endif PRINTK3 ("%s: Trying to xmit packet of length %x\n", SMC_DEV_NAME, length); @@ -683,7 +694,7 @@ again: */ #ifdef USE_32_BIT SMC_outsl (SMC91111_DATA_REG, buf, length >> 2); -#ifndef CONFIG_XAENIAX +#ifndef SMC_WRITE_32 if (length & 0x2) SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG); @@ -708,7 +719,7 @@ again: SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1); #endif /* USE_32_BIT */ -#ifndef CONFIG_XAENIAX +#ifndef CONFIG_SMC_WRITE_32 /* Send the last byte, if there is one. */ if ((length & 1) == 0) { SMC_outw (0, SMC91111_DATA_REG); @@ -716,7 +727,6 @@ again: SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG); } #endif - /* and let the chipset deal with it */ SMC_outw (MC_ENQUEUE, MMU_CMD_REG); @@ -729,7 +739,7 @@ again: /* release packet */ /* no need to release, MMU does that now */ -#ifdef CONFIG_XAENIAX +#ifdef SMC_WRITE_32 SMC_outw (MC_FREEPKT, MMU_CMD_REG); #endif @@ -743,6 +753,24 @@ again: return 0; } else { +#ifdef USE_32_BIT + /* ack. int */ + status = SMC_inb (SMC91111_INT_REG); + if (status & IM_TX_INT ) + { + SMC_outb (IM_TX_INT, SMC91111_INT_REG); + } + status = SMC_inb (SMC91111_INT_REG); + if (status & IM_TX_EMPTY_INT ) + SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG); + PRINTK2 ("%s: Sent packet of length %d, int status=0x%08x \n", SMC_DEV_NAME, length, status); + + /* release packet */ + /* auto release now set, no need to release the tx packet + * manually + SMC_outb (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + */ +#else /* ack. int */ SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG); /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ @@ -751,10 +779,10 @@ again: /* release packet */ /* no need to release, MMU does that now */ -#ifdef CONFIG_XAENIAX +#ifdef SMC_WRITE_32 SMC_outw (MC_FREEPKT, MMU_CMD_REG); #endif - +#endif /* wait for MMU getting ready (low) */ while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { udelay (10); @@ -766,7 +794,7 @@ again: } /* restore previously saved registers */ -#ifndef CONFIG_XAENIAX +#ifndef SMC_WRITE_32 SMC_outb( saved_pnr, PN_REG ); #else /* On Xaeniax board, we can't use SMC_outb here because that way @@ -805,7 +833,13 @@ void smc_destructor() */ static int smc_open (bd_t * bd) { - int i, err; + int err; +#ifdef CONFIG_SMC_PXA270 + long addr0_3; + word addr4_5; +#else + int i; +#endif PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME); @@ -828,6 +862,18 @@ static int smc_open (bd_t * bd) memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */ return (-1); /* upper code ignores this, but NOT bi_enetaddr */ } +#ifdef CONFIG_SMC_PXA270 + /* writes must be on a 32 bit boundary. write first 4 bytes of mac addr, + * then the last 2 bytes. + */ + addr0_3 = smc_mac_addr[3]<<24 | smc_mac_addr[2]<<16 | smc_mac_addr[1] <<8 | smc_mac_addr[0]; + /* write first 4 bytes. write address should be on a 32 bit boundary */ + SMC_outl (addr0_3, ADDR0_REG); + addr4_5 = smc_mac_addr[5]<<8 | smc_mac_addr[4]; + PRINTK2("writing smc_mac_addr=0x%06x%x\n",addr0_3,addr4_5); + /* write last 2 bytes. write address should be on a 32 bit boundary */ + SMC_outw (addr4_5, ADDR0_REG+4); +#else #ifdef USE_32_BIT for (i = 0; i < 6; i += 2) { word address; @@ -840,7 +886,7 @@ static int smc_open (bd_t * bd) for (i = 0; i < 6; i++) SMC_outb (smc_mac_addr[i], (ADDR0_REG + i)); #endif - +#endif /* end CONFIG_SMC_PXA270 */ return 0; } @@ -882,7 +928,12 @@ static int smc_rcv() PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); /* start reading from the start of the packet */ +#ifndef CONFIG_SMC_PXA270 SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); +#else + SMC_outl ((PTR_READ | PTR_RCV | + PTR_AUTOINC)<<16, 4); +#endif /* First two words are status and packet_length */ #ifdef USE_32_BIT @@ -952,7 +1003,7 @@ static int smc_rcv() udelay(1); /* Wait until not busy */ /* restore saved registers */ -#ifndef CONFIG_XAENIAX +#ifndef SMC_WRITE_32 SMC_outb( saved_pnr, PN_REG ); #else /* On Xaeniax board, we can't use SMC_outb here because that way @@ -1381,7 +1432,11 @@ static void smc_phy_configure () /* Configure the Receive/Phy Control register */ SMC_SELECT_BANK (0); +#ifdef CONFIG_SMC_PXA270 + SMC_outl (RPC_DEFAULT<<16, RPC_REG-2); +#else SMC_outw (RPC_DEFAULT, RPC_REG); +#endif /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ my_phy_caps = smc_read_phy_register (PHY_STAT_REG); @@ -1459,7 +1514,11 @@ static void smc_phy_configure () } /* Re-Configure the Receive/Phy Control register */ +#ifdef CONFIG_SMC_PXA270 + SMC_outl (RPC_DEFAULT<<16, RPC_REG-2); +#else SMC_outw (RPC_DEFAULT, RPC_REG); +#endif smc_phy_configure_exit: ; Index: drivers/smc91111.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/drivers/smc91111.h,v retrieving revision 1.11 diff -p -u -r1.11 smc91111.h --- drivers/smc91111.h 2 Nov 2004 13:00:56 -0000 1.11 +++ drivers/smc91111.h 26 Oct 2005 13:57:41 -0000 @@ -74,7 +74,12 @@ typedef unsigned long int dword; #define SMC_IO_EXTENT 16 -#ifdef CONFIG_PXA250 +/* XANEIAX and other boards can only do 32-bit writes */ +#if defined (CONFIG_XAENIX) || defined (CONFIG_SMC_PXA270) +#define SMC_WRITE_32 +#endif + +#if defined (CONFIG_PXA250) || defined (CONFIG_PXA27X) #ifdef CONFIG_XSENGINE #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) @@ -176,7 +181,7 @@ typedef unsigned long int dword; }; \ }) -#else /* if not CONFIG_PXA250 */ +#else /* if not (CONFIG_PXA250 || CONFIG_PXA27X) */ #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ /* @@ -678,8 +683,11 @@ enum { --------------------------------------------------------------------------*/ /* select a register bank, 0 to 3 */ - +#ifdef CONFIG_SMC_PXA270 +#define SMC_SELECT_BANK(x) { SMC_outl( (x)<<16, 12 ); } +#else #define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); } +#endif /* this enables an interrupt in the interrupt mask register */ #define SMC_ENABLE_INT(x) {\

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[U-Boot-Users] help on u-boot
by prabha.j＠tcs.com 26 Oct '05

26 Oct '05

Hi all, I was able to build u-boot for my custom board. when i tried to load it nothing is coming. I am using TRACE32 ICE and the board is almost similar to MPC8260ADS. I had set the baudrate as 115200 and flowcontrol as none. when i give run command in TRACE32, nothing is coming in hyperterminal. My flash base is 0x0000 0000 so i had given this in the board/mpc8260ads/config.mk . I have done some changes in the include/configs/MPC8260ADS.h for my board. Any help is appreciated. Thanks in advance. Prabha J. Tata Consultancy Services Limited Mailto: prabha.j(a)tcs.com Website: http://www.tcs.com Notice: The information contained in this e-mail message and/or attachments to it may contain confidential or privileged information. If you are not the intended recipient, any dissemination, use, review, distribution, printing or copying of the information contained in this e-mail message and/or attachments to it are strictly prohibited. If you have received this communication in error, please notify us by reply e-mail or telephone and immediately and permanently delete the message and any attachments. Thank you

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RE: [U-Boot-Users] Running test code from RAM while having GOT po inting to flash
by atul.sabharwal＠exgate.tek.com 25 Oct '05

25 Oct '05

Other possibility is the linker script. There is no method I can think of to know if this is correct (basically compare system.map vs u-boot.lds). It was derived from the mbx8xx board's u-boot.lds. If you could double check it? I have a beta version of MontaVista toolchain which was compiled for PPC860. Otheriwse, it should work with 852T. Thanks, Atul OUTPUT_ARCH(powerpc) SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS { /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } .rela.data : { *(.rela.data) } .rel.rodata : { *(.rel.rodata) } .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } .rela.ctors : { *(.rela.ctors) } .rel.dtors : { *(.rel.dtors) } .rela.dtors : { *(.rela.dtors) } .rel.bss : { *(.rel.bss) } .rela.bss : { *(.rela.bss) } .rel.plt : { *(.rel.plt) } .rela.plt : { *(.rela.plt) } .init : { *(.init) } .plt : { *(.plt) } .text : { /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/mpc8xx/start.o (.text) cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) lib_ppc/ppcstring.o (.text) lib_generic/vsprintf.o (.text) lib_generic/crc32.o (.text) lib_generic/zlib.o (.text) lib_ppc/cache.o (.text) lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/environment.o (.ppcenv) *(.text) *(.fixup) *(.got1) } _etext = .; PROVIDE (etext = .); .rodata : { *(.rodata) *(.rodata1) *(.rodata.str1.4) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } .dtors : { *(.dtors) } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; _erotext = .; PROVIDE (erotext = .); .reloc : { *(.got) _GOT2_TABLE_ = .; *(.got2) _FIXUP_TABLE_ = .; *(.fixup) } __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; __fixup_entries = (. - _FIXUP_TABLE_)>>2; .data : { *(.data) *(.data1) *(.sdata) *(.sdata2) *(.dynamic) CONSTRUCTORS } _edata = .; PROVIDE (edata = .); __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; __start___ex_table = .; __ex_table : { *(__ex_table) } __stop___ex_table = .; . = ALIGN(256); __init_begin = .; .text.init : { *(.text.init) } .data.init : { *(.data.init) } . = ALIGN(256); __init_end = .; __bss_start = .; .bss : { *(.sbss) *(.scommon) *(.dynbss) *(.bss) *(COMMON) } _end = . ; PROVIDE (end = .); }

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RE: [U-Boot-Users] Running test code from RAM while having GOT po inting to flash
by atul.sabharwal＠exgate.tek.com 25 Oct '05

25 Oct '05

But as I said, I have disabled the I-cache & D-cache & CFG_CACHE. On reset, in start.S, you set IDC_DISABLE@h to spr DC_CST & IC_CST. So, I don't know if a cache flush can magically turn the cache ON!! -- Atul

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RE: [U-Boot-Users] Running test code from RAM while having GOT po inting to flash
by atul.sabharwal＠exgate.tek.com 25 Oct '05

25 Oct '05

The hardware engineer is initializing the DDR memory correctly. Otherwise we won't be able to read/write to the memory. As I understand, the GOT table is used for relocating the exception vectors. I am most likely crashing while copying the fixups or when doing a cache flush. In start.S, if I disable the ICACHE & do not run the cache POST test which Enables the I-cache and never disables it, I should be fine. Unless its some 852T processor cache bug. We had problem with ICTRL with value of 7. Value of 3 seems to work better. Processor is at 50MHz and memory is at 100MHz with TA line based handshake ( so atomic). -- Atul

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