September 2004 - U-Boot

[U-Boot-Users] I can not drive cs8900 on mx1ads by u-boot.
by 齐尧 21 Sep '04

21 Sep '04

Hi,everyone: i am sorry to have sent mails unreadable.Now,i changed the format of letter and try again. I have downloaded u-boot-1.1.1 amd u-boot-1.1.1-imx1.diff,and I have cross-compile them successfully.luckly,the bootloader can init the serial port.then ,I want to enable the CS8900,but failed. I used to boot mx1ads by BLOB,and blob can get the ID of cs8900 correctly,so I cpoy these codes in blob to U-boot,but these codes are useless to get the ID of CS8900.The codes are as follows: unsigned short c; //set chip select 4 upper control register *(volatile P_U32)(0x00220020) = 0x00000F00; //set chip select 4 lower control register *(volatile P_U32)(0x00220024) = 0x80001501; //p the GPIO muxing to use Chip Select 4 *(volatile unsigned int *)(0x0021C020) &= 0xFF3FFFFF; *(volatile unsigned int *)(0x0021C038) &= 0xFF3FFFFF; //QiYao change the GPIO pin to PortC pin 17 *((volatile unsigned int * ) 0x0021c220)&=~0x00020000; *((volatile unsigned int *) 0x0021c238)&=~0x00020000; c = *(volatile unsigned short *)(0x15000300);//The Base address of CS8900 CS8900_PPTR = regno; printf("CS8900_PDATA = %x\n",CS8900_PDATA); I have check the codes for some times ,and i dnot know where the mistake is,so i ask you to help me. Qiyao , Beijing Institute of Technology

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[U-Boot-Users] u-boot as second stage boot loader
by Z.N. 21 Sep '04

21 Sep '04

Hi! I've got an at 91 rm 9200 based board with a 2MB _SERIAL_ flash connected to it. Since the flash is serial, it is not mapped to memory, and the board cannot boot from it. However, the first 16kbyte of this serial flash gets copied into the 16kbyte SRAM of the processor. Now I have a small boot loader loaded into the SRAM which initializes the SDRAM, can load pages from the serial flash, talk on the serial line,etc. The next step would be to load u-boot as a second stage boot loader, however how can someone do this? The memory configuration is like this: 0x0-0x4000 processor SRAM 0x4000-0x8000 processor ROM 0x20000000-0x21000000 SDRAM As it can be seen, the SRAM is too small for the 80-90kbyte u-boot image... What is the solution? Maybe i could take the u-boot image apart, and copy the code before relocation into the sram and the code after relocation into SDRAM and then make a "mov r5,#0;mov pc,r5"? Any help is appreciated! Regards, Zo

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RE: [U-Boot-Users] u-boot as second stage boot loader
by Friedrich, Lars 21 Sep '04

21 Sep '04

> The next step would be to load u-boot as a second stage boot loader, > however how can someone do this? [...] > As it can be seen, the SRAM is too small for the 80-90kbyte u-boot > image... What is the solution? Maybe i could take the u-boot image > apart, and copy the code before relocation into the sram and the code > after relocation into SDRAM and then make a "mov r5,#0;mov pc,r5"? In the 16kbyte flash area you put an universal first stage bootloader. This bootloader should not have any knowledge about _what_ it will start. It should only: - prepare the hardware to retrieve data from the flash device - copy contents from the flash device to ram - jump to a defined address in ram (- maybe init the serial and do some output for debugging purposes) So the first stage bootloader will need four things: 1) the start of data to copy 2) the destination in ram to copy it to 3) the amount of data to copy 4) the address to set the pc after copy, maybe the same as 2) As a start, these values can be hardcoded into the first stage bootloader. Later you might consider putting these values into the u-boot image (in other words: in a defined area on the flash), so you will never have to touch the first stage bootloader again if the second stage bootloader changes. The first stage bootloader copies U-Boot completely into the ram and U-Boot should be able to recognize that it is executed from ram already and not do any relocation itself. Regards, Lars Friedrich

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[U-Boot-Users] I can not drive the cs8900 on mx1ads by u-boot-1.1.1-imx1
by 齐尧 21 Sep '04

21 Sep '04

hi, I am sorry to send unreadable mail so many times.I want to try again. Now ,the u-boot can work well ,but the i can not controlethcad cs8900 very well.i can not read the id of cs8900.I have ported the blob to mx1ads ,and i can get the id of cs8900 .now ,i just copy the code in blob to u-boot to get the id of cs8900 ,but i am failed .I do not know why . the code related to is as follows : //set CS4U *(volatile unsigned long*)(0x00220020) = 0x00000F00; //set CS4L control register *(volatile unsigned long*)(0x00220024) = 0x80001501; //set the GPIO muxing to use Chip Select 4 *(volatile unsigned long*)(0x0021C020) &= 0xFF3FFFFF; *(volatile unsigned long*)(0x0021C038) &= 0xFF3FFFFF; //the irq is connect to GPIO pin to PortC pin 17 *((volatile unsigned long* ) 0x0021c220)&=~0x00020000; *((volatile unsigned long*) 0x0021c238)&=~0x00020000; //send the base address of cs8900 on the ADD Bus c = *(volatile unsigned char *)(0x15000300); CS8900_PPTR = regno; printf("CS8900_PDATA = %x\n",CS8900_PDATA); the result is always 0x5555,i do not know why,these codes above can work well in blob. I am looking forward your reply,thank ahead!

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[U-Boot-Users] samsung 4510B in big endian mode
by gold ares 21 Sep '04

21 Sep '04

hello,guy I have a cpu board with samsung 4510b. The cpu is set in big endian mode. I also find there is a u-boot port with 4510b in u-boot cvs. But the u-boot.lds says: OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") what can i do ? Whether or not That just changing "elf32-littlearm" to "elf32-bigarm" is all over?? -- _____________________________________________________________ Web-based SMS services available at http://www.operamail.com. >From your mailbox to local or overseas cell phones. Powered by Outblaze

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[U-Boot-Users] U-boot for MIPS problems compiling...
by Chris Jones 21 Sep '04

21 Sep '04

Jerry; I did a search through the u-boot mailing list archives as I was having problems compiling for my MIPS AU1550. Ironically, you seemed to be having problems and made the exact fixes that I did in order to get as far as you did in the compile process. However, my progress has come to a standstil as has the thread bearing your problem. I was hoping you could shed some light on the situation if you've made any progress as of 2004-01-30 19:01 Cheers, -=Chris -- Chris Jones | Software Developer | Sutus, Inc. t: +1.604.987.8866 x 2204 | e: cjones(a)sutus.com

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[U-Boot-Users] Re: ramdisk image question
by Alexander Povolotsky 20 Sep '04

20 Sep '04

Yes, Wolfgang - I am using U-Boot - but do I need somehow create ramdisk image first (please note that I am building kernel in cygwin Windows XP environment) ? Firstly I tried to use root file system using NFS server on the same Windows XP machine where I am building via cygwin - by copying pre-made root file system from Arabella CD-ROM to my windows disk drive - this did not work because hard links were not preserved during copying ... bootargs=root /dev/nfs rw nfsroot=192.168.1.100:/home/apovolot/fadsroot -I was getting during the kernel boot: ... Looking up port of RPC 100003/2 on 192.168.1.100 Looking up port of RPC 100005/1 on 192.168.1.100 VFS: Mounted root (nfs filesystem). Freeing unused kernel memory: 272k init Warning: unable to open an initial console. Kernel panic: No init found. Try passing init= option to kernel. <0>Rebooting in 180 seconds.. Then I tried to use to NFS mount (read only) onto the Arabella CD-ROM itself (within my Windows XP): bootargs=root /dev/nfs ro nfsroot=192.168.1.100:/E/fadsroot This caused kernel booting hanging: ... Looking up port of RPC 100003/2 on 192.168.1.100 Looking up port of RPC 100005/1 on 192.168.1.100 VFS: Mounted root (nfs filesystem). Freeing unused kernel memory: 272k init *********** hanging ********** Finally I tried: bootargs=root=/dev/ram rw devfs=nomount init=/bin/sh bootm 200000 ## Booting image at 16 08:49:38 EDT 2004 PQ2 ADS Portame: Linux 68.1.103 PID hash table entries: 256 (order 8: 2048 bytes) Warning: real time clock seems stuck! Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 30432k available (1348k kernel code, 324k data, 272k init, 0k highmem) Calibrating delay loop... 131.07 BogoMIPS Mount-cache hash table entries: 512 (order: 0, 4096 bytes) NET: Registered protocol family 16 PCI: Probing PCI hardware Generic RTC Driver v1.07 Serial: CPM driver $Revision: 0.01 $ ttyCPM0 at MMIO 0xf0011a00 (irq = 40) is a CPM UART RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize loop: loaded (max 8 devices) eth0: FCC ENET Version 0.3, 08:00:17:40:00:03 NET: Registered protocol family 2 IP: routing cache hash table of 512 buckets, 4Kbytes TCP: Hash tables configured (established 2048 bind 4096) NET: Registered protocol family 1 NET: Registered protocol family 17 Sending DHCP requests ...... timed out! Sending DHCP requests ...... timed out! ... So what is the real solution ? Thanks, Alex ************************ In message <20040920.070149.1935.907342(a)webmail13.lax.untd.com> you wrote: > > Are there any h/w architecture and board specific details to be > taken in account while coding/building the ramdisk ? > If so, does the ramdisk explanation in the book covers those details > for PPC (Freescale's PQ2FADS-VR 82xx board with MPC8275)? All the details you may collect here and there are completely misleading and irrelevant as you wrote you were using U-Boot, which has it's own way of handling ramdisk images, which is independent of the architecture or the kernel version. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de Mistakes are often the stepping stones to utter failure. ________________________________________________________________ Get your name as your email address. Includes spam protection, 1GB storage, no ads and more Only $1.99/ month - visit http://www.mysite.com/name today!

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[U-Boot-Users] PQ2FADS-ZU, was Code Warrior 8.14 + WireTAP + U-boot bootloader image ( Arabella 2 .0 C D-ROM "Linux for Motorola 82xx")
by VanBaren, Gerald (AGRE) 20 Sep '04

20 Sep '04

> -----Original Message----- > From: u-boot-users-admin(a)lists.sourceforge.net > [mailto:u-boot-users-admin@lists.sourceforge.net]On Behalf Of Alex > Povolotsky > Sent: Tuesday, September 07, 2004 1:00 PM > To: wd(a)denx.de > Cc: u-boot-users(a)lists.sourceforge.net > Subject: [U-Boot-Users] Re: Code Warrior 8.14 + WireTAP + U-boot > bootloader image ( Arabella 2 .0 C D-ROM "Linux for Motorola 82xx") > > > > Wolfgang, > > Your recommendation was well noted but at this point I want > to avoid using u-boot image, compiled by myself from the source. > At this point I want to use the "tried"/"tested" bootloader > In my opinion, my question re usability of the u-boot > bootloader images provided on the Arabella 2.0 CD-ROM "Linux > for Motorola 82xx" is still worth to be asked/answered - this > cdrom is "packaged" by the Freescale, when they ship the > brand new board. Also FreeScale "packages" Code Warrior 8.14 > (with one month evaluation license) + WireTAP probe into the > shipment. > > Do you yourself have the PQ2FADS_VR 66 MHz board (with the > MPC8275 processor) by any chance (as well as Arabella 2.0 > CD-ROM "Linux for Motorola 82xx" ?) ? > > Thanks > Alex, > > in message > <20040907.084113.509.485968(a)webmail14.lax.untd.com> you wrote: > > > > > > Did any one on this list used elf bootloader for PQ2FADS_VR > > 66 MHz board (with the MPC8275 processor) provided on the > > Arabella 2.0 CD-ROM "Linux for Motorola 82xx" ? > > I already replied to your question on the etux mailing list. There > was no need to repost the very same question here. My hinto to post > on u-boot-users was intended for _new_ questions. > > > While the programming of the flash seemingly completed without > > errors - however the resulted bootloader is not functional ... - > > I repeat my recommendation: > > Use the latest version of U-Boot (top of CVS tree). > See http://sourceforge.net/projects/u-boot and > http://www.denx.de/twiki/bin/view/DULG/Manual > > Best regards, > > Wolfgang Denk I'm not answering the questions that were asked, but I figured a testimonial wouldn't hurt: My configuration: * PQ2FADS-ZU with a MPC8260 * BDI2000, MPC8280 configuration downloaded from denx.de * Remaps the IMMR from 0x0F000000 to 0xF0000000 * Initializes SDRAM * U-boot build top of the u-boot CVS tree (synced the week of 2004-09-12, I don't remember the exact date). I had to change the BDI2000 JTAG clocking to 8MHz (JTAGCLOCK 1) from the default 16MHz (JTAGCLOCK 0) before the flash would program reliably. With the 16MHz clock it would only program 1K+ and then have an error. The board is booting with the (default) BCSR-supplied HRCW ((IMMR = 0x0F000000) == yech). I cannot boot it with the BDI2000 plugged in, probably due to the HRCW. If the BDI2000 is plugged in, u-boot starts to run and then the BDI2000 gets unhappy and resets the board. ToDo: * Change the J7 jumper to use flash for the HRCW * Reconfigure u-boot to boot low (preferred configuration) * Reconfigure the BDI2000 to... * Not move the IMMR (not necessary or desired with a flash HRCW) * Remove the SDRAM initialization (SDRAM init is poor practice) * Get ethernet configured and running... * Boot linux! gvb ****************************************** The following messages are brought to you by the Lawyers' League of IdioSpeak: ****************************************** The information contained in, or attached to, this e-mail, may contain confidential information and is intended solely for the use of the individual or entity to whom they are addressed and may be subject to legal privilege. If you have received this e-mail in error you should notify the sender immediately by reply e-mail, delete the message from your system and notify your system manager. Please do not copy it for any purpose, or disclose its contents to any other person. The views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the company. The recipient should check this e-mail and any attachments for the presence of viruses. The company accepts no liability for any damage caused, directly or indirectly, by any virus transmitted in this email. ******************************************

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[U-Boot-Users] I can not drive CS8900 on mx1ads by U-boot-1.1.1-imx1
by 齐尧 20 Sep '04

20 Sep '04

Hi I have downlodaded the u-boot-1.1.1 and patch for imx1,and i have cross-compiled them successfully!. Now ,the u-boot can work well on mx1ads, but the i can not control ethcad cs8900 very well.i can not read the id of cs8900.I have ported the blob to mx1ads ,and i can get the id of cs8900 .now ,i just copy the code in blob to u-boot to get the id of cs8900 ,but i am failed .I do not know why . the code related to is as follows : //set CS4U *(volatile unsigned long*)(0x00220020) = 0x00000F00; //set CS4L control register *(volatile unsigned long*)(0x00220024) = 0x80001501; //set the GPIO muxing to use Chip Select 4 *(volatile unsigned long*)(0x0021C020) &= 0xFF3FFFFF; *(volatile unsigned long*)(0x0021C038) &= 0xFF3FFFFF; //the irq is connect to GPIO pin to PortC pin 17 *((volatile unsigned long* ) 0x0021c220)&=~0x00020000; *((volatile unsigned long*) 0x0021c238)&=~0x00020000; //send the base address of cs8900 on the ADD Bus c = *(volatile unsigned char *)(0x15000300); CS8900_PPTR = regno; printf("CS8900_PDATA = %x\n",CS8900_PDATA); the result is always 0x5555 or 0x5575,i do not know why,these codes above can work well in blob. I am looking forward your reply,thank ahead! Beijing Institute of Technology Qiyao E-mail : qtopia(a)126.com msn: qiyaobit(a)hotmail.com

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[U-Boot-Users] off topic: Linux Kernel
by Frank 19 Sep '04

19 Sep '04

I am working on an 8245 based board running Linux.:-) I realize this is not the place to post questions about the Kernel, but I'm trying get a driver working using OpenPic and cascading 8259 interrupts. I was wondering which mailing list would be the best to join and post questions. Any help (about the mailing lists) would be greatly appreciated... _______________________________ Do you Yahoo!? Declare Yourself - Register online to vote today! http://vote.yahoo.com

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[U-Boot-Users] I can not drive CS8900 on mx1ads by U-boot-1.1.1-imx1
by 齐尧 19 Sep '04

19 Sep '04

I have downloaded u-boot-1.1.1 amd u-boot-1.1.1-imx1.diff,and I have cross-compile them successfully.luckly,the bootloader can init the serial port.then ,I want to enable the CS8900,but failed. I used to boot mx1ads by BLOB,and blob can get the ID of cs8900 correctly,so I cpoy these codes in blob to U-boot,but these codes are useless to get the ID of CS8900.The codes are as follows: unsigned short c; //set chip select 4 upper control register *(volatile P_U32)(0x00220020) = 0x00000F00; //set chip select 4 lower control register *(volatile P_U32)(0x00220024) = 0x80001501; //p the GPIO muxing to use Chip Select 4 *(volatile unsigned int *)(0x0021C020) &= 0xFF3FFFFF; *(volatile unsigned int *)(0x0021C038) &= 0xFF3FFFFF; //QiYao change the GPIO pin to PortC pin 17 *((volatile unsigned int * ) 0x0021c220)&=~0x00020000; *((volatile unsigned int *) 0x0021c238)&=~0x00020000; c = *(volatile unsigned short *)(0x15000300);//The Base address of CS8900 CS8900_PPTR = regno; printf("CS8900_PDATA = %x\n",CS8900_PDATA); I have check the codes for some times ,and i dnot know where the mistake is,so i ask you to help me. Qiyao , Beijing Institute of Technology

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[U-Boot-Users] Anyone using pcnet.c ? can't make it work on 100mb link
by Brad Parker 17 Sep '04

17 Sep '04

Hi Is anyone using pcnet.c ? (CONFIG_PCNET_79C973) I can't make it work on 100mb link. It works fine with a 10mbit link. It stops transmitting on a 100mbit. (it's odd - the descriptor ring status is 8300 - like there is no link) Once linux is running (and the pcnet32.c driver takes over) then 100mbit works fine. So I presume the hardware is ok. This is using the internal phy. I've tried everything I can think in terms of programming the chip registers including setting the mii control register to zero (which should force 10mbit). No matter what I do it works fine on 10mb and not on 100mb. What's odd is that I turn auto-neg off, 100mb off, reset the phy and write zero to the phy control register and it still negotiates a 100mbit link. -brad

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[U-Boot-Users] Accessing a LBC Peripheral thru LCS in MPC8540
by Sudhakar 17 Sep '04

17 Sep '04

Hi All.. I have a problem in Accessing LBC Peripheral [CPLD] connected thru LCS7 in MPC8540 based board. In such case I can get a pulse in the LCS 7 when I use UPM Mode. But when I use GPCM Mode I couldnt get any pulse.. If anyone knows the answer please pass it on to me. The steps followed for Accessing the CPLD(LCS 7) in GPCM Mode are as follows ================================================================= #define CFG_BR7_PRELIM 0xf8000801 #define CFG_OR7_PRELIM 0xffff0ee6 [Detailed BR7/OR7 Setting I have explained below] I tried accessing the device [CPLD Control Register [Offset 0]] as below void cpldconfig( ) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; volatile ushort *dummy = (uchar *)CFG_CPLD_BASE; /* set all BA bits */ short x; x = *dummy; } ================================================================= We Configured BR7/OR7 as follows #define CFG_CPLD_BASE 0xF8000000 #define CFG_CPLD_SIZE 0x00010000 /*64 Kbytes */ #define BRx_PS_8 0x00000800 /* 8 bit port size */ #define BRx_MS_GPCM_P 0x00000000 /* G.P.C.M. Bus Machine Select*/ #define BRx_V 0x00000001 /* Bank Valid */ #define ORxG_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ #define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */ #define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ #define ORxG_TRLX 0x00000004 /* Timing Relaxed */ #define ORxG_EHTR 0x00000002 /* Extended Hold Time on Read */ ================================================================= /* * BR7 is configured as follows: * * - Base address of 0xF8000000 * - 8 bit port size * - Data errors checking is disabled * - Read and write access * - GPCM * - Access are handled by the memory controller according to MSEL * - Not used for atomic operations * - No data pipelining is done * - Valid */ # define CFG_BR7_PRELIM ((CFG_CPLD_BASE & BRx_BA_MSK) |\ BRx_PS_8 |\ BRx_MS_GPCM_P |\ BRx_V) ================================================================= /* OR7 is configured as follows: * * - 64 KB byte * - *BCTL0 is asserted upon access to the current memory bank * - *CW / *WE are negated a quarter of a clock earlier * - *CS is output at the same time as the address lines * - Uses a clock cycle length of 15 * - *PSDVAL is generated internally by the memory controller * unless *GTA is asserted earlier externally. * - Relaxed timing is generated by the GPCM for accesses * initiated to this memory region. * - One idle clock is inserted between a read access from the * current bank and the next access. */ #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ # define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_CPLD_SIZE) |\ ORxG_CSNT |\ ORxG_ACS_DIV2 |\ ORxG_SCY_14_CLK |\ ORxG_TRLX |\ ORxG_EHTR) ================================================================= -- Thanks and Regards, Sudhakar V GDA Technologies Ltd. http://www.gdatech.com

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[U-Boot-Users] Regarding Local Bus Peripheral Access thru LCS Chip Selects ?
by Sudhakar 17 Sep '04

17 Sep '04

Hi all, I'm working in a MPC 8540 based board where the Local Bus Chip Selects [ LCS1 - LCS 7 ] are used to connect variuos peripherals such as NPU,CPLD etc. To access the devices thru Uboot , What are the changes to be done ? I have configured the BRn/ORn Settings and I treid to access the devices by reading a Read Only Register.But when i try to probe i could find any chip select Assertion. Is there any configuration to be done to start using the Chip selects ? If anyone have some idea please share some info to me. -- Thanks and Regards, Sudhakar V GDA Technologies Ltd. http://www.gdatech.com

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RE: [U-Boot-Users] MPC8272ADS and uboot program check
by Bastos Fernandez Alexandre 17 Sep '04

17 Sep '04

Hi, >First of all, I would acknowleging that Wolfgang is probably right and you probably have a hardware problem. It could be. I had some problem with the Flash in the past, but there, the board didn't start at all and kept rebooting in a few miliseconds with a HRESET. > In case that is not true, my follow-up questions and observations are... >#1 question in debugging: what changed between when it last worked and now? > Nothing changed. The uboot version is exactly the same it was before. >Looking at the above, what is the software trying to do when all the garbage is being spewed out (just before it prints "8MB"? What it is doing is likely related to the problem. > I don't really now what it was doing at this point. So this is the point where I would need your help. I have tried to guess it. Has it any relation with the CRC warning, or some other problem with SDRAM? >Did the board previously print the correct clock rate, or has it always been wrong? Why is it wrong? > No. Previously it showed the correct clock rate (400 Mhz). I can't imagine why this is not right. Could be some problem with the integer unit ??? SDRAM ??? >#1 rule in debugging: always fix the known bugs before hunting for the unknown, known (but discounted and ignored) bugs tend to cause additional "unknown bugs" in strange and mysterious ways. > OK. I will try to follow this method. >gvb Thanks Alex

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[U-Boot-Users] MPC8540 FEC/TSEC -Issues while enabling both controllers
by Sudhakar 16 Sep '04

16 Sep '04

Hi all.. I have some issues in Uboot while enabling both the controllers FEC/TSEC in MPC8540 based board.. Individually they are working fine..but when enabled together , both are not working. Now im trying to analyze why they are not working ? If anyone can provide me details to enable both it would save some time for me. -- Thanks and Regards, Sudhakar V

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[U-Boot-Users] LCD Hang
by angelo.santangelo＠tectel.it 16 Sep '04

16 Sep '04

Hi, I try to portin U-Boot on my custom pxa board. This platform is like Lubbock. At this time u-boot hang with this message [LCD] Initializing LCD frambuffer at 00000000 palette_mem_size = 0x00000200 Configuring PXA LCD vid: vl_col=640 hslen=1 lm=3 rm=3 vid: vl_row=480 vslen=1 um=0 bm=0 I have put som puts("") message to find where u-boot hang and i have discovered it hangs before this initializzzation /* populate descriptors */ fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow; Filename is pxafb.c, function name pxafb_init(..). Have, anyone a solution for my problem? Thanks a lot Angelo

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[U-Boot-Users] LCD Hang
by angelo.santangelo＠tectel.it 16 Sep '04

16 Sep '04

Hi, I try to portin U-Boot on my custom pxa board. This platform is like Lubbock. At this time u-boot hang with this message [LCD] Initializing LCD frambuffer at 00000000 palette_mem_size = 0x00000200 Configuring PXA LCD vid: vl_col=640 hslen=1 lm=3 rm=3 vid: vl_row=480 vslen=1 um=0 bm=0 I have put som puts("") message to find where u-boot hang and i have discovered it hangs before this initializzzation /* populate descriptors */ fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow; Filename is pxafb.c, function name pxafb_init(..). Have, anyone a solution for my problem? Thanks a lot Angelo

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RE: [U-Boot-Users] MPC8272ADS and uboot program check
by Bastos Fernandez Alexandre 16 Sep '04

16 Sep '04

Wolfgang, >> >> >First of all, I would acknowleging that Wolfgang is probably right and you >> probably have a hardware problem. >Please configure your mailer to quote correctly. >BOTH lines above are quotes, but only the first line is marked as >such. This essentially makes your messages unreadable. please fix >this! Sorry about that. For me all this was the same line. I haven't arrived to configure my mailer to quote this way at all (so I have to do it by hand) :-( Sometimes, I have some problems to send plain-text only, but this is another discussion. >> It could be. I had some problem with the Flash in the past, but there, the >> board didn't start at all and kept rebooting in a few miliseconds with a >> HRESET. >I think all additional discussion is in vain. You have known hardware >problems, so it makes no sense to continue. >Don't try to understand why the failure mode is a reset in one case >or a spectacular crash in another one - when yoiur flash is failing >you must assume that the CPU is executing random data. This can be >anything, and fail at any time andin any way you can or cannot >imagine. >Stop here, and fix or replace the hardware. OK. I will. Thank for all. Alex

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RE: [U-Boot-Users] MPC8272ADS and uboot program check
by Bastos Fernandez Alexandre 16 Sep '04

16 Sep '04

> >Is it your private port of U-Boot to 8272? If so, the problem can be in > H/W initialisation. U-Boot supports this family and MPC8272ADS since > version 1.1.1. I work with it on daily basis without any problems. > > No, it is not my private port. And aparently, it was working fine til > monday. > > Alex >

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Re: [U-Boot-Users] MPC8540 gigabit ethernet
by Scott Harper 16 Sep '04

16 Sep '04

That was one of the first things we checked. It is now configured exactly the same as the ADS board. Still the same problems. Thank you for you help. Scott On Monday 13 September 2004 20:59, Andy Fleming wrote: > One tricky thing about that Marvell PHY is the CONFIG pins, which set > up a bunch of default values. The u-boot driver resets some of those > settings (to make sure that all the supported speed and duplex options > are advertised), but there are some settings which the driver doesn't > bother to change. If one of those settings is screwed up, then > strange things can happen. > > So check the sanity of the settings. :) > > Andy Fleming > > On Mon, 13 Sep 2004 17:35:38 -0700, Scott Harper <scott(a)lassen.com> wrote: > > Hello, > > > > We are having problem getting gigbit ethernet working with u-boot on our > > board. I suspect that we have a hardware problem but I am double > > checking to make sure that I am not missing anything. > > > > u-boot with 8540ADS board and gigabit works fine. > > u-boot with our 8540 board gigabit has checksum errors as seen by > > etherreal. our 8540 board 100Mbit works fine in all modes. > > > > We are using the same PHY as the 8540ADS (Marvell 88E1011S) > > > > Since 100Megabit works and Gigabit doesn't have I missed a configuration > > or is this really a hardware problem. > > > > Scott > > > > ------------------------------------------------------- > > This SF.Net email is sponsored by: YOU BE THE JUDGE. Be one of 170 > > Project Admins to receive an Apple iPod Mini FREE for your judgement on > > who ports your project to Linux PPC the best. Sponsored by IBM. > > Deadline: Sept. 13. Go here: http://sf.net/ppc_contest.php > > _______________________________________________ > > U-Boot-Users mailing list > > U-Boot-Users(a)lists.sourceforge.net > > https://lists.sourceforge.net/lists/listinfo/u-boot-users

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RE: [U-Boot-Users] soft or hard I2C code for AT91RM9200?
by VanBaren, Gerald (AGRE) 15 Sep '04

15 Sep '04

> -----Original Message----- > From: u-boot-users-admin(a)lists.sourceforge.net > [mailto:u-boot-users-admin@lists.sourceforge.net]On Behalf Of David A. > Peters > Sent: Wednesday, September 15, 2004 10:07 AM > To: U-Boot Users List > Subject: RE: [U-Boot-Users] soft or hard I2C code for AT91RM9200? > > > I have the soft I2C working except for one small problem. > When I try to > read more than 2 bytes from the eeprom, I get the first two bytes, and > anything else that follows is 0xFF. I've verified that data > is written to > the eeprom in other locations. I am using a 24AA256. > Has anyone else seen this problem? > > -----Original Message----- > From: u-boot-users-admin(a)lists.sourceforge.net > [mailto:u-boot-users-admin@lists.sourceforge.net]On Behalf Of David A. > Peters > Sent: Tuesday, September 14, 2004 3:10 PM > To: U-Boot Users List > Subject: [U-Boot-Users] soft or hard I2C code for AT91RM9200? > > > Does anyone have I2C code for the AT92RM9200 that they would > be willing to > share? I am trying to get the soft I2C working, but I am struggling. > Thank you! Do you have the "alen" set to 2? The 24AA256 has two bytes of address. "Returning" 0xFF sounds like the chip is not responding for the reads after the first two bytes. How did you verify the data you wrote? If you are using the read that you complained about, you cannot be sure it is reading _anything_ right (e.g. if your addressing is wrong, you likely are writing to the same wrong location that you are reading from). If all else fails, hook up a logic analyzer (or digital scope). This is the most efficient way to debug i2c problems. gvb ****************************************** The following messages are brought to you by the Lawyers' League of IdioSpeak: ****************************************** The information contained in, or attached to, this e-mail, may contain confidential information and is intended solely for the use of the individual or entity to whom they are addressed and may be subject to legal privilege. If you have received this e-mail in error you should notify the sender immediately by reply e-mail, delete the message from your system and notify your system manager. Please do not copy it for any purpose, or disclose its contents to any other person. The views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the company. The recipient should check this e-mail and any attachments for the presence of viruses. The company accepts no liability for any damage caused, directly or indirectly, by any virus transmitted in this email. ******************************************

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[U-Boot-Users] Question about SERIAL_MULTI
by Travis Sawyer 15 Sep '04

15 Sep '04

Now that the patch has been submitted... I was looking at common/serial.c, specifically the serial_devices_init function: dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; Shouldn't DEV_FLAGS_SYSTEM also be set? Regards, Travis

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Re: [U-Boot-Users] Re: [PATCH] - fixed missing System ACE CF device
by Sean Chang 15 Sep '04

15 Sep '04

Hi Stephen, Stephen Williams wrote: > > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > I think I've got a handle on why your "fat" patch doesn't work > on my system. There is no call to init_part(&systemace_dev) > anywhere. The cmd_ace.c:systemace_get_dev function should most > likely be the place to make that call. When the sourceforge > CVS server comes back to life, I'll make a version of your > ace_fat patch that works for me. Then you can try it and see > if it works for you as well. > I though you were going to send me a new patch to try out :p . By adding the second patch, "ace_init.patch", to my original patch, "ace_fat.patch", everything should work out happily. Let me know otherwise. Regards, Sean

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[U-Boot-Users] MPC8272ADS and uboot program check
by Bastos Fernandez Alexandre 15 Sep '04

15 Sep '04

Hi to all, After some days working ok with my MPC8272ADS board, now it keeps rebooting all the time with a Program Check report. It has arrived after a hang. I have been checking the output as this is all the information i have at the moment. I have realized that clock reporting is incoherent (the true one is cpu_clk=400Mhz), so i wonder if it has any relation. Any idea? The output I get is: U-Boot 1.0.0 (Jun 30 2004 - 20:20:47) MPC8272 Reset Status: Check Stop, External Soft, External Hard MPC8272 Clock Configuration - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core Freq 100-300 - dfbrg 1, corecnf 0x0a, busdf 3, cpmdf 1, plldf 0, pllmf 3 - vco_out 400000000, scc_clk 100000000, brg_clk 25000000 - cpu_clk 400000000, cpm_clk 200000000, bus_clk 100000000 CPU: MPC8272 (HiP7 Rev 13, Mask 0.1 0K50M) at 18.382000 MHz Board: Motorola MPC8272ADS I2C: ready DRAM: 64 MB þrTþrTþr\þr\þrdþrdþrlþrlþrtþrtþr|þr|þr þr þrþrþrþrþrþrþr¤þr¤þr¬þr¬þr´þr´þr¼þr¼þrÄþ rÄþrÌþrÌþrÔþrÔþrÜþrÜþräþräþrìþrìþrôþrôþrüþrüþrþrþr þr þrþrþrþrþr$þr$þr,þr,þr4þr4þr <þr<þrDþrDþrLþrLþrTþrTþr\þr\þrdþrdþrlþrlþrtþrtþr|þr|þr þr þrþrþrþrþrþrþr¤þr¤þr¬þr¬ þr´þr´þr¼þr¼þrÄþrÄþrÌþrÌþrÔþrÔþrÜþrÜþräþräþrìþrìþrôþrôþrüþrüþrþrþr þr þrþrþrþrþr$þ r$þr,þr,þr4þr4þr<þr<þrDþrDþrLþrLþrTþrT 8 MB *** Warning - bad CRC, using default environment pci init start-----pci init end In: serial Out: serial Err: serial NIP: 03F968D8 XER: 20000000 LR: 03FB621C REGS: 03f3fdd8 TRAP: 0700 DAR: 03FB5374 MSR: 00083002 EE: 0 PR: 0 FP: 1 ME: 1 IR/DR: 00 GPR00: CCC0E043 03F3FEC8 E7FFFFFF 00000001 00000000 00000010 000003A0 000003C4 GPR08: 00000264 B0FFFFFB 03FC86D0 001A6306 48002024 E7FFF3BF 03FC8000 058A0000 GPR16: FBFF9F7B FF7FFFED 00000000 FE729328 00003002 00000001 00000000 03FA3098 GPR24: 03FA390C 00000000 00000010 00000000 00000000 03F3FF64 00000020 F0010D40 Call backtrace: Program Check Exception

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