July 2004 - U-Boot

[U-Boot-Users] u-boot 1.1.1 & Intel LXT972A
by Knowledge Seeker 21 Jul '04

21 Jul '04

I have LXT972A on 852T. From u-boot, I have set mac, ip and netmask. When I try to ping a ip address on LAN. I get "TX timeout" I have traced this. During u-boot init, fec_initialize is called, which does not do much to comfiugre the hardware. When I ping fec_init is called in cpu/mpc8xx/fec.c and then it eventually times out in fec_send function. I have ether real running on another computer, which can see arp packet coming out of fec. So at this point what should I look next. Help. Completely lost.

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RE: [U-Boot-Users] Newbie question - cross
by Michael Bendzick 21 Jul '04

21 Jul '04

Is there an easy way to update the PPC binutils in ELDK 3.0? Is there an estimated time of arrival for ELDK 3.1? For thoroughness, I'd like to test a patch on an 85xx board, but don't see a good way to do that yet. Thanks, -Michael Bendzick -----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Tuesday, July 20, 2004 10:00 AM To: Jon Loeliger Cc: u-boot-users Subject: Re: [U-Boot-Users] Newbie question - cross In message <1090334884.4910.11.camel(a)blarg.somerset.sps.mot.com> you wrote: > > I currently use this for most of my development: > > gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a) ...whichis identical to the tools used in ELDK 3.0 (which actually is based on YD-3.0). > I have heard a rumor of the current code not compiling > with GCC 2.95, but have not yet had a chance to verify it. > I believe it was a reported problem with an assembler > interpretation of a C macro for the TLB_MAS() handling. Yes. You need binutils 2.14 or later. See "doc/README.mpc85xxads". > You should plan on uprev'ing to a modern GCC, of course. Like ELDK 3.1 :-) Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de Anything free is worth what you pay for it. ------------------------------------------------------- This SF.Net email is sponsored by BEA Weblogic Workshop FREE Java Enterprise J2EE developer tools! Get your free copy of BEA WebLogic Workshop 8.1 today. http://ads.osdn.com/?ad_idG21&alloc_id040&op=click _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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RE: [U-Boot-Users] Newbie question - cross
by Michael Bendzick 21 Jul '04

21 Jul '04

(My apologies if this email comes through twice...Outlook didn't seem to do anything useful with it the first time I sent it.) Is there an easy way to update the PPC binutils in ELDK 3.0? Is there an estimated time of arrival for ELDK 3.1? For thoroughness, I'd like to test a patch on an 85xx board, but don't see a good way to do that yet. Thanks, -Michael Bendzick -----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Tuesday, July 20, 2004 10:00 AM To: Jon Loeliger Cc: u-boot-users Subject: Re: [U-Boot-Users] Newbie question - cross In message <1090334884.4910.11.camel(a)blarg.somerset.sps.mot.com> you wrote: > > I currently use this for most of my development: > > gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a) ...whichis identical to the tools used in ELDK 3.0 (which actually is based on YD-3.0). > I have heard a rumor of the current code not compiling > with GCC 2.95, but have not yet had a chance to verify it. > I believe it was a reported problem with an assembler > interpretation of a C macro for the TLB_MAS() handling. Yes. You need binutils 2.14 or later. See "doc/README.mpc85xxads". > You should plan on uprev'ing to a modern GCC, of course. Like ELDK 3.1 :-) Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de Anything free is worth what you pay for it. ------------------------------------------------------- This SF.Net email is sponsored by BEA Weblogic Workshop FREE Java Enterprise J2EE developer tools! Get your free copy of BEA WebLogic Workshop 8.1 today. http://ads.osdn.com/?ad_idG21&alloc_id040&op=click _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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RE: [U-Boot-Users] No more omap1510inn/omap1610inn Maintainer?
by Michael Bendzick 20 Jul '04

20 Jul '04

George- Those two added lines do look good. It would be handy to have access to the second chip of user flash. Do you think it would be good to add some kind of support for the AMD boot flash? It claims to be CFI compliant, though tracking it as it moves through the memory map as the DIP switches are changed would be a bit tough. Perhaps if we updated the config file with #define's for the DIP switch settings, and based on that, it reasons out the correct memory settings for you? -Michael Bendzick -----Original Message----- From: 'George G. Davis' [mailto:gdavis@mvista.com] Sent: Tuesday, July 20, 2004 10:38 AM To: Michael Bendzick Cc: U-Boot-Users (E-mail) Subject: Re: [U-Boot-Users] No more omap1510inn/omap1610inn Maintainer? On Mon, Jul 19, 2004 at 04:35:23PM -0500, Michael Bendzick wrote: > Attached is a patch that makes the omap1510inn board use the > drivers/cfi_flash.c flash driver. > > NOTE to Wolfgang: This patch is NOT for CVS yet. > > Instead, it is for testing by other people to make sure this looks like a > good change to make to this board configuration. If reports are positive, I > will submit a patch for real. It seems to work ok for me. How about adding this: diff -u include/configs/omap1510inn.h include/configs/omap1510inn.h --- include/configs/omap1510inn.h 19 Jul 2004 20:50:28 -0000 +++ include/configs/omap1510inn.h 20 Jul 2004 15:18:48 -0000 @@ -159,7 +159,7 @@ /*----------------------------------------------------------------------- * FLASH and environment organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ #define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) /* addr of environment */ @@ -168,6 +168,7 @@ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (10x faster) */ #define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128kB */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE } /* timeout values are in ticks */ #ifndef CFG_FLASH_CFI_DRIVER FWIW, I'm having problems running U-Boot CVS HEAD on Innovator/OMAP1510 lately. The target hangs during early init. I haven't figured out what's wrong but I'm only able to use U-Boot CVS HEAD on Innovator/OMAP1510 while the BDI2000 is connected. If I disconnect the BDI2000, the darn target hangs during early init. Unfortunately I've no time to debug the early hang problem. But that problem is independent from your CFI patch anyway. Thanks! <snip> -- Regards, George

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RE: [U-Boot-Users] u-boot 1.1.1 & Intel LXT972A
by VanBaren, Gerald (AGRE) 20 Jul '04

20 Jul '04

> -----Original Message----- > From: u-boot-users-admin(a)lists.sourceforge.net > [mailto:u-boot-users-admin@lists.sourceforge.net]On Behalf Of > Knowledge > Seeker > Sent: Tuesday, July 20, 2004 2:40 PM > To: U-Boot List > Subject: [U-Boot-Users] u-boot 1.1.1 & Intel LXT972A > > > I have LXT972A on 852T. From u-boot, I have set mac, ip and netmask. > When I try to ping a ip address on LAN. I get "TX timeout" > > I have traced this. During u-boot init, fec_initialize is called, > which does not do much to comfiugre the hardware. When I ping fec_init > is called in cpu/mpc8xx/fec.c and then it eventually times out in > fec_send function. > > I have ether real running on another computer, which can see arp > packet coming out of fec. > > So at this point what should I look next. > > Help. Completely lost. I understand you are pinging _from_ u-boot. If not, that is a problem. Do you see ARP replies from your ping target? If not, you have a problem with either the target machine or the ARP packet itself (most likely the former: ethereal should tell you about packet problems). Is the FEC interrupt happening? Do you see packets in the FEC Rx queue? If you are seeing ARP replies on the network, you have a ethernet receive problem. Based on others similar questions in the archives, most likely you don't have the Rx clocking configured properly. You might not have the port pins used by the ethernet Rx functions configured properly. You might not have the PHY configured correctly. gvb ****************************************** The information contained in, or attached to, this e-mail, may contain confidential information and is intended solely for the use of the individual or entity to whom they are addressed and may be subject to legal privilege. If you have received this e-mail in error you should notify the sender immediately by reply e-mail, delete the message from your system and notify your system manager. Please do not copy it for any purpose, or disclose its contents to any other person. The views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the company. The recipient should check this e-mail and any attachments for the presence of viruses. The company accepts no liability for any damage caused, directly or indirectly, by any virus transmitted in this email. ******************************************

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RE: [U-Boot-Users] No more omap1510inn/omap1610inn Maintainer?
by Michael Bendzick 20 Jul '04

20 Jul '04

Attached is a patch that makes the omap1510inn board use the drivers/cfi_flash.c flash driver. NOTE to Wolfgang: This patch is NOT for CVS yet. Instead, it is for testing by other people to make sure this looks like a good change to make to this board configuration. If reports are positive, I will submit a patch for real. -Michael Bendzick -----Original Message----- From: 'George G. Davis' [mailto:gdavis@mvista.com] Sent: Friday, July 16, 2004 7:05 PM To: Michael Bendzick Cc: U-Boot-Users (E-mail) Subject: Re: [U-Boot-Users] No more omap1510inn/omap1610inn Maintainer? On Fri, Jul 16, 2004 at 05:11:20PM -0500, Michael Bendzick wrote: > George- > > Mostly I was interested in seeing if he would be interested in submitting a > patch to the omap1510inn board to use the driver/cfi_flash.c driver. I > tested that configuration in developing my recent patch for the file, and > found it worked quite well. I certainly can't complain about writing to > flash about 10x as fast as before. Sounds agreeable. Just submit it and we can all give it a try. : ) > If Kshitij is no longer around, I'm sure he's probably still around but probably quite busy. > and others are interested in trying it out, I'll give it a try. > I can make a patch for the modifications I made to that board configuration. Please do send a patch. > I don't see a reason to stick with the non-central, slow flash writing code > for omap1510inn if a better option is available. Agreed, it sounds good to me to use the common flash driver when/where possible. FWIW, the OMAP1610 H2 uses Intel L18 flash parts. I'm not sure if the common cfi_flash.c driver supports this part yet. -- Regards, George > > -Michael Bendzick > > -----Original Message----- > From: George G. Davis [mailto:gdavis@mvista.com] > Sent: Friday, July 16, 2004 4:43 PM > To: Michael Bendzick > Cc: 'wd(a)denx.de'; U-Boot-Users (E-mail) > Subject: Re: [U-Boot-Users] No more omap1510inn/omap1610inn Maintainer? > > > On Thu, Jul 15, 2004 at 02:44:35PM -0500, Michael Bendzick wrote: > > Wolfgang- > > > > It appears that Kshitij Gupta, the maintainer for the omap1510inn & > > omap1610inn, is no longer reachable at his email address listed in the > > MAINTAINERS file. Is there anyone else that has been closely associated > > with this board, > > I'm casually aquainted with the OMAP1610 H2 and Innovator/OMAP1510. > > What's the problem? > > > or does anyone know of a new way to contact Kshitij? > > Perhaps you can ask questions about those boards here and he or someone > else may answer eventually? I'm sure he is just as busy as the rest us are. > > -- > Regards, > George > > > > -Michael Bendzick > > Systems and Software Engineering > > Logic Product Development > > michael.b(a)logicpd.com > > 612-436-5122 > > www.logicpd.com > > > > > > > > ------------------------------------------------------- > > This SF.Net email is sponsored by BEA Weblogic Workshop > > FREE Java Enterprise J2EE developer tools! > > Get your free copy of BEA WebLogic Workshop 8.1 today. > > http://ads.osdn.com/?ad_id=4721&alloc_id=10040&op=click > > _______________________________________________ > > U-Boot-Users mailing list > > U-Boot-Users(a)lists.sourceforge.net > > https://lists.sourceforge.net/lists/listinfo/u-boot-users > > > ------------------------------------------------------- > This SF.Net email is sponsored by BEA Weblogic Workshop > FREE Java Enterprise J2EE developer tools! > Get your free copy of BEA WebLogic Workshop 8.1 today. > http://ads.osdn.com/?ad_id=4721&alloc_id=10040&op=click > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] PQ2FADS-VR 2nd Ethernet port
by Jihua Cheng 20 Jul '04

20 Jul '04

Wolfgang, U-boot does not automatically support the 2nd Ethernet port for PQ2FADS-VR board. Do you think it is necessary for u-boot to support the two ethernet ports for PQ2FADS-VR automatically? Jihua

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RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
by Jihua Cheng 20 Jul '04

20 Jul '04

Yuli, We finally found the reason of the 2nd ethernet is some hardware parts got some problem. Now, the 2nd ethernet port works fine. I noticed in include\configs\MPC8260ADS.h #define FETHIEN2 0x01000000 should be changed to #define FETHIEN2 0x10000000 /*BCSR3 bit3 FETHIEN2*/ Thanks a lot for your advice and help! charles -----Original Message----- From: Yuli Barcohen [mailto:yuli@arabellasw.com] Sent: Monday, July 19, 2004 10:55 AM To: Jihua Cheng Cc: u-boot-users(a)lists.sourceforge.net Subject: RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet >>>>> Jihua Cheng writes: Jihua> Yuli, Thanks very much for your instruction. It seems I move Jihua> further, however I still do not make Ethernet port2 works Jihua> fine. Following is the my modification and the symptom. Jihua> 1) I changed the BCSRs bit FETHIEN2 to 0, reset the Ethernet Jihua> Port2 (Phy addr 3) to enable auto-negatiation. Now, the Jihua> MII reg0 = 0x3100, reg1=0x782D. IP Addr 172.18.100.54 Jihua> does exist. when I enable FCC2 and ping 172.18.100.54, Jihua> ping success. When I "ping 172.18.100.54", the message Jihua> "fex: tx error" is gone. It seems TX is fine. Is it Jihua> correct? Probably it is. Try a sniffer (ethereal, tcpdump) on the host to see if anything is transmitted by the board. Jihua> 2) However, "ping 172.18.100.54" fail. the message "ping Jihua> failed; host 172.18.100.54" is not alive. FCC3 Rx Clock Jihua> is set to CLK15. PortB4~17, PortC16~17 are enabled. Why do you think that the problem is still at the hardware level? What are the board's IP address, MAC address, subnet mask, etc. (just type printenv). You write that 172.18.100.54 exists but you don't write anything about the host to which this address belongs. Is it a Linux machine? Does it respond to pings at all? What's about subnets? There are too many possible reasons for ping failure. [...code deleted...] -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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[U-Boot-Users] POST: 8xx cache basic test #2
by Scott McNutt 20 Jul '04

20 Jul '04

Hi All, I'm writing POST cache tests for MPC82xx. I'm trying to maintain the same "objectives" of the tests found in post/cache_8xx.S, but I need some clarification: Basic test #2 (post/cache_8xx.S) does the following: 1. turn on the data cache 2. switch the data cache to write-back mode 3. invalidate the data cache 4. write the zero pattern to a cached area 5. turn off the data cache 6. write the negative pattern to the area 7. turn on the data cache 8. read the area (confirm negative pattern) At step 6, the data cache is disabled, so it operates as if accessing a cache-inhibited region. i.e. - the data is written to memory, but not to cache, and the cache status bits are not affected. Clarification needed here: At step 8, I would expect to read the zero pattern unless disabling/enabling the data cache affects the status bits. What's actually happening? Thanks, --Scott

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[U-Boot-Users] Newbie question - cross
by Reza Salehi 20 Jul '04

20 Jul '04

Hello, I am newbie to u-boot and linux. I am working on a board that uses MPC8540 and my host environment is Red Hat 9.0. I have a u-boot (ver 1.0.1) that works fine on my board. However, this u-boot was built using the toolchain provided by Metroworks(gcc version 2.95.3) and this toolchain is not under GPL! My question is can someone point me to a GPL toolchain that I can use to build the u-boot for MPC8540? I have already tried using the croos-toolchain provided from kegel.com (gcc-3.3.2-glibc-2.3.2). I use this toolchain to build my linux image and it works fine. However, the u-boot I built using this toolchain does not work! Unfortunately, I don't have a BDI debugger to be able to see how far the u-boot runs before it hangs! Thanks in advance for your help, Reza. __________________________________ Do you Yahoo!? Vote for the stars of Yahoo!'s next ad campaign! http://advision.webevents.yahoo.com/yahoo/votelifeengine/

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RE: [U-Boot-Users] LITE5200 board: Bus Fault with 2 network cards
by Glenn Heard 20 Jul '04

20 Jul '04

Wolfgang, As it happens, I'm adding a board entry for the Cogent CSB337. I'm new to gdb debugging and am unsure on setting up the bdi2000 for this. I have followed the steps in the bdi manual but they are quite lacking. Do you have anything written on the typical bdi setup for debugging u-boot? Glenn Heard gheard(a)zoominternet.net Software Engineer gheard(a)altronicinc.com Altronic Inc. www.altronicinc.com ICQ: 123194600 --- A politician is a person who can tell you to go to hell and make you feel good to be on your way. > -----Original Message----- > From: u-boot-users-admin(a)lists.sourceforge.net > [mailto:u-boot-users-admin@lists.sourceforge.net] On Behalf > Of Wolfgang Denk > Sent: Tuesday, July 20, 2004 9:38 AM > To: Olivier Singla > Cc: u-boot-users(a)lists.sourceforge.net > Subject: Re: [U-Boot-Users] LITE5200 board: Bus Fault with 2 > network cards > > The recommended (most efficient) way to debug the system is > with a BDI, though. > > Best regards, > > Wolfgang Denk > > -- > Software Engineering: Embedded and Realtime Systems, Embedded Linux > Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: > wd(a)denx.de If it has syntax, it isn't user friendly. > > > ------------------------------------------------------- > This SF.Net email is sponsored by BEA Weblogic Workshop > FREE Java Enterprise J2EE developer tools! > Get your free copy of BEA WebLogic Workshop 8.1 today. > http://ads.osdn.com/?ad_idG21&alloc_id040&op=ick > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users >

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[U-Boot-Users] LITE5200 board: Bus Fault with 2 network cards
by Olivier Singla 20 Jul '04

20 Jul '04

Hi, I use a Lite5200 board (ref. board from Motorola). With the two PCI network cards I tried (which I would want to use under Linux 2.4.25), u-boot crashes: U-Boot 1.1.2 (Jul 12 2004 - 20:10:35) CPU: MPC5200 v1.2 at 396 MHz Bus 132 MHz, IPB 132 MHz, PCI 33 MHz Board: Motorola MPC5200 (IceCube) I2C: 85 kHz, ready DRAM: 64 MB FLASH: 16 MB PCI: Bus Dev VenId DevId Class Int Bus Fault @ 0x03fac1e8, fixup 0x00000000 Machine check in kernel mode. Caused by (from msr): regs 03f5ad68 Unknown values in msr NIP: 03FAC1E8 XER: 00000000 LR: 03FAC1DC REGS: 03f5ad68 TRAP: 0200 DAR: 00000000 MSR: 00003000 EE: 0 PR: 0 FP: 1 ME: 1 IR/DR: 00 GPR00: 03FAC1DC 03F5AE58 00000000 FFFFFFFF FFFFFFFF 00000000 00000000 003325E9 GPR08: 03F8FA50 50AEF503 03FCB950 00000000 44004004 00000000 03FBA000 03F6B000 GPR16: 00000000 00000000 00000000 00000000 00000000 00000001 00000000 00000000 GPR24: 00000000 00000001 00000000 03F5AE88 F0000DF8 03F5AF84 03F5AEA8 0000000E Call backtrace: machine check (I tried 1.1.1 first and then gave a try to the cvs version). One network card I tried is the SMC9452TX (Marvell chip). Two others PCI cards, not network (Maxtor SATA and USB-2.0) did not bring any issue with u-boot 1.1.1 Is there a known issue with the PCI on the MPC5200, and more specifically with PCI network cards ? Or is-that with the u-boot PCI implementation for this board ? I tried to disable the PCI from the u-boot/IceCube config file, but then u-boot hangs up... Any suggestion ? Best regards, Olivier

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[U-Boot-Users] ARM: initial ramdisk
by llandre 20 Jul '04

20 Jul '04

I have a doubt about initial ramdisk placement. I'm working with Cogent CSB336. The 8MB Flash starts at 0x1000:0000. The initial cramfs ramdisk image was generated as follows: mkimage -n 'RAM disk' -A arm -O linux -T ramdisk -C none -a 9000000 -e 9000000 -d initrd.cramfs initrd.cramfs.u-boot The image has been stored at 0x1020:0000. I expect that U-Boot, before launching the kernel, copies the cramfs image from 0x1020:0000 to 0x0900:0000 but it does not. When the kernel boots, it can not mount the cramfs image because it is placed outside the RAM boundaries: Uncompressing Linux..................................................... done, booting the kern el. Linux version 2.6.7-imx3 (llandre@LinuxServer) (gcc version 3.3.2) #2 Thu Jul 15 18:43:28 CEST 2004 CPU: ARM920Tid(wb) [41129200] revision 0 (ARMv4T) ... Machine: Cogent CSB336 initrd (0x10200040 - 0x105a6040) extends beyond physical memory - disabling initrd Memory policy: ECC disabled, Data cache writeback ... Kernel command line: root=/dev/ram rw ip=192.168.0.85:192.168.0.23::255.255.255.0:CSB336:eth0:o ff panic=1 console=ttySMX0,115200 PID hash table entries: 256 (order 8: 2048 bytes) Memory: 32MB = 32MB total Memory: 30744KB available (1428K code, 185K data, 56K init) Calibrating delay loop... 75.16 BogoMIPS ... RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize loop: loaded (max 8 devices) Using deadline io scheduler ... Kernel panic: VFS: Unable to mount root fs on ram0 <0>Rebooting in 1 seconds.. Am I missing something? Regards, llandre DAVE Electronics System House - R&D Department www.dave-tech.it

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[U-Boot-Users] Environment Flash Sector Protection w/ cfi_flash.c?
by Michael Bendzick 20 Jul '04

20 Jul '04

I have noticed that when using the cfi_flash.c driver that the environment sector (the second sector, counting from one) in flash is not protected by default. When I was working with the omap1510inn board using its original flash.c driver, it would protect the environment in flash_init. Would it be good to add default to protection for the environment sector to cfi_flash.c? -Michael Bendzick Systems and Software Engineering Logic Product Development michael.b(a)logicpd.com 612-436-5122 www.logicpd.com

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[U-Boot-Users] Patch: Fix tools building in Cygwin environment
by Yuli Barcohen 19 Jul '04

19 Jul '04

Host tools in tools/ sub-directory fail to compile in the latest Cygwin environment. This failure caused by unnecessary __WIN32__ definition and incorrect header files search order which can affect other platforms too. The attached patch fixes the problem. CHANGELOG - Fix host tools building in Cygwin environment - Fix header files search order for host tools -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ======================================================================== Index: tools/Makefile =================================================================== RCS file: /home/CVS/u-boot/u-boot/tools/Makefile,v retrieving revision 1.1.1.7 diff -p -u -r1.1.1.7 Makefile --- tools/Makefile 22 Dec 2003 14:36:12 -0000 1.1.1.7 +++ tools/Makefile 19 Jul 2004 19:56:56 -0000 @@ -96,12 +96,10 @@ endif # ifeq ($(HOSTOS),cygwin) SFX = .exe -HOST_CFLAGS += -D__WIN32__ else SFX = endif - # # Include this after HOSTOS HOSTARCH check # so that we can act intelligently. @@ -111,7 +109,7 @@ include $(TOPDIR)/config.mk # # Use native tools and options # -CPPFLAGS = -I../include -I.. -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC +CPPFLAGS = -idirafter ../include -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC CFLAGS = $(HOST_CFLAGS) $(CPPFLAGS) -O AFLAGS = -D__ASSEMBLY__ $(CPPFLAGS) CC = $(HOSTCC)

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Re: [U-Boot-Users] [PATCH] Part 1 of 2 MPC85XXADS-20040716.patch-1 for TLB/DDR
by Jon Loeliger 19 Jul '04

19 Jul '04

On Fri, 2004-07-16 at 16:51, Wolfgang Denk wrote: > In message <1090009011.23992.5.camel(a)blarg.somerset.sps.mot.com> you wrote: > > > > Here is a patch for the MPC8540/8560ADS and STXGP3 boards > > that is primarily to support larger DDR memories up to 2G. > > Can you please think of a better subject line for your patches? What would you like? I meant to convey that: - It was a [PATCH] - It was for the MPC85XXADS boards, - A specific patch release identified by date, - That it came in multiple parts, in this case -1 and -2, - That its primary purpose was TLB/DDR related Most of that information is geared towards potential searching of the archives, your information, my internal logging, and hopefully some form of "quick identification". Where did I go wrong? > I find it extremely confusing when I first get a patch titled: > > [PATCH] MPC85XXADS-20040716.patch for TLB/DDR > > and then another one (split in 2 parts) titled > > [PATCH] MPC85XXADS-20040716.patch-1 for TLB/DDR > > I tend to assume that these are redundand, and dump one of them. In fact, I was 5K over the mailing list size limit and was informed that it wasn't sent to the list. Last time I sent something to the list that was over the size limit, you specifically asked me to resend it in multiple parts. So this time, that is exactly what I did. So yes, it was redundant and one of the patches, the first, was expected to be /dev/nulled. In the second posts, I clearly indicated that it was a re-send of the earlier one due to size limit problems. > Looking closer, I find that at least one subject is totally wrong. My apologies. > > Wolfgang Denk jdl

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RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
by Jihua Cheng 19 Jul '04

19 Jul '04

Yuli, Thanks so much for your help. Let me explan the experiments which I did. 1) 172.18.100.54 is a redhat linux. Netmask is 255:255:255:0. I verified by use of ifconfig command. 1) Here is the environment variable for PQ2FADS-VR. => printenv bootdelay=5 baudrate=38400 ethaddr=00:30:d4:00:01:02 g=bootm 100000 ipaddr=172.18.100.99 serverip=172.18.100.54 stdin=serial stdout=serial stderr=serial 2) I use arp command and found "172.18.100.99 ether 00:30:d4:00:01:02 C eth0" is in the ARP display. When I use ifconfig, I found RX packets and Tx packets increase the same number. It seems Linux host received the ping from Pq2FADS-VR board and replied. 4) Why I suspect some hardware setting is probabily quite right is I use same U-boot environment parameter and linux machine(172.18.100.54) for ethernet port1 with FCC2, the ping works fine. I only the u-boot to use FCC3 for ethernet port2, ping fails. 5) I check the RxBD status. I found the Empty bit is 1, means no data received in Rx. Could I suspect something is wrong for FCC3 Rx portion? Could you please tell me what I must to check, or what I missed? I greatly appreciate your help. Reagrds, Charles -----Original Message----- From: Yuli Barcohen [mailto:yuli@arabellasw.com] Sent: Monday, July 19, 2004 10:55 AM To: Jihua Cheng Cc: u-boot-users(a)lists.sourceforge.net Subject: RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet >>>>> Jihua Cheng writes: Jihua> Yuli, Thanks very much for your instruction. It seems I move Jihua> further, however I still do not make Ethernet port2 works Jihua> fine. Following is the my modification and the symptom. Jihua> 1) I changed the BCSRs bit FETHIEN2 to 0, reset the Ethernet Jihua> Port2 (Phy addr 3) to enable auto-negatiation. Now, the Jihua> MII reg0 = 0x3100, reg1=0x782D. IP Addr 172.18.100.54 Jihua> does exist. when I enable FCC2 and ping 172.18.100.54, Jihua> ping success. When I "ping 172.18.100.54", the message Jihua> "fex: tx error" is gone. It seems TX is fine. Is it Jihua> correct? Probably it is. Try a sniffer (ethereal, tcpdump) on the host to see if anything is transmitted by the board. Jihua> 2) However, "ping 172.18.100.54" fail. the message "ping Jihua> failed; host 172.18.100.54" is not alive. FCC3 Rx Clock Jihua> is set to CLK15. PortB4~17, PortC16~17 are enabled. Why do you think that the problem is still at the hardware level? What are the board's IP address, MAC address, subnet mask, etc. (just type printenv). You write that 172.18.100.54 exists but you don't write anything about the host to which this address belongs. Is it a Linux machine? Does it respond to pings at all? What's about subnets? There are too many possible reasons for ping failure. [...code deleted...] -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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[U-Boot-Users] U-boot with IBM-PPC440GP - questions
by Helio Fujimoto 19 Jul '04

19 Jul '04

Hi, there, (please answer with copy to me, because I am not subscribed to the mailing list) My company is starting to develop an IBM-PPC440GP based board, and, as it is a new processor for me, I am thinking on using the u-boot as the boot loader. I installed the source code and I generated the image for ebony (IBM-PPC440GP eval board), though I don't have it. I analysed the features the packet have, and it seems to have everything I need. However, I would like to ask some questions before deciding for it: (1) - Did anyone use the U-boot with the IBM-440GP? If so, could you give me an idea of the boot time, both with the default configuration and with an optimized configuration? (2) - The binary file (u-boot.bin) generated was too big for me (almost half Mbytes). Could it be smaller, how? Is it already compressed? (3) - My board uses the LXT972 as the Ethernet transceiver (PHY). Does the boot loader support it? (4) - I will use the Montavista Linux as operating system. Have anyone done that already? How hard is it to integrate the U-boot with it? (5) - Will I have to publish the changes which are specific to my board, if I use the u-boot? Thank you, Helio Fujimoto.

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RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
by Jihua Cheng 19 Jul '04

19 Jul '04

Yuli, Thanks very much for your instruction. It seems I move further, however I still do not make Ethernet port2 works fine. Following is the my modification and the symptom. 1) I changed the BCSRs bit FETHIEN2 to 0, reset the Ethernet Port2 (Phy addr 3) to enable auto-negatiation. Now, the MII reg0 = 0x3100, reg1=0x782D. IP Addr 172.18.100.54 does exist. when I enable FCC2 and ping 172.18.100.54, ping success. When I "ping 172.18.100.54", the message "fex: tx error" is gone. It seems TX is fine. Is it correct? 2) However, "ping 172.18.100.54" fail. the message "ping failed; host 172.18.100.54" is not alive. FCC3 Rx Clock is set to CLK15. PortB4~17, PortC16~17 are enabled. I added a debug message to fec_recv(...) in cpu\mpc8260\ether_fcc.c, as follows. static int fec_recv(struct eth_device* dev) { int length; for (;;) { if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { length = -1; #ifdef ET_DEBUG printf("%s::%s Nothing Rcv\n", __FILE__, __FUNCTION__); /*Added Debug*/ #endif break; /* nothing received - leave for() loop */ } ..... } I got "ether_fcc.c::fec_recv Nothing Rcv" message. The following few lines for the CPM clock route in added in include\configs\MPC8260ADS.h: #if (CONFIG_ETHER_INDEX == 3) /* * - Rx-CLK is CLK15 * - Tx-CLK is CLK16 * - Select bus for bd/buffers (see 28-13) * - Full duplex */ # define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) # define CFG_CPMFCR_RAMTYPE 0 # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) #endif /* CONFIG_ETHER_INDEX */ Ethernet port2 dedicated Pin setting for PortB 4~17 and PortC 17~17 are enabled. The definition in board\mpc8260ads\mpc8260ads.c is shown as follows: /* Port B configuration */ { /* conf ppar psor pdir podr pdat */ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV*/ /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ }, /* Port C */ { /* conf ppar psor pdir podr pdat */ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* RX Clk15*/ /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* Tx Clock (CLK16) */ /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ }, Thanks a lot! Regards, Charles -----Original Message----- From: Yuli Barcohen [mailto:yuli@arabellasw.com] Sent: Monday, July 19, 2004 8:47 AM To: Jihua Cheng Cc: u-boot-users(a)lists.sourceforge.net Subject: RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet >>>>> Jihua Cheng writes: Jihua> Yuli, Thanks very much! Jihua> Here is the sympotoms. Jihua> Based on the PQ2FADS-VR schematic, I route parallel portC pin Jihua> PC17(Clk 15 for RX) and pin PC16(Clk16 for TX) for Jihua> FCC3. PortB PB4~PB17 are enabled for FCC3. When I use ping Jihua> command, I got "fec: tx error!" message in the console. I Jihua> found the message is from fec_send(...) at Jihua> cpu/mpc8260/ether_fcc.c. It seems CPM did not send out the Jihua> data to Phy. This usually indicates that there is no Tx clock, probably because the PHY does not provide it. Jihua> 1) I check BCSR3. Both FETHIEN2 and FETH2_RST are 1. FETHIEN2=1 means that the PHY is isolated after power-up. This is not what you want. Set FETHIEN2 to zero and reset PHY by toggling FETH2_RST. Jihua> 2) Phy Register seems OK (Reg0 = 0x2100, reg1 = 0x7809). It's not completely OK because auto-negotiation is disabled. It's can be a result of above mentioned isolation. Check what happens after enabling the PHY, and set as necessary. Jihua> 3) I check PortB PB4~PB17. Dedicated Pin setting seems OK. Jihua> Where do I need to check? Jihua> I appreciate your help! -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
by Jihua Cheng 19 Jul '04

19 Jul '04

Yuli, Thanks very much! Here is the sympotoms. Based on the PQ2FADS-VR schematic, I route parallel portC pin PC17(Clk 15 for RX) and pin PC16(Clk16 for TX) for FCC3. PortB PB4~PB17 are enabled for FCC3. When I use ping command, I got "fec: tx error!" message in the console. I found the message is from fec_send(...) at cpu/mpc8260/ether_fcc.c. It seems CPM did not send out the data to Phy. 1) I check BCSR3. Both FETHIEN2 and FETH2_RST are 1. 2) Phy Register seems OK (Reg0 = 0x2100, reg1 = 0x7809). 3) I check PortB PB4~PB17. Dedicated Pin setting seems OK. Where do I need to check? I appreciate your help! Regards, Jihua -----Original Message----- From: Yuli Barcohen [mailto:yuli@arabellasw.com] Sent: Saturday, July 17, 2004 3:53 PM To: Jihua Cheng Cc: u-boot-users(a)lists.sourceforge.net Subject: Re: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet >>>>> Jihua Cheng writes: Jihua> Hi, I have a PQ2FADS-VR board which u-boot 1.0.0 Upgrade to the top of CVS before you start changing anything. 1.0.0 is too old. Jihua> runs well. Ethernet port1(FCC2) and Serial port1(SCC1) run Jihua> pretty well. Jihua> I am trying to make Ethernet port2(FCC3) work. In the Jihua> configuration file mpc8260ads.h, I added [...code deleted...] Jihua> And in board\mpc8260ads\mpc8260ads.c, I enabled the parall Jihua> portC pin PC16 and PC17; PortB PB4~PB17. The new definition Jihua> for portB and portC are [...code deleted...] Jihua> However, Ethernet port2 on SCC3 still does not work. Jihua> Could anyone tell me where I am wrong, or what I missed? First of all, "does not work" is not good problem description. Could you explain what happens exactly? On this board, there are several more things which can require initialisation. Check BCSR and PHY. If you upgrade to CVS top, you'll see what's done for FCC2. To check PHY state, you can use mii command. -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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[U-Boot-Users] PQ2FADS-VR 2nd Ethernet
by Jihua Cheng 18 Jul '04

18 Jul '04

Hi, I have a PQ2FADS-VR board which u-boot 1.0.0 runs well. Ethernet port1(FCC2) and Serial port1(SCC1) run pretty well. I am trying to make Ethernet port2(FCC3) work. In the configuration file mpc8260ads.h, I added #undef CONFIG_ETHER_INDEX #define CONFIG_ETHER_INDEX 3 #if (CONFIG_ETHER_INDEX == 3) # define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) /* Clk15 and Clk16 for Rx and Tx*/ # define CFG_CPMFCR_RAMTYPE 0 # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) #endif And in board\mpc8260ads\mpc8260ads.c, I enabled the parall portC pin PC16 and PC17; PortB PB4~PB17. The new definition for portB and portC are /* Port B configuration */ { /* conf ppar psor pdir podr pdat */ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ }, /* Port C */ { /* conf ppar psor pdir podr pdat */ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* RX Clk15 jhc&m*/ /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* Tx Clock (CLK16) */ /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ }. However, Ethernet port2 on SCC3 still does not work. Could anyone tell me where I am wrong, or what I missed? Thanks a lot! Regards, Charles

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[U-Boot-Users] Re: Re: Unable to send keys inputs from keyboard to u-boot
by Jordan Foo 17 Jul '04

17 Jul '04

Yup disabling HUSH definitely gave me less code to tackle through. Though it did went back to the same problem. Since it now is not running HUSH any more, it runs the else section of the code and goes to the line len = readline (CFG_PROMPT); It appears to have stopped in c = getc(); of the readline() function in common/main.c. From the output that I've got Running: assigning len IZARUS> Running: Entering infinit loop of readline() Running: WATCHDOG_RESET() Running: Assigning c = getc() Running: Entering Case statements Running: WATCHDOG_RESET() Running: Assigning c = getc() and then it gets not further after the second time round the infinite loops in readline and no manual inputs are being accepted. could it be that I've done something wrong somewhere before this all actually began? Many thanks, Jordan

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[U-Boot-Users] Using ELF File in gdb
by Knowledge Seeker 17 Jul '04

17 Jul '04

Wolfgang, Regarding my problem of gdb not finding certain source file (debugging u-boot remotely) which I posted few days ago. You suggested to use ELF binary in ddd (ppc_8xx-gdb). what would be the sequence of steps. I try following GNU DDD 3.3.1 (i686-pc-linux-gnu), by Dorothea L(gdb) file /sw/bootcode/u-boot-1.1.1/u-boot (gdb) Function "" not defined. (gdb) target remote bdi:2001 0xfff00100 in ?? () (gdb) set $pc = 0x02000100 (gdb) break start.S:574 Breakpoint 1 at 0x2002324: file /sw/bootcode/u-boot-1.1.1/cpu/mpc8xx/start.S, line 574. (gdb) break fec.c:212 Breakpoint 2 at 0x2017640: file fec.c, line 212. (gdb) stepi (gdb) cont It still has problem finding fec.c, serial.c files.

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RE: [U-Boot-Users] No more omap1510inn/omap1610inn Maintainer?
by Michael Bendzick 17 Jul '04

17 Jul '04

George- Mostly I was interested in seeing if he would be interested in submitting a patch to the omap1510inn board to use the driver/cfi_flash.c driver. I tested that configuration in developing my recent patch for the file, and found it worked quite well. I certainly can't complain about writing to flash about 10x as fast as before. If Kshitij is no longer around, and others are interested in trying it out, I can make a patch for the modifications I made to that board configuration. I don't see a reason to stick with the non-central, slow flash writing code for omap1510inn if a better option is available. -Michael Bendzick -----Original Message----- From: George G. Davis [mailto:gdavis@mvista.com] Sent: Friday, July 16, 2004 4:43 PM To: Michael Bendzick Cc: 'wd(a)denx.de'; U-Boot-Users (E-mail) Subject: Re: [U-Boot-Users] No more omap1510inn/omap1610inn Maintainer? On Thu, Jul 15, 2004 at 02:44:35PM -0500, Michael Bendzick wrote: > Wolfgang- > > It appears that Kshitij Gupta, the maintainer for the omap1510inn & > omap1610inn, is no longer reachable at his email address listed in the > MAINTAINERS file. Is there anyone else that has been closely associated > with this board, I'm casually aquainted with the OMAP1610 H2 and Innovator/OMAP1510. What's the problem? > or does anyone know of a new way to contact Kshitij? Perhaps you can ask questions about those boards here and he or someone else may answer eventually? I'm sure he is just as busy as the rest us are. -- Regards, George > > -Michael Bendzick > Systems and Software Engineering > Logic Product Development > michael.b(a)logicpd.com > 612-436-5122 > www.logicpd.com > > > > ------------------------------------------------------- > This SF.Net email is sponsored by BEA Weblogic Workshop > FREE Java Enterprise J2EE developer tools! > Get your free copy of BEA WebLogic Workshop 8.1 today. > http://ads.osdn.com/?ad_id=4721&alloc_id=10040&op=click > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] Compilation error for lubbock
by Zou Xiangyu-W15716 16 Jul '04

16 Jul '04

Hello, After checking out the latest u-boot source via CVS this week, I try to compile it for "lubbock" with pre-built arm-linux-gnu toolchain (arm-linux-gcc 3.4.0). Undefined symbol in lib_arm/board.c (Revision: 1.29, Sun Jul 11 18:10:31 2004 UTC (3 days, 22 hours ago) by wdenk ) board.c: In function `start_armboot': board.c:257: error: `PAGE_SIZE' undeclared (first use in this function) board.c:257: error: (Each undeclared identifier is reported only once board.c:257: error: for each function it appears in.) make[1]: *** [board.o] Error 1 make: *** [lib_arm/libarm.a] Error 2 I also notice "PAGE_SIZE" was introduced after u-boot (1.1.1) Assuming this error is not due to user error, has the latest CVS source been compiled for all supported boards? Or it is "user be aware"? Thanks for the help. Xiangyu Zou mailto:Xiangyu.Zou@Motorola.com

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