July 2004 - U-Boot

[U-Boot-Users] New NAND code
by Stefan Roese 10 Aug '06

10 Aug '06

Hi! I was just wondering about state of the NAND code. When I remember correctly a pretty big rewrite was done but not commited yet. Is the last patch sent to this list from Pantelis Antoniou on 5th May still the latest version? Best regards, Stefan

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[U-Boot-Users] [PATCH] support for CF/IDE on PCMCIA for PXA25X
by Christian Pell 13 Aug '05

13 Aug '05

Hi, I tried this with some different CFs with FAT file-systems on them. There is a README in the patch itself that goes in documentation directory. Bye, -- Christian Pellegrin <chri(a)ascensit.com>, <c.pellegrin(a)eurotech.it>, <chri(a)infis.univ.ts.it>, <c.pellegrin(a)exadron.com>

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[U-Boot-Users] mkimage for DOS
by Dave Westwood 10 Jun '05

10 Jun '05

long shot really, but does anyone have a working executable mkimage for DOS or a dos window in windows (don't flame me for using windows !!)

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Re: [U-Boot-Users] Support for Samsung 1Giga bit NAND device
by Laurent Mohin 01 Jun '05

01 Jun '05

Andy, U-boot 1.1.0 doesn't provide support for NAND flash with a page size of 2K-byte instead of 512 byte (and you're right, theses devices require special handling). Pantelis Antoniou submitted a patch on 2004-04-30 which seems to manage these new chips, but I don't think it has been added to the latest CVS tree. By the way, Samsung also offer 1 Giga bit devices with a 512 byte page size (K9K1G08UOM - Manufacturer ID : 0xEC, Chip ID: 0x79). Hope this helps, Laurent Andy Hawkins <a.hawkins(a)cabletime.com> Sent by: u-boot-users-admin(a)lists.sourceforge.net 14/06/04 13:40 To: u-boot-users(a)lists.sourceforge.net cc: Subject: [U-Boot-Users] Support for Samsung 1Giga bit NAND device Hi, Can anyone tell me if U-Boot has support for the Samsung 1 Giga Bit NAND devices (Manufacturer ID: 0xec, Chip ID: 0xf1)? I understand these devices have an unusually large block size, that needs special handling. Is this correct? Thanks. Andy ------------------------------------------------------- This SF.Net email is sponsored by the new InstallShield X. >From Windows to Linux, servers to mobile, InstallShield X is the one installation-authoring solution that does it all. Learn more and evaluate today! http://www.installshield.com/Dev2Dev/0504 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] Environment in flash rather than EEProm
by Andy Hawkins 11 Feb '05

11 Feb '05

Hi all I'm using a PPChameleonEVB, and am trying to move the u-boot environment into flash. I've modified the include/configs/PPChameleon.h file as follows: #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR 0xFFFFA000 #define CFG_ENV_OFFSET (CFG_ENV_ADDR - 0xFFFC0000) #define CFG_ENV_SIZE 0x2000 I've added some debugging into the section where it reads the environment, and I'm seeing the following: U-Boot 1.0.2-adh-2004/03/29 (Mar 30 2004 - 13:40:38) CPU: IBM PowerPC 405EP Rev. B at 133.333 MHz (PLB=133, OPB=66, EBC=33 MHz) IIC Boot EEPROM disabled PCI async ext clock used, internal PCI arbiter enabled 16 kB I-Cache 16 kB D-Cache Board: ### No HW ID - assuming PPChameleonEVB I2C: ready DRAM: 32 MB Top of RAM usable for U-Boot at: 02000000 Reserving 189k for U-Boot at: 01fd0000 Reserving 256k for malloc() at: 01f90000 Reserving 128 Bytes for Board Info at: 01f8ff80 Reserving 48 Bytes for Global Data at: 01f8ff50 Stack Pointer at: 01f8ff38 New Stack Pointer is: 01f8ff38 Now running in RAM - U-Boot at: 01fd0000 FLASH: 4 MB env_relocate[204] offset = 0x2010000 env_relocate[216] embedded ENV (before reloc) at fffd9474 env_relocate[218] embedded ENV (after reloc) at 01fe9474 U-Boot relocated to 01fd0000 NAND:Probing at 0xff000000 32 MB ### main_loop entered: bootdelay=5 ### main_loop: bootcmd="<UNDEFINED>" => As you can see, the address of the environment before relocation is 0xfffd9474. Shouldn't this be 0xFFFFA000? Is there anything else I need to do to force the location of the environment into the required place? It looks like the address of the environment is based on the location of the 'environment' variable in common/environment.c. Do I need to change the LD script to force this variable to a certain location? If so, can anyone help with what I need to do (I'm not familiar with LD scripts yet). Many thanks. Andy

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[U-Boot-Users] Ping issue
by Vidya S 07 Dec '04

07 Dec '04

Hi, I am using smc91111.c driver of u-boot. all my network functionalities are working well. i am able to ping an other ip address and i get a message that the host is alive or not. Only problem is, when someone pings the target ip (my network card ip), it says destination not reachable. Is this really a problem? if so, pls help me solving it. regards vidya

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[U-Boot-Users] Generating b-records for DragonBall i.MX
by Steven Scholz 10 Oct '04

10 Oct '04

Hi there, I just hacked a simple script that converts u-boot.bin into a text file containg processor init code, SynchFlash programming code and U-Boot data in form of so called b-records. This can be used to programm U-Boot into (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L 0AFE1F3410202E2E2E000000002073756363656564/ 0AFE1F44102E0A0000206661696C656420210A0000/ 0AFE100000 ... MX1ADS Sync-flash Programming Utility v0.5 2002/08/21 Source address (stored in 0x0AFE0000): 0x0A000000 Target address (stored in 0x0AFE0004): 0x0C000000 Size (stored in 0x0AFE0008): 0x0001A320 Press any key to start programming ... Erasing ... Blank checking ... Programming ... Verifying flash ... succeed. Programming finished. So no need for a BDI2000 anymore... ;-) This is working on my MX1ADS eval board. Hope this could be useful for someone. (Maybe we even want to include this into the tools directory.) Steven

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[U-Boot-Users] [PATCH] MPC85XX i2c patches
by Jon Loeliger 28 Sep '04

28 Sep '04

Wolfgang, Here is a patch for the cpu/mpc85xx/i2c.c file that converts some long reads into byte reads. I also removed the superfluous DEB() macro. Since this file was all crummy 2-space indented, I TAB-ified it all. Hope that is OK. * Patch by Jon Loeliger, 15-Jul-2004: Fixes MPC85xx I2C driver: - Matt McClintock's conversion from long to byte IO - Remove redundant DEB() debug macro. TAB indenting. This should apply with a patch -p2, likely. Thanks, jdl --- u-boot-public-cvs/u-boot-20040712/cpu/mpc85xx/i2c.c 2003-10-15 18:53:51.000000000 -0500 +++ internal-development/u-boot-pq3-merged/cpu/mpc85xx/i2c.c 2004-07-14 10:57:36.000000000 -0500 @@ -30,78 +30,57 @@ #include <common.h> #include <command.h> - -#define DEBUG - -#if defined(DEBUG) -#define DEB(x) x -#else -#define DEB(x) -#endif +#include <asm/io.h> #ifdef CONFIG_HARD_I2C #include <i2c.h> #define TIMEOUT (CFG_HZ/4) -#define I2C_Addr ((unsigned *)(CFG_CCSRBAR + 0x3000)) +#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000)) #define I2CADR &I2C_Addr[0] -#define I2CFDR &I2C_Addr[1] -#define I2CCCR &I2C_Addr[2] -#define I2CCSR &I2C_Addr[3] -#define I2CCDR &I2C_Addr[4] -#define I2CDFSRR &I2C_Addr[5] +#define I2CFDR &I2C_Addr[4] +#define I2CCCR &I2C_Addr[8] +#define I2CCSR &I2C_Addr[12] +#define I2CCDR &I2C_Addr[16] +#define I2CDFSRR &I2C_Addr[20] #define I2C_READ 1 #define I2C_WRITE 0 -/* taken from linux include/asm-ppc/io.h */ -inline unsigned in_le32(volatile unsigned *addr) +void +i2c_init(int speed, int slaveadd) { - unsigned ret; + /* stop I2C controller */ + writeb(0x0, I2CCCR); - __asm__ __volatile__("lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} + /* set clock */ + writeb(0x3f, I2CFDR); -inline void out_le32(volatile unsigned *addr, int val) -{ - __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); -} + /* set default filter */ + writeb(0x10,I2CDFSRR); -#define writel(val, addr) out_le32(addr, val) -#define readl(addr) in_le32(addr) + /* write slave address */ + writeb(slaveadd, I2CADR); -void -i2c_init(int speed, int slaveadd) -{ - /* stop I2C controller */ - writel (0x0, I2CCCR); - /* set clock */ - writel (0x3f, I2CFDR); - /* set default filter */ - writel (0x10,I2CDFSRR); - /* write slave address */ - writel (slaveadd, I2CADR); - /* clear status register */ - writel (0x0, I2CCSR); - /* start I2C controller */ - writel (MPC85xx_I2CCR_MEN, I2CCCR); + /* clear status register */ + writeb(0x0, I2CCSR); + + /* start I2C controller */ + writeb(MPC85xx_I2CCR_MEN, I2CCCR); } static __inline__ int i2c_wait4bus (void) { - ulong timeval = get_timer (0); + ulong timeval = get_timer (0); - while (readl (I2CCSR) & MPC85xx_I2CSR_MBB) - if (get_timer (timeval) > TIMEOUT) - return -1; + while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) { + if (get_timer (timeval) > TIMEOUT) { + return -1; + } + } return 0; } @@ -109,153 +88,151 @@ static __inline__ int i2c_wait (int write) { - u32 csr; - ulong timeval = get_timer (0); + u32 csr; + ulong timeval = get_timer (0); - do - { - csr = readl (I2CCSR); - - if (!(csr & MPC85xx_I2CSR_MIF)) - continue; - - writel (0x0, I2CCSR); - - if (csr & MPC85xx_I2CSR_MAL) - { - DEB(printf ("i2c_wait: MAL\n")); - return -1; - } + do { + csr = readb(I2CCSR); - if (!(csr & MPC85xx_I2CSR_MCF)) - { - DEB(printf ("i2c_wait: unfinished\n")); - return -1; - } + if (!(csr & MPC85xx_I2CSR_MIF)) + continue; - if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) - { - DEB(printf ("i2c_wait: No RXACK\n")); - return -1; - } + writeb(0x0, I2CCSR); + + if (csr & MPC85xx_I2CSR_MAL) { + debug("i2c_wait: MAL\n"); + return -1; + } + + if (!(csr & MPC85xx_I2CSR_MCF)) { + debug("i2c_wait: unfinished\n"); + return -1; + } + + if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } - return 0; - } while (get_timer (timeval) < TIMEOUT); + return 0; + } while (get_timer (timeval) < TIMEOUT); - DEB(printf ("i2c_wait: timed out\n")); - return -1; + debug("i2c_wait: timed out\n"); + return -1; } static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta) { - writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX | - (rsta?MPC85xx_I2CCR_RSTA:0), I2CCCR); + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX | + (rsta?MPC85xx_I2CCR_RSTA:0), + I2CCCR); - writel ((dev << 1) | dir, I2CCDR); + writeb((dev << 1) | dir, I2CCDR); - if (i2c_wait (I2C_WRITE) < 0) - return 0; + if (i2c_wait (I2C_WRITE) < 0) + return 0; - return 1; + return 1; } static __inline__ int __i2c_write (u8 *data, int length) { - int i; + int i; - writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, I2CCCR); + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, + I2CCCR); - for (i=0; i < length; i++) - { - writel (data[i], I2CCDR); + for (i=0; i < length; i++) { + writeb(data[i], I2CCDR); - if (i2c_wait (I2C_WRITE) < 0) - break; - } + if (i2c_wait (I2C_WRITE) < 0) + break; + } - return i; + return i; } static __inline__ int __i2c_read (u8 *data, int length) { - int i; - - writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | - ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), I2CCCR); - - /* dummy read */ - readl (I2CCDR); + int i; - for (i=0; i < length; i++) - { - if (i2c_wait (I2C_READ) < 0) - break; + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | + ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), + I2CCCR); + + /* dummy read */ + readb(I2CCDR); + + for (i=0; i < length; i++) { + if (i2c_wait (I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | + MPC85xx_I2CCR_TXAK, + I2CCCR); + + /* Generate stop on last byte */ + if (i == length - 1) + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR); - /* Generate ack on last next to last byte */ - if (i == length - 2) - writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | - MPC85xx_I2CCR_TXAK, I2CCCR); - - /* Generate stop on last byte */ - if (i == length - 1) - writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR); - - data[i] = readl (I2CCDR); - } + data[i] = readb(I2CCDR); + } - return i; + return i; } int i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) { - int i = 0; - u8 *a = (u8*)&addr; + int i = 0; + u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) - goto exit; + if (i2c_wait4bus () < 0) + goto exit; - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; + if (i2c_write_addr (dev, I2C_READ, 1) == 0) + goto exit; - i = __i2c_read (data, length); + i = __i2c_read (data, length); exit: - writel (MPC85xx_I2CCR_MEN, I2CCCR); + writeb(MPC85xx_I2CCR_MEN, I2CCCR); - return !(i == length); + return !(i == length); } int i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) { - int i = 0; - u8 *a = (u8*)&addr; + int i = 0; + u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) - goto exit; + if (i2c_wait4bus () < 0) + goto exit; - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; - i = __i2c_write (data, length); + i = __i2c_write (data, length); exit: - writel (MPC85xx_I2CCR_MEN, I2CCCR); + writeb(MPC85xx_I2CCR_MEN, I2CCCR); - return !(i == length); + return !(i == length); } int i2c_probe (uchar chip)

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[U-Boot-Users] PATCH for JSE configuration of its host bridge
by Stephen Williams 28 Sep '04

28 Sep '04

The attached patch tweaks the configuration of the PCI device class that the host system seeof if this board. The change is very simple and affects only the JSE. Patch is attached. CHANGELOG entry: * Patch by Stephen Williams, 15 July 2004 Set the PCI class code as part of PCI interface setup -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." Index: board/jse/host_bridge.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/board/jse/host_bridge.c,v retrieving revision 1.1 diff -p -u -r1.1 host_bridge.c --- board/jse/host_bridge.c 15 Apr 2004 23:14:49 -0000 1.1 +++ board/jse/host_bridge.c 15 Jul 2004 19:30:52 -0000 @@ -40,9 +40,12 @@ void host_bridge_init (void) pci_dev_t dev = PCI_BDF (0, 10, 0); int rc; - u32 val32; - rc = pci_read_config_dword (dev, 0, &val32); + /* Set PCI Class code -- + The primary side sees this class code at 0x08 in the + primary config space. This must be something other then a + bridge, or MS Windows starts doing weird stuff to me. */ + pci_write_config_dword (dev, 0x48, 0x04800000); /* Set subsystem ID -- The primary side sees this value at 0x2c. We set it here so

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[U-Boot-Users] Patch: Dynamic clock settings for MPC866 and newer chips
by Yuli Barcohen 28 Sep '04

28 Sep '04

The attached patch makes it possible to set clock on MPC866/MPC885 series chips according to cpuclk environment variable. This is generalisation of Wolfgang's mechanism which was implemented for TQM866M board. CHANGELOG: Allow clock setting on MPC866/MPC885 series chips according to environment variable `cpuclk' -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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