April 2004 - U-Boot

[U-Boot-Users] [patch #11/11] Trivial fixes
by Pantelis Antoniou 15 Apr '04

15 Apr '04

Hello These are two trivial patches. Regards Pantelis diff -ruNb u-boot-original/common/console.c u-boot-trivial/common/console.c --- u-boot-original/common/console.c 2004-03-30 14:37:28.666930872 +0300 +++ u-boot-trivial/common/console.c 2004-03-30 15:36:25.977177976 +0300 @@ -412,6 +412,9 @@ DECLARE_GLOBAL_DATA_PTR; char *stdinname, *stdoutname, *stderrname; device_t *inputdev = NULL, *outputdev = NULL, *errdev = NULL; +#ifdef CFG_CONSOLE_ENV_OVERWRITE + int i; +#endif /* set default handlers at first */ gd->jt[XF_getc] = serial_getc; diff -ruNb u-boot-original/Makefile u-boot-build/Makefile --- u-boot-original/Makefile 2004-03-30 14:37:28.394972216 +0300 +++ u-boot-build/Makefile 2004-03-30 15:39:12.141917096 +0300 @@ -166,6 +166,9 @@ tags: ctags -w `find $(SUBDIRS) include \ + lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \ + fs/cramfs fs/fat fs/fdos fs/jffs2 \ + net disk rtc dtt drivers drivers/sk98lin common \ $ -name CVS -prune $ -o $ -name '*.[ch]' -print $` etags: @@ -1225,8 +1228,8 @@ rm -f examples/hello_world examples/timer \ examples/eepro100_eeprom examples/sched \ examples/mem_to_mem_idma2intr examples/82559_eeprom - rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr + rm -f tools/mpc86x_clk rm -f tools/easylogo/easylogo tools/bmp_logo rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend rm -f tools/env/fw_printenv tools/env/fw_setenv

2 1

[U-Boot-Users] [patch #8/11] Trivial new NAND flash functionality
by Pantelis Antoniou 15 Apr '04

15 Apr '04

Hello The following patch adds a new mode for reading from a NAND device. The option is named .jffs2s, and on read it just skips over bad blocks. Regards Pantelis cmd_nand.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletion(-) diff -ruNb u-boot-original/common/cmd_nand.c u-boot-nand/common/cmd_nand.c --- u-boot-original/common/cmd_nand.c 2004-03-30 14:37:28.663931328 +0300 +++ u-boot-nand/common/cmd_nand.c 2004-03-30 15:38:40.985653568 +0300 @@ -9,6 +9,7 @@ #include <command.h> #include <malloc.h> #include <asm/io.h> +#include <watchdog.h> #ifdef CONFIG_SHOW_BOOT_PROGRESS # include <status_led.h> @@ -63,6 +64,7 @@ #define NANDRW_READ 0x01 #define NANDRW_WRITE 0x00 #define NANDRW_JFFS2 0x02 +#define NANDRW_JFFS2_SKIP 0x04 /* * Function Prototypes @@ -207,6 +209,11 @@ } else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2)) cmd |= NANDRW_JFFS2; /* skip bad blocks */ + else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) { + cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ + if (cmd & NANDRW_READ) + cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ + } #ifdef SXNI855T /* need ".e" same as ".j" for compatibility with older units */ else if (cmdtail && !strcmp(cmdtail, ".e")) @@ -258,7 +265,7 @@ "nand - NAND sub-system\n", "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" - "nand read[.jffs2] addr off size\n" + "nand read[.jffs2[s]] addr off size\n" "nand write[.jffs2] addr off size - read/write `size' bytes starting\n" " at offset `off' to/from memory address `addr'\n" "nand erase [clean] [off size] - erase `size' bytes from\n" @@ -420,6 +427,7 @@ * 1: NANDRW_READ read, fail on bad block * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks + * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks */ static int nand_rw (struct nand_chip* nand, int cmd, size_t start, size_t len, @@ -450,6 +458,10 @@ } continue; } + else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) { + start += erasesize; + continue; + } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) { /* skip bad block */ start += erasesize;

2 1

[U-Boot-Users] [patch #7/11] Small MII fix
by Pantelis Antoniou 15 Apr '04

15 Apr '04

Hello The following patch fixes a problem when reading the MII status register. Due to the internal design of many PHYs you have to read the register twice. The problem is more apparent in 10Mbit mode. Regards Pantelis miiphyutil.c | 2 ++ 1 files changed, 2 insertions(+) diff -ruNb u-boot-original/common/miiphyutil.c u-boot-miifix/common/miiphyutil.c --- u-boot-original/common/miiphyutil.c 2004-03-30 14:37:28.670930264 +0300 +++ u-boot-miifix/common/miiphyutil.c 2004-03-30 15:40:31.779810296 +0300 @@ -203,6 +203,8 @@ { unsigned short reg; + /* dummy read; needed to latch some phys */ + (void)miiphy_read(addr, PHY_BMSR, &reg); if (miiphy_read (addr, PHY_BMSR, &reg)) { puts ("PHY_BMSR read failed, assuming no link\n"); return (0);

2 1

[U-Boot-Users] [patch #6/11] New option for crc32 command
by Pantelis Antoniou 15 Apr '04

15 Apr '04

Hello The following patch add a -v (verify) flag to the crc32 command. Regards Pantelis cmd_mem.c | 40 ++++++++++++++++++++++++++++++++-------- 1 files changed, 32 insertions(+), 8 deletions(-) diff -ruNb u-boot-original/common/cmd_mem.c u-boot-mem/common/cmd_mem.c --- u-boot-original/common/cmd_mem.c 2004-03-30 14:37:28.663931328 +0300 +++ u-boot-mem/common/cmd_mem.c 2004-03-30 15:37:08.092775432 +0300 @@ -968,28 +968,52 @@ ulong addr, length; ulong crc; ulong *ptr; + ulong vcrc; + int verify; + int ac; + char **av; if (argc < 3) { + usage: printf ("Usage:\n%s\n", cmdtp->usage); return 1; } - addr = simple_strtoul (argv[1], NULL, 16); - addr += base_address; + av = argv + 1; + ac = argc - 1; + if (strcmp(*av, "-v") == 0) { + verify = 1; + av++; + ac--; + if (ac < 3) + goto usage; + } else + verify = 0; - length = simple_strtoul (argv[2], NULL, 16); + addr = simple_strtoul(*av++, NULL, 16); + addr += base_address; + length = simple_strtoul(*av++, NULL, 16); - crc = crc32 (0, (const uchar *) addr, length); + crc = crc32(0, (const uchar *) addr, length); + if (!verify) { printf ("CRC32 for %08lx ... %08lx ==> %08lx\n", addr, addr + length - 1, crc); - - if (argc > 3) { - ptr = (ulong *) simple_strtoul (argv[3], NULL, 16); + if (ac > 2) { + ptr = (ulong *) simple_strtoul (*av++, NULL, 16); *ptr = crc; } + } else { + vcrc = simple_strtoul(*av++, NULL, 16); + if (vcrc != crc) { + printf ("CRC32 for %08lx ... %08lx ==> %08lx != %08lx ** ERROR **\n", + addr, addr + length - 1, crc, vcrc); + return 1; + } + } return 0; + } /**************************************************/ @@ -1033,7 +1057,7 @@ ); U_BOOT_CMD( - crc32, 4, 1, do_mem_crc, + crc32, 5, 1, do_mem_crc, "crc32 - checksum calculation\n", "address count [addr]\n - compute CRC32 checksum [save at addr]\n" );

2 1

[U-Boot-Users] [patch #5/11] FEC driver update for 8xx
by Pantelis Antoniou 15 Apr '04

15 Apr '04

Hello The following patch improves and fixes various things in the FEC driver on the 8xx series of processors. The changes are as following: 1. The new 87x and 88x series of processors have two FECs, and the new driver supports them both. 2. Another change in the 87x/88x series is support for the RMII (Reduced MII) interface. However numerous changes are needed to make it work since the PHYs are connected to the same lines. That means that you have to address them correctly over the MII interface. 3. We now correctly match the MII/RMII interface configuration to what the PHY reports. The following new defines are supported: CONFIG_ETHER_ON_FEC[12] Enable FEC on given FEC CONFIG_FEC[12]_PHY Assign PHY address to FEC. If -1 means probe. CONFIG_FEC[12]_PHY_NORXERR The PHY does not have a RXERR line (RMII only). CONFIG_RMII Enable RMII mode common for any activated FECs. For compatibility reasons the name of the first interface remains unchanged at 'FEC ETHERNET' while the second is name 'FEC2 ETHERNET'. Regards Pantelis cpu/mpc8xx/fec.c | 540 +++++++++++++++++++++++++++++++------------- include/asm-ppc/8xx_immap.h | 6 include/mpc8xx.h | 6 3 files changed, 395 insertions(+), 157 deletions(-) diff -ruNb u-boot-original/cpu/mpc8xx/fec.c u-boot-fec/cpu/mpc8xx/fec.c --- u-boot-original/cpu/mpc8xx/fec.c 2004-03-30 14:37:28.695926464 +0300 +++ u-boot-fec/cpu/mpc8xx/fec.c 2004-03-30 16:39:29.881937016 +0300 @@ -29,13 +29,71 @@ #undef ET_DEBUG -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) && \ + (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) -#ifdef CFG_DISCOVER_PHY +/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ +#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2) +#define CONFIG_ETHER_ON_FEC1 1 +#endif + +/* define WANT_MII when MII support is required */ +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) +#define WANT_MII +#else +#undef WANT_MII +#endif + +#if defined(WANT_MII) #include <miiphy.h> -static void mii_discover_phy(void); #endif +#if defined(CONFIG_RMII) && !defined(WANT_MII) +#error RMII support is unusable without a working PHY. +#endif + +#ifdef CFG_DISCOVER_PHY +static int mii_discover_phy(struct eth_device *dev); +#endif + +static struct ether_fcc_info_s +{ + int ether_index; + int fecp_offset; + int bd_offset; + int phy_addr; + int actual_phy_addr; +} + ether_fcc_info[] = { +#if defined(CONFIG_ETHER_ON_FEC1) + { + 0, + offsetof(immap_t, im_cpm.cp_fec1), + CPM_FEC_BASE, +#if defined(CONFIG_FEC1_PHY) + CONFIG_FEC1_PHY, +#else + -1, /* discover */ +#endif + -1, + + }, +#endif +#if defined(CONFIG_ETHER_ON_FEC2) + { + 1, + offsetof(immap_t, im_cpm.cp_fec2), + CPM_FEC_BASE + 0x50, +#if defined(CONFIG_FEC2_PHY) + CONFIG_FEC2_PHY, +#else + -1, +#endif + -1, + }, +#endif +}; + /* Ethernet Transmit and Receive Buffers */ #define DBUF_LENGTH 1520 @@ -47,8 +105,11 @@ #define PKT_MINBUF_SIZE 64 #define PKT_MAXBLR_SIZE 1520 - -static char txbuf[DBUF_LENGTH]; +#ifdef __GNUC__ +static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8))); +#else +#error txbuf must be aligned. +#endif static uint rxIdx; /* index of the current RX buffer */ static uint txIdx; /* index of the current TX buffer */ @@ -74,28 +135,47 @@ int fec_initialize(bd_t *bis) { struct eth_device* dev; + struct ether_fcc_info_s *efis; + int i; - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); + for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) { + dev = malloc(sizeof(*dev)); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + + /* for FEC1 make sure that the name of the interface is the same + as the old one for compatibility reasons */ + if (i == 0) sprintf(dev->name, "FEC ETHERNET"); - dev->iobase = 0; - dev->priv = 0; + else + sprintf(dev->name, "FEC%d ETHERNET", ether_fcc_info[i].ether_index + 1); + + efis = &ether_fcc_info[i]; + + /* + * reset actual phy addr + */ + efis->actual_phy_addr = -1; + + dev->priv = efis; dev->init = fec_init; dev->halt = fec_halt; dev->send = fec_send; dev->recv = fec_recv; eth_register(dev); - + } return 1; } static int fec_send(struct eth_device* dev, volatile void *packet, int length) { int j, rc; - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile fec_t *fecp = &(immr->im_cpm.cp_fec); + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); /* section 16.9.23.3 * Wait for ready @@ -144,9 +224,9 @@ static int fec_recv(struct eth_device* dev) { + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); int length; - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile fec_t *fecp = &(immr->im_cpm.cp_fec); for (;;) { /* section 16.9.23.2 */ @@ -163,8 +243,19 @@ __FUNCTION__,__LINE__,rtx->rxbd[rxIdx].cbd_sc); #endif } else { - /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[rxIdx], length - 4); + volatile uchar *rx = NetRxPackets[rxIdx]; + + length -= 4; + +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + if ((rx[0] & 1) != 0 && memcmp((uchar *)rx, NetBcastAddr, 6) != 0 && memcmp((uchar *)rx, NetCDPAddr, 6) != 0) + rx = NULL; +#endif + /* + * Pass the packet up to the protocol layers. + */ + if (rx != NULL) + NetReceive(rx, length); } /* Give the buffer back to the FEC. */ @@ -210,13 +301,228 @@ #define FEC_RESET_DELAY 50 -static int fec_init(struct eth_device* dev, bd_t * bd) +#if defined(CONFIG_RMII) + +static inline void fec_10Mbps(struct eth_device *dev) { + struct ether_fcc_info_s *efis = dev->priv; + int fecidx = efis->ether_index; - int i; + if ((unsigned int)fecidx >= 2) + hang(); + + if (fecidx == 0) + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= 0x0000010; + else + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= 0x0000008; +} + +static inline void fec_100Mbps(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + int fecidx = efis->ether_index; + + if ((unsigned int)fecidx >= 2) + hang(); + + if (fecidx == 0) + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~0x0000010; + else + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~0x0000008; +} + +#endif + +static inline void fec_full_duplex(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + + fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT; + fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */ +} + +static inline void fec_half_duplex(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + + fecp->fec_r_cntrl |= FEC_RCNTRL_DRT; + fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */ +} + +static void fec_pin_init(int fecidx) +{ + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd = gd->bd; volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile fec_t *fecp = &(immr->im_cpm.cp_fec); + volatile fec_t *fecp; + + /* + * only two FECs please + */ + if ((unsigned int)fecidx >= 2) + hang(); + + if (fecidx == 0) + fecp = &immr->im_cpm.cp_fec1; + else + fecp = &immr->im_cpm.cp_fec2; + + /* + * Set MII speed to 2.5 MHz or slightly below. + * * According to the MPC860T (Rev. D) Fast ethernet controller user + * * manual (6.2.14), + * * the MII management interface clock must be less than or equal + * * to 2.5 MHz. + * * This MDC frequency is equal to system clock / (2 * MII_SPEED). + * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. + */ + fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; + +#if defined(CONFIG_DUET) && defined(WANT_MII) + /* use MDC for MII */ + immr->im_ioport.iop_pdpar |= 0x0080; + immr->im_ioport.iop_pddir &= ~0x0080; +#endif + + if (fecidx == 0) { +#if defined(CONFIG_ETHER_ON_FEC1) + +#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */ + +#if !defined(CONFIG_RMII) + + immr->im_ioport.iop_papar |= 0xf830; + immr->im_ioport.iop_padir |= 0x0830; + immr->im_ioport.iop_padir &= ~0xf000; + + immr->im_cpm.cp_pbpar |= 0x00001001; + immr->im_cpm.cp_pbdir &= ~0x00001001; + + immr->im_ioport.iop_pcpar |= 0x000c; + immr->im_ioport.iop_pcdir &= ~0x000c; + + immr->im_cpm.cp_pepar |= 0x00000003; + immr->im_cpm.cp_pedir |= 0x00000003; + immr->im_cpm.cp_peso &= ~0x00000003; + + immr->im_cpm.cp_cptr &= ~0x00000100; + +#else + +#if !defined(CONFIG_FEC1_PHY_NORXERR) + immr->im_ioport.iop_papar |= 0x1000; + immr->im_ioport.iop_padir &= ~0x1000; +#endif + immr->im_ioport.iop_papar |= 0xe810; + immr->im_ioport.iop_padir |= 0x0810; + immr->im_ioport.iop_padir &= ~0xe000; + + immr->im_cpm.cp_pbpar |= 0x00000001; + immr->im_cpm.cp_pbdir &= ~0x00000001; + + immr->im_cpm.cp_cptr |= 0x00000100; + immr->im_cpm.cp_cptr &= ~0x00000050; + +#endif /* !CONFIG_RMII */ + +#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) + /* + * Configure all of port D for MII. + */ + immr->im_ioport.iop_pdpar = 0x1fff; + + /* + * Bits moved from Rev. D onward + */ + if ((get_immr(0) & 0xffff) < 0x0501) + immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ + else + immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ +#else + /* + * Configure port A for MII. + */ + +#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY) + + /* + * On the ICU862 board the MII-MDC pin is routed to PD8 pin + * * of CPU, so for this board we need to configure Utopia and + * * enable PD8 to MII-MDC function + */ + immr->im_ioport.iop_pdpar |= 0x4080; +#endif + + /* + * Has Utopia been configured? + */ + if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) { + /* + * YES - Use MUXED mode for UTOPIA bus. + * This frees Port A for use by MII (see 862UM table 41-6). + */ + immr->im_ioport.utmode &= ~0x80; + } else { + /* + * NO - set SPLIT mode for UTOPIA bus. + * + * This doesn't really effect UTOPIA (which isn't + * enabled anyway) but just tells the 862 + * to use port A for MII (see 862UM table 41-6). + */ + immr->im_ioport.utmode |= 0x80; + } +#endif /* !defined(CONFIG_ICU862) */ + +#endif /* CONFIG_ETHER_ON_FEC1 */ + } else if (fecidx == 1) { + +#if defined(CONFIG_ETHER_ON_FEC2) + +#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */ + +#if !defined(CONFIG_RMII) + +#warning this configuration is not tested; please report if it works + immr->im_cpm.cp_pepar |= 0x0003fffc; + immr->im_cpm.cp_pedir |= 0x0003fffc; + immr->im_cpm.cp_peso &= ~0x000087fc; + immr->im_cpm.cp_peso |= 0x00037800; + + immr->im_cpm.cp_cptr &= ~0x00000080; +#else + +#if !defined(CONFIG_FEC2_PHY_NORXERR) + immr->im_cpm.cp_pepar |= 0x00000010; + immr->im_cpm.cp_pedir |= 0x00000010; + immr->im_cpm.cp_peso &= ~0x00000010; +#endif + immr->im_cpm.cp_pepar |= 0x00039620; + immr->im_cpm.cp_pedir |= 0x00039620; + immr->im_cpm.cp_peso |= 0x00031000; + immr->im_cpm.cp_peso &= ~0x00008620; + + immr->im_cpm.cp_cptr |= 0x00000080; + immr->im_cpm.cp_cptr &= ~0x00000028; +#endif /* CONFIG_RMII */ + +#endif /* CONFIG_DUET */ + +#endif /* CONFIG_ETHER_ON_FEC2 */ + + } +} + +static int fec_init(struct eth_device *dev, bd_t * bd) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + int i; + if (efis->ether_index == 0) { #if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */ #if defined(CONFIG_DUET_ADS) *(vu_char *)BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST); @@ -238,6 +544,8 @@ } #endif /* CONFIG_DUET_ADS */ #endif /* CONFIG_FADS */ + } + /* Whack a reset. * A delay is required between a reset of the FEC block and * initialization of other FEC registers because the reset takes @@ -274,10 +582,18 @@ fecp->fec_addr_high = (ea[4] << 8) | (ea[5] ) ; #undef ea +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + /* + * Turn on multicast address hash table + */ + fecp->fec_hash_table_high = 0xffffffff; + fecp->fec_hash_table_low = 0xffffffff; +#else /* Clear multicast address hash table */ fecp->fec_hash_table_high = 0; fecp->fec_hash_table_low = 0; +#endif /* Set maximum receive buffer size. */ @@ -343,82 +659,53 @@ */ fecp->fec_fun_code = 0x78000000; - /* Set MII speed to 2.5 MHz or slightly below. - * According to the MPC860T (Rev. D) Fast ethernet controller user - * manual (6.2.14), - * the MII management interface clock must be less than or equal - * to 2.5 MHz. - * This MDC frequency is equal to system clock / (2 * MII_SPEED). - * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. - */ - fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; - -#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */ - immr->im_ioport.iop_papar |= 0xf830; - immr->im_ioport.iop_padir |= 0x0830; - immr->im_ioport.iop_padir &= ~0xf000; - immr->im_cpm.cp_pbpar |= 0x00001001; - immr->im_cpm.cp_pbdir &= ~0x00001001; - immr->im_ioport.iop_pcpar |= 0x000c; - immr->im_ioport.iop_pcdir &= ~0x000c; - immr->im_ioport.iop_pdpar |= 0x0080; - immr->im_ioport.iop_pddir &= ~0x0080; - immr->im_cpm.cp_pepar |= 0x00000003; - immr->im_cpm.cp_pedir |= 0x00000003; - immr->im_cpm.cp_peso &= ~0x00000003; -#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) - /* Configure all of port D for MII. - */ - immr->im_ioport.iop_pdpar = 0x1fff; - - /* Bits moved from Rev. D onward */ - if ((get_immr (0) & 0xffff) < 0x0501) { - immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ - } else { - immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ - } -#else - /* Configure port A for MII. + /* + * Setup the pin configuration of the FEC */ + fec_pin_init(efis->ether_index); -#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY) - - /* On the ICU862 board the MII-MDC pin is routed to PD8 pin - * of CPU, so for this board we need to configure Utopia and - * enable PD8 to MII-MDC function */ - immr->im_ioport.iop_pdpar |= 0x4080; -#endif + rxIdx = 0; + txIdx = 0; - /* Has Utopia been configured? */ - if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) { /* - * YES - Use MUXED mode for UTOPIA bus. - * This frees Port A for use by MII (see 862UM table 41-6). + * Now enable the transmit and receive processing */ - immr->im_ioport.utmode &= ~0x80; - } else { + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; + + if (efis->phy_addr == -1) { +#ifdef CFG_DISCOVER_PHY /* - * NO - set SPLIT mode for UTOPIA bus. - * - * This doesn't really effect UTOPIA (which isn't - * enabled anyway) but just tells the 862 - * to use port A for MII (see 862UM table 41-6). + * wait for the PHY to wake up after reset */ - immr->im_ioport.utmode |= 0x80; + efis->actual_phy_addr = mii_discover_phy(dev); +#else + efis->actual_phy_addr = -1; +#endif + if (efis->actual_phy_addr == -1) { + printf("Unable to discover phy!\n"); + return 0; } -#endif /* !defined(CONFIG_ICU862) */ - - rxIdx = 0; - txIdx = 0; + } else + efis->actual_phy_addr = efis->phy_addr; - /* Now enable the transmit and receive processing +#if defined(CONFIG_MII) && defined(CONFIG_RMII) + /* + * adapt the RMII speed to the speed of the phy */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; + if (miiphy_speed(efis->actual_phy_addr) == _100BASET) + fec_100Mbps(dev); + else + fec_10Mbps(dev); +#endif -#ifdef CFG_DISCOVER_PHY - /* wait for the PHY to wake up after reset +#if defined(CONFIG_MII) + /* + * adapt to the half/full speed settings */ - mii_discover_phy(); + if (miiphy_duplex(efis->actual_phy_addr) == FULL) + fec_full_duplex(dev); + else + fec_half_duplex(dev); #endif /* And last, try to fill Rx Buffer Descriptors */ @@ -444,10 +731,7 @@ } #endif -#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) - -static int phyaddr = -1; /* didn't find a PHY yet */ -static uint phytype; +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) /* Make MII read/write commands for the FEC. */ @@ -508,12 +792,13 @@ #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ #if defined(CFG_DISCOVER_PHY) -static void -mii_discover_phy(void) +static int mii_discover_phy(struct eth_device *dev) { #define MAX_PHY_PASSES 11 uint phyno; int pass; + uint phytype; + int phyaddr; phyaddr = -1; /* didn't find a PHY yet */ for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { @@ -571,10 +856,11 @@ if (phyaddr < 0) { printf("No PHY device found.\n"); } + return phyaddr; } #endif /* CFG_DISCOVER_PHY */ -#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII) static int mii_init_done = 0; @@ -585,17 +871,16 @@ */ void mii_init (void) { - DECLARE_GLOBAL_DATA_PTR; - bd_t *bd = gd->bd; - volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile fec_t *fecp = &(immr->im_cpm.cp_fec); - int i; + int i, j; if (mii_init_done != 0) { return; } + for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) { + /* Whack a reset. * A delay is required between a reset of the FEC block and * initialization of other FEC registers because the reset takes @@ -623,76 +908,19 @@ */ fecp->fec_ievent = 0xffc0; - /* Set MII speed to 2.5 MHz or slightly below. - * According to the MPC860T (Rev. D) Fast ethernet controller user - * manual (6.2.14), - * the MII management interface clock must be less than or equal - * to 2.5 MHz. - * This MDC frequency is equal to system clock / (2 * MII_SPEED). - * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. - */ - fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; - -#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */ - immr->im_ioport.iop_papar |= 0xf830; - immr->im_ioport.iop_padir |= 0x0830; - immr->im_ioport.iop_padir &= ~0xf000; - immr->im_cpm.cp_pbpar |= 0x00001001; - immr->im_cpm.cp_pbdir &= ~0x00001001; - immr->im_ioport.iop_pcpar |= 0x000c; - immr->im_ioport.iop_pcdir &= ~0x000c; - immr->im_ioport.iop_pdpar |= 0x0080; - immr->im_ioport.iop_pddir &= ~0x0080; - immr->im_cpm.cp_pepar |= 0x00000003; - immr->im_cpm.cp_pedir |= 0x00000003; - immr->im_cpm.cp_peso &= ~0x00000003; -#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) - /* Configure all of port D for MII. - */ - immr->im_ioport.iop_pdpar = 0x1fff; - - /* Bits moved from Rev. D onward */ - if ((get_immr (0) & 0xffff) < 0x0501) { - immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ - } else { - immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ - } -#else - /* Configure port A for MII. + /* Setup the pin configuration of the FEC(s) */ + fec_pin_init(ether_fcc_info[i].ether_index); -#if defined(CONFIG_ICU862) - - /* On the ICU862 board the MII-MDC pin is routed to PD8 pin - * of CPU, so for this board we need to configure Utopia and - * enable PD8 to MII-MDC function */ - immr->im_ioport.iop_pdpar |= 0x4080; -#endif - - /* Has Utopia been configured? */ - if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) { - /* - * YES - Use MUXED mode for UTOPIA bus. - * This frees Port A for use by MII (see 862UM table 41-6). - */ - immr->im_ioport.utmode &= ~0x80; - } else { - /* - * NO - set SPLIT mode for UTOPIA bus. - * - * This doesn't really effect UTOPIA (which isn't - * enabled anyway) but just tells the 862 - * to use port A for MII (see 862UM table 41-6). - */ - immr->im_ioport.utmode |= 0x80; - } -#endif /* !defined(CONFIG_ICU862) */ /* Now enable the transmit and receive processing */ fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; + } mii_init_done = 1; + } + /***************************************************************************** * Read and write a MII PHY register, routines used by MII Utilities * diff -ruNb u-boot-original/include/asm-ppc/8xx_immap.h u-boot-fec/include/asm-ppc/8xx_immap.h --- u-boot-original/include/asm-ppc/8xx_immap.h 2004-03-30 14:37:28.780913544 +0300 +++ u-boot-fec/include/asm-ppc/8xx_immap.h 2004-03-30 15:43:35.258917232 +0300 @@ -473,7 +473,11 @@ union fec_lcd fl_un; #define cp_fec fl_un.fl_un_fec #define lcd_cmap fl_un.fl_un_cmap - char res18[0x1000]; + char res18[0xE00]; + + /* The DUET family has a second FEC here */ + fec_t cp_fec2; +#define cp_fec1 cp_fec /* consistency macro */ /* Dual Ported RAM follows. * There are many different formats for this memory area diff -ruNb u-boot-original/include/mpc8xx.h u-boot-fec/include/mpc8xx.h --- u-boot-original/include/mpc8xx.h 2004-03-30 14:37:28.755917344 +0300 +++ u-boot-fec/include/mpc8xx.h 2004-03-30 16:07:08.545065080 +0300 @@ -208,6 +208,12 @@ #define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ #define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ +#define SCCR_DFNL001 0x00000100 /* Division by 4 */ +#define SCCR_DFNL010 0x00000200 /* Division by 8 */ +#define SCCR_DFNL011 0x00000300 /* Division by 16 */ +#define SCCR_DFNL100 0x00000400 /* Division by 32 */ +#define SCCR_DFNL101 0x00000500 /* Division by 64 */ +#define SCCR_DFNL110 0x00000600 /* Division by 128 */ #define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ #define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */

2 1

[U-Boot-Users] [patch #4/11] Add support for DSP diagnostics
by Pantelis Antoniou 15 Apr '04

15 Apr '04

Hello The following patch adds the infrastructure needed in order to POST any DSPs in a board. Regards Pantelis include/post.h | 1 + post/Makefile | 2 +- post/dsp.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ post/tests.c | 13 +++++++++++++ 4 files changed, 64 insertions(+), 1 deletion(-) diff -ruNb u-boot-original/include/post.h u-boot-dsppost/include/post.h --- u-boot-original/include/post.h 2004-03-30 14:37:28.758916888 +0300 +++ u-boot-dsppost/include/post.h 2004-03-30 16:01:34.283880504 +0300 @@ -89,6 +89,7 @@ #define CFG_POST_USB 0x00000200 #define CFG_POST_SPR 0x00000400 #define CFG_POST_SYSMON 0x00000800 +#define CFG_POST_DSP 0x00001000 #endif /* CONFIG_POST */ diff -ruNb u-boot-original/post/Makefile u-boot-dsppost/post/Makefile --- u-boot-original/post/Makefile 2004-03-30 14:37:28.829906096 +0300 +++ u-boot-dsppost/post/Makefile 2004-03-30 16:01:34.284880352 +0300 @@ -28,6 +28,6 @@ AOBJS = cache_8xx.o COBJS = post.o tests.o cpu.o rtc.o watchdog.o memory.o i2c.o cache.o sysmon.o -COBJS += uart.o ether.o usb.o spr.o +COBJS += uart.o ether.o usb.o spr.o dsp.o include $(TOPDIR)/post/rules.mk diff -ruNb u-boot-original/post/dsp.c u-boot-dsppost/post/dsp.c --- u-boot-original/post/dsp.c 1970-01-01 02:00:00.000000000 +0200 +++ u-boot-dsppost/post/dsp.c 2004-03-30 16:01:34.284880352 +0300 @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2004 + * Pantelis Antoniou, Intracom S.A. , panto(a)intracom.gr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* + * DSP test + * + * This test verifies the connection and performs a memory test + * on any connected DSP(s). The meat of the work is done + * in the board specific function. + */ + +#ifdef CONFIG_POST + +#include <post.h> + +#if CONFIG_POST & CFG_POST_DSP + +extern int board_post_dsp(int flags); + +int dsp_post_test (int flags) +{ + return board_post_dsp(flags); +} + +#endif /* CONFIG_POST & CFG_POST_DSP */ +#endif /* CONFIG_POST */ + diff -ruNb u-boot-original/post/tests.c u-boot-dsppost/post/tests.c --- u-boot-original/post/tests.c 2004-03-30 14:37:28.831905792 +0300 +++ u-boot-dsppost/post/tests.c 2004-03-30 16:01:34.284880352 +0300 @@ -43,6 +43,7 @@ extern int usb_post_test (int flags); extern int spr_post_test (int flags); extern int sysmon_post_test (int flags); +extern int dsp_post_test (int flags); extern int sysmon_init_f (void); @@ -196,6 +197,18 @@ CFG_POST_SYSMON }, #endif +#if CONFIG_POST & CFG_POST_DSP + { + "DSP test", + "dsp", + "This test checks any connected DSP(s).", + POST_RAM | POST_MANUAL, + &dsp_post_test, + NULL, + NULL, + CFG_POST_DSP + }, +#endif }; unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);

2 1

[U-Boot-Users] [patch #3/11] Driver for SED156x displays
by Pantelis Antoniou 15 Apr '04

15 Apr '04

Hello The following patch adds support for the Epson 156x series of graphical displays. These displays are serial and unsuitable for using a normal framebuffer console on them. Regards Pantelis drivers/Makefile | 2 drivers/sed156x.c | 566 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/sed156x.h | 42 ++++ 3 files changed, 609 insertions(+), 1 deletion(-) diff -ruNb u-boot-original/drivers/Makefile u-boot-display/drivers/Makefile --- u-boot-original/drivers/Makefile 2004-03-30 14:37:28.713923728 +0300 +++ u-boot-display/drivers/Makefile 2004-03-30 15:39:52.105841656 +0300 @@ -43,7 +43,7 @@ smc91111.o smiLynxEM.o status_led.o sym53c8xx.o \ ti_pci1410a.o tigon3.o w83c553f.o omap1510_i2c.o \ usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ - videomodes.o + videomodes.o sed156x.o all: $(LIB) diff -ruNb u-boot-original/drivers/sed156x.c u-boot-display/drivers/sed156x.c --- u-boot-original/drivers/sed156x.c 1970-01-01 02:00:00.000000000 +0200 +++ u-boot-display/drivers/sed156x.c 2004-03-30 15:39:52.105841656 +0300 @@ -0,0 +1,566 @@ +/* + * (C) Copyright 2003 + * + * Pantelis Antoniou <panto(a)intracom.gr> + * Intracom S.A. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> + +#include <sed156x.h> + +#ifdef CONFIG_SED156X + +/* configure according to the selected display */ +#if defined(CONFIG_SED156X_PG12864Q) +#define LCD_WIDTH 128 +#define LCD_HEIGHT 64 +#define LCD_LINES 64 +#define LCD_PAGES 9 +#define LCD_COLUMNS 132 +#else +#error Unsupported SED156x configuration +#endif + +/* include the font data */ +#include <video_font.h> + +#if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16 +#error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16 +#endif + +#define LCD_BYTE_WIDTH (LCD_WIDTH / 8) +#define VIDEO_FONT_BYTE_WIDTH (VIDEO_FONT_WIDTH / 8) + +#define LCD_TEXT_WIDTH (LCD_WIDTH / VIDEO_FONT_WIDTH) +#define LCD_TEXT_HEIGHT (LCD_HEIGHT / VIDEO_FONT_HEIGHT) + +#define LCD_BYTE_LINESZ (LCD_BYTE_WIDTH * VIDEO_FONT_HEIGHT) + +const int sed156x_text_width = LCD_TEXT_WIDTH; +const int sed156x_text_height = LCD_TEXT_HEIGHT; + +/**************************************************************************************/ + +#define SED156X_SPI_RXD() (SED156X_SPI_RXD_PORT & SED156X_SPI_RXD_MASK) + +#define SED156X_SPI_TXD(x) \ + do { \ + if (x) \ + SED156X_SPI_TXD_PORT |= SED156X_SPI_TXD_MASK; \ + else \ + SED156X_SPI_TXD_PORT &= ~SED156X_SPI_TXD_MASK; \ + } while(0) + +#define SED156X_SPI_CLK(x) \ + do { \ + if (x) \ + SED156X_SPI_CLK_PORT |= SED156X_SPI_CLK_MASK; \ + else \ + SED156X_SPI_CLK_PORT &= ~SED156X_SPI_CLK_MASK; \ + } while(0) + +#define SED156X_SPI_CLK_TOGGLE() (SED156X_SPI_CLK_PORT ^= SED156X_SPI_CLK_MASK) + +#define SED156X_SPI_BIT_DELAY() /* no delay */ + +#define SED156X_CS(x) \ + do { \ + if (x) \ + SED156X_CS_PORT |= SED156X_CS_MASK; \ + else \ + SED156X_CS_PORT &= ~SED156X_CS_MASK; \ + } while(0) + +#define SED156X_A0(x) \ + do { \ + if (x) \ + SED156X_A0_PORT |= SED156X_A0_MASK; \ + else \ + SED156X_A0_PORT &= ~SED156X_A0_MASK; \ + } while(0) + +/**************************************************************************************/ + +/*** LCD Commands ***/ + +#define LCD_ON 0xAF /* Display ON */ +#define LCD_OFF 0xAE /* Display OFF */ +#define LCD_LADDR 0x40 /* Display start line set + (6-bit) address */ +#define LCD_PADDR 0xB0 /* Page address set + (4-bit) page */ +#define LCD_CADRH 0x10 /* Column address set upper + (4-bit) column hi */ +#define LCD_CADRL 0x00 /* Column address set lower + (4-bit) column lo */ +#define LCD_ADC_NRM 0xA0 /* ADC select Normal */ +#define LCD_ADC_REV 0xA1 /* ADC select Reverse */ +#define LCD_DSP_NRM 0xA6 /* LCD display Normal */ +#define LCD_DSP_REV 0xA7 /* LCD display Reverse */ +#define LCD_DPT_NRM 0xA4 /* Display all points Normal */ +#define LCD_DPT_ALL 0xA5 /* Display all points ON */ +#define LCD_BIAS9 0xA2 /* LCD bias set 1/9 */ +#define LCD_BIAS7 0xA3 /* LCD bias set 1/7 */ +#define LCD_CAINC 0xE0 /* Read/modify/write */ +#define LCD_CAEND 0xEE /* End */ +#define LCD_RESET 0xE2 /* Reset */ +#define LCD_C_NRM 0xC0 /* Common output mode select Normal direction */ +#define LCD_C_RVS 0xC8 /* Common output mode select Reverse direction */ +#define LCD_PWRMD 0x28 /* Power control set + (3-bit) mode */ +#define LCD_RESRT 0x20 /* V5 v. reg. int. resistor ratio set + (3-bit) ratio */ +#define LCD_EVSET 0x81 /* Electronic volume mode set + byte = (6-bit) volume */ +#define LCD_SIOFF 0xAC /* Static indicator OFF */ +#define LCD_SION 0xAD /* Static indicator ON + byte = (2-bit) mode */ +#define LCD_NOP 0xE3 /* NOP */ +#define LCD_TEST 0xF0 /* Test/Test mode reset (Note: *DO NOT USE*) */ + +/*------------------------------------------------------------------------------- + Compound commands + ------------------------------------------------------------------------------- + Command Description Commands + ---------- ------------------------ ------------------------------------- + POWS_ON POWER SAVER ON command LCD_OFF, LCD_D_ALL + POWS_OFF POWER SAVER OFF command LCD_D_NRM + SLEEPON SLEEP mode LCD_SIOFF, POWS_ON + SLEEPOFF SLEEP mode cancel LCD_D_NRM, LCD_SION, LCD_SIS_??? + STDBYON STAND BY mode LCD_SION, POWS_ON + STDBYOFF STAND BY mode cancel LCD_D_NRM + -------------------------------------------------------------------------------*/ + +/*** LCD various parameters ***/ +#define LCD_PPB 8 /* Pixels per byte (display is B/W, 1 bit per pixel) */ + +/*** LCD Status byte masks ***/ +#define LCD_S_BUSY 0x80 /* Status Read - BUSY mask */ +#define LCD_S_ADC 0x40 /* Status Read - ADC mask */ +#define LCD_S_ONOFF 0x20 /* Status Read - ON/OFF mask */ +#define LCD_S_RESET 0x10 /* Status Read - RESET mask */ + +/*** LCD commands parameter masks ***/ +#define LCD_M_LADDR 0x3F /* Display start line (6-bit) address mask */ +#define LCD_M_PADDR 0x0F /* Page address (4-bit) page mask */ +#define LCD_M_CADRH 0x0F /* Column address upper (4-bit) column hi mask */ +#define LCD_M_CADRL 0x0F /* Column address lower (4-bit) column lo mask */ +#define LCD_M_PWRMD 0x07 /* Power control (3-bit) mode mask */ +#define LCD_M_RESRT 0x07 /* V5 v. reg. int. resistor ratio (3-bit) ratio mask */ +#define LCD_M_EVSET 0x3F /* Electronic volume mode byte (6-bit) volume mask */ +#define LCD_M_SION 0x03 /* Static indicator ON (2-bit) mode mask */ + +/*** LCD Power control cirquits control masks ***/ +#define LCD_PWRBSTR 0x04 /* Power control mode - Booster cirquit ON */ +#define LCD_PWRVREG 0x02 /* Power control mode - Voltage regulator cirquit ON */ +#define LCD_PWRVFOL 0x01 /* Power control mode - Voltage follower cirquit ON */ + +/*** LCD Static indicator states ***/ +#define LCD_SIS_OFF 0x00 /* Static indicator register set - OFF state */ +#define LCD_SIS_BL 0x01 /* Static indicator register set - 1s blink state */ +#define LCD_SIS_RBL 0x02 /* Static indicator register set - .5s rapid blink state */ +#define LCD_SIS_ON 0x03 /* Static indicator register set - constantly on state */ + +/*** LCD functions special parameters (commands) ***/ +#define LCD_PREVP 0x80 /* Page number for moving to previous */ +#define LCD_NEXTP 0x81 /* or next page */ +#define LCD_ERR_P 0xFF /* Error in page number */ + +/*** LCD initialization settings ***/ +#define LCD_BIAS LCD_BIAS9 /* Bias: 1/9 */ +#define LCD_ADCMODE LCD_ADC_NRM /* ADC mode: normal */ +#define LCD_COMDIR LCD_C_NRM /* Common output mode: normal */ +#define LCD_RRATIO 0 /* Resistor ratio: 0 */ +#define LCD_CNTRST 0x1C /* electronic volume: 1Ch */ +#define LCD_POWERM (LCD_PWRBSTR | LCD_PWRVREG | LCD_PWRVFOL) /* Power mode: All on */ + +/**************************************************************************************/ + +static inline unsigned int sed156x_transfer(unsigned int val) +{ + unsigned int rx; + int b; + + rx = 0; b = 8; + while (--b >= 0) { + SED156X_SPI_TXD(val & 0x80); + val <<= 1; + SED156X_SPI_CLK_TOGGLE(); + SED156X_SPI_BIT_DELAY(); + rx <<= 1; + if (SED156X_SPI_RXD()) + rx |= 1; + SED156X_SPI_CLK_TOGGLE(); + SED156X_SPI_BIT_DELAY(); + } + + return rx; +} + +unsigned int sed156x_data_transfer(unsigned int val) +{ + unsigned int rx; + + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(1); + + rx = sed156x_transfer(val); + + SED156X_CS(1); + + return rx; +} + +void sed156x_data_block_transfer(const u8 *p, int size) +{ + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(1); + + while (--size >= 0) + sed156x_transfer(*p++); + + SED156X_CS(1); +} + +unsigned int sed156x_cmd_transfer(unsigned int val) +{ + unsigned int rx; + + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(0); + + rx = sed156x_transfer(val); + + SED156X_CS(1); + SED156X_A0(1); + + return rx; +} + +/******************************************************************************/ + +static u8 hw_screen[LCD_PAGES][LCD_COLUMNS]; +static u8 last_hw_screen[LCD_PAGES][LCD_COLUMNS]; +static u8 sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT]; + +void sed156x_sync(void) +{ + int i, j, last_page; + u8 *d; + const u8 *s, *e, *b, *r; + u8 v0, v1, v2, v3, v4, v5, v6, v7; + + /* copy and rotate sw_screen to hw_screen */ + for (i = 0; i < LCD_HEIGHT / 8; i++) { + + d = &hw_screen[i][0]; + s = &sw_screen[LCD_BYTE_WIDTH * 8 * i + LCD_BYTE_WIDTH - 1]; + + for (j = 0; j < LCD_WIDTH / 8; j++) { + + v0 = s[0 * LCD_BYTE_WIDTH]; + v1 = s[1 * LCD_BYTE_WIDTH]; + v2 = s[2 * LCD_BYTE_WIDTH]; + v3 = s[3 * LCD_BYTE_WIDTH]; + v4 = s[4 * LCD_BYTE_WIDTH]; + v5 = s[5 * LCD_BYTE_WIDTH]; + v6 = s[6 * LCD_BYTE_WIDTH]; + v7 = s[7 * LCD_BYTE_WIDTH]; + + d[0] = ((v7 & 0x01) << 7) | + ((v6 & 0x01) << 6) | + ((v5 & 0x01) << 5) | + ((v4 & 0x01) << 4) | + ((v3 & 0x01) << 3) | + ((v2 & 0x01) << 2) | + ((v1 & 0x01) << 1) | + (v0 & 0x01) ; + + d[1] = ((v7 & 0x02) << 6) | + ((v6 & 0x02) << 5) | + ((v5 & 0x02) << 4) | + ((v4 & 0x02) << 3) | + ((v3 & 0x02) << 2) | + ((v2 & 0x02) << 1) | + ((v1 & 0x02) << 0) | + ((v0 & 0x02) >> 1) ; + + d[2] = ((v7 & 0x04) << 5) | + ((v6 & 0x04) << 4) | + ((v5 & 0x04) << 3) | + ((v4 & 0x04) << 2) | + ((v3 & 0x04) << 1) | + (v2 & 0x04) | + ((v1 & 0x04) >> 1) | + ((v0 & 0x04) >> 2) ; + + d[3] = ((v7 & 0x08) << 4) | + ((v6 & 0x08) << 3) | + ((v5 & 0x08) << 2) | + ((v4 & 0x08) << 1) | + (v3 & 0x08) | + ((v2 & 0x08) >> 1) | + ((v1 & 0x08) >> 2) | + ((v0 & 0x08) >> 3) ; + + d[4] = ((v7 & 0x10) << 3) | + ((v6 & 0x10) << 2) | + ((v5 & 0x10) << 1) | + (v4 & 0x10) | + ((v3 & 0x10) >> 1) | + ((v2 & 0x10) >> 2) | + ((v1 & 0x10) >> 3) | + ((v0 & 0x10) >> 4) ; + + d[5] = ((v7 & 0x20) << 2) | + ((v6 & 0x20) << 1) | + (v5 & 0x20) | + ((v4 & 0x20) >> 1) | + ((v3 & 0x20) >> 2) | + ((v2 & 0x20) >> 3) | + ((v1 & 0x20) >> 4) | + ((v0 & 0x20) >> 5) ; + + d[6] = ((v7 & 0x40) << 1) | + (v6 & 0x40) | + ((v5 & 0x40) >> 1) | + ((v4 & 0x40) >> 2) | + ((v3 & 0x40) >> 3) | + ((v2 & 0x40) >> 4) | + ((v1 & 0x40) >> 5) | + ((v0 & 0x40) >> 6) ; + + d[7] = (v7 & 0x80) | + ((v6 & 0x80) >> 1) | + ((v5 & 0x80) >> 2) | + ((v4 & 0x80) >> 3) | + ((v3 & 0x80) >> 4) | + ((v2 & 0x80) >> 5) | + ((v1 & 0x80) >> 6) | + ((v0 & 0x80) >> 7) ; + + d += 8; + s--; + } + } + + /* and now output only the differences */ + for (i = 0; i < LCD_PAGES; i++) { + + b = &hw_screen[i][0]; + e = &hw_screen[i][LCD_COLUMNS]; + + d = &last_hw_screen[i][0]; + s = b; + + last_page = -1; + + /* update only the differences */ + do { + while (s < e && *s == *d) { + s++; + d++; + } + if (s == e) + break; + r = s; + while (s < e && *s != *d) + *d++ = *s++; + + j = r - b; + + if (i != last_page) { + sed156x_cmd_transfer(LCD_PADDR | i); + last_page = i; + } + + sed156x_cmd_transfer(LCD_CADRH | ((j >> 4) & 0x0F)); + sed156x_cmd_transfer(LCD_CADRL | (j & 0x0F)); + sed156x_data_block_transfer(r, s - r); + + } while (s < e); + } + + /* + for (i = 0; i < LCD_PAGES; i++) { + sed156x_cmd_transfer(LCD_PADDR | i); + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS); + } + memcpy(last_hw_screen, hw_screen, sizeof(last_hw_screen)); + */ +} + +void sed156x_clear(void) +{ + memset(sw_screen, 0, sizeof(sw_screen)); +} + +void sed156x_output_at(int x, int y, const char *str, int size) +{ + int i, j; + u8 *p; + const u8 *s; + + if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH) + return; + + p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH]; + + while (--size >= 0) { + + s = &video_fontdata[((int)*str++ & 0xff) * VIDEO_FONT_BYTE_WIDTH * VIDEO_FONT_HEIGHT]; + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++) + *p++ = *s++; + p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH; + } + p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH); + + if (x >= LCD_TEXT_WIDTH) + break; + x++; + } +} + +void sed156x_reverse_at(int x, int y, int size) +{ + int i, j; + u8 *p; + + if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH) + return; + + p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH]; + + while (--size >= 0) { + + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++, p++) + *p = ~*p; + p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH; + } + p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH); + + if (x >= LCD_TEXT_WIDTH) + break; + x++; + } +} + +void sed156x_scroll_line(void) +{ + memmove(&sw_screen[0], + &sw_screen[LCD_BYTE_LINESZ], + LCD_BYTE_WIDTH * (LCD_HEIGHT - VIDEO_FONT_HEIGHT)); +} + +void sed156x_scroll(int dx, int dy) +{ + u8 *p1 = NULL, *p2 = NULL, *p3 = NULL; /* pacify gcc */ + int adx, ady, i, sz; + + adx = dx > 0 ? dx : -dx; + ady = dy > 0 ? dy : -dy; + + /* overscroll? erase everything */ + if (adx >= LCD_TEXT_WIDTH || ady >= LCD_TEXT_HEIGHT) { + memset(sw_screen, 0, sizeof(sw_screen)); + return; + } + + sz = LCD_BYTE_LINESZ * ady; + if (dy > 0) { + p1 = &sw_screen[0]; + p2 = &sw_screen[sz]; + p3 = &sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT - sz]; + } else if (dy < 0) { + p1 = &sw_screen[sz]; + p2 = &sw_screen[0]; + p3 = &sw_screen[0]; + } + + if (ady > 0) { + memmove(p1, p2, LCD_BYTE_WIDTH * LCD_HEIGHT - sz); + memset(p3, 0, sz); + } + + sz = VIDEO_FONT_BYTE_WIDTH * adx; + if (dx > 0) { + p1 = &sw_screen[0]; + p2 = &sw_screen[0] + sz; + p3 = &sw_screen[0] + LCD_BYTE_WIDTH - sz; + } else if (dx < 0) { + p1 = &sw_screen[0] + sz; + p2 = &sw_screen[0]; + p3 = &sw_screen[0]; + } + + /* xscroll */ + if (adx > 0) { + for (i = 0; i < LCD_HEIGHT; i++) { + memmove(p1, p2, LCD_BYTE_WIDTH - sz); + memset(p3, 0, sz); + p1 += LCD_BYTE_WIDTH; + p2 += LCD_BYTE_WIDTH; + p3 += LCD_BYTE_WIDTH; + } + } +} + +void sed156x_init(void) +{ + int i; + + SED156X_CS(1); + SED156X_A0(1); + + /* Send initialization commands to the LCD */ + sed156x_cmd_transfer(LCD_OFF); /* Turn display OFF */ + sed156x_cmd_transfer(LCD_BIAS); /* set the LCD Bias, */ + sed156x_cmd_transfer(LCD_ADCMODE); /* ADC mode, */ + sed156x_cmd_transfer(LCD_COMDIR); /* common output mode, */ + sed156x_cmd_transfer(LCD_RESRT | LCD_RRATIO); /* resistor ratio, */ + sed156x_cmd_transfer(LCD_EVSET); /* electronic volume, */ + sed156x_cmd_transfer(LCD_CNTRST); + sed156x_cmd_transfer(LCD_PWRMD | LCD_POWERM); /* and power mode */ + sed156x_cmd_transfer(LCD_PADDR | 0); /* cursor home */ + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_cmd_transfer(LCD_LADDR | 0); /* and display start line */ + sed156x_cmd_transfer(LCD_DSP_NRM); /* LCD display Normal */ + + /* clear everything */ + memset(sw_screen, 0, sizeof(sw_screen)); + memset(hw_screen, 0, sizeof(hw_screen)); + memset(last_hw_screen, 0, sizeof(last_hw_screen)); + + for (i = 0; i < LCD_PAGES; i++) { + sed156x_cmd_transfer(LCD_PADDR | i); + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS); + } + + sed156x_clear(); + sed156x_sync(); + sed156x_cmd_transfer(LCD_ON); /* Turn display ON */ +} + +#endif diff -ruNb u-boot-original/include/sed156x.h u-boot-display/include/sed156x.h --- u-boot-original/include/sed156x.h 1970-01-01 02:00:00.000000000 +0200 +++ u-boot-display/include/sed156x.h 2004-03-30 15:39:52.106841504 +0300 @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2004 + * + * Pantelis Antoniou <panto(a)intracom.gr> + * Intracom S.A. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Video support for Epson SED156x chipset(s) */ + +#ifndef SED156X_H +#define SED156X_H + +void sed156x_init(void); +void sed156x_clear(void); +void sed156x_output_at(int x, int y, const char *str, int size); +void sed156x_reverse_at(int x, int y, int size); +void sed156x_sync(void); +void sed156x_scroll(int dx, int dy); + +/* export display */ +extern const int sed156x_text_width; +extern const int sed156x_text_height; + +#endif

2 1

RE: [U-Boot-Users] MPC885 and Abatron BDI2000
by Rod Boyce 15 Apr '04

15 Apr '04

Abatron are very good and are still sending me software updates even though our BDI is several years old. When ever I have had an issue with the BDI Abatron are very responsive what else can anybody ask for in a tool company. Regards, Rod Boyce -----Original Message----- From: u-boot-users-admin(a)lists.sourceforge.net [mailto:u-boot-users-admin@lists.sourceforge.net]On Behalf Of Wolfgang Denk Sent: Thursday, April 15, 2004 10:39 PM To: Sam Song Cc: jmmello2004(a)yahoo.com.br; u-boot-users(a)lists.sourceforge.net Subject: Re: [U-Boot-Users] MPC885 and Abatron BDI2000 In message <20040415090800.66258.qmail(a)web15203.mail.bjs.yahoo.com> you wrote: > > > I recommend to contact the excellent Abatron > > support. > > But how to? They are apt to make third party vendors > to do technical support as fas as I know.

1 0

[U-Boot-Users] Re: [patch #2/11] Intracom Boards patch
by Wolfgang Denk 15 Apr '04

15 Apr '04

In message <406988B4.4040105(a)intracom.gr> you wrote: > > The following patch adds two new Intracom boards in > u-boot and fixes to one more. Added, thanks. For the future: please strip trailing white space, and trailing empty lines. And use shorter lines (in general follow the Coding Standards as described in the README). Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de "Probably the best operating system in the world is the [operating system] made for the PDP-11 by Bell Laboratories." - Ted Nelson, October 1977

1 0

[U-Boot-Users] [patch #1/11] Auto Complete support
by Pantelis Antoniou 15 Apr '04

15 Apr '04

Hello The following patch adds auto-complete support to the u-boot command line. Using TAB the parser will try to auto complete all commands and for a few commands it will also try to do the same for their arguments. The commands that accept auto completion of their arguments are: setenv printenv & run. To enable just #define CONFIG_AUTO_COMPLETE at the board config.h file. Regards Pantelis README | 4 common/command.c | 281 ++++++++++++++++++++++++++++++++++++++++++++++++++++ common/env_common.c | 41 +++++++ common/main.c | 12 ++ include/command.h | 9 + include/common.h | 4 6 files changed, 351 insertions(+) diff -ruNb u-boot-original/README u-boot-autocomplete/README --- u-boot-original/README 2004-03-30 14:37:28.395972064 +0300 +++ u-boot-autocomplete/README 2004-03-30 15:54:54.321684000 +0300 @@ -1231,6 +1231,10 @@ default value of 5 is used. - Command Interpreter: + CFG_AUTO_COMPLETE + + Enable auto completion of commands using TAB. + CFG_HUSH_PARSER Define this variable to enable the "hush" shell (from diff -ruNb u-boot-original/common/command.c u-boot-autocomplete/common/command.c --- u-boot-original/common/command.c 2004-03-30 14:37:28.665931024 +0300 +++ u-boot-autocomplete/common/command.c 2004-03-30 15:42:19.877376968 +0300 @@ -217,3 +217,284 @@ return NULL; /* not found or ambiguous command */ } + +#ifdef CONFIG_AUTO_COMPLETE + +int var_complete(int argc, char *argv[], char last_char, int maxv, char *cmdv[]) +{ + static char tmp_buf[512]; + int space; + + space = last_char == '\0' || last_char == ' ' || last_char == '\t'; + + if (space && argc == 1) + return env_complete("", maxv, cmdv, sizeof(tmp_buf), tmp_buf); + + if (!space && argc == 2) + return env_complete(argv[1], maxv, cmdv, sizeof(tmp_buf), tmp_buf); + + return 0; +} + +static void install_auto_complete_handler(const char *cmd, + int (*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[])) +{ + cmd_tbl_t *cmdtp; + + cmdtp = find_cmd(cmd); + if (cmdtp == NULL) + return; + + cmdtp->complete = complete; +} + +void install_auto_complete(void) +{ + install_auto_complete_handler("printenv", var_complete); + install_auto_complete_handler("setenv", var_complete); +#if (CONFIG_COMMANDS & CFG_CMD_RUN) + install_auto_complete_handler("run", var_complete); +#endif +} + +/*************************************************************************************/ + +static int complete_cmdv(int argc, char *argv[], char last_char, int maxv, char *cmdv[]) +{ + cmd_tbl_t *cmdtp; + const char *p; + int len, clen; + int n_found = 0; + const char *cmd; + + /* sanity? */ + if (maxv < 2) + return -2; + + cmdv[0] = NULL; + + if (argc == 0) { + /* output full list of commands */ + for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + if (n_found >= maxv - 2) { + cmdv[n_found++] = "..."; + break; + } + cmdv[n_found++] = cmdtp->name; + } + cmdv[n_found] = NULL; + return n_found; + } + + /* more than one arg or one but the start of the next */ + if (argc > 1 || (last_char == '\0' || last_char == ' ' || last_char == '\t')) { + cmdtp = find_cmd(argv[0]); + if (cmdtp == NULL || cmdtp->complete == NULL) { + cmdv[0] = NULL; + return 0; + } + return (*cmdtp->complete)(argc, argv, last_char, maxv, cmdv); + } + + cmd = argv[0]; + /* + * Some commands allow length modifiers (like "cp.b"); + * compare command name only until first dot. + */ + p = strchr(cmd, '.'); + if (p == NULL) + len = strlen(cmd); + else + len = p - cmd; + + /* return the partial matches */ + for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + + clen = strlen(cmdtp->name); + if (clen < len) + continue; + + if (memcmp(cmd, cmdtp->name, len) != 0) + continue; + + /* too many! */ + if (n_found >= maxv - 2) { + cmdv[n_found++] = "..."; + break; + } + + cmdv[n_found++] = cmdtp->name; + } + + cmdv[n_found] = NULL; + return n_found; +} + +static int make_argv(char *s, int argvsz, char *argv[]) +{ + int argc = 0; + + /* split into argv */ + while (argc < argvsz - 1) { + + /* skip any white space */ + while ((*s == ' ') || (*s == '\t')) + ++s; + + if (*s == '\0') /* end of s, no more args */ + break; + + argv[argc++] = s; /* begin of argument string */ + + /* find end of string */ + while (*s && (*s != ' ') && (*s != '\t')) + ++s; + + if (*s == '\0') /* end of s, no more args */ + break; + + *s++ = '\0'; /* terminate current arg */ + } + argv[argc] = NULL; + + return argc; +} + +static void print_argv(const char *banner, const char *leader, const char *sep, int linemax, char *argv[]) +{ + int ll = leader != NULL ? strlen(leader) : 0; + int sl = sep != NULL ? strlen(sep) : 0; + int len, i; + + if (banner) { + puts("\n"); + puts(banner); + } + + i = linemax; /* force leader and newline */ + while (*argv != NULL) { + len = strlen(*argv) + sl; + if (i + len >= linemax) { + puts("\n"); + if (leader) + puts(leader); + i = ll - sl; + } else if (sep) + puts(sep); + puts(*argv++); + i += len; + } + printf("\n"); +} + +static int find_common_prefix(char *argv[]) +{ + int i, len; + char *anchor, *s, *t; + + if (*argv == NULL) + return 0; + + /* begin with max */ + anchor = *argv++; + len = strlen(anchor); + while ((t = *argv++) != NULL) { + s = anchor; + for (i = 0; i < len; i++, t++, s++) + if (*t != *s) + break; + len = s - anchor; + } + return len; +} + +static char tmp_buf[CFG_CBSIZE]; /* copy of console I/O buffer */ + +int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp) +{ + int n = *np, col = *colp; + char *argv[CFG_MAXARGS + 1]; /* NULL terminated */ + char *cmdv[20]; + char *s, *t; + const char *sep; + int i, j, k, len, seplen, argc; + int cnt; + char last_char; + + if (strcmp(prompt, CFG_PROMPT) != 0) + return 0; /* not in normal console */ + + cnt = strlen(buf); + if (cnt >= 1) + last_char = buf[cnt - 1]; + else + last_char = '\0'; + + /* copy to secondary buffer which will be affected */ + strcpy(tmp_buf, buf); + + /* separate into argv */ + argc = make_argv(tmp_buf, sizeof(argv)/sizeof(argv[0]), argv); + + /* do the completion and return the possible completions */ + i = complete_cmdv(argc, argv, last_char, sizeof(cmdv)/sizeof(cmdv[0]), cmdv); + + /* no match; bell and out */ + if (i == 0) { + if (argc > 1) /* allow tab for non command */ + return 0; + putc('\a'); + return 1; + } + + s = NULL; + len = 0; + sep = NULL; + seplen = 0; + if (i == 1) { /* one match; perfect */ + k = strlen(argv[argc - 1]); + s = cmdv[0] + k; + len = strlen(s); + sep = " "; + seplen = 1; + } else if (i > 1 && (j = find_common_prefix(cmdv)) != 0) { /* more */ + k = strlen(argv[argc - 1]); + j -= k; + if (j > 0) { + s = cmdv[0] + k; + len = j; + } + } + + if (s != NULL) { + k = len + seplen; + /* make sure it fits */ + if (n + k >= CFG_CBSIZE - 2) { + putc('\a'); + return 1; + } + + t = buf + cnt; + for (i = 0; i < len; i++) + *t++ = *s++; + if (sep != NULL) + for (i = 0; i < seplen; i++) + *t++ = sep[i]; + *t = '\0'; + n += k; + col += k; + puts(t - k); + if (sep == NULL) + putc('\a'); + *np = n; + *colp = col; + } else { + print_argv(NULL, " ", " ", 78, cmdv); + + puts(prompt); + puts(buf); + } + return 1; +} + +#endif diff -ruNb u-boot-original/common/env_common.c u-boot-autocomplete/common/env_common.c --- u-boot-original/common/env_common.c 2004-03-30 14:37:28.668930568 +0300 +++ u-boot-autocomplete/common/env_common.c 2004-03-30 15:42:19.878376816 +0300 @@ -260,3 +260,44 @@ disable_nvram(); #endif } + +#ifdef CONFIG_AUTO_COMPLETE +int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf) +{ + int i, nxt, len, vallen, found; + const char *lval, *rval; + + found = 0; + cmdv[0] = NULL; + + len = strlen(var); + /* now iterate over the variables and select those that match */ + for (i=0; env_get_char(i) != '\0'; i=nxt+1) { + + for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) + ; + + lval = env_get_addr(i); + rval = strchr(lval, '='); + if (rval != NULL) { + vallen = rval - lval; + rval++; + } else + vallen = strlen(lval); + + if (len > 0 && (vallen < len || memcmp(lval, var, len) != 0)) + continue; + + if (found >= maxv - 2 || bufsz < vallen + 1) { + cmdv[found++] = "..."; + break; + } + cmdv[found++] = buf; + memcpy(buf, lval, vallen); buf += vallen; bufsz -= vallen; + *buf++ = '\0'; bufsz--; + } + + cmdv[found] = NULL; + return found; +} +#endif diff -ruNb u-boot-original/common/main.c u-boot-autocomplete/common/main.c --- u-boot-original/common/main.c 2004-03-30 14:37:28.670930264 +0300 +++ u-boot-autocomplete/common/main.c 2004-03-30 15:42:19.879376664 +0300 @@ -365,6 +365,10 @@ u_boot_hush_start (); #endif +#ifdef CONFIG_AUTO_COMPLETE + install_auto_complete(); +#endif + #ifdef CONFIG_PREBOOT if ((p = getenv ("preboot")) != NULL) { # ifdef CONFIG_AUTOBOOT_KEYED @@ -608,6 +612,14 @@ */ if (n < CFG_CBSIZE-2) { if (c == '\t') { /* expand TABs */ +#ifdef CONFIG_AUTO_COMPLETE + /* if auto completion triggered just continue */ + *p = '\0'; + if (cmd_auto_complete(prompt, console_buffer, &n, &col)) { + p = console_buffer + n; /* reset */ + continue; + } +#endif puts (tab_seq+(col&07)); col += 8 - (col&07); } else { diff -ruNb u-boot-original/include/command.h u-boot-autocomplete/include/command.h --- u-boot-original/include/command.h 2004-03-30 14:37:28.749918256 +0300 +++ u-boot-autocomplete/include/command.h 2004-03-30 15:42:19.880376512 +0300 @@ -46,6 +46,10 @@ #ifdef CFG_LONGHELP char *help; /* Help message (long) */ #endif +#ifdef CONFIG_AUTO_COMPLETE + /* do auto completion on the arguments */ + int (*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[]); +#endif }; typedef struct cmd_tbl_s cmd_tbl_t; @@ -57,6 +61,11 @@ /* common/command.c */ cmd_tbl_t *find_cmd(const char *cmd); +#ifdef CONFIG_AUTO_COMPLETE +extern void install_auto_complete(void); +extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp); +#endif + /* * Monitor Command * diff -ruNb u-boot-original/include/common.h u-boot-autocomplete/include/common.h --- u-boot-original/include/common.h 2004-03-30 14:37:28.750918104 +0300 +++ u-boot-autocomplete/include/common.h 2004-03-30 15:42:19.880376512 +0300 @@ -196,6 +196,10 @@ # include <asm/u-boot-i386.h> #endif /* CONFIG_I386 */ +#ifdef CONFIG_AUTO_COMPLETE +int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); +#endif + void pci_init (void); void pci_init_board(void); void pciinfo (int, int);

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[U-Boot-Users] Support for new Motorola chips 8247/48/71/72 and MPC8272ADS board
by Yuli Barcohen 15 Apr '04

15 Apr '04

This patch adds support for new members of Motorola PowerQUICC II family (MPC8247/48/71/72) and new Motorola evaluation board MPC8272ADS which is a derivative of MPC8260ADS. CHANGELOG: - Add support for MPC8272 family including MPC8247/8248/8271/8272 - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS) - Change configuration method for MPC8260ADS family -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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[U-Boot-Users] PATCH: PCMCIA and PXA250
by Leon KUKOVEC 15 Apr '04

15 Apr '04

Hi Woflgang, Note that I had to change TEXT_ADDRESS for board/wepep250, otherwise the image does not fit in (with IDE, PCMCIA, FAT support). The TEXT_ADDRESS change is as minimal as it can get. Note that before applying PXA PCMCIA, you need to apply Pierre's patch for IDE. Can anyone that worked on ARM memory layout confirm that please? Changes: o PCMCIA support for PXA Build Report: U-BOOT TOP BUILD REPORT: builds that FAILED to build: AR405 ERIC EVAL5200 MPC8540ADS MPC8560ADS U-BOOT PXA PCMCIA BUILD REPORT: (applied top-pxa-pcmcia patch) builds that FAILED to build: AR405 ERIC EVAL5200 MPC8540ADS MPC8560ADS U-BOOT PXA PCMCIA BUILD REPORT: (applied top-pxa-pcmcia patch + configuration changes) builds that FAILED to build: AR405 ERIC EVAL5200 MPC8540ADS MPC8560ADS Any issues, let me know. -- Best Regards, Leon.

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Re: [U-Boot-Users] MPC885 and Abatron BDI2000
by Sam Song 15 Apr '04

15 Apr '04

Wolfgang Denk wrote: > I don't think so, and my speculation is more of an > incorrect BDI2000 config file. But I may be wrong. > > I recommend to contact the excellent Abatron > support. But how to? They are apt to make third party vendors to do technical support as fas as I know. Best regards, Sam _________________________________________________________ Do You Yahoo!? 惠普TT游戏剧，玩游戏，中大奖！ http://cn.rd.yahoo.com/mail_cn/tag/SIG=1402c0to2/**http%3A%2F%2Fhp.allyes.c…

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RE: [U-Boot-Users] 440GX PHY/MII access
by Kerl, John 14 Apr '04

14 Apr '04

I may be mistaken, but we always avoid strapping PHY addresses to 0 since this is some sort of broadcast address. I think this is an industry-standard fact. The issues we've been experiencing (which are most likely due to a board-design issue) persist in spite of the PHYs having non-zero addresses. -----Original Message----- From: u-boot-users-admin(a)lists.sourceforge.net [mailto:u-boot-users-admin@lists.sourceforge.net] Sent: Wednesday, April 14, 2004 5:04 AM To: Yutao He Cc: u-boot-users(a)lists.sourceforge.net Subject: Re: [U-Boot-Users] 440GX PHY/MII access I don't know of anyway to bypass. You must restrap the PHY to a different address. I used the JTAG interface to disable all PHYs and the 440GX aways responds to address zero. Carl --- Yutao He <yutao(a)doremilabs.com> wrote: > Hi Carl, > > We have a customized 440GX-based board with only > EMAC2 and EMAC3. > And the PHY is using address zero. Yes we've got the > problem with the Ethernet interface. Could you > please > shed lights on how to by-pass this "un-documented" > feature to make EMACS2/3 work? > > Many thanks, > > --Yutao > > Carl Riechers wrote: > > If you are using address zero for the PHY you will > > have problems. The 440GX seems to use this > address > > for diagnostics. I could not find any > documentation > > on this. I have a simular configuration with only > > eth2 and eth3. If you are using the Marvel PHYs, > make > > sure you hardware reset them per the specification > > otherwise the soft reset will not work correctly. > > > > The author of the code was most likely using a > > different brand of PHY and needed to reset the PHY > to > > have access to certain registers. The code > > reconfigures the selected MAC to interface with > the > > serial bus to the PHYs. Each MAC has a MII serial > bus > > master, but only one can drive the MII serial > > interface to the PHYs though the bridge. > > > > Carl > > > > --- "Kerl, John" <John.Kerl(a)Avnet.com> wrote: > > > >>Hello, > >> > >>I am wondering if anyone can illuminate the > >>following code snippet, > >>from ppc_440x_eth_init() in > cpu/ppc4xx/440gx_enet.c: > >> > >> out32 (ZMII_SSR, ZMII_SSR_SP << > >>ZMII_SSR_V(devnum)); > >> __asm__ volatile ("eieio"); > >> > >> /* reset emac so we have access to the phy */ > >> out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); > >> __asm__ volatile ("eieio"); > >> > >> failsafe = 1000; > >> while ((in32 (EMAC_M0 + hw_p->hw_addr) & > >>(EMAC_M0_SRST)) && failsafe) { > >> udelay (1000); > >> failsafe--; > >> } > >> in32(EMAC_M0 + hw_p->hw_addr), EMAC_M0 + > >>hw_p->hw_addr); > >> > >>In particular I don't understand the comment > "reset > >>emac so we have > >>access to the phy". In fact, print statements > >>before and after > >>the MAC reset indicate that we *can* read PHY > >>registers before > >>the MAC reset, but we *lose* the ability to read > PHY > >>registers > >>after the MAC reset. Note that this does not > happen > >>on all > >>three boards, and not all the time. Also this > loss > >>of PHY-register > >>access after MAC reset is more likely to happen if > >>the Ethernet cable > >>is connected. > >> > >>Now, there are a couple oddities: (1) these are > >>brand-new boards, > >>still being debugged and flywired; (2) we are > using > >>EMACs 2 & 3 over > >>RGMII, but we have EMACs 0 & 1 not connected to > >>anything (unlike > >>the Ocotea board). > >> > >>In particular, I don't doubt that the above code > is > >>correct; certainly > >>the finger of doubt points in the direction of our > >>new board. Still, > >>though, I don't yet understand why the MAC reset > >>would cause PHY > >>access to go away. The scope reveals that after > the > >>MAC reset, the > >>MDIO line is no longer being driven. > >> > >>Does this ring any bells for anyone? > >> > >>Thanks. > >> > >> > >> > > > > > ------------------------------------------------------- > > > >>This SF.Net email is sponsored by: IBM Linux > >>Tutorials > >>Free Linux tutorial presented by Daniel Robbins, > >>President and CEO of > >>GenToo technologies. Learn everything from > >>fundamentals to system > >> > > > > > administration.http://ads.osdn.com/?ad_id70&alloc_id638&op=click > > > >>_______________________________________________ > >>U-Boot-Users mailing list > >>U-Boot-Users(a)lists.sourceforge.net > >> > > > > > https://lists.sourceforge.net/lists/listinfo/u-boot-users > > > > > > > > > > > > __________________________________ > > Do you Yahoo!? > > Yahoo! Small Business $15K Web Design Giveaway > > http://promotions.yahoo.com/design_giveaway/ > > > > > > > ------------------------------------------------------- > > This SF.Net email is sponsored by: IBM Linux > Tutorials > > Free Linux tutorial presented by Daniel Robbins, > President and CEO of > > GenToo technologies. Learn everything from > fundamentals to system > > > administration.http://ads.osdn.com/?ad_id=1470&alloc_id=3638&op=click > > _______________________________________________ > > U-Boot-Users mailing list > > U-Boot-Users(a)lists.sourceforge.net > > > https://lists.sourceforge.net/lists/listinfo/u-boot-users > > > > __________________________________ Do you Yahoo!? Yahoo! Tax Center - File online by April 15th http://taxes.yahoo.com/filing.html ------------------------------------------------------- This SF.Net email is sponsored by: IBM Linux Tutorials Free Linux tutorial presented by Daniel Robbins, President and CEO of GenToo technologies. Learn everything from fundamentals to system administration.http://ads.osdn.com/?ad_id=1470&alloc_id=3638&op=click _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] How to enable EMAC1 on IBM 405EP Bubinga board?
by Andy Vo 14 Apr '04

14 Apr '04

I'm trying to use the second EMAC channel on the IBM 450EP Bubinga board using U-boot but have no luck. I modified all the EMAC registers to point to the new EMAC1 base address. The PHY h/w is ok because I could tftp an image using the IBM monitor over the 2nd ethernet port. Am I missing something obvious? Thanks for any suggestion. Andy

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Re: [U-Boot-Users] 440GX PHY/MII access
by Carl Riechers 14 Apr '04

14 Apr '04

I don't know of anyway to bypass. You must restrap the PHY to a different address. I used the JTAG interface to disable all PHYs and the 440GX aways responds to address zero. Carl --- Yutao He <yutao(a)doremilabs.com> wrote: > Hi Carl, > > We have a customized 440GX-based board with only > EMAC2 and EMAC3. > And the PHY is using address zero. Yes we've got the > problem with the Ethernet interface. Could you > please > shed lights on how to by-pass this "un-documented" > feature to make EMACS2/3 work? > > Many thanks, > > --Yutao > > Carl Riechers wrote: > > If you are using address zero for the PHY you will > > have problems. The 440GX seems to use this > address > > for diagnostics. I could not find any > documentation > > on this. I have a simular configuration with only > > eth2 and eth3. If you are using the Marvel PHYs, > make > > sure you hardware reset them per the specification > > otherwise the soft reset will not work correctly. > > > > The author of the code was most likely using a > > different brand of PHY and needed to reset the PHY > to > > have access to certain registers. The code > > reconfigures the selected MAC to interface with > the > > serial bus to the PHYs. Each MAC has a MII serial > bus > > master, but only one can drive the MII serial > > interface to the PHYs though the bridge. > > > > Carl > > > > --- "Kerl, John" <John.Kerl(a)Avnet.com> wrote: > > > >>Hello, > >> > >>I am wondering if anyone can illuminate the > >>following code snippet, > >>from ppc_440x_eth_init() in > cpu/ppc4xx/440gx_enet.c: > >> > >> out32 (ZMII_SSR, ZMII_SSR_SP << > >>ZMII_SSR_V(devnum)); > >> __asm__ volatile ("eieio"); > >> > >> /* reset emac so we have access to the phy */ > >> out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); > >> __asm__ volatile ("eieio"); > >> > >> failsafe = 1000; > >> while ((in32 (EMAC_M0 + hw_p->hw_addr) & > >>(EMAC_M0_SRST)) && failsafe) { > >> udelay (1000); > >> failsafe--; > >> } > >> in32(EMAC_M0 + hw_p->hw_addr), EMAC_M0 + > >>hw_p->hw_addr); > >> > >>In particular I don't understand the comment > "reset > >>emac so we have > >>access to the phy". In fact, print statements > >>before and after > >>the MAC reset indicate that we *can* read PHY > >>registers before > >>the MAC reset, but we *lose* the ability to read > PHY > >>registers > >>after the MAC reset. Note that this does not > happen > >>on all > >>three boards, and not all the time. Also this > loss > >>of PHY-register > >>access after MAC reset is more likely to happen if > >>the Ethernet cable > >>is connected. > >> > >>Now, there are a couple oddities: (1) these are > >>brand-new boards, > >>still being debugged and flywired; (2) we are > using > >>EMACs 2 & 3 over > >>RGMII, but we have EMACs 0 & 1 not connected to > >>anything (unlike > >>the Ocotea board). > >> > >>In particular, I don't doubt that the above code > is > >>correct; certainly > >>the finger of doubt points in the direction of our > >>new board. Still, > >>though, I don't yet understand why the MAC reset > >>would cause PHY > >>access to go away. The scope reveals that after > the > >>MAC reset, the > >>MDIO line is no longer being driven. > >> > >>Does this ring any bells for anyone? > >> > >>Thanks. > >> > >> > >> > > > > > ------------------------------------------------------- > > > >>This SF.Net email is sponsored by: IBM Linux > >>Tutorials > >>Free Linux tutorial presented by Daniel Robbins, > >>President and CEO of > >>GenToo technologies. Learn everything from > >>fundamentals to system > >> > > > > > administration.http://ads.osdn.com/?ad_id70&alloc_id638&op=click > > > >>_______________________________________________ > >>U-Boot-Users mailing list > >>U-Boot-Users(a)lists.sourceforge.net > >> > > > > > https://lists.sourceforge.net/lists/listinfo/u-boot-users > > > > > > > > > > > > __________________________________ > > Do you Yahoo!? > > Yahoo! Small Business $15K Web Design Giveaway > > http://promotions.yahoo.com/design_giveaway/ > > > > > > > ------------------------------------------------------- > > This SF.Net email is sponsored by: IBM Linux > Tutorials > > Free Linux tutorial presented by Daniel Robbins, > President and CEO of > > GenToo technologies. Learn everything from > fundamentals to system > > > administration.http://ads.osdn.com/?ad_id=1470&alloc_id=3638&op=click > > _______________________________________________ > > U-Boot-Users mailing list > > U-Boot-Users(a)lists.sourceforge.net > > > https://lists.sourceforge.net/lists/listinfo/u-boot-users > > > > __________________________________ Do you Yahoo!? Yahoo! Tax Center - File online by April 15th http://taxes.yahoo.com/filing.html

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[U-Boot-Users] SCC Ethernet and "Linux crashes by early packets" ???
by Steven Scholz 14 Apr '04

14 Apr '04

Hi there, the CHANGELOG contains the lines * Make sure SCC Ethernet is always stopped by the time we boot Linux to avoid Linux crashes by early packets coming in. in "Changes for U-Boot 1.0.2". My two question: 1.) How can I find out which changes in the CVS do excactly this? 2.) Do we need the same with 8xx FEC Ethernet? I am asking because I am expierencing sporadic crashes when booting linux from U-Boot 1.0.0. But only when I init the ethernet (e.g. by doing "dhcp" or "tftp") before booting... -- Steven Scholz imc Measurement & Control imc Meßsysteme GmbH Voltastr. 5 Voltastr. 5 13355 Berlin 13355 Berlin Germany Deutschland

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RE: [U-Boot-Users] Cascaded U-Boot setup question
by VanBaren, Gerald (AGRE) 13 Apr '04

13 Apr '04

Yup, that is the u-boot execute out of RAM issue #1 -- your new u-boot is trying to (re)initialize the RAM that it is executing out of, effectively pulling the rug out from under itself. You have to suppress the RAM initialization and possibly other hardware initializations (issues #2-#n) in the second u-boot before you can run it. gvb > -----Original Message----- > From: u-boot-users-admin(a)lists.sourceforge.net > [mailto:u-boot-users-admin@lists.sourceforge.net]On Behalf Of Mike > Wellington > Sent: Tuesday, April 13, 2004 12:22 PM > To: u-boot-users(a)lists.sourceforge.net > Subject: Re: [U-Boot-Users] Cascaded U-Boot setup question > > > Now I tried: > > > tftp 0x200000 u-boot.bin ; go 0x200100 > > U-boot begins execution but hangs after the DRAM message. > > > > Mike Wellington wrote: > > > > Hi- > > I have multiple Xilinx ML300 boards. Each one has its own > > ip address. Each board may have different boot parameters - baud > > rate, root file system, etc. Basically each board needs its > > own boot parameters stored in some kind of non-volatile storage. > > But there is no working non-volatile storage on these boards (yet), > > until I get I2C EEPROM working. Each board just boots from its > > copy of u-boot (which is generic) from the microdrive. Now, I > > could sit at each board and as it comes up, stop the autoboot > > and manually enter the parameters, but that's clunky. What > > I want to do is build a board-specific u-boot with parameters > > that are specific to that machine-name. So my boot > > process would be: > > > > 1) Load the generic u-boot off the microdrive. It knows what > > *machine-name* is and where to get the next stage at. > > > > 2) Use the generic u-boot to download a machine-specific u-boot, > > uboot-<machine-name>, which I can recompile and change at will > > since it resides on my tftp server. I don't have to rewrite > > the microdrive every time I want to change the boot parameters, > > all I have to do is build a new *second-stage* machine-specific > > u-boot-<machine-name> and put it in the /tftp download > directory. > > > > 3) Run the 2nd u-boot (u-boot-<machine-name>) > > (which has the machine specific parameters) > > and let it boot the kernel with the arguments that I want. > > > > I tried downloading an uncompressed u-boot and loading it > at 0x20000, > > then just saying "go 0x20000" and it doesn't work, it generates and > > illegal instruction exception. (is the starting address of > u-boot not > > at the beginning of the .TEXT section - I'll go check after > I send this > > email) > > > > I tried downloading a compressed u-boot with '-T > standalone' and then > > saying "bootm 0x200000" and that doesn't work either. > > > > Is this doable? It should be. Does anybody know how to do it? > > > > I guess the other thing I "could" do is run expect on the > serial port > > and set up the paramters that way, but I think the *cascaded u-boot* > > idea is better. > > > > -mike wellington > > wellington(a)lucent.com > > platforms(a)bithead.com > > > > > > > > ------------------------------------------------------- > > This SF.Net email is sponsored by: IBM Linux Tutorials > > Free Linux tutorial presented by Daniel Robbins, President > and CEO of > > GenToo technologies. Learn everything from fundamentals to system > > > administration.http://ads.osdn.com/?ad_id=1470&alloc_id=3638&op=click > > _______________________________________________ > > U-Boot-Users mailing list > > U-Boot-Users(a)lists.sourceforge.net > > https://lists.sourceforge.net/lists/listinfo/u-boot-users > > > > ------------------------------------------------------- > This SF.Net email is sponsored by: IBM Linux Tutorials > Free Linux tutorial presented by Daniel Robbins, President and CEO of > GenToo technologies. Learn everything from fundamentals to system > administration.http://ads.osdn.com/?ad_id=1470&alloc_id=3638&op=click > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users > ****************************************** The information contained in, or attached to, this e-mail, may contain confidential information and is intended solely for the use of the individual or entity to whom they are addressed and may be subject to legal privilege. If you have received this e-mail in error you should notify the sender immediately by reply e-mail, delete the message from your system and notify your system manager. Please do not copy it for any purpose, or disclose its contents to any other person. The views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the company. The recipient should check this e-mail and any attachments for the presence of viruses. The company accepts no liability for any damage caused, directly or indirectly, by any virus transmitted in this email. ******************************************

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[U-Boot-Users] 440GX PHY/MII access
by Kerl, John 13 Apr '04

13 Apr '04

Hello, I am wondering if anyone can illuminate the following code snippet, from ppc_440x_eth_init() in cpu/ppc4xx/440gx_enet.c: out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); __asm__ volatile ("eieio"); /* reset emac so we have access to the phy */ out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); __asm__ volatile ("eieio"); failsafe = 1000; while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { udelay (1000); failsafe--; } in32(EMAC_M0 + hw_p->hw_addr), EMAC_M0 + hw_p->hw_addr); In particular I don't understand the comment "reset emac so we have access to the phy". In fact, print statements before and after the MAC reset indicate that we *can* read PHY registers before the MAC reset, but we *lose* the ability to read PHY registers after the MAC reset. Note that this does not happen on all three boards, and not all the time. Also this loss of PHY-register access after MAC reset is more likely to happen if the Ethernet cable is connected. Now, there are a couple oddities: (1) these are brand-new boards, still being debugged and flywired; (2) we are using EMACs 2 & 3 over RGMII, but we have EMACs 0 & 1 not connected to anything (unlike the Ocotea board). In particular, I don't doubt that the above code is correct; certainly the finger of doubt points in the direction of our new board. Still, though, I don't yet understand why the MAC reset would cause PHY access to go away. The scope reveals that after the MAC reset, the MDIO line is no longer being driven. Does this ring any bells for anyone? Thanks.

3 3

AW: [U-Boot-Users] MIPS, little endian, supported cross tool vers ions?
by Jörg Albert 13 Apr '04

13 Apr '04

Hi Wolfgang, you wrote: > > mipsel-uclibc-gcc: unrecognized option `-EL' > > It seems obvious that your tools and or compiler options are broken > and/or misconfigured. > > Where is this "-mips2 -EL" stuff coming from? You don't find this in > U-Boot. Sorry for skipping the first steps. I changed the prefix "mips_4KC-" into "mipsel-uclibc-" (./Makefile) leading to: mipsel-uclibc-gcc -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/opt/work/fw/b ootloader/u-boot-1.0.0.purple/include -fno-builtin -ffreestanding -nostdinc -isy stem /opt/toolchains/toolchain_mipsel/lib/gcc-lib/mipsel-linux/3.3.1/include -pi pe -DCONFIG_MIPS -D__MIPS__ -mcpu=4kc -EB -mabicalls -Wall -Wstrict-prototypes -c -o stubs.o stubs.c cc1: error: invalid option `cpu=4kc' Afterwards I changed "-mcpu=4kc" into "-mips2" in cpu/mips/config.mk. "-EL" to replace "-EB" as I want a little-endian boot loader, but "-EL" is default anyway and ignored. > Obviously this is a tool problem first. I guess you will need to fix > this anyway, or you will run into the same problems later when you > want to compile your OS kernel and/or applications. Doubt this, as I've already compiled a running 2.4.22 kernel. I've replaced "-mcpu=4kc" by "-march=4kc" (a better match I guess), applied Masami's patch of the linker control files and got: mipsel-uclibc-gcc -Wa,-gstabs -D__ASSEMBLY__ -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/opt/work/fw/bootloader/u-boot-1.0.0.work/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/toolchains/toolchain_mipsel/lib/gcc-lib/mipsel-linux/3.3.1/include -pipe -DCONFIG_MIPS -D__MIPS__ -march=4kc -mabicalls -c -o start.o /opt/work/fw/bootloader/u-boot-1.0.0.work/cpu/mips/start.S /opt/work/fw/bootloader/u-boot-1.0.0.work/cpu/mips/start.S: Assembler messages: /opt/work/fw/bootloader/u-boot-1.0.0.work/cpu/mips/start.S:242: Error: Cannot branch to undefined symbol. /opt/work/fw/bootloader/u-boot-1.0.0.work/cpu/mips/start.S:247: Error: Cannot branch to undefined symbol. /opt/work/fw/bootloader/u-boot-1.0.0.work/cpu/mips/start.S:259: Error: Cannot branch to undefined symbol. I guess gcc 3.3.1 doesn't like the option "-mcpu=" nor branch-and-link to undefined symbols anymore. AFAIK the toolchain Masami recommended is verson 2.96.x I've replaced the three branches (bal) by jumps (jal) and moved the GOT initialization before them which let me successfully compile the boot loader. I'll now add the board-specific stuff (serial driver, flash, network). Wonder if anyone out there has ever tried gcc 3.3.x for compiling a MIPS U-Boot (big or little-endian)? /Jörg

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[U-Boot-Users] IMMAP M5282 correct?
by nafiton smith 13 Apr '04

13 Apr '04

Hello I am having problems trying to use the net features on a new board configuration. Is it possible that the include/asm-m68k/immap_5282.h file is wrong? It seems to not coincide with Motorola documentation about its FEC registers. Thanks

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[U-Boot-Users] Ethner RxBd init problem
by Dave Johnson 13 Apr '04

13 Apr '04

Hi All: I have 8260 based board and am using u-boot for that. I boot kernel from the flash. All works fine however sometimes Linux Kernel does not boot after uncompressing, further investigation found that as the kernel entry point is address 0, and that is also address of netRxPackets, if a packet is received after the kernel is unzipped by u-boot, ethernet driver corrupts data at address 0 thinking it as its buffer pointer. Hence kernel does not boot up in that case. My first question is that why we dont initialize netRxPackets in net.c?? (these are only initialized once a network related operation (like ping) is done). Is this the corect behaviour?? has anyone observed this problem?? Thanks Dave. __________________________________ Do you Yahoo!? Yahoo! Tax Center - File online by April 15th http://taxes.yahoo.com/filing.html

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[U-Boot-Users] Re: How to create the JFFS2?
by Wolfgang Denk 12 Apr '04

12 Apr '04

In message <BAY9-F29iP3ih1oVNkE000114ad(a)hotmail.com> you wrote: > The embedded system i will use is JFFS2, I followed the steps of DULG, > run net_nfs, at first,I suppose the uRamdisk is in /tmp/flashtools > but the wrong message is following : > root@172.16.115.7:/# mkfs.jffs2 --pad=4194304 --eraseblock=262144 \ > > --root=/tmp/flashtools/ --output image.jffs2 does this really match your system parameters? > eraseall /dev/mtd4 > eraseall: /dev/mtd4: No such device > root@172.16.115.7:/# dd if=image.jffs2 of=/dev/mtd4 bs=256k > dd: opening `/dev/mtd4': No such device Did you enable MTD in your Linux kernel? > but there has /dev/mtd4 ,this is why? what is the following steps for > creating JFFS2? Go back in the DULG to read the section about MTD: http://www.denx.de/twiki/bin/view/DULG/FlashFilesystemsMTD Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de There's no honorable way to kill, no gentle way to destroy. There is nothing good in war. Except its ending. -- Abraham Lincoln, "The Savage Curtain", stardate 5906.5

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[U-Boot-Users] Hush 'elif' operation?
by Robin Gilks 12 Apr '04

12 Apr '04

Greetings I'm trying to get as close to a switch statement in hush shell language as possible and thought that a set of if/then/elif/else would be tidier than nested if/then/else. It doesn't work how I expected however. The example below illustrates the problem - I was expecting execution after a true test (in the first 'if' in this case) to continue after the 'fi' but instead it ploughs through all the other executable (echo) statements having skipped the elif statements. It does correctly skip the else clause however :-)) Could someone assist in the navigation of this module to point out where would be a good place to start (i.e. some basic principles and assumptions of how the parser works). [apologies for the word wrapping] =>if iml; then echo "one"; elif iml; then echo "two"; elif iml; then echo "three"; else echo "four"; fi Image at 40340000: Image Name: Linux-2.4.22-20040129-12:57 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 630253 Bytes = 615.5 kB Load Address: 00000000 Entry Point: 00000000 one two three => Many thanks -- Robin Gilks Senior Design Engineer Phone: (+64)(3) 357 1569 Tait Electronics Fax : (+64)(3) 359 4632 PO Box 1645 Christchurch Email : robin.gilks(a)tait.co.nz New Zealand

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[U-Boot-Users] ELDK
by zhu hao 11 Apr '04

11 Apr '04

>>Hello everybody, >Where can I download the .pdf of ELDK? >Best regards, > _________________________________________________________________ 与联机的朋友进行交流，请使用 MSN Messenger: http://messenger.msn.com/cn

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