February 2004 - U-Boot

[U-Boot-Users] Intel LXT971A PHY support
by Tolunay Orkun 08 Feb '04

08 Feb '04

Hi, I am in the process of creating a U-Boot port for Cogent CSB272 board (PPC405) Working from U-Boot 1.0.0 tarball sources, I got CSB272 running. I still have some work done for it so I am not submitting CSB272 board support yet. Maybe next week or so after I complete work on it and make sure Linux boots OK. Anyway, CSB272 board has Intel LXT971A PHY. I could not get this PHY working initially. After investigation I have found: 1) LXT971A requires some recovery time (~300usec) before any register access after reset. This is documented in the datasheet on page 70, table 40. 2) LXT971A requires some time after command is issued before polling EMAC_STACR_OC is valid. I am not sure why this is needed but it is needed for this particular PHY or otherwise it does not work. I have found this to be minimum 32usec. I used 40usec for some safety margin. Thus, to get it working I had to patch two shared files: cpu/ppc4xx/miiphy.c common/miiphyutil.c The code added are conditional for each change and without those macro definitions it compiles exactly as it is right now. The macros are as follows (from my include/configs/csb272.h): #define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ /* 32usec min. for LXT971A */ #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ Here is the patch (I can resend it as an attachment if format is broken) --- u-boot-1.0.0/cpu/ppc4xx/miiphy.c 2003-09-02 18:08:13.000000000 -0500 +++ u-boot/cpu/ppc4xx/miiphy.c 2004-01-11 02:56:16.000000000 -0600 @@ -110,7 +110,9 @@ int miiphy_read (unsigned char addr, uns #if 0 /* test-only */ printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif - +#if defined(CONFIG_PHY_CMD_DELAY) + udelay(CONFIG_PHY_CMD_DELAY); /* Intel LXT971A needs this */ +#endif sta_reg = in32 (EMAC_STACR); i = 0; while ((sta_reg & EMAC_STACR_OC) == 0) { @@ -166,6 +168,9 @@ int miiphy_write (unsigned char addr, un memcpy (&sta_reg, &value, 2); /* put in data */ out32 (EMAC_STACR, sta_reg); +#if defined(CONFIG_PHY_CMD_DELAY) + udelay(CONFIG_PHY_CMD_DELAY); /* Intel LXT971A needs this */ +#endif /* wait for completion */ i = 0; --- u-boot-1.0.0/common/miiphyutil.c 2003-10-08 17:33:00.000000000 -0500 +++ u-boot/common/miiphyutil.c 2004-01-11 22:42:42.249886108 -0600 @@ -103,6 +103,9 @@ int miiphy_reset (unsigned char addr) return (-1); } +#if defined(CONFIG_PHY_RESET_DELAY) + udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ +#endif /* * Poll the control register for the reset bit to go to 0 (it is * auto-clearing). This should happen within 0.5 seconds per the

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[U-Boot-Users] [PATCH] small correction (again)
by Stephan Linz 08 Feb '04

08 Feb '04

Hi all, - makes the DK1C20 board configuration related to ASMI more conform to documentation Best Regards, Stephan Linz

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[U-Boot-Users] [PATCH] small correction
by Stephan Linz 08 Feb '04

08 Feb '04

Hi all, - avoid harmless warning: unused variable `piop' in board/altera/common/sevenseg.c Best Regards, Stephan Linz

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[U-Boot-Users] [PATCH] fix the ARM memory layout
by Anders Larsen 08 Feb '04

08 Feb '04

Hi, here's a fresh version of my rather intrusive patch from the 17.th sept. to rearrange the ARM memory layout to bring it in line with the README. This has the positive side-effect of actually allow U-Boot to run on PXA- and IXP-based targets; the current implementation sets up the heap using bogus addresses causing u-boot to crash (this even applies to the recently added board "ixdp425"). This patch doesn't go all the way, though, since doing away with the board-specific setting of TEXT_BASE would require the code to be position-independent, which at least the cpu initialization code in cpu/*/start.S is _not_. CHANGELOG: Bring the ARM memory layout in line with the documentation. Cheers Anders

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[U-Boot-Users] Re: A small mistake in flash.h
by Wolfgang Denk 07 Feb '04

07 Feb '04

Hello, in message <HR7SJN00.ORT(a)mail.cs.sjtu.edu.cn> you wrote: > > There is a small mistake in file "include/flash.h" of uboot-1.0.0 > > #define INTEL_ID_28F128J3 0x89189818 /* 16M øM x 16 x 128 */ <--- "0x89189818" or "0x89188918" > #define INTEL_ID_28F320J5 0x00140014 /* 32M ñ28K x 32 */ > #define INTEL_ID_28F640J5 0x00150015 /* 64M ñ28K x 64 */ You are right. Thanks. Fixed in CVS. Best regards, Wolfgang Denk -- See us @ Embedded World, Nuremberg, Feb 17 - 19, Hall 12.0 Booth 440 Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de "You know, after a woman's raised a family and so on, she wants to start living her own life." "Whose life she's _been_ living, then?" - Terry Pratchett, _Witches Abroad_

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[U-Boot-Users] Re: Patch for TB0229 board
by Wolfgang Denk 07 Feb '04

07 Feb '04

Dear Masami Komiya, in message <3FFE675B.9030006(a)sonare.it> you wrote: > > I send the patch against the current CVS to add support for TB0229 > board in Japan. NEC's VR4131 MIPS type CPU is on this board. Thanks a lot. Added to CVS. Sorry this took so long. Ummm... will yuou please also send patch to add yourself to the CREDITS and MAINTAINERS files? Thanks in advance. Best regards, Wolfgang Denk -- See us @ Embedded World, Nuremberg, Feb 17 - 19, Hall 12.0 Booth 440 Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de "There is no distinctly American criminal class except Congress." - Mark Twain

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[U-Boot-Users] cpu/mpc8xx/cpu.c version 1.7 breaks get_tbclk for mpc850
by Ruhland, Paul 07 Feb '04

07 Feb '04

In 'cpu/mpc8xx/cpu.c' the 'get_tbclk()' function was modified to check the immr PARTNUM and MASKNUM fields in an attempt to identify newer parts. As it is now, if the PARTNUM field is >= 0x08 the osclk divisor is calculated for newer parts. However, an 850s PARTNUM field is 0x20. This causes the divisor to be calculated incorrectly using the 'new' method. I don't know all the PARTNUM fields so I can't really fix this. I'm just commenting it out for now. -- Paul Ruhland Microwave Data Systems, Inc. 175 Science Parkway Rochester, NY 14620 pruhland(a)microwavedata.com

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[U-Boot-Users] PATCH: include/linux/byteorder/swab.h
by Leon Kukovec 07 Feb '04

07 Feb '04

Fixes: o the optimization can now be disabled (config.mk: OPTFLAGS = -O0) (makes debugging easier) Change: o changed extern __inline__ into static __inline__ in include/linux/byteorder/swab.h COMPILER: ELDK x86 2.1.0 (RedHat 9.0) BUILD FOR: ppc mips arm BUILD STATUS: ERIC FAILED ixdp425 FAILED lubbock FAILED MPC8540ADS FAILED MPC8560ADS FAILED NOTE: the same builds fail for U-Boot HEAD branch. -- Best Regards, Leon.

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[U-Boot-Users] PATCH: itest - an integer compare function
by Robin Gilks 07 Feb '04

07 Feb '04

Changelog: Introduce a new command to be used in conditional expressions (such as hush 'if') to test the value of a memory location. Supports -eq, -ne, -gt, -lt, -ge, -le Allows scalars or memory contents (value prefixed by '*') Makes use of command data width expression of .l, .wm .b for 4, 2 or 1 byte wide comparisons e.g. if itest.l *40000 -eq 12345678; then bootm 41000; else bootm 80000; fi Patch is against u-boot-1.0.0 Note: I'm still concerned that the CONFIG_COMMANDS mask has run out of bits - maybe time for a different mechanism as I'm sure the bit I've used has gone by now!! -- Robin Gilks Senior Design Engineer Phone: (+64)(3) 357 1569 Tait Electronics Fax : (+64)(3) 359 4632 PO Box 1645 Christchurch Email : robin.gilks(a)tait.co.nz New Zealand

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[U-Boot-Users] Re: Patch Resubmit: PPC440GX
by Wolfgang Denk 07 Feb '04

07 Feb '04

In message <1072815902.5925.4.camel(a)pavement.sandburst.com> you wrote: > > Attached please find the patch file for support of the IBM > PPC440GX processor. Included in the patch is support for the > XES Inc. xpedite1000 440GX based PrPMC board. > > This patch also includes support for all four EMAC Ethernet > devices on the GX, which can be used with the 2 EMACs contained > within the 440GP. > > Most of this work is a port from the 405/440GP based work previously > done by other contributors. > > CHANGELOG: > 30 DEC 2003 Travis B. Sawyer <travis.sawyer(a)sandburst.com> > Add support for IBM PPC440GX. Multiple EMAC Ethernet devices, select > MDI port based on enabled EMAC device. > Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX > base PrPMC board. Added. Thanks. Best regards, Wolfgang Denk -- See us @ Embedded World, Nuremberg, Feb 17 - 19, Hall 12.0 Booth 440 Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de The most exciting phrase to hear in science, the one that heralds new discoveries, is not "Eureka!" (I found it!) but "That's funny ..." -- Isaac Asimov

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[U-Boot-Users] [patch] CONFIG_SILENT_CONSOLE
by Wolter Kamphuis 06 Feb '04

06 Feb '04

Hi all, I've changed the implementation of the CONFIG_SILENT_CONSOLE flag a bit. Instead of checking for the CONFIG_SILENT_CONSOLE flag in lib_*/board.c I've moved the code to common/console.c. Now all (and future) architectures and boards can use the CONFIG_SILENT_CONSOLE flag. The patch is against the current CVS. Wolter Kamphuis MuLogic B.V. diff -purN u-boot/common/console.c u-boot.silent/common/console.c --- u-boot/common/console.c 2003-10-16 01:53:50.000000000 +0200 +++ u-boot.silent/common/console.c 2003-12-15 10:37:49.000000000 +0100 @@ -191,6 +191,11 @@ void putc (const char c) { DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SILENT_CONSOLE + if (gd->flags & GD_FLG_SILENT) + return(0); +#endif + if (gd->flags & GD_FLG_DEVINIT) { /* Send to the standard output */ fputc (stdout, c); @@ -204,6 +209,11 @@ void puts (const char *s) { DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SILENT_CONSOLE + if (gd->flags & GD_FLG_SILENT) + return; +#endif + if (gd->flags & GD_FLG_DEVINIT) { /* Send to the standard output */ fputs (stdout, s); diff -purN u-boot/doc/README.silent u-boot.silent/doc/README.silent --- u-boot/doc/README.silent 2003-10-10 12:05:42.000000000 +0200 +++ u-boot.silent/doc/README.silent 2003-12-15 10:54:52.000000000 +0100 @@ -9,8 +9,6 @@ The following actions are taken if "sile - Until the console devices have been initialized, output has to be suppressed by testing for the flag "GD_FLG_SILENT" in "gd->flags". - Currently only the messages for the TRAB board are handled in this - way. - When the console devices have been initialized, "stdout" and "stderr" are set to "nulldev", so subsequent messages are diff -purN u-boot/lib_arm/board.c u-boot.silent/lib_arm/board.c --- u-boot/lib_arm/board.c 2003-12-07 01:46:27.000000000 +0100 +++ u-boot.silent/lib_arm/board.c 2003-12-15 10:39:02.000000000 +0100 @@ -115,13 +115,6 @@ static int init_baudrate (void) static int display_banner (void) { -#ifdef CONFIG_SILENT_CONSOLE - DECLARE_GLOBAL_DATA_PTR; - - if (gd->flags & GD_FLG_SILENT) - return (0); -#endif - printf ("\n\n%s\n\n", version_string); printf ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", _armboot_start, _armboot_end_data, _armboot_end); @@ -148,11 +141,6 @@ static int display_dram_config (void) DECLARE_GLOBAL_DATA_PTR; int i; -#ifdef CONFIG_SILENT_CONSOLE - if (gd->flags & GD_FLG_SILENT) - return (0); -#endif - puts ("RAM Configuration:\n"); for(i=0; i<CONFIG_NR_DRAM_BANKS; i++) { @@ -165,12 +153,6 @@ static int display_dram_config (void) static void display_flash_config (ulong size) { -#ifdef CONFIG_SILENT_CONSOLE - DECLARE_GLOBAL_DATA_PTR; - - if (gd->flags & GD_FLG_SILENT) - return; -#endif puts ("Flash: "); print_size (size, "\n"); }

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[U-Boot-Users] Editing u-boot parameters from Linux using MTD
by Jeff Angielski 06 Feb '04

06 Feb '04

Has anybody converted the environment code from u-boot into a Linux application that can change the u-boot parameters through the MTD layer? I am just trying to save some time by not duplicating previous efforts. Jeff Angielski The PTR Group

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RE: [U-Boot-Users] Editing u-boot parameters from Linux using MTD
by Diekema, Jon (AGRE) 06 Feb '04

06 Feb '04

> Has anybody converted the environment code from u-boot into a > Linux application that can change the u-boot parameters > through the MTD layer? We are using two busybox applets: setenv and printenv I have attached two files that do all the real work. These files could be converted into stand alone application. ------------------\\----------------------\\---------------------------- Jon Diekema | | Smiths Aerospace (616) 241-8310 | | 3290 Patterson Avenue, SE jon.diekema(a)smiths-aerospace.com \\ Grand Rapids, MI 49512 ****************************************** The information contained in, or attached to, this e-mail, may contain confidential information and is intended solely for the use of the individual or entity to whom they are addressed and may be subject to legal privilege. If you have received this e-mail in error you should notify the sender immediately by reply e-mail, delete the message from your system and notify your system manager. Please do not copy it for any purpose, or disclose its contents to any other person. The views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the company. The recipient should check this e-mail and any attachments for the presence of viruses. The company accepts no liability for any damage caused, directly or indirectly, by any virus transmitted in this email. ******************************************

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[U-Boot-Users] IDE Access from U-Boot
by sudhakar rajashekhara 06 Feb '04

06 Feb '04

Hi All, We are trying to boot Linux from SATA 150 Tx2plus Promise HDD using U-Boot from a MPC8280 board. The ATA card is a 33Mhz PCI card. After U-Boot comes up, it's able to detect the PCI card and also identifies the IDE device. But the IDE initializations of U-Boot fails. Is the memory mapping for the Promise device correct? How can I confirm it? Following is the U-Boot log: Intializing 8250 PCI, Hose Addres 0xffaec10 In: serial Out: serial Err: serial Net: FCC2 ETHERNET IDE: Bus 0: not available Bus 1: not available Hit any key to stop autoboot: 5 4 0 => => => => => => => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1057 0x18c0 Bridge device 0x00 00.10.00 0x105a 0x3375 Mass storage 0x80 00.11.00 0x104c 0xac51 Bridge device 0x07 00.11.01 0x104c 0xac51 Bridge device 0x07 00.12.00 0x1014 0x01a7 Bridge device 0x04 // PCI Bridge Configuration Space => pci header 0.0.0 vendor ID = 0x1057 device ID = 0x18c0 command register = 0x0006 status register = 0x20b0 revision ID = 0x20 class code = 0x06 (Bridge device) sub class code = 0x00 programming interface = 0x00 cache line = 0x08 latency time = 0xf8 header type = 0x00 BIST = 0x00 base address 0 = 0x00000000 base address 1 = 0x00000008 base address 2 = 0x00000000 base address 3 = 0x00000000 base address 4 = 0x00000000 base address 5 = 0x00000000 cardBus CIS pointer = 0x00000000 sub system vendor ID = 0x0000 sub system ID = 0x0000 expansion ROM base address = 0x00000000 interrupt line = 0x00 interrupt pin = 0x01 min Grant = 0x00 max Latency = 0x00 // Promise Card Configuration Space => pci header 0.10.0 vendor ID = 0x105a device ID = 0x3375 command register = 0x0007 status register = 0x0230 revision ID = 0x02 class code = 0x01 (Mass storage controller) sub class code = 0x80 programming interface = 0x00 cache line = 0x08 latency time = 0x80 header type = 0x00 BIST = 0x00 base address 0 = 0xa0000001 base address 1 = 0xa0000041 base address 2 = 0xa0000081 base address 3 = 0x80000000 base address 4 = 0x80020000 base address 5 = 0x00000000 cardBus CIS pointer = 0x00000000 sub system vendor ID = 0x105a sub system ID = 0x3375 expansion ROM base address = 0x00080001 interrupt line = 0x0e interrupt pin = 0x01 min Grant = 0x04 max Latency = 0x12 => md 80020000 80020000: 55aa20e9 de320000 52000000 00000000 U. ..2..R....... 80020010: 00000000 00000000 8e110c2e 00000000 ................ 80020020: 75335a10 75336000 00bd1e06 5633d232 u3Z.u3`.....V3.2 80020030: e4d1e08a d48ae032 c0be2000 1e2e8e1e .......2.. ..... 80020040: 6f11f606 7b00201f 7402eb29 894414c7 o...{. .t..).D.. 80020050: 44160080 8cc08af4 c0ee04c1 e00403d8 D............... 80020060: 8ac61400 32e48ec0 895c108c 4412b901 ....2....\..D... 80020070: 005e071f c3890489 5402895c 04c74406 .^......T..\..D. 80020080: 00008c44 08c7440c 1000c744 10ffffc7 ...D..D....D.... 80020090: 4412ffff 5006578c d88ec0bf 2000b805 D...P.W..... ... 800200a0: 8133d2cd 4b5f0758 72a2837c 10ff749c .3..K_.Xr..|..t. 800200b0: 837c12ff 74968cd8 8ec057bf 2000b806 .|..t.....W. ... 800200c0: 81ba0000 cd4b5fbe 20008b4c 0e518d74 .....K_. ..L.Q.t 800200d0: 10c74406 000083c6 08e2f683 ee08804c ..D............L 800200e0: 078059eb 8c568a04 d0e00244 01b410f6 ..Y..V.....D.... 800200f0: e4be6710 03f02e8a 64022e8a 440e5e50 ..g.....d...D.^P regards, Sudhakar. __________________________________ Do you Yahoo!? Yahoo! Finance: Get your refund fast by filing online. http://taxes.yahoo.com/filing.html

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[U-Boot-Users] u-boot PCMCIA and 405GPr
by Laurent Mohin 06 Feb '04

06 Feb '04

Hello all, Sorry if my question has been already answered but I'm unable to browse the u-boot mailing lists (it seems that I need a subscription to perform search). I would like to add PCMCIA support on my board based around a 405GPr and a Texas PCI1520 chip. I've enabled CFG_CMD_PCMCIA and encountered an error when compiling cmd_pcmcia.c (immap_t not defined). This is due to the fact that this file is mainly build for mpc8xx processors. The only way I've found to get rid of this error is to enable the CONFIG_I82365 flag which is relevant to an Intel chip. Am I missing something? Laurent

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[U-Boot-Users] Booting VxWorks using U-Boot
by sudhakar rajashekhara 06 Feb '04

06 Feb '04

Hi All, I am trying to bring up VxWorks using U-Boot on MPC8280. U-Boot has come up correctly on my system. I am following the following procedure after u-boot comes up. 1) download the vxworks elf file throgh TFTP. 2) I have defined bootargs to "motfcc(1,0)192.168.15.17:vxWorks e=192.168.15.224 h=192.168.15.17 g=0.0.0.0 u=test pw=test f=0x00" 3) booting the vxworks by issuing the command bootvx. When I give bootvx, U-Boot prints "Starting vxWorks at 0x00100000" and hangs at this point. Are the steps I am following are OK or Am I missing any other environment variable setting? regards, Sudhakar. __________________________________ Do you Yahoo!? Yahoo! Finance: Get your refund fast by filing online. http://taxes.yahoo.com/filing.html

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[U-Boot-Users] Boot Code Chip Select
by Raghu 06 Feb '04

06 Feb '04

Hello All, I have a MPC852T based board with a Boot Flash on CS0 and User Flash on CS2. Boot Flash mapped at Address 0xFE000000 and User Flash location at Address 0xFA000000. Can we load the u-boot code on to the User Flash on CS1, and boot from there ? If so what are the changes required ? Warm Regards, Raghu. __________________________________ Do you Yahoo!? Yahoo! Finance: Get your refund fast by filing online. http://taxes.yahoo.com/filing.html

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RE: [U-Boot-Users] Need mips arch Makefile w/ uImage target
by Jerry Walden 05 Feb '04

05 Feb '04

I got all the files from :pserver:anonymous@www.denx.de:/cvsroot/linux-mips, and I grepped through all the files looking for the string "uImage" and got a negative result. I also looked for a tools directory and found neither - what am I doing wrong? Thanks -----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Thursday, February 05, 2004 1:24 AM To: Jerry Walden Cc: u-boot-users(a)lists.sourceforge.net Subject: Re: [U-Boot-Users] Need mips arch Makefile w/ uImage target In message <603BA0CFF3788E46A0DB0918D9AA95100A09731B(a)sj580004wcom.int.lantronix.com > you wrote: > > I am working with the latest linux-mips kernel and was wondering if > someone out there has an existing makefile for the mips arch that has > a uImage target. We have a MIPS kernel on our CVS server. > -----Original Message----- > From: Brian S. Park [mailto:brian@corelis.com]=20 > Sent: Wednesday, February 04, 2004 5:22 PM > To: u-boot-users(a)lists.sourceforge.net > Subject: [U-Boot-Users] PPC405GP and PCI parked state Why are you quoting a completely unrelated message here??? Wolfgang Denk -- See us @ Embedded World, Nuremberg, Feb 17 - 19, Hall 12.0 Booth 440 Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de We, the unwilling, led by the unknowing, are doing the impossible for the ungrateful. We have done so much, for so long, with so little, we are now qualified to do anything with nothing.

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[U-Boot-Users] Pci multi bridge bug
by Philippe Simal 05 Feb '04

05 Feb '04

Hello, I'm running u-boot-1.0.0 on a IBM PPC440GP. I have a custom made board with 2 pci-to-pci bridge Intel 21154BE and several devices behind it. (* PCI bus layout) On boot-up, u-boot immediately recognizes the 2 bridges and 1 device on bus 0. It also has no problem for enumirating all the devices on bus 1, but u-boot can't find any device on bus 2. When I look at the bridge configuration using the 'pci 0 long' command, I see that the secondary bus address field of bridge 1 is set to 1. This should be 2. I also see that on bridge 1 but also on bridge 0 the subordinate bus address field always is filled with a 0. First of all I already implemented the type1 configuration cycle bug fix at (..\drivers\Pci_indirect.c). To work this kind of PCI configuration, I changed the following lines: 1. The problem with the secondary bus address is fixed by changing pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus + 1); to pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, hose->current_busno); in (file: '..\drivers\Pci_auto.c'; function: 'static void pciauto_prescan_setup_bridge()) 2. The problem with the subordinate bus address is solved by swapping the code lines from pciauto_postscan_setup_bridge(hose, dev, sub_bus); sub_bus = hose->current_busno; to sub_bus = hose->current_busno; pciauto_postscan_setup_bridge(hose, dev, sub_bus); (file: '..\drivers\Pci_auto.c'; function: int pciauto_config_device()) I'm not sure if this fix is fully failed proof but it works fine for this design. I hope my findings can be a contribution to the u-boot project. * PCI bus layout. BUS0 | | | /-------\ BUS1 |---| |-------- -> 7 PCI devices | \-------/ | Bridge 0 | | | /-------\ BUS2 |---| |-------- -> 7 PCI devices | \-------/ | Bridge 1 | | |--- 1 PCI device Greetings, Philippe

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RE: [U-Boot-Users] ELDK 2.2.0 (patched 2.1.0) doesn't install on Gentoo
by Ruhland, Paul 05 Feb '04

05 Feb '04

By 'patched' I assume you mean using the patch found here: ftp://ftp.denx.de/pub/tmp/ELDK-update-2.2.0.tar.bz2 If that is the case, you have not patched it correctly or forgot to patch it before creating your iso/cdrom. I have installed the 'patched' version on several Gentoo boxes and it works fine. The problem you describe was the behavior prior to patching. -----Original Message----- From: Jonas Mark-r50740 [mailto:Mark.Jonas@motorola.com] Sent: Monday, February 02, 2004 12:04 PM To: u-boot-users(a)lists.sourceforge.net Cc: wd(a)denx.de Subject: [U-Boot-Users] ELDK 2.2.0 (patched 2.1.0) doesn't install on Gentoo Hello, I'm trying to install the ELDK 2.2.0 (i.e. a patched 2.1.0) on a Gentoo 1.4 system. To do so I prepared a CD as described on www.denx.de. I already used the CD on two SuSE 8.2 systems with no problems. On the Gentoo system the installation starts just fine but suddenly stops without an error message. -- # ./install -d /opt/eldk-2.2.0 ppc_82xx Do you really want to install into /opt/eldk-2.2.0 directory[y/n]?: y Creating directories Done Installing cross RPMs Preparing... ################################################## [100%] # -- I attached a strace of what the installer is doing. Maybe somebody has an idea what is going wrong and how to work around. TIA Mark Jonas

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[U-Boot-Users] Need mips arch Makefile w/ uImage target
by Jerry Walden 05 Feb '04

05 Feb '04

Hello - I am working with the latest linux-mips kernel and was wondering if someone out there has an existing makefile for the mips arch that has a uImage target. Thanks! -----Original Message----- From: Brian S. Park [mailto:brian@corelis.com] Sent: Wednesday, February 04, 2004 5:22 PM To: u-boot-users(a)lists.sourceforge.net Subject: [U-Boot-Users] PPC405GP and PCI parked state Hi all, I have questions on how to leave internal PCI controller of PPC405GP in a parked state. Our custom board currently does not use the PCI and we want it to be in a parked state. According to the data sheet, ppc405gp needs pull up resisters if the PCI controller on the processor is not parked in proper state. Our custom board is based on IBM Walnut board and I undefined CONFIG_PCI. Would it leave it in a parked state? What is the proper configuration to do this? Also, would Linux override this setting if it is not properly configured as well? We like to avoid putting on large number of pull up resister if possible. Thank you. =============================================================== Brian S. Park brian(a)corelis.com (562) 926-6727 x132 --------------------------------------------------------------- Everything we do helps our customers get to market FASTER with HIGHER quality and LOWER cost =============================================================== ------------------------------------------------------- The SF.Net email is sponsored by EclipseCon 2004 Premiere Conference on Open Tools Development and Integration See the breadth of Eclipse activity. February 3-5 in Anaheim, CA. http://www.eclipsecon.org/osdn _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] PPC405GP and PCI parked state
by Brian S. Park 05 Feb '04

05 Feb '04

Hi all, I have questions on how to leave internal PCI controller of PPC405GP in a parked state. Our custom board currently does not use the PCI and we want it to be in a parked state. According to the data sheet, ppc405gp needs pull up resisters if the PCI controller on the processor is not parked in proper state. Our custom board is based on IBM Walnut board and I undefined CONFIG_PCI. Would it leave it in a parked state? What is the proper configuration to do this? Also, would Linux override this setting if it is not properly configured as well? We like to avoid putting on large number of pull up resister if possible. Thank you. =============================================================== Brian S. Park brian(a)corelis.com (562) 926-6727 x132 --------------------------------------------------------------- Everything we do helps our customers get to market FASTER with HIGHER quality and LOWER cost ===============================================================

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[U-Boot-Users] SystemACE support for u-boot via fat
by Stephen Williams 05 Feb '04

05 Feb '04

I've made a patch relative the current CVS (at sourceforge) that adds support for a Xilinx SystemACE chip directly attached to the PPC. (Well, conceivably any CPU type.) I've made the bundle of diffs and new files available for ftp download here: <ftp://ftp.icarus.com/pub/steve/u-boot-ace.tar.gz> Changelog here: * Add support for Xilinx SystemACE chip: New file common/cmd_ace.c New file include/systemace.h Hook systemace support into cmd_fat and the partition manager. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."

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RE: [U-Boot-Users] Can't get ide to work
by Jerry Walden 05 Feb '04

05 Feb '04

Okay - got it! My IDE interface (dbau1500) is at 0xf80000000 (pays to read the data sheet) - so I just mapped TLB 22 to phy 0xf80000000 and it works just dandy. Thanks! -----Original Message----- From: Thomas Lange [mailto:thomas@corelatus.se] Sent: Wednesday, February 04, 2004 10:51 AM To: Jerry Walden Cc: u-boot-users(a)lists.sourceforge.net Subject: Re: [U-Boot-Users] Can't get ide to work tlb 20 is mapped to phy 0xF00000000 ( not used ) tlb 21 is mapped to phy 0xF40000000 ( not used ) tlb 22 is mapped to phy 0xF80000000 TLB 22 was enough to make CF work on my dbau1000 board ( only tested in big endian mode ). /Thomas Jerry Walden wrote: > Thanks for the response. > > Okay - I found the TLB mapping for CFG_PCMCIA_MEM_ADDR (0x20000000), > however the IDE device is at AU1X_SOCK0_IO (0xF00000000). True - the > PCMCIA is at 0x20000000, however not the ide device. If I look at the > YAMON source - there is a mapping done for 0xF00000000. > > I don't see it in u-boot. Where am I going wrong? > > Thanks > > -----Original Message----- > From: Thomas Lange [mailto:thomas@corelatus.se] > Sent: Tuesday, February 03, 2004 1:29 PM > To: Jerry Walden > Cc: u-boot-users(a)lists.sourceforge.net > Subject: Re: [U-Boot-Users] Can't get ide to work > > > TLB is created in board/dbau1x00/dbau1x00.c > > Could be an endian problem, i.e. you read the wrong byte. > > /Thomas > > Jerry Walden wrote: > >>Our board is based on the Alchemy DBAu1500 >> >>We are using a compact flash card that as an IDE drive (tied into the >>IDE interface of the CPU just like the DBAu1500). >> >>During ide_init, the ATA_STATUS byte is read, and there is a wait loop > > >>which waits for the status to be ready. This loop always times out. >>I am trying to debug this. Tracing through ide_inb, and ide_outb, the > > >>address of the interface is fine CFG_PCMCIA_MEM_ADDR (0x20000000). I >>know that there has to be some TLB mapping between CFG_PCMCIA_MEM_ADDR > > >>(0x20000000) and AU1X_SOCK0_IO >>(F00000000) - I just cannot find where this is done. >> >>Any suggestions? >> >>Thanks > > > > > ------------------------------------------------------- > The SF.Net email is sponsored by EclipseCon 2004 > Premiere Conference on Open Tools Development and Integration See the > breadth of Eclipse activity. February 3-5 in Anaheim, CA. > http://www.eclipsecon.org/osdn > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users >

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[U-Boot-Users] environment not being used
by Shamile Khan 05 Feb '04

05 Feb '04

Hi, I am using U-boot on our FPGA based board. Currently, its not possible to execute instructions directly from flash on our board since our flash device is configured as an 8-bit device and it is connected to a 32-bit processor bus. To get around this, we have a small program which is stored in FPGA bitstream and runs in FPGA on-chip memory (called BRAM). This program copies u-boot binary image from flash to sdram and jumps to it. This allows U-boot to run. However the problem is that the environment variables saved in flash are not being used even though U-boot has been configured with the CFG_ENV_IS_IN_FLASH option turned on. CFG_FLASH_BASE has been set to the flash base address of u-boot and when I use saveenv the environment is saved at the proper offset CFG_ENV_OFFSET. The only thing thats a bit different for my U-boot configuration is that CFG_MONITOR_BASE is set to the sdram base address where U-boot starts executing from instead of being set to CFG_FLASH_BASE. Any ideas why the environment variables in flash do not get used? Thanks, Shamile

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