November 2004 - U-Boot

[U-Boot-Users] PATCH: Removing all these "extern void reset_cpu()"
by Steven Scholz 03 Apr '05

03 Apr '05

Hi there, please consider the patch attached. CHANGELOG: * Patch by Steven Scholz, 25 Oct 2004: - Replace all "extern void reset_cpu()" with one occurence of "void reset_cpu (ulong addr)" in include/common.h -- Steven Scholz Index: cpu/arm720t/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm720t/cpu.c,v retrieving revision 1.6 diff -p -u -r1.6 cpu.c --- cpu/arm720t/cpu.c 1 Aug 2004 22:48:19 -0000 1.6 +++ cpu/arm720t/cpu.c 25 Oct 2004 14:03:13 -0000 @@ -84,8 +84,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm720t/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm720t/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/arm720t/interrupts.c 11 Jul 2004 22:19:27 -0000 1.6 +++ cpu/arm720t/interrupts.c 25 Oct 2004 14:03:13 -0000 @@ -31,8 +31,6 @@ #include <asm/proc-armv/ptrace.h> #include <asm/hardware.h> -extern void reset_cpu(ulong addr); - #ifndef CONFIG_NETARM /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff Index: cpu/arm920t/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/arm920t/cpu.c 8 Feb 2004 19:38:43 -0000 1.3 +++ cpu/arm920t/cpu.c 25 Oct 2004 14:03:13 -0000 @@ -124,8 +124,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm920t/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/arm920t/interrupts.c 1 Aug 2004 22:48:19 -0000 1.6 +++ cpu/arm920t/interrupts.c 25 Oct 2004 14:03:13 -0000 @@ -34,8 +34,6 @@ #include <arm920t.h> #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ interrupts */ void enable_interrupts (void) Index: cpu/arm920t/s3c24x0/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/s3c24x0/interrupts.c,v retrieving revision 1.1 diff -p -u -r1.1 interrupts.c --- cpu/arm920t/s3c24x0/interrupts.c 9 Oct 2004 22:21:30 -0000 1.1 +++ cpu/arm920t/s3c24x0/interrupts.c 25 Oct 2004 14:03:13 -0000 @@ -39,7 +39,6 @@ #include <s3c2410.h> #endif -extern void reset_cpu(ulong addr); int timer_load_val = 0; /* macro to read the 16 bit timer */ Index: cpu/arm925t/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm925t/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/arm925t/cpu.c 8 Feb 2004 19:38:43 -0000 1.3 +++ cpu/arm925t/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -125,8 +125,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm925t/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm925t/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/arm925t/interrupts.c 25 Apr 2004 14:37:30 -0000 1.6 +++ cpu/arm925t/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -38,7 +38,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ Index: cpu/arm926ejs/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm926ejs/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/arm926ejs/cpu.c 8 Feb 2004 19:38:43 -0000 1.3 +++ cpu/arm926ejs/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -125,8 +125,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm926ejs/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm926ejs/interrupts.c,v retrieving revision 1.7 diff -p -u -r1.7 interrupts.c --- cpu/arm926ejs/interrupts.c 23 Mar 2004 21:43:08 -0000 1.7 +++ cpu/arm926ejs/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -40,7 +40,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ Index: cpu/at91rm9200/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/at91rm9200/cpu.c,v retrieving revision 1.9 diff -p -u -r1.9 cpu.c --- cpu/at91rm9200/cpu.c 10 Oct 2004 20:23:59 -0000 1.9 +++ cpu/at91rm9200/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -115,8 +115,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag { #ifdef CFG_SOFT_RESET - extern void reset_cpu(ulong addr); - disable_interrupts(); reset_cpu(0); #else Index: cpu/at91rm9200/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/at91rm9200/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/at91rm9200/interrupts.c 11 Oct 2004 22:25:50 -0000 1.6 +++ cpu/at91rm9200/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -35,8 +35,6 @@ #include <asm/arch/hardware.h> #include <asm/proc/ptrace.h> -extern void reset_cpu(ulong addr); - /* the number of clocks per CFG_HZ */ #define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ) Index: cpu/i386/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/i386/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/i386/cpu.c 27 Jun 2003 21:32:33 -0000 1.3 +++ cpu/i386/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -50,8 +50,6 @@ int cpu_init(void) int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu(ulong addr); - printf ("resetting ...\n"); udelay(50000); /* wait 50 ms */ disable_interrupts(); Index: cpu/ixp/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/ixp/cpu.c,v retrieving revision 1.2 diff -p -u -r1.2 cpu.c --- cpu/ixp/cpu.c 8 Feb 2004 19:38:44 -0000 1.2 +++ cpu/ixp/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -76,8 +76,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - printf ("resetting ...\n"); udelay (50000); /* wait 50 ms */ Index: cpu/ixp/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/ixp/interrupts.c,v retrieving revision 1.2 diff -p -u -r1.2 interrupts.c --- cpu/ixp/interrupts.c 15 Oct 2003 23:53:51 -0000 1.2 +++ cpu/ixp/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -30,8 +30,6 @@ #include <common.h> #include <asm/arch/ixp425.h> -extern void reset_cpu (ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ void enable_interrupts (void) Index: cpu/lh7a40x/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/lh7a40x/cpu.c,v retrieving revision 1.1 diff -p -u -r1.1 cpu.c --- cpu/lh7a40x/cpu.c 9 Jun 2004 13:37:53 -0000 1.1 +++ cpu/lh7a40x/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -124,8 +124,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/lh7a40x/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/lh7a40x/interrupts.c,v retrieving revision 1.2 diff -p -u -r1.2 interrupts.c --- cpu/lh7a40x/interrupts.c 10 Jun 2004 21:55:34 -0000 1.2 +++ cpu/lh7a40x/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -35,7 +35,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); static ulong timer_load_val = 0; /* macro to read the 16 bit timer */ Index: cpu/pxa/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/pxa/cpu.c,v retrieving revision 1.5 diff -p -u -r1.5 cpu.c --- cpu/pxa/cpu.c 8 Feb 2004 19:38:44 -0000 1.5 +++ cpu/pxa/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -74,8 +74,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - printf ("resetting ...\n"); udelay (50000); /* wait 50 ms */ Index: cpu/pxa/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/pxa/interrupts.c,v retrieving revision 1.4 diff -p -u -r1.4 interrupts.c --- cpu/pxa/interrupts.c 9 Jun 2004 13:37:53 -0000 1.4 +++ cpu/pxa/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -29,8 +29,6 @@ #include <common.h> #include <asm/arch/pxa-regs.h> -extern void reset_cpu (ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ void enable_interrupts (void) Index: cpu/s3c44b0/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/s3c44b0/cpu.c,v retrieving revision 1.2 diff -p -u -r1.2 cpu.c --- cpu/s3c44b0/cpu.c 17 Oct 2004 21:12:11 -0000 1.2 +++ cpu/s3c44b0/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -86,8 +86,6 @@ void reset_cpu (ulong addr) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); Index: cpu/s3c44b0/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/s3c44b0/interrupts.c,v retrieving revision 1.1 diff -p -u -r1.1 interrupts.c --- cpu/s3c44b0/interrupts.c 24 Feb 2004 00:16:44 -0000 1.1 +++ cpu/s3c44b0/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -29,8 +29,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); - /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff Index: cpu/sa1100/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/sa1100/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/sa1100/cpu.c 8 Feb 2004 19:38:44 -0000 1.3 +++ cpu/sa1100/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -73,8 +73,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - printf ("resetting ...\n"); udelay (50000); /* wait 50 ms */ Index: cpu/sa1100/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/sa1100/interrupts.c,v retrieving revision 1.3 diff -p -u -r1.3 interrupts.c --- cpu/sa1100/interrupts.c 14 Mar 2004 15:20:56 -0000 1.3 +++ cpu/sa1100/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -31,8 +31,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu (ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ void enable_interrupts (void) Index: include/common.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/common.h,v retrieving revision 1.46 diff -p -u -r1.46 common.h --- include/common.h 10 Oct 2004 18:41:14 -0000 1.46 +++ include/common.h 25 Oct 2004 14:03:15 -0000 @@ -378,6 +378,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); +void reset_cpu (ulong addr); /* $(CPU)/serial.c */ int serial_init (void);

2 2

[U-Boot-Users] Resending PATCH: Support for Motorola HiddenDragon board
by Santoso, Yusdi 03 Apr '05

03 Apr '05

Arrgh...ignore my first patch...I send a wrong patch version, the first one was agains the 2004-08-18 build. This is the correct one based on the daily snapshot. So sorry.... Thanks, Yusdi

2 1

[U-Boot-Users] common/serial.c patch
by Curtis, Allen 03 Apr '05

03 Apr '05

This is a patch to support multiple serial ports. Existing code will compile and run without modification. I hope you find this useful. THX

2 1

[U-Boot-Users] PATCH: Nios-II EPCS support
by Scott McNutt 31 Mar '05

31 Mar '05

Patch: Add support for Nios-II EPCS Controller core. Regards, --Scott diff -Naurb u-boot-2004-10-21/cpu/nios2/Makefile u-boot-work/cpu/nios2/Makefile --- u-boot-2004-10-21/cpu/nios2/Makefile 2004-10-21 19:43:18.000000000 -0400 +++ u-boot-work/cpu/nios2/Makefile 2004-10-21 18:14:03.000000000 -0400 @@ -27,7 +27,7 @@ START = start.o AOBJS = exceptions.o -OBJS = cpu.o interrupts.o serial.o sysid.o traps.o +OBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o all: .depend $(START) $(LIB) diff -Naurb u-boot-2004-10-21/cpu/nios2/epcs.c u-boot-work/cpu/nios2/epcs.c --- u-boot-2004-10-21/cpu/nios2/epcs.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-work/cpu/nios2/epcs.c 2004-10-21 19:30:00.000000000 -0400 @@ -0,0 +1,711 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CFG_NIOS_EPCSBASE) +#include <command.h> +#include <nios2.h> +#include <nios2-io.h> +#include <nios2-epcs.h> + + +/*-----------------------------------------------------------------------*/ +#define SHORT_HELP\ + "epcs - read/write Cyclone EPCS configuration device.\n" + +#define LONG_HELP\ + "\n"\ + "epcs erase start [end]\n"\ + " - erase sector start or sectors start through end.\n"\ + "epcs info\n"\ + " - display EPCS device information.\n"\ + "epcs protect on | off\n"\ + " - turn device protection on or off.\n"\ + "epcs read addr offset count\n"\ + " - read count bytes from offset to addr.\n"\ + "epcs write addr offset count\n"\ + " - write count bytes to offset from addr.\n"\ + "epcs verify addr offset count\n"\ + " - verify count bytes at offset from addr.\n" + + +/*-----------------------------------------------------------------------*/ +/* Operation codes for serial configuration devices + */ +#define EPCS_WRITE_ENA 0x06 /* Write enable */ +#define EPCS_WRITE_DIS 0x04 /* Write disable */ +#define EPCS_READ_STAT 0x05 /* Read status */ +#define EPCS_READ_BYTES 0x03 /* Read bytes */ +#define EPCS_READ_ID 0xab /* Read silicon id */ +#define EPCS_WRITE_STAT 0x01 /* Write status */ +#define EPCS_WRITE_BYTES 0x02 /* Write bytes */ +#define EPCS_ERASE_BULK 0xc7 /* Erase entire device */ +#define EPCS_ERASE_SECT 0xd8 /* Erase sector */ + +/* Device status register bits + */ +#define EPCS_STATUS_WIP (1<<0) /* Write in progress */ +#define EPCS_STATUS_WEL (1<<1) /* Write enable latch */ + +/* Misc + */ +#define EPCS_TIMEOUT 100 /* 100 msec timeout */ + +static nios_spi_t *epcs = + (nios_spi_t *)CACHE_BYPASS(CFG_NIOS_EPCSBASE); + +/*********************************************************************** + * Device access + ***********************************************************************/ +static int epcs_cs (int assert) +{ + ulong start; + + if (assert) { + epcs->control |= NIOS_SPI_SSO; + } else { + /* Let all bits shift out */ + start = get_timer (0); + while ((epcs->status & NIOS_SPI_TMT) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + epcs->control &= ~NIOS_SPI_SSO; + } + return (0); +} + +static int epcs_tx (unsigned char c) +{ + ulong start; + + start = get_timer (0); + while ((epcs->status & NIOS_SPI_TRDY) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + epcs->txdata = c; + return (0); +} + +static int epcs_rx (void) +{ + ulong start; + + start = get_timer (0); + while ((epcs->status & NIOS_SPI_RRDY) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + return (epcs->rxdata); +} + +static unsigned char bitrev[] = { + 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, + 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f +}; + +static unsigned char epcs_bitrev (unsigned char c) +{ + unsigned char val; + + val = bitrev[c>>4]; + val |= bitrev[c & 0x0f]<<4; + return (val); +} + +static void epcs_rcv (unsigned char *dst, int len) +{ + while (len--) { + epcs_tx (0); + *dst++ = epcs_rx (); + } +} + +static void epcs_rrcv (unsigned char *dst, int len) +{ + while (len--) { + epcs_tx (0); + *dst++ = epcs_bitrev (epcs_rx ()); + } +} + +static void epcs_snd (unsigned char *src, int len) +{ + while (len--) { + epcs_tx (*src++); + epcs_rx (); + } +} + +static void epcs_rsnd (unsigned char *src, int len) +{ + while (len--) { + epcs_tx (epcs_bitrev (*src++)); + epcs_rx (); + } +} + +static void epcs_wr_enable (void) +{ + epcs_cs (1); + epcs_tx (EPCS_WRITE_ENA); + epcs_rx (); + epcs_cs (0); +} + +static unsigned char epcs_status_rd (void) +{ + unsigned char status; + + epcs_cs (1); + epcs_tx (EPCS_READ_STAT); + epcs_rx (); + epcs_tx (0); + status = epcs_rx (); + epcs_cs (0); + return (status); +} + +static void epcs_status_wr (unsigned char status) +{ + epcs_wr_enable (); + epcs_cs (1); + epcs_tx (EPCS_WRITE_STAT); + epcs_rx (); + epcs_tx (status); + epcs_rx (); + epcs_cs (0); + return; +} + +/*********************************************************************** + * Device information + ***********************************************************************/ + +static struct epcs_devinfo_t devinfo[] = { + { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, + { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, + { 0, 0, 0, 0, 0, 0 } +}; + +epcs_devinfo_t *epcs_dev_find (void) +{ + unsigned char buf[4]; + unsigned char id; + int i; + struct epcs_devinfo_t *dev = NULL; + + /* Read silicon id requires 3 "dummy bytes" before it's put + * on the wire. + */ + buf[0] = EPCS_READ_ID; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rcv (buf,1); + if (epcs_cs (0) == -1) + return (NULL); + id = buf[0]; + + /* Find the info struct */ + i = 0; + while (devinfo[i].name) { + if (id == devinfo[i].id) { + dev = &devinfo[i]; + break; + } + i++; + } + + return (dev); +} + +/*********************************************************************** + * Misc Utilities + ***********************************************************************/ +int epcs_cfgsz (void) +{ + int sz = 0; + unsigned char buf[128]; + unsigned char *p; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + /* Read in the first 128 bytes of the device */ + buf[0] = EPCS_READ_BYTES; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rrcv (buf, sizeof(buf)); + epcs_cs (0); + + /* Search for the starting 0x6a which is followed by the + * 4-byte 'register' and 4-byte bit-count. + */ + p = buf; + while (p < buf + sizeof(buf)-8) { + if ( *p == 0x6a ) { + /* Point to bit count and extract */ + p += 5; + sz = *p++; + sz |= *p++ << 8; + sz |= *p++ << 16; + sz |= *p++ << 24; + /* Convert to byte count */ + sz += 7; + sz >>= 3; + } else if (*p == 0xff) { + /* 0xff is ok ... just skip */ + p++; + continue; + } else { + /* Not 0xff or 0x6a ... something's not + * right ... report 'unknown' (sz=0). + */ + break; + } + } + return (sz); +} + +int epcs_erase (unsigned start, unsigned end) +{ + unsigned off, sectsz; + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev || (start>end)) + return (-1); + + /* Erase the requested sectors. An address is required + * that lies within the requested sector -- we'll just + * use the first address in the sector. + */ + printf ("epcs erasing sector %d ", start); + if (start != end) + printf ("to %d ", end); + sectsz = (1 << dev->sz_sect); + while (start <= end) { + off = start * sectsz; + start++; + + buf[0] = EPCS_ERASE_SECT; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_wr_enable (); + epcs_cs (1); + epcs_snd (buf,4); + epcs_cs (0); + + printf ("."); /* Some user feedback */ + + /* Wait for erase to complete */ + while (epcs_status_rd() & EPCS_STATUS_WIP) + ; + } + printf (" done.\n"); + return (0); +} + +int epcs_read (ulong addr, ulong off, ulong cnt) +{ + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + buf[0] = EPCS_READ_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rrcv ((unsigned char *)addr, cnt); + epcs_cs (0); + + return (0); +} + +int epcs_write (ulong addr, ulong off, ulong cnt) +{ + ulong wrcnt; + unsigned pgsz; + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + pgsz = (1<<dev->sz_page); + while (cnt) { + if (off % pgsz) + wrcnt = pgsz - (off % pgsz); + else + wrcnt = pgsz; + wrcnt = (wrcnt > cnt) ? cnt : wrcnt; + + buf[0] = EPCS_WRITE_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_wr_enable (); + epcs_cs (1); + epcs_snd (buf,4); + epcs_rsnd ((unsigned char *)addr, wrcnt); + epcs_cs (0); + + /* Wait for write to complete */ + while (epcs_status_rd() & EPCS_STATUS_WIP) + ; + + cnt -= wrcnt; + off += wrcnt; + addr += wrcnt; + } + + return (0); +} + +int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err) +{ + ulong rdcnt; + unsigned char buf[256]; + unsigned char *start,*end; + int i; + + start = end = (unsigned char *)addr; + while (cnt) { + rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; + epcs_read ((ulong)buf, off, rdcnt); + for (i=0; i<rdcnt; i++) { + if (*end != buf[i]) { + *err = end - start; + return(-1); + } + end++; + } + cnt -= rdcnt; + off += rdcnt; + } + return (0); +} + +static int epcs_sect_erased (int sect, unsigned *offset, + struct epcs_devinfo_t *dev) +{ + unsigned char buf[128]; + unsigned off, end; + unsigned sectsz; + int i; + + sectsz = (1 << dev->sz_sect); + off = sectsz * sect; + end = off + sectsz; + + while (off < end) { + epcs_read ((ulong)buf, off, sizeof(buf)); + for (i=0; i < sizeof(buf); i++) { + if (buf[i] != 0xff) { + *offset = off + i; + return (0); + } + } + off += sizeof(buf); + } + return (1); +} + + +/*********************************************************************** + * Commands + ***********************************************************************/ +static +void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + int i; + unsigned char stat; + unsigned tmp; + int erased; + + /* Basic device info */ + printf ("%s: %d kbytes (%d sectors x %d kbytes," + " %d bytes/page)\n", + dev->name, 1 << (dev->size-10), + dev->num_sects, 1 << (dev->sz_sect-10), + 1 << dev->sz_page ); + + /* Status -- for now protection is all-or-nothing */ + stat = epcs_status_rd(); + printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", + stat, + (stat & EPCS_STATUS_WIP) ? 1 : 0, + (stat & EPCS_STATUS_WEL) ? 1 : 0, + (stat & dev->prot_mask) ? "on" : "off" ); + + /* Configuration */ + tmp = epcs_cfgsz (); + if (tmp) { + printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); + } else { + printf ("config: unknown\n" ); + } + + /* Sector info */ + for (i=0; i<dev->num_sects; i++) { + erased = epcs_sect_erased (i, &tmp, dev); + printf (" %d: %06x ", + i, i*(1<<dev->sz_sect) ); + if (erased) + printf ("erased\n"); + else + printf ("data @ 0x%06x\n", tmp); + } + + return; +} + +static +void do_epcs_erase (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned start,end; + + if ((argc < 3) || (argc > 4)) { + printf ("USAGE: epcs erase sect [end]\n"); + return; + } + if ((epcs_status_rd() & dev->prot_mask) != 0) { + printf ( "epcs: device protected.\n"); + return; + } + + start = simple_strtoul (argv[2], NULL, 10); + if (argc > 3) + end = simple_strtoul (argv[3], NULL, 10); + else + end = start; + if ((start >= dev->num_sects) || (start > end)) { + printf ("epcs: invalid sector range: [%d:%d]\n", + start, end ); + return; + } + + epcs_erase (start, end); + + return; +} + +static +void do_epcs_protect (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned char stat; + + /* For now protection is all-or-nothing to keep things + * simple. The protection bits don't map in a linear + * fashion ... and we would rather protect the bottom + * of the device since it contains the config data and + * leave the top unprotected for app use. But unfortunately + * protection works from top-to-bottom so it does + * really help very much from a software app point-of-view. + */ + if (argc < 3) { + printf ("USAGE: epcs protect on | off\n"); + return; + } + if (!dev) + return; + + /* Protection on/off is just a matter of setting/clearing + * all protection bits in the status register. + */ + stat = epcs_status_rd (); + if (strcmp ("on", argv[2]) == 0) { + stat |= dev->prot_mask; + } else if (strcmp ("off", argv[2]) == 0 ) { + stat &= ~dev->prot_mask; + } else { + printf ("epcs: unknown protection: %s\n", argv[2]); + return; + } + epcs_status_wr (stat); + return; +} + +static +void do_epcs_read (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + + if (argc < 5) { + printf ("USAGE: epcs read addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: read %08lx <- %06lx (0x%lx bytes)\n", + addr, off, cnt); + epcs_read (addr, off, cnt); + + return; +} + +static +void do_epcs_write (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: epcs write addr offset count\n"); + return; + } + if ((epcs_status_rd() & dev->prot_mask) != 0) { + printf ( "epcs: device protected.\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: write %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + epcs_write (addr, off, cnt); + if (epcs_verify (addr, off, cnt, &err) != 0) + printf ("epcs: write error at offset %06lx\n", err); + + return; +} + +static +void do_epcs_verify (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: epcs verify addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: verify %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + if (epcs_verify (addr, off, cnt, &err) != 0) + printf ("epcs: verify error at offset %06lx\n", err); + + return; +} + +/*-----------------------------------------------------------------------*/ +int do_epcs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int len; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) { + printf ("epcs: device not found.\n"); + return (-1); + } + + if (argc < 2) { + do_epcs_info (dev, argc, argv); + return (0); + } + + len = strlen (argv[1]); + if (strncmp ("info", argv[1], len) == 0) { + do_epcs_info (dev, argc, argv); + } else if (strncmp ("erase", argv[1], len) == 0) { + do_epcs_erase (dev, argc, argv); + } else if (strncmp ("protect", argv[1], len) == 0) { + do_epcs_protect (dev, argc, argv); + } else if (strncmp ("read", argv[1], len) == 0) { + do_epcs_read (dev, argc, argv); + } else if (strncmp ("write", argv[1], len) == 0) { + do_epcs_write (dev, argc, argv); + } else if (strncmp ("verify", argv[1], len) == 0) { + do_epcs_verify (dev, argc, argv); + } else { + printf ("epcs: unknown operation: %s\n", argv[1]); + } + + return (0); +} + +/*-----------------------------------------------------------------------*/ + + +U_BOOT_CMD( epcs, 5, 0, do_epcs, SHORT_HELP, LONG_HELP ); + +#endif /* CONFIG_NIOS_EPCS */ diff -Naurb u-boot-2004-10-21/include/configs/PK1C20.h u-boot-work/include/configs/PK1C20.h --- u-boot-2004-10-21/include/configs/PK1C20.h 2004-10-10 17:27:34.000000000 -0400 +++ u-boot-work/include/configs/PK1C20.h 2004-10-21 19:53:22.000000000 -0400 @@ -52,7 +52,7 @@ #define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ #define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ #define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */ -#define CFG_SRAM_SIZE 0x00200000 /* 2 MByte */ +#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ /*------------------------------------------------------------------------ * MEMORY ORGANIZATION @@ -107,6 +107,14 @@ #define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ /*------------------------------------------------------------------------ + * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for + * epcs device access is enabled. The base address is the epcs + * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. + * The register base is currently at offset 0x400 from the memory base. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */ + +/*------------------------------------------------------------------------ * DEBUG *----------------------------------------------------------------------*/ #undef CONFIG_ROM_STUBS /* Stubs not in ROM */ @@ -173,6 +181,36 @@ #include <cmd_confdefs.h> /*------------------------------------------------------------------------ + * COMPACT FLASH + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CONFIG_IDE_PREINIT /* Implement id_preinit */ +#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x00900800 /* ATA base addr */ +#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ +#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ +#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */ +#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ +#define CFG_ATA_STRIDE 4 /* Width betwix addrs */ +#define CONFIG_DOS_PARTITION + +/* Board-specific cf regs */ +#define CFG_CF_PRESENT 0x00900880 /* CF Present PIO base */ +#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/ +#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ + +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ + +/*------------------------------------------------------------------------ + * JFFS2 + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CFG_JFFS_CUSTOM_PART /* board defined part */ +#endif + +/*------------------------------------------------------------------------ * MISC *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* Provide extended help*/ @@ -185,4 +223,7 @@ #define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ #define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + #endif /* __CONFIG_H */ diff -Naurb u-boot-2004-10-21/include/nios2-epcs.h u-boot-work/include/nios2-epcs.h --- u-boot-2004-10-21/include/nios2-epcs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-work/include/nios2-epcs.h 2004-10-21 19:13:53.000000000 -0400 @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera Nios-II EPCS Controller Core interfaces + ************************************************************************/ + +#ifndef __NIOS2_EPCS_H__ +#define __NIOS2_EPCS_H__ + +typedef struct epcs_devinfo_t { + const char *name; /* Device name */ + unsigned char id; /* Device silicon id */ + unsigned char size; /* Total size log2(bytes)*/ + unsigned char num_sects; /* Number of sectors */ + unsigned char sz_sect; /* Sector size log2(bytes) */ + unsigned char sz_page; /* Page size log2(bytes) */ + unsigned char prot_mask; /* Protection mask */ +}epcs_devinfo_t; + +/* Returns the devinfo struct if EPCS device is found; + * NULL otherwise. + */ +extern epcs_devinfo_t *epcs_dev_find (void); + +/* Returns the number of bytes used by config data. + * Negative on error. + */ +extern int epcs_cfgsz (void); + +/* Erase sectors 'start' to 'end' - return zero on success + */ +extern int epcs_erase (unsigned start, unsigned end); + +/* Read 'cnt' bytes from device offset 'off' into buf at 'addr' + * Zero return on success + */ +extern int epcs_read (ulong addr, ulong off, ulong cnt); + +/* Write 'cnt' bytes to device offset 'off' from buf at 'addr'. + * Zero return on success + */ +extern int epcs_write (ulong addr, ulong off, ulong cnt); + +/* Verify 'cnt' bytes at device offset 'off' comparing with buf + * at 'addr'. On failure, write first invalid offset to *err. + * Zero return on success + */ +extern int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err); + +#endif /* __NIOS2_EPCS_H__ */ diff -Naurb u-boot-2004-10-21/include/nios2-io.h u-boot-work/include/nios2-io.h --- u-boot-2004-10-21/include/nios2-io.h 2004-10-10 17:27:34.000000000 -0400 +++ u-boot-work/include/nios2-io.h 2004-10-21 17:33:05.000000000 -0400 @@ -137,37 +137,6 @@ #define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ /*------------------------------------------------------------------------ - * ASMI - *----------------------------------------------------------------------*/ -typedef volatile struct nios_asmi_t { - unsigned rxdata; /* Rx data reg */ - unsigned txdata; /* Tx data reg */ - unsigned status; /* Status reg */ - unsigned control; /* Control reg */ - unsigned reserved; - unsigned slavesel; /* Slave select */ - unsigned endofpacket; /* End-of-packet reg */ -}nios_asmi_t; - -/* status register */ -#define NIOS_ASMI_ROE (1 << 3) /* rx overrun */ -#define NIOS_ASMI_TOE (1 << 4) /* tx overrun */ -#define NIOS_ASMI_TMT (1 << 5) /* tx empty */ -#define NIOS_ASMI_TRDY (1 << 6) /* tx ready */ -#define NIOS_ASMI_RRDY (1 << 7) /* rx ready */ -#define NIOS_ASMI_E (1 << 8) /* exception */ -#define NIOS_ASMI_EOP (1 << 9) /* eop detected */ - -/* control register */ -#define NIOS_ASMI_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_ASMI_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_ASMI_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_ASMI_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_ASMI_IE (1 << 8) /* exception int ena */ -#define NIOS_ASMI_IEOP (1 << 9) /* rx eop int ena */ -#define NIOS_ASMI_SSO (1 << 10) /* slave select enable */ - -/*------------------------------------------------------------------------ * JTAG UART *----------------------------------------------------------------------*/ typedef volatile struct nios_jtag_t {

2 1

[U-Boot-Users] Question on do_bootm in cmd_bootm.c
by Nick Barendt 31 Mar '05

31 Mar '05

Can someone, maybe Wolfgang, comment on the maximum 4MB uncompressed size of gunzip (and, possibly, bzip2) images? I've been working on a Coldfire 5272 system for quite some time with u-boot and uClinux. Both have been remarkably stable. We use the uClinux default build wherein the root filesystem (romfs) is appended to the end of the kernel image, starting where the bss would normally be. The kernel startup code relocates the romfs image to just beyond the bss, then, and everything runs smoothly. I know that many folks in the PPC world use separate kernel and root filesystem images, for many good reasons, but many (most?) of the uClinux platforms use this concatenated kernel+romfs image. Recently, we've been adding more content to the root filesystem. As our root filesystem grew larger (say about 3MB), however, we started seeing boot problems where the kernel would boot fine but the root filesystem was clearly corrupt. I've spent the better part of two days trying to track down where things go wrong, from the kernel to u-boot. Of course, I used a hardware debugger, looked at u-boot's memory assignments, image load addresses, entry points, malloc areas, etc. I just located the source of my trouble, a hard-coded 4MB maximum uncompressed size in do_bootm: int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong iflag; ulong addr; ulong data, len, checksum; ulong *len_ptr; uint unc_len = 0x400000; ^^^^^^^^^ int i, verify; SNIP case IH_COMP_GZIP: printf (" Uncompressing %s ... ", name); if (gunzip ((void *)ntohl(hdr->ih_load), unc_len, ^^^^^^^^ (uchar *)data, (int *)&len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); SHOW_BOOT_PROGRESS (-6); do_reset (cmdtp, flag, argc, argv); } break; SNIP Increasing unc_len to larger values (like 6MB) seems to solve my problem. With an uncompressed image larger than 4MB, gunzip doesn't seem to generate any errors (granted, I haven't stepped through gunzip and zlib), but merrily runs along, although the data beyond the 4MB boundary seems to be missing or corrupt. It looks like there's a truncation (about line 1875 in zlib.c) to z.avail_out in zlib that prevents data from being copied beyond unc_len - maybe that should be an error instead of silently truncating data? Just a thought. I'll into submitting a patch for that. I was wondering if there was some reason for the 0x400000 magic number for unc_len. Is that just a magic number? Is that larger than anyone uses for images? I guess I'm a little surprised that this hasn't bitten anyone else so far (nothing I could see on the mailing list archive, at least). Our 1MB kernel and 3MB romfs root filesystem might be exceptionally large, I don't know. Would there be any issues with making unc_len a CFG_ macro, if I submitted a patch? Nick Barendt

4 8

[U-Boot-Users] PATCH: Nios-II cleanups
by Scott McNutt 31 Mar '05

31 Mar '05

Patch has some minor Nios-II cleanups: -Add sysid command (Nios-II only). -Locate default exception trampoline at proper offset. -Implement I/O routines (readb, writeb, etc). -Implement do_bootm_linux Regards, --Scott diff -Naurb u-boot-2004-10-20/cpu/nios2/Makefile u-boot-work/cpu/nios2/Makefile --- u-boot-2004-10-20/cpu/nios2/Makefile 2004-10-10 17:27:33.000000000 -0400 +++ u-boot-work/cpu/nios2/Makefile 2004-10-11 21:38:41.000000000 -0400 @@ -27,7 +27,7 @@ START = start.o AOBJS = exceptions.o -OBJS = cpu.o interrupts.o serial.o traps.o +OBJS = cpu.o interrupts.o serial.o sysid.o traps.o all: .depend $(START) $(LIB) diff -Naurb u-boot-2004-10-20/cpu/nios2/cpu.c u-boot-work/cpu/nios2/cpu.c --- u-boot-2004-10-20/cpu/nios2/cpu.c 2004-10-10 17:27:33.000000000 -0400 +++ u-boot-work/cpu/nios2/cpu.c 2004-10-11 21:40:55.000000000 -0400 @@ -26,19 +26,7 @@ #include <nios2-io.h> #if defined (CFG_NIOS_SYSID_BASE) -#include <linux/time.h> -static void check_sysid (void) -{ - struct nios_sysid_t *sysid = - (struct nios_sysid_t *)CACHE_BYPASS(CFG_NIOS_SYSID_BASE); - struct tm t; - char asc[32]; - - localtime_r ((time_t *)&sysid->timestamp, &t); - asctime_r (&t, asc); - printf ("SYSID : %08x, %s", sysid->id, asc); - -} +extern void display_sysid (void); #endif /* CFG_NIOS_SYSID_BASE */ int checkcpu (void) @@ -47,7 +35,7 @@ #if !defined(CFG_NIOS_SYSID_BASE) printf ("SYSID : <unknown>\n"); #else - check_sysid (); + display_sysid (); #endif return (0); } diff -Naurb u-boot-2004-10-20/cpu/nios2/start.S u-boot-work/cpu/nios2/start.S --- u-boot-2004-10-20/cpu/nios2/start.S 2004-10-10 17:27:33.000000000 -0400 +++ u-boot-work/cpu/nios2/start.S 2004-10-20 10:50:47.000000000 -0400 @@ -39,14 +39,24 @@ * just be invalidating the cache a second time. If cache * is not implemented initi behaves as nop. */ - movhi r4, %hi(CFG_ICACHELINE_SIZE) - ori r4, r4, %lo(CFG_ICACHELINE_SIZE) + ori r4, r0, %lo(CFG_ICACHELINE_SIZE) movhi r5, %hi(CFG_ICACHE_SIZE) ori r5, r5, %lo(CFG_ICACHE_SIZE) mov r6, r0 0: initi r6 add r6, r6, r4 bltu r6, r5, 0b + br _except_end /* Skip the tramp */ + + /* EXCEPTION TRAMPOLINE -- the following gets copied + * to the exception address (below), but is otherwise at the + * default exception vector offset (0x0020). + */ +_except_start: + movhi et, %hi(_exception) + ori et, et, %lo(_exception) + jmp et +_except_end: /* INTERRUPTS -- for now, all interrupts masked and globally * disabled. @@ -117,7 +127,9 @@ _reloc: /* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the - * exception address. + * exception address. Define CONFIG_ROM_STUBS to prevent + * the copy (e.g. exception in flash or in other + * softare/firmware component). */ #if !defined(CONFIG_ROM_STUBS) movhi r4, %hi(_except_start) @@ -126,12 +138,14 @@ ori r5, r5, %lo(_except_end) movhi r6, %hi(CFG_EXCEPTION_ADDR) ori r6, r6, %lo(CFG_EXCEPTION_ADDR) + beq r4, r6, 7f /* Skip if at proper addr */ 6: ldwio r7, 0(r4) stwio r7, 0(r6) addi r4, r4, 4 addi r6, r6, 4 bne r4, r5, 6b +7: #endif /* STACK INIT -- zero top two words for call back chain. @@ -155,15 +169,6 @@ */ br _start - /* EXCEPTION TRAMPOLINE -- the following gets copied - * to the exception address. - */ -_except_start: - movhi et, %hi(_exception) - ori et, et, %lo(_exception) - jmp et -_except_end: - /* * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in diff -Naurb u-boot-2004-10-20/cpu/nios2/sysid.c u-boot-work/cpu/nios2/sysid.c --- u-boot-2004-10-20/cpu/nios2/sysid.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-work/cpu/nios2/sysid.c 2004-10-11 21:45:42.000000000 -0400 @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined (CFG_NIOS_SYSID_BASE) + +#include <command.h> +#include <nios2.h> +#include <nios2-io.h> +#include <linux/time.h> + +void display_sysid (void) +{ + struct nios_sysid_t *sysid = + (struct nios_sysid_t *)CACHE_BYPASS(CFG_NIOS_SYSID_BASE); + struct tm t; + char asc[32]; + + localtime_r ((time_t *)&sysid->timestamp, &t); + asctime_r (&t, asc); + printf ("SYSID : %08x, %s", sysid->id, asc); + +} + +int do_sysid (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + display_sysid (); + return (0); +} + +U_BOOT_CMD( + sysid, 1, 1, do_sysid, + "sysid - display Nios-II system id\n\n", + "\n - display Nios-II system id\n" +); +#endif /* CFG_NIOS_SYSID_BASE */ diff -Naurb u-boot-2004-10-20/include/asm-nios2/io.h u-boot-work/include/asm-nios2/io.h --- u-boot-2004-10-20/include/asm-nios2/io.h 2004-10-10 17:27:34.000000000 -0400 +++ u-boot-work/include/asm-nios2/io.h 2004-10-18 23:57:39.000000000 -0400 @@ -29,8 +29,61 @@ extern unsigned char inb (unsigned char *port); extern unsigned short inw (unsigned short *port); extern unsigned inl (unsigned port); -extern void outb (unsigned char val, unsigned char *port); -extern void outw (unsigned short val, unsigned short *port); -extern void outl (unsigned val, unsigned port); + +#define readb(addr)\ + ({unsigned char val;\ + asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readw(addr)\ + ({unsigned short val;\ + asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readl(addr)\ + ({unsigned long val;\ + asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define writeb(addr,val)\ + asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val)) +#define writew(addr,val)\ + asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val)) +#define writel(addr,val)\ + asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val)) + +#define inb(addr) readb(addr) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(addr,val) writeb(addr,val) +#define outw(addr,val) writew(addr,val) +#define outl(addr,val) writel(addr,val) + +static inline void insb (unsigned long port, void *dst, unsigned long count) +{ + unsigned char *p = dst; + while (count--) *p++ = inb (port); +} +static inline void insw (unsigned long port, void *dst, unsigned long count) +{ + unsigned short *p = dst; + while (count--) *p++ = inw (port); +} +static inline void insl (unsigned long port, void *dst, unsigned long count) +{ + unsigned long *p = dst; + while (count--) *p++ = inl (port); +} + +static inline void outsb (unsigned long port, const void *src, unsigned long count) +{ + const unsigned char *p = src; + while (count--) outb (*p++, port); +} + +static inline void outsw (unsigned long port, const void *src, unsigned long count) +{ + const unsigned short *p = src; + while (count--) outw (*p++, port); +} +static inline void outsl (unsigned long port, const void *src, unsigned long count) +{ + const unsigned long *p = src; + while (count--) outl (*p++, port); +} #endif /* __ASM_NIOS2_IO_H_ */ diff -Naurb u-boot-2004-10-20/lib_nios2/nios_linux.c u-boot-work/lib_nios2/nios_linux.c --- u-boot-2004-10-20/lib_nios2/nios_linux.c 2004-10-10 17:27:35.000000000 -0400 +++ u-boot-work/lib_nios2/nios_linux.c 2004-10-20 10:29:35.000000000 -0400 @@ -23,10 +23,18 @@ #include <common.h> #include <command.h> +#include <asm/byteorder.h> + +extern image_header_t header; /* common/cmd_bootm.c */ -/* TODO - */ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong addr, ulong *len_ptr, int verify) { + image_header_t *hdr = &header; + void (*kernel)(void) = (void (*)(void))ntohl (hdr->ih_ep); + + /* For now we assume the Microtronix linux ... which only + * needs to be called ;-) + */ + kernel (); }

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[U-Boot-Users] Make drivers/cfi_flash.c protect environment and redundant enviro nment
by Michael Bendzick 26 Feb '05

26 Feb '05

Included is a patch to the drivers/cfi_flash.c driver that will automatically enable environment and redundant environment protection protection upon booting. Previously, only the monitor (U-Boot) was protected by the driver. Change log snippet: * Patch by Michael Bendzick, 12 Jul 2004: - Make drivers/cfi_flash.c protect environment and redundant environment. -Michael Bendzick Systems and Software Engineering Logic Product Development michael.b(a)logicpd.com 612-436-5122 www.logicpd.com

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[U-Boot-Users] Environment in flash rather than EEProm
by Andy Hawkins 11 Feb '05

11 Feb '05

Hi all I'm using a PPChameleonEVB, and am trying to move the u-boot environment into flash. I've modified the include/configs/PPChameleon.h file as follows: #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR 0xFFFFA000 #define CFG_ENV_OFFSET (CFG_ENV_ADDR - 0xFFFC0000) #define CFG_ENV_SIZE 0x2000 I've added some debugging into the section where it reads the environment, and I'm seeing the following: U-Boot 1.0.2-adh-2004/03/29 (Mar 30 2004 - 13:40:38) CPU: IBM PowerPC 405EP Rev. B at 133.333 MHz (PLB=133, OPB=66, EBC=33 MHz) IIC Boot EEPROM disabled PCI async ext clock used, internal PCI arbiter enabled 16 kB I-Cache 16 kB D-Cache Board: ### No HW ID - assuming PPChameleonEVB I2C: ready DRAM: 32 MB Top of RAM usable for U-Boot at: 02000000 Reserving 189k for U-Boot at: 01fd0000 Reserving 256k for malloc() at: 01f90000 Reserving 128 Bytes for Board Info at: 01f8ff80 Reserving 48 Bytes for Global Data at: 01f8ff50 Stack Pointer at: 01f8ff38 New Stack Pointer is: 01f8ff38 Now running in RAM - U-Boot at: 01fd0000 FLASH: 4 MB env_relocate[204] offset = 0x2010000 env_relocate[216] embedded ENV (before reloc) at fffd9474 env_relocate[218] embedded ENV (after reloc) at 01fe9474 U-Boot relocated to 01fd0000 NAND:Probing at 0xff000000 32 MB ### main_loop entered: bootdelay=5 ### main_loop: bootcmd="<UNDEFINED>" => As you can see, the address of the environment before relocation is 0xfffd9474. Shouldn't this be 0xFFFFA000? Is there anything else I need to do to force the location of the environment into the required place? It looks like the address of the environment is based on the location of the 'environment' variable in common/environment.c. Do I need to change the LD script to force this variable to a certain location? If so, can anyone help with what I need to do (I'm not familiar with LD scripts yet). Many thanks. Andy

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[U-Boot-Users] Re: [PATCH] Cleanup cpu/arm920t using SoC
by Wolfgang Denk 24 Jan '05

24 Jan '05

In message <4120DD8B.8040709(a)imc-berlin.de> you wrote: > > * Patch by Steven Scholz, 16 Aug 2004: > - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)" > - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0 > - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/ > - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/ > into cpu/arm920t/$(SOC)/ Added, thanks. Please feel free to go on now with the next step of cleanup. And sorry it took so long. Viele Grüße, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de Anyone who isn't confused here doesn't really know what's going on.

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[U-Boot-Users] [PATCH] ARM Integrator CP flash fix
by Shawn 12 Jan '05

12 Jan '05

Hi, Here is the patch fixing the flash support of ARM Integrator CP board. Now it supports 28F640J3C and 28F128J3C flash chips. Best regards, -Shawn.

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