October 2004 - U-Boot

[U-Boot-Users] New NAND code
by Stefan Roese 10 Aug '06

10 Aug '06

Hi! I was just wondering about state of the NAND code. When I remember correctly a pretty big rewrite was done but not commited yet. Is the last patch sent to this list from Pantelis Antoniou on 5th May still the latest version? Best regards, Stefan

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[U-Boot-Users] [PATCH] support for CF/IDE on PCMCIA for PXA25X
by Christian Pell 13 Aug '05

13 Aug '05

Hi, I tried this with some different CFs with FAT file-systems on them. There is a README in the patch itself that goes in documentation directory. Bye, -- Christian Pellegrin <chri(a)ascensit.com>, <c.pellegrin(a)eurotech.it>, <chri(a)infis.univ.ts.it>, <c.pellegrin(a)exadron.com>

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[U-Boot-Users] u-boot 1.1.1 and USB mass storage devices
by Shannon Holland 03 Aug '05

03 Aug '05

Hello, We are using u-boot on a Samsung S3C2410 based board and have USB mostly working using the arm920t USB driver. I say mostly working as some mass storage devices work fine, but most do not. Typically the behavior we see when they don't work is a "usb reset" reports the correct number of devices, a "usb tree" will return the correct device tree but "usb scan" will typically return a lot of CLI:TIMEOUT errors and seemingly never return. Sometimes it is able to find the storage device, but reading from it (it has a FAT16 filesystem) will return similar errors. I'm curious if these are known problems or likely to be something in the way we have (or have not) set up usb? Might anyone have some recommendations as to where to start looking? Thanks for any help! Shannon

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[U-Boot-Users] mkimage for DOS
by Dave Westwood 10 Jun '05

10 Jun '05

long shot really, but does anyone have a working executable mkimage for DOS or a dos window in windows (don't flame me for using windows !!)

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Re: [U-Boot-Users] Support for Samsung 1Giga bit NAND device
by Laurent Mohin 01 Jun '05

01 Jun '05

Andy, U-boot 1.1.0 doesn't provide support for NAND flash with a page size of 2K-byte instead of 512 byte (and you're right, theses devices require special handling). Pantelis Antoniou submitted a patch on 2004-04-30 which seems to manage these new chips, but I don't think it has been added to the latest CVS tree. By the way, Samsung also offer 1 Giga bit devices with a 512 byte page size (K9K1G08UOM - Manufacturer ID : 0xEC, Chip ID: 0x79). Hope this helps, Laurent Andy Hawkins <a.hawkins(a)cabletime.com> Sent by: u-boot-users-admin(a)lists.sourceforge.net 14/06/04 13:40 To: u-boot-users(a)lists.sourceforge.net cc: Subject: [U-Boot-Users] Support for Samsung 1Giga bit NAND device Hi, Can anyone tell me if U-Boot has support for the Samsung 1 Giga Bit NAND devices (Manufacturer ID: 0xec, Chip ID: 0xf1)? I understand these devices have an unusually large block size, that needs special handling. Is this correct? Thanks. Andy ------------------------------------------------------- This SF.Net email is sponsored by the new InstallShield X. >From Windows to Linux, servers to mobile, InstallShield X is the one installation-authoring solution that does it all. Learn more and evaluate today! http://www.installshield.com/Dev2Dev/0504 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] Re: u-boot error message
by Detlev Zundel 03 Apr '05

03 Apr '05

Hello Bruce, > I used u-boot-1.1.1 to boot linux.My target board is ALTERA DK1C20 and cpu is > nios.I used tools/mkimage to encapsulate a linux kernel image with header > information.But it display some error messages,it like that: > > > > [root@a901 u-boot-20040316cvs]# tools/mkimage -n 'linux kernel' \ > >> -A nios -O linux -T kernel -C none -a 1010000 -e 1010000 \ > >> -d /opt/cdk4nios/src/u-boot-20040316cvs/linux.bin uimage > > > > Invalid CPU Type - valid names are: alpha, arm, x86, ia64, mips, mips64, ppc, > s3 90, sh, sparc, sparc64, m68k > > > > Because my cpu is nios,so my linux kernel can't boot.Can you tell me what can i > do? > > Ps:my name is Bruce Hm, I haven't worked with a NIOS system, but obviously the port forgot to include support in the mkimage tool. cmd_bootm.c tests for those values so that might be your problem. Try the attached patch and maybe some NIOS people on this mailing list can speak up. Cheers Detlev PS: Mail F'up-to set to u-boot-users(a)lists.sourceforge.net -- (define Y (lambda (f) ((lambda (g) (f (lambda (x) ((g g) x)))) (lambda (g) (f (lambda (x) ((g g) x)))))))

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[U-Boot-Users] Missing 440GX SDRAM Controller reset?
by David Adair 03 Apr '05

03 Apr '05

I have this same problem described a few months ago and corrected by adding the SDRAM controller reset present in the PIBS code but missing in rev 1.1.1 of u-boot e.g: mtsdr(sdr_srst, 0x00200000); mtsdr(sdr_srst, 0x00000000); Was this left out on purpose? It seems like if the BDI configuration can cause a hang then a warm-reboot is going to be problematic too?? > Re: problems with BDI2000 / u-boot / Linux on IBM 440GX Ocotea reference board > > The first problem is if I try to run u-boot from flash with a BDI2000 > > connected (i.e. do "reset" and "go" commands), then u-boot starts > > running but hangs in the SDRAM init. Specifically, it hangs waiting > > for the MRS Command Complete status bit to be set. > > IIRC I ran into the same thing, all I needed to do was remove the sdram > configuration from the config for the BDI.

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[U-Boot-Users] PATCH: Removing all these "extern void reset_cpu()"
by Steven Scholz 03 Apr '05

03 Apr '05

Hi there, please consider the patch attached. CHANGELOG: * Patch by Steven Scholz, 25 Oct 2004: - Replace all "extern void reset_cpu()" with one occurence of "void reset_cpu (ulong addr)" in include/common.h -- Steven Scholz Index: cpu/arm720t/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm720t/cpu.c,v retrieving revision 1.6 diff -p -u -r1.6 cpu.c --- cpu/arm720t/cpu.c 1 Aug 2004 22:48:19 -0000 1.6 +++ cpu/arm720t/cpu.c 25 Oct 2004 14:03:13 -0000 @@ -84,8 +84,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm720t/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm720t/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/arm720t/interrupts.c 11 Jul 2004 22:19:27 -0000 1.6 +++ cpu/arm720t/interrupts.c 25 Oct 2004 14:03:13 -0000 @@ -31,8 +31,6 @@ #include <asm/proc-armv/ptrace.h> #include <asm/hardware.h> -extern void reset_cpu(ulong addr); - #ifndef CONFIG_NETARM /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff Index: cpu/arm920t/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/arm920t/cpu.c 8 Feb 2004 19:38:43 -0000 1.3 +++ cpu/arm920t/cpu.c 25 Oct 2004 14:03:13 -0000 @@ -124,8 +124,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm920t/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/arm920t/interrupts.c 1 Aug 2004 22:48:19 -0000 1.6 +++ cpu/arm920t/interrupts.c 25 Oct 2004 14:03:13 -0000 @@ -34,8 +34,6 @@ #include <arm920t.h> #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ interrupts */ void enable_interrupts (void) Index: cpu/arm920t/s3c24x0/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/s3c24x0/interrupts.c,v retrieving revision 1.1 diff -p -u -r1.1 interrupts.c --- cpu/arm920t/s3c24x0/interrupts.c 9 Oct 2004 22:21:30 -0000 1.1 +++ cpu/arm920t/s3c24x0/interrupts.c 25 Oct 2004 14:03:13 -0000 @@ -39,7 +39,6 @@ #include <s3c2410.h> #endif -extern void reset_cpu(ulong addr); int timer_load_val = 0; /* macro to read the 16 bit timer */ Index: cpu/arm925t/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm925t/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/arm925t/cpu.c 8 Feb 2004 19:38:43 -0000 1.3 +++ cpu/arm925t/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -125,8 +125,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm925t/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm925t/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/arm925t/interrupts.c 25 Apr 2004 14:37:30 -0000 1.6 +++ cpu/arm925t/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -38,7 +38,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ Index: cpu/arm926ejs/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm926ejs/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/arm926ejs/cpu.c 8 Feb 2004 19:38:43 -0000 1.3 +++ cpu/arm926ejs/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -125,8 +125,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/arm926ejs/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm926ejs/interrupts.c,v retrieving revision 1.7 diff -p -u -r1.7 interrupts.c --- cpu/arm926ejs/interrupts.c 23 Mar 2004 21:43:08 -0000 1.7 +++ cpu/arm926ejs/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -40,7 +40,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ Index: cpu/at91rm9200/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/at91rm9200/cpu.c,v retrieving revision 1.9 diff -p -u -r1.9 cpu.c --- cpu/at91rm9200/cpu.c 10 Oct 2004 20:23:59 -0000 1.9 +++ cpu/at91rm9200/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -115,8 +115,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag { #ifdef CFG_SOFT_RESET - extern void reset_cpu(ulong addr); - disable_interrupts(); reset_cpu(0); #else Index: cpu/at91rm9200/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/at91rm9200/interrupts.c,v retrieving revision 1.6 diff -p -u -r1.6 interrupts.c --- cpu/at91rm9200/interrupts.c 11 Oct 2004 22:25:50 -0000 1.6 +++ cpu/at91rm9200/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -35,8 +35,6 @@ #include <asm/arch/hardware.h> #include <asm/proc/ptrace.h> -extern void reset_cpu(ulong addr); - /* the number of clocks per CFG_HZ */ #define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ) Index: cpu/i386/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/i386/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/i386/cpu.c 27 Jun 2003 21:32:33 -0000 1.3 +++ cpu/i386/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -50,8 +50,6 @@ int cpu_init(void) int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu(ulong addr); - printf ("resetting ...\n"); udelay(50000); /* wait 50 ms */ disable_interrupts(); Index: cpu/ixp/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/ixp/cpu.c,v retrieving revision 1.2 diff -p -u -r1.2 cpu.c --- cpu/ixp/cpu.c 8 Feb 2004 19:38:44 -0000 1.2 +++ cpu/ixp/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -76,8 +76,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - printf ("resetting ...\n"); udelay (50000); /* wait 50 ms */ Index: cpu/ixp/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/ixp/interrupts.c,v retrieving revision 1.2 diff -p -u -r1.2 interrupts.c --- cpu/ixp/interrupts.c 15 Oct 2003 23:53:51 -0000 1.2 +++ cpu/ixp/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -30,8 +30,6 @@ #include <common.h> #include <asm/arch/ixp425.h> -extern void reset_cpu (ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ void enable_interrupts (void) Index: cpu/lh7a40x/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/lh7a40x/cpu.c,v retrieving revision 1.1 diff -p -u -r1.1 cpu.c --- cpu/lh7a40x/cpu.c 9 Jun 2004 13:37:53 -0000 1.1 +++ cpu/lh7a40x/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -124,8 +124,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ Index: cpu/lh7a40x/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/lh7a40x/interrupts.c,v retrieving revision 1.2 diff -p -u -r1.2 interrupts.c --- cpu/lh7a40x/interrupts.c 10 Jun 2004 21:55:34 -0000 1.2 +++ cpu/lh7a40x/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -35,7 +35,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); static ulong timer_load_val = 0; /* macro to read the 16 bit timer */ Index: cpu/pxa/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/pxa/cpu.c,v retrieving revision 1.5 diff -p -u -r1.5 cpu.c --- cpu/pxa/cpu.c 8 Feb 2004 19:38:44 -0000 1.5 +++ cpu/pxa/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -74,8 +74,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - printf ("resetting ...\n"); udelay (50000); /* wait 50 ms */ Index: cpu/pxa/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/pxa/interrupts.c,v retrieving revision 1.4 diff -p -u -r1.4 interrupts.c --- cpu/pxa/interrupts.c 9 Jun 2004 13:37:53 -0000 1.4 +++ cpu/pxa/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -29,8 +29,6 @@ #include <common.h> #include <asm/arch/pxa-regs.h> -extern void reset_cpu (ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ void enable_interrupts (void) Index: cpu/s3c44b0/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/s3c44b0/cpu.c,v retrieving revision 1.2 diff -p -u -r1.2 cpu.c --- cpu/s3c44b0/cpu.c 17 Oct 2004 21:12:11 -0000 1.2 +++ cpu/s3c44b0/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -86,8 +86,6 @@ void reset_cpu (ulong addr) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - disable_interrupts (); reset_cpu (0); Index: cpu/s3c44b0/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/s3c44b0/interrupts.c,v retrieving revision 1.1 diff -p -u -r1.1 interrupts.c --- cpu/s3c44b0/interrupts.c 24 Feb 2004 00:16:44 -0000 1.1 +++ cpu/s3c44b0/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -29,8 +29,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu(ulong addr); - /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff Index: cpu/sa1100/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/sa1100/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/sa1100/cpu.c 8 Feb 2004 19:38:44 -0000 1.3 +++ cpu/sa1100/cpu.c 25 Oct 2004 14:03:14 -0000 @@ -73,8 +73,6 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - extern void reset_cpu (ulong addr); - printf ("resetting ...\n"); udelay (50000); /* wait 50 ms */ Index: cpu/sa1100/interrupts.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/sa1100/interrupts.c,v retrieving revision 1.3 diff -p -u -r1.3 interrupts.c --- cpu/sa1100/interrupts.c 14 Mar 2004 15:20:56 -0000 1.3 +++ cpu/sa1100/interrupts.c 25 Oct 2004 14:03:14 -0000 @@ -31,8 +31,6 @@ #include <asm/proc-armv/ptrace.h> -extern void reset_cpu (ulong addr); - #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ void enable_interrupts (void) Index: include/common.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/common.h,v retrieving revision 1.46 diff -p -u -r1.46 common.h --- include/common.h 10 Oct 2004 18:41:14 -0000 1.46 +++ include/common.h 25 Oct 2004 14:03:15 -0000 @@ -378,6 +378,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); +void reset_cpu (ulong addr); /* $(CPU)/serial.c */ int serial_init (void);

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[U-Boot-Users] Resending PATCH: Support for Motorola HiddenDragon board
by Santoso, Yusdi 03 Apr '05

03 Apr '05

Arrgh...ignore my first patch...I send a wrong patch version, the first one was agains the 2004-08-18 build. This is the correct one based on the daily snapshot. So sorry.... Thanks, Yusdi

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[U-Boot-Users] common/serial.c patch
by Curtis, Allen 03 Apr '05

03 Apr '05

This is a patch to support multiple serial ports. Existing code will compile and run without modification. I hope you find this useful. THX

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[U-Boot-Users] PATCH: Nios-II EPCS support
by Scott McNutt 31 Mar '05

31 Mar '05

Patch: Add support for Nios-II EPCS Controller core. Regards, --Scott diff -Naurb u-boot-2004-10-21/cpu/nios2/Makefile u-boot-work/cpu/nios2/Makefile --- u-boot-2004-10-21/cpu/nios2/Makefile 2004-10-21 19:43:18.000000000 -0400 +++ u-boot-work/cpu/nios2/Makefile 2004-10-21 18:14:03.000000000 -0400 @@ -27,7 +27,7 @@ START = start.o AOBJS = exceptions.o -OBJS = cpu.o interrupts.o serial.o sysid.o traps.o +OBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o all: .depend $(START) $(LIB) diff -Naurb u-boot-2004-10-21/cpu/nios2/epcs.c u-boot-work/cpu/nios2/epcs.c --- u-boot-2004-10-21/cpu/nios2/epcs.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-work/cpu/nios2/epcs.c 2004-10-21 19:30:00.000000000 -0400 @@ -0,0 +1,711 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CFG_NIOS_EPCSBASE) +#include <command.h> +#include <nios2.h> +#include <nios2-io.h> +#include <nios2-epcs.h> + + +/*-----------------------------------------------------------------------*/ +#define SHORT_HELP\ + "epcs - read/write Cyclone EPCS configuration device.\n" + +#define LONG_HELP\ + "\n"\ + "epcs erase start [end]\n"\ + " - erase sector start or sectors start through end.\n"\ + "epcs info\n"\ + " - display EPCS device information.\n"\ + "epcs protect on | off\n"\ + " - turn device protection on or off.\n"\ + "epcs read addr offset count\n"\ + " - read count bytes from offset to addr.\n"\ + "epcs write addr offset count\n"\ + " - write count bytes to offset from addr.\n"\ + "epcs verify addr offset count\n"\ + " - verify count bytes at offset from addr.\n" + + +/*-----------------------------------------------------------------------*/ +/* Operation codes for serial configuration devices + */ +#define EPCS_WRITE_ENA 0x06 /* Write enable */ +#define EPCS_WRITE_DIS 0x04 /* Write disable */ +#define EPCS_READ_STAT 0x05 /* Read status */ +#define EPCS_READ_BYTES 0x03 /* Read bytes */ +#define EPCS_READ_ID 0xab /* Read silicon id */ +#define EPCS_WRITE_STAT 0x01 /* Write status */ +#define EPCS_WRITE_BYTES 0x02 /* Write bytes */ +#define EPCS_ERASE_BULK 0xc7 /* Erase entire device */ +#define EPCS_ERASE_SECT 0xd8 /* Erase sector */ + +/* Device status register bits + */ +#define EPCS_STATUS_WIP (1<<0) /* Write in progress */ +#define EPCS_STATUS_WEL (1<<1) /* Write enable latch */ + +/* Misc + */ +#define EPCS_TIMEOUT 100 /* 100 msec timeout */ + +static nios_spi_t *epcs = + (nios_spi_t *)CACHE_BYPASS(CFG_NIOS_EPCSBASE); + +/*********************************************************************** + * Device access + ***********************************************************************/ +static int epcs_cs (int assert) +{ + ulong start; + + if (assert) { + epcs->control |= NIOS_SPI_SSO; + } else { + /* Let all bits shift out */ + start = get_timer (0); + while ((epcs->status & NIOS_SPI_TMT) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + epcs->control &= ~NIOS_SPI_SSO; + } + return (0); +} + +static int epcs_tx (unsigned char c) +{ + ulong start; + + start = get_timer (0); + while ((epcs->status & NIOS_SPI_TRDY) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + epcs->txdata = c; + return (0); +} + +static int epcs_rx (void) +{ + ulong start; + + start = get_timer (0); + while ((epcs->status & NIOS_SPI_RRDY) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + return (epcs->rxdata); +} + +static unsigned char bitrev[] = { + 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, + 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f +}; + +static unsigned char epcs_bitrev (unsigned char c) +{ + unsigned char val; + + val = bitrev[c>>4]; + val |= bitrev[c & 0x0f]<<4; + return (val); +} + +static void epcs_rcv (unsigned char *dst, int len) +{ + while (len--) { + epcs_tx (0); + *dst++ = epcs_rx (); + } +} + +static void epcs_rrcv (unsigned char *dst, int len) +{ + while (len--) { + epcs_tx (0); + *dst++ = epcs_bitrev (epcs_rx ()); + } +} + +static void epcs_snd (unsigned char *src, int len) +{ + while (len--) { + epcs_tx (*src++); + epcs_rx (); + } +} + +static void epcs_rsnd (unsigned char *src, int len) +{ + while (len--) { + epcs_tx (epcs_bitrev (*src++)); + epcs_rx (); + } +} + +static void epcs_wr_enable (void) +{ + epcs_cs (1); + epcs_tx (EPCS_WRITE_ENA); + epcs_rx (); + epcs_cs (0); +} + +static unsigned char epcs_status_rd (void) +{ + unsigned char status; + + epcs_cs (1); + epcs_tx (EPCS_READ_STAT); + epcs_rx (); + epcs_tx (0); + status = epcs_rx (); + epcs_cs (0); + return (status); +} + +static void epcs_status_wr (unsigned char status) +{ + epcs_wr_enable (); + epcs_cs (1); + epcs_tx (EPCS_WRITE_STAT); + epcs_rx (); + epcs_tx (status); + epcs_rx (); + epcs_cs (0); + return; +} + +/*********************************************************************** + * Device information + ***********************************************************************/ + +static struct epcs_devinfo_t devinfo[] = { + { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, + { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, + { 0, 0, 0, 0, 0, 0 } +}; + +epcs_devinfo_t *epcs_dev_find (void) +{ + unsigned char buf[4]; + unsigned char id; + int i; + struct epcs_devinfo_t *dev = NULL; + + /* Read silicon id requires 3 "dummy bytes" before it's put + * on the wire. + */ + buf[0] = EPCS_READ_ID; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rcv (buf,1); + if (epcs_cs (0) == -1) + return (NULL); + id = buf[0]; + + /* Find the info struct */ + i = 0; + while (devinfo[i].name) { + if (id == devinfo[i].id) { + dev = &devinfo[i]; + break; + } + i++; + } + + return (dev); +} + +/*********************************************************************** + * Misc Utilities + ***********************************************************************/ +int epcs_cfgsz (void) +{ + int sz = 0; + unsigned char buf[128]; + unsigned char *p; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + /* Read in the first 128 bytes of the device */ + buf[0] = EPCS_READ_BYTES; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rrcv (buf, sizeof(buf)); + epcs_cs (0); + + /* Search for the starting 0x6a which is followed by the + * 4-byte 'register' and 4-byte bit-count. + */ + p = buf; + while (p < buf + sizeof(buf)-8) { + if ( *p == 0x6a ) { + /* Point to bit count and extract */ + p += 5; + sz = *p++; + sz |= *p++ << 8; + sz |= *p++ << 16; + sz |= *p++ << 24; + /* Convert to byte count */ + sz += 7; + sz >>= 3; + } else if (*p == 0xff) { + /* 0xff is ok ... just skip */ + p++; + continue; + } else { + /* Not 0xff or 0x6a ... something's not + * right ... report 'unknown' (sz=0). + */ + break; + } + } + return (sz); +} + +int epcs_erase (unsigned start, unsigned end) +{ + unsigned off, sectsz; + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev || (start>end)) + return (-1); + + /* Erase the requested sectors. An address is required + * that lies within the requested sector -- we'll just + * use the first address in the sector. + */ + printf ("epcs erasing sector %d ", start); + if (start != end) + printf ("to %d ", end); + sectsz = (1 << dev->sz_sect); + while (start <= end) { + off = start * sectsz; + start++; + + buf[0] = EPCS_ERASE_SECT; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_wr_enable (); + epcs_cs (1); + epcs_snd (buf,4); + epcs_cs (0); + + printf ("."); /* Some user feedback */ + + /* Wait for erase to complete */ + while (epcs_status_rd() & EPCS_STATUS_WIP) + ; + } + printf (" done.\n"); + return (0); +} + +int epcs_read (ulong addr, ulong off, ulong cnt) +{ + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + buf[0] = EPCS_READ_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rrcv ((unsigned char *)addr, cnt); + epcs_cs (0); + + return (0); +} + +int epcs_write (ulong addr, ulong off, ulong cnt) +{ + ulong wrcnt; + unsigned pgsz; + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + pgsz = (1<<dev->sz_page); + while (cnt) { + if (off % pgsz) + wrcnt = pgsz - (off % pgsz); + else + wrcnt = pgsz; + wrcnt = (wrcnt > cnt) ? cnt : wrcnt; + + buf[0] = EPCS_WRITE_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_wr_enable (); + epcs_cs (1); + epcs_snd (buf,4); + epcs_rsnd ((unsigned char *)addr, wrcnt); + epcs_cs (0); + + /* Wait for write to complete */ + while (epcs_status_rd() & EPCS_STATUS_WIP) + ; + + cnt -= wrcnt; + off += wrcnt; + addr += wrcnt; + } + + return (0); +} + +int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err) +{ + ulong rdcnt; + unsigned char buf[256]; + unsigned char *start,*end; + int i; + + start = end = (unsigned char *)addr; + while (cnt) { + rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; + epcs_read ((ulong)buf, off, rdcnt); + for (i=0; i<rdcnt; i++) { + if (*end != buf[i]) { + *err = end - start; + return(-1); + } + end++; + } + cnt -= rdcnt; + off += rdcnt; + } + return (0); +} + +static int epcs_sect_erased (int sect, unsigned *offset, + struct epcs_devinfo_t *dev) +{ + unsigned char buf[128]; + unsigned off, end; + unsigned sectsz; + int i; + + sectsz = (1 << dev->sz_sect); + off = sectsz * sect; + end = off + sectsz; + + while (off < end) { + epcs_read ((ulong)buf, off, sizeof(buf)); + for (i=0; i < sizeof(buf); i++) { + if (buf[i] != 0xff) { + *offset = off + i; + return (0); + } + } + off += sizeof(buf); + } + return (1); +} + + +/*********************************************************************** + * Commands + ***********************************************************************/ +static +void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + int i; + unsigned char stat; + unsigned tmp; + int erased; + + /* Basic device info */ + printf ("%s: %d kbytes (%d sectors x %d kbytes," + " %d bytes/page)\n", + dev->name, 1 << (dev->size-10), + dev->num_sects, 1 << (dev->sz_sect-10), + 1 << dev->sz_page ); + + /* Status -- for now protection is all-or-nothing */ + stat = epcs_status_rd(); + printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", + stat, + (stat & EPCS_STATUS_WIP) ? 1 : 0, + (stat & EPCS_STATUS_WEL) ? 1 : 0, + (stat & dev->prot_mask) ? "on" : "off" ); + + /* Configuration */ + tmp = epcs_cfgsz (); + if (tmp) { + printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); + } else { + printf ("config: unknown\n" ); + } + + /* Sector info */ + for (i=0; i<dev->num_sects; i++) { + erased = epcs_sect_erased (i, &tmp, dev); + printf (" %d: %06x ", + i, i*(1<<dev->sz_sect) ); + if (erased) + printf ("erased\n"); + else + printf ("data @ 0x%06x\n", tmp); + } + + return; +} + +static +void do_epcs_erase (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned start,end; + + if ((argc < 3) || (argc > 4)) { + printf ("USAGE: epcs erase sect [end]\n"); + return; + } + if ((epcs_status_rd() & dev->prot_mask) != 0) { + printf ( "epcs: device protected.\n"); + return; + } + + start = simple_strtoul (argv[2], NULL, 10); + if (argc > 3) + end = simple_strtoul (argv[3], NULL, 10); + else + end = start; + if ((start >= dev->num_sects) || (start > end)) { + printf ("epcs: invalid sector range: [%d:%d]\n", + start, end ); + return; + } + + epcs_erase (start, end); + + return; +} + +static +void do_epcs_protect (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned char stat; + + /* For now protection is all-or-nothing to keep things + * simple. The protection bits don't map in a linear + * fashion ... and we would rather protect the bottom + * of the device since it contains the config data and + * leave the top unprotected for app use. But unfortunately + * protection works from top-to-bottom so it does + * really help very much from a software app point-of-view. + */ + if (argc < 3) { + printf ("USAGE: epcs protect on | off\n"); + return; + } + if (!dev) + return; + + /* Protection on/off is just a matter of setting/clearing + * all protection bits in the status register. + */ + stat = epcs_status_rd (); + if (strcmp ("on", argv[2]) == 0) { + stat |= dev->prot_mask; + } else if (strcmp ("off", argv[2]) == 0 ) { + stat &= ~dev->prot_mask; + } else { + printf ("epcs: unknown protection: %s\n", argv[2]); + return; + } + epcs_status_wr (stat); + return; +} + +static +void do_epcs_read (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + + if (argc < 5) { + printf ("USAGE: epcs read addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: read %08lx <- %06lx (0x%lx bytes)\n", + addr, off, cnt); + epcs_read (addr, off, cnt); + + return; +} + +static +void do_epcs_write (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: epcs write addr offset count\n"); + return; + } + if ((epcs_status_rd() & dev->prot_mask) != 0) { + printf ( "epcs: device protected.\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: write %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + epcs_write (addr, off, cnt); + if (epcs_verify (addr, off, cnt, &err) != 0) + printf ("epcs: write error at offset %06lx\n", err); + + return; +} + +static +void do_epcs_verify (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: epcs verify addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: verify %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + if (epcs_verify (addr, off, cnt, &err) != 0) + printf ("epcs: verify error at offset %06lx\n", err); + + return; +} + +/*-----------------------------------------------------------------------*/ +int do_epcs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int len; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) { + printf ("epcs: device not found.\n"); + return (-1); + } + + if (argc < 2) { + do_epcs_info (dev, argc, argv); + return (0); + } + + len = strlen (argv[1]); + if (strncmp ("info", argv[1], len) == 0) { + do_epcs_info (dev, argc, argv); + } else if (strncmp ("erase", argv[1], len) == 0) { + do_epcs_erase (dev, argc, argv); + } else if (strncmp ("protect", argv[1], len) == 0) { + do_epcs_protect (dev, argc, argv); + } else if (strncmp ("read", argv[1], len) == 0) { + do_epcs_read (dev, argc, argv); + } else if (strncmp ("write", argv[1], len) == 0) { + do_epcs_write (dev, argc, argv); + } else if (strncmp ("verify", argv[1], len) == 0) { + do_epcs_verify (dev, argc, argv); + } else { + printf ("epcs: unknown operation: %s\n", argv[1]); + } + + return (0); +} + +/*-----------------------------------------------------------------------*/ + + +U_BOOT_CMD( epcs, 5, 0, do_epcs, SHORT_HELP, LONG_HELP ); + +#endif /* CONFIG_NIOS_EPCS */ diff -Naurb u-boot-2004-10-21/include/configs/PK1C20.h u-boot-work/include/configs/PK1C20.h --- u-boot-2004-10-21/include/configs/PK1C20.h 2004-10-10 17:27:34.000000000 -0400 +++ u-boot-work/include/configs/PK1C20.h 2004-10-21 19:53:22.000000000 -0400 @@ -52,7 +52,7 @@ #define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ #define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ #define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */ -#define CFG_SRAM_SIZE 0x00200000 /* 2 MByte */ +#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ /*------------------------------------------------------------------------ * MEMORY ORGANIZATION @@ -107,6 +107,14 @@ #define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ /*------------------------------------------------------------------------ + * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for + * epcs device access is enabled. The base address is the epcs + * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. + * The register base is currently at offset 0x400 from the memory base. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */ + +/*------------------------------------------------------------------------ * DEBUG *----------------------------------------------------------------------*/ #undef CONFIG_ROM_STUBS /* Stubs not in ROM */ @@ -173,6 +181,36 @@ #include <cmd_confdefs.h> /*------------------------------------------------------------------------ + * COMPACT FLASH + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CONFIG_IDE_PREINIT /* Implement id_preinit */ +#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x00900800 /* ATA base addr */ +#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ +#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ +#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */ +#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ +#define CFG_ATA_STRIDE 4 /* Width betwix addrs */ +#define CONFIG_DOS_PARTITION + +/* Board-specific cf regs */ +#define CFG_CF_PRESENT 0x00900880 /* CF Present PIO base */ +#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/ +#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ + +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ + +/*------------------------------------------------------------------------ + * JFFS2 + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CFG_JFFS_CUSTOM_PART /* board defined part */ +#endif + +/*------------------------------------------------------------------------ * MISC *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* Provide extended help*/ @@ -185,4 +223,7 @@ #define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ #define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + #endif /* __CONFIG_H */ diff -Naurb u-boot-2004-10-21/include/nios2-epcs.h u-boot-work/include/nios2-epcs.h --- u-boot-2004-10-21/include/nios2-epcs.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-work/include/nios2-epcs.h 2004-10-21 19:13:53.000000000 -0400 @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera Nios-II EPCS Controller Core interfaces + ************************************************************************/ + +#ifndef __NIOS2_EPCS_H__ +#define __NIOS2_EPCS_H__ + +typedef struct epcs_devinfo_t { + const char *name; /* Device name */ + unsigned char id; /* Device silicon id */ + unsigned char size; /* Total size log2(bytes)*/ + unsigned char num_sects; /* Number of sectors */ + unsigned char sz_sect; /* Sector size log2(bytes) */ + unsigned char sz_page; /* Page size log2(bytes) */ + unsigned char prot_mask; /* Protection mask */ +}epcs_devinfo_t; + +/* Returns the devinfo struct if EPCS device is found; + * NULL otherwise. + */ +extern epcs_devinfo_t *epcs_dev_find (void); + +/* Returns the number of bytes used by config data. + * Negative on error. + */ +extern int epcs_cfgsz (void); + +/* Erase sectors 'start' to 'end' - return zero on success + */ +extern int epcs_erase (unsigned start, unsigned end); + +/* Read 'cnt' bytes from device offset 'off' into buf at 'addr' + * Zero return on success + */ +extern int epcs_read (ulong addr, ulong off, ulong cnt); + +/* Write 'cnt' bytes to device offset 'off' from buf at 'addr'. + * Zero return on success + */ +extern int epcs_write (ulong addr, ulong off, ulong cnt); + +/* Verify 'cnt' bytes at device offset 'off' comparing with buf + * at 'addr'. On failure, write first invalid offset to *err. + * Zero return on success + */ +extern int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err); + +#endif /* __NIOS2_EPCS_H__ */ diff -Naurb u-boot-2004-10-21/include/nios2-io.h u-boot-work/include/nios2-io.h --- u-boot-2004-10-21/include/nios2-io.h 2004-10-10 17:27:34.000000000 -0400 +++ u-boot-work/include/nios2-io.h 2004-10-21 17:33:05.000000000 -0400 @@ -137,37 +137,6 @@ #define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ /*------------------------------------------------------------------------ - * ASMI - *----------------------------------------------------------------------*/ -typedef volatile struct nios_asmi_t { - unsigned rxdata; /* Rx data reg */ - unsigned txdata; /* Tx data reg */ - unsigned status; /* Status reg */ - unsigned control; /* Control reg */ - unsigned reserved; - unsigned slavesel; /* Slave select */ - unsigned endofpacket; /* End-of-packet reg */ -}nios_asmi_t; - -/* status register */ -#define NIOS_ASMI_ROE (1 << 3) /* rx overrun */ -#define NIOS_ASMI_TOE (1 << 4) /* tx overrun */ -#define NIOS_ASMI_TMT (1 << 5) /* tx empty */ -#define NIOS_ASMI_TRDY (1 << 6) /* tx ready */ -#define NIOS_ASMI_RRDY (1 << 7) /* rx ready */ -#define NIOS_ASMI_E (1 << 8) /* exception */ -#define NIOS_ASMI_EOP (1 << 9) /* eop detected */ - -/* control register */ -#define NIOS_ASMI_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_ASMI_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_ASMI_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_ASMI_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_ASMI_IE (1 << 8) /* exception int ena */ -#define NIOS_ASMI_IEOP (1 << 9) /* rx eop int ena */ -#define NIOS_ASMI_SSO (1 << 10) /* slave select enable */ - -/*------------------------------------------------------------------------ * JTAG UART *----------------------------------------------------------------------*/ typedef volatile struct nios_jtag_t {

2 1

[U-Boot-Users] Question on do_bootm in cmd_bootm.c
by Nick Barendt 31 Mar '05

31 Mar '05

Can someone, maybe Wolfgang, comment on the maximum 4MB uncompressed size of gunzip (and, possibly, bzip2) images? I've been working on a Coldfire 5272 system for quite some time with u-boot and uClinux. Both have been remarkably stable. We use the uClinux default build wherein the root filesystem (romfs) is appended to the end of the kernel image, starting where the bss would normally be. The kernel startup code relocates the romfs image to just beyond the bss, then, and everything runs smoothly. I know that many folks in the PPC world use separate kernel and root filesystem images, for many good reasons, but many (most?) of the uClinux platforms use this concatenated kernel+romfs image. Recently, we've been adding more content to the root filesystem. As our root filesystem grew larger (say about 3MB), however, we started seeing boot problems where the kernel would boot fine but the root filesystem was clearly corrupt. I've spent the better part of two days trying to track down where things go wrong, from the kernel to u-boot. Of course, I used a hardware debugger, looked at u-boot's memory assignments, image load addresses, entry points, malloc areas, etc. I just located the source of my trouble, a hard-coded 4MB maximum uncompressed size in do_bootm: int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong iflag; ulong addr; ulong data, len, checksum; ulong *len_ptr; uint unc_len = 0x400000; ^^^^^^^^^ int i, verify; SNIP case IH_COMP_GZIP: printf (" Uncompressing %s ... ", name); if (gunzip ((void *)ntohl(hdr->ih_load), unc_len, ^^^^^^^^ (uchar *)data, (int *)&len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); SHOW_BOOT_PROGRESS (-6); do_reset (cmdtp, flag, argc, argv); } break; SNIP Increasing unc_len to larger values (like 6MB) seems to solve my problem. With an uncompressed image larger than 4MB, gunzip doesn't seem to generate any errors (granted, I haven't stepped through gunzip and zlib), but merrily runs along, although the data beyond the 4MB boundary seems to be missing or corrupt. It looks like there's a truncation (about line 1875 in zlib.c) to z.avail_out in zlib that prevents data from being copied beyond unc_len - maybe that should be an error instead of silently truncating data? Just a thought. I'll into submitting a patch for that. I was wondering if there was some reason for the 0x400000 magic number for unc_len. Is that just a magic number? Is that larger than anyone uses for images? I guess I'm a little surprised that this hasn't bitten anyone else so far (nothing I could see on the mailing list archive, at least). Our 1MB kernel and 3MB romfs root filesystem might be exceptionally large, I don't know. Would there be any issues with making unc_len a CFG_ macro, if I submitted a patch? Nick Barendt

4 8

[U-Boot-Users] PATCH: Nios-II cleanups
by Scott McNutt 31 Mar '05

31 Mar '05

Patch has some minor Nios-II cleanups: -Add sysid command (Nios-II only). -Locate default exception trampoline at proper offset. -Implement I/O routines (readb, writeb, etc). -Implement do_bootm_linux Regards, --Scott diff -Naurb u-boot-2004-10-20/cpu/nios2/Makefile u-boot-work/cpu/nios2/Makefile --- u-boot-2004-10-20/cpu/nios2/Makefile 2004-10-10 17:27:33.000000000 -0400 +++ u-boot-work/cpu/nios2/Makefile 2004-10-11 21:38:41.000000000 -0400 @@ -27,7 +27,7 @@ START = start.o AOBJS = exceptions.o -OBJS = cpu.o interrupts.o serial.o traps.o +OBJS = cpu.o interrupts.o serial.o sysid.o traps.o all: .depend $(START) $(LIB) diff -Naurb u-boot-2004-10-20/cpu/nios2/cpu.c u-boot-work/cpu/nios2/cpu.c --- u-boot-2004-10-20/cpu/nios2/cpu.c 2004-10-10 17:27:33.000000000 -0400 +++ u-boot-work/cpu/nios2/cpu.c 2004-10-11 21:40:55.000000000 -0400 @@ -26,19 +26,7 @@ #include <nios2-io.h> #if defined (CFG_NIOS_SYSID_BASE) -#include <linux/time.h> -static void check_sysid (void) -{ - struct nios_sysid_t *sysid = - (struct nios_sysid_t *)CACHE_BYPASS(CFG_NIOS_SYSID_BASE); - struct tm t; - char asc[32]; - - localtime_r ((time_t *)&sysid->timestamp, &t); - asctime_r (&t, asc); - printf ("SYSID : %08x, %s", sysid->id, asc); - -} +extern void display_sysid (void); #endif /* CFG_NIOS_SYSID_BASE */ int checkcpu (void) @@ -47,7 +35,7 @@ #if !defined(CFG_NIOS_SYSID_BASE) printf ("SYSID : <unknown>\n"); #else - check_sysid (); + display_sysid (); #endif return (0); } diff -Naurb u-boot-2004-10-20/cpu/nios2/start.S u-boot-work/cpu/nios2/start.S --- u-boot-2004-10-20/cpu/nios2/start.S 2004-10-10 17:27:33.000000000 -0400 +++ u-boot-work/cpu/nios2/start.S 2004-10-20 10:50:47.000000000 -0400 @@ -39,14 +39,24 @@ * just be invalidating the cache a second time. If cache * is not implemented initi behaves as nop. */ - movhi r4, %hi(CFG_ICACHELINE_SIZE) - ori r4, r4, %lo(CFG_ICACHELINE_SIZE) + ori r4, r0, %lo(CFG_ICACHELINE_SIZE) movhi r5, %hi(CFG_ICACHE_SIZE) ori r5, r5, %lo(CFG_ICACHE_SIZE) mov r6, r0 0: initi r6 add r6, r6, r4 bltu r6, r5, 0b + br _except_end /* Skip the tramp */ + + /* EXCEPTION TRAMPOLINE -- the following gets copied + * to the exception address (below), but is otherwise at the + * default exception vector offset (0x0020). + */ +_except_start: + movhi et, %hi(_exception) + ori et, et, %lo(_exception) + jmp et +_except_end: /* INTERRUPTS -- for now, all interrupts masked and globally * disabled. @@ -117,7 +127,9 @@ _reloc: /* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the - * exception address. + * exception address. Define CONFIG_ROM_STUBS to prevent + * the copy (e.g. exception in flash or in other + * softare/firmware component). */ #if !defined(CONFIG_ROM_STUBS) movhi r4, %hi(_except_start) @@ -126,12 +138,14 @@ ori r5, r5, %lo(_except_end) movhi r6, %hi(CFG_EXCEPTION_ADDR) ori r6, r6, %lo(CFG_EXCEPTION_ADDR) + beq r4, r6, 7f /* Skip if at proper addr */ 6: ldwio r7, 0(r4) stwio r7, 0(r6) addi r4, r4, 4 addi r6, r6, 4 bne r4, r5, 6b +7: #endif /* STACK INIT -- zero top two words for call back chain. @@ -155,15 +169,6 @@ */ br _start - /* EXCEPTION TRAMPOLINE -- the following gets copied - * to the exception address. - */ -_except_start: - movhi et, %hi(_exception) - ori et, et, %lo(_exception) - jmp et -_except_end: - /* * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in diff -Naurb u-boot-2004-10-20/cpu/nios2/sysid.c u-boot-work/cpu/nios2/sysid.c --- u-boot-2004-10-20/cpu/nios2/sysid.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-work/cpu/nios2/sysid.c 2004-10-11 21:45:42.000000000 -0400 @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined (CFG_NIOS_SYSID_BASE) + +#include <command.h> +#include <nios2.h> +#include <nios2-io.h> +#include <linux/time.h> + +void display_sysid (void) +{ + struct nios_sysid_t *sysid = + (struct nios_sysid_t *)CACHE_BYPASS(CFG_NIOS_SYSID_BASE); + struct tm t; + char asc[32]; + + localtime_r ((time_t *)&sysid->timestamp, &t); + asctime_r (&t, asc); + printf ("SYSID : %08x, %s", sysid->id, asc); + +} + +int do_sysid (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + display_sysid (); + return (0); +} + +U_BOOT_CMD( + sysid, 1, 1, do_sysid, + "sysid - display Nios-II system id\n\n", + "\n - display Nios-II system id\n" +); +#endif /* CFG_NIOS_SYSID_BASE */ diff -Naurb u-boot-2004-10-20/include/asm-nios2/io.h u-boot-work/include/asm-nios2/io.h --- u-boot-2004-10-20/include/asm-nios2/io.h 2004-10-10 17:27:34.000000000 -0400 +++ u-boot-work/include/asm-nios2/io.h 2004-10-18 23:57:39.000000000 -0400 @@ -29,8 +29,61 @@ extern unsigned char inb (unsigned char *port); extern unsigned short inw (unsigned short *port); extern unsigned inl (unsigned port); -extern void outb (unsigned char val, unsigned char *port); -extern void outw (unsigned short val, unsigned short *port); -extern void outl (unsigned val, unsigned port); + +#define readb(addr)\ + ({unsigned char val;\ + asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readw(addr)\ + ({unsigned short val;\ + asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readl(addr)\ + ({unsigned long val;\ + asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define writeb(addr,val)\ + asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val)) +#define writew(addr,val)\ + asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val)) +#define writel(addr,val)\ + asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val)) + +#define inb(addr) readb(addr) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(addr,val) writeb(addr,val) +#define outw(addr,val) writew(addr,val) +#define outl(addr,val) writel(addr,val) + +static inline void insb (unsigned long port, void *dst, unsigned long count) +{ + unsigned char *p = dst; + while (count--) *p++ = inb (port); +} +static inline void insw (unsigned long port, void *dst, unsigned long count) +{ + unsigned short *p = dst; + while (count--) *p++ = inw (port); +} +static inline void insl (unsigned long port, void *dst, unsigned long count) +{ + unsigned long *p = dst; + while (count--) *p++ = inl (port); +} + +static inline void outsb (unsigned long port, const void *src, unsigned long count) +{ + const unsigned char *p = src; + while (count--) outb (*p++, port); +} + +static inline void outsw (unsigned long port, const void *src, unsigned long count) +{ + const unsigned short *p = src; + while (count--) outw (*p++, port); +} +static inline void outsl (unsigned long port, const void *src, unsigned long count) +{ + const unsigned long *p = src; + while (count--) outl (*p++, port); +} #endif /* __ASM_NIOS2_IO_H_ */ diff -Naurb u-boot-2004-10-20/lib_nios2/nios_linux.c u-boot-work/lib_nios2/nios_linux.c --- u-boot-2004-10-20/lib_nios2/nios_linux.c 2004-10-10 17:27:35.000000000 -0400 +++ u-boot-work/lib_nios2/nios_linux.c 2004-10-20 10:29:35.000000000 -0400 @@ -23,10 +23,18 @@ #include <common.h> #include <command.h> +#include <asm/byteorder.h> + +extern image_header_t header; /* common/cmd_bootm.c */ -/* TODO - */ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong addr, ulong *len_ptr, int verify) { + image_header_t *hdr = &header; + void (*kernel)(void) = (void (*)(void))ntohl (hdr->ih_ep); + + /* For now we assume the Microtronix linux ... which only + * needs to be called ;-) + */ + kernel (); }

2 1

[U-Boot-Users] Make drivers/cfi_flash.c protect environment and redundant enviro nment
by Michael Bendzick 26 Feb '05

26 Feb '05

Included is a patch to the drivers/cfi_flash.c driver that will automatically enable environment and redundant environment protection protection upon booting. Previously, only the monitor (U-Boot) was protected by the driver. Change log snippet: * Patch by Michael Bendzick, 12 Jul 2004: - Make drivers/cfi_flash.c protect environment and redundant environment. -Michael Bendzick Systems and Software Engineering Logic Product Development michael.b(a)logicpd.com 612-436-5122 www.logicpd.com

3 2

[U-Boot-Users] Environment in flash rather than EEProm
by Andy Hawkins 11 Feb '05

11 Feb '05

Hi all I'm using a PPChameleonEVB, and am trying to move the u-boot environment into flash. I've modified the include/configs/PPChameleon.h file as follows: #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR 0xFFFFA000 #define CFG_ENV_OFFSET (CFG_ENV_ADDR - 0xFFFC0000) #define CFG_ENV_SIZE 0x2000 I've added some debugging into the section where it reads the environment, and I'm seeing the following: U-Boot 1.0.2-adh-2004/03/29 (Mar 30 2004 - 13:40:38) CPU: IBM PowerPC 405EP Rev. B at 133.333 MHz (PLB=133, OPB=66, EBC=33 MHz) IIC Boot EEPROM disabled PCI async ext clock used, internal PCI arbiter enabled 16 kB I-Cache 16 kB D-Cache Board: ### No HW ID - assuming PPChameleonEVB I2C: ready DRAM: 32 MB Top of RAM usable for U-Boot at: 02000000 Reserving 189k for U-Boot at: 01fd0000 Reserving 256k for malloc() at: 01f90000 Reserving 128 Bytes for Board Info at: 01f8ff80 Reserving 48 Bytes for Global Data at: 01f8ff50 Stack Pointer at: 01f8ff38 New Stack Pointer is: 01f8ff38 Now running in RAM - U-Boot at: 01fd0000 FLASH: 4 MB env_relocate[204] offset = 0x2010000 env_relocate[216] embedded ENV (before reloc) at fffd9474 env_relocate[218] embedded ENV (after reloc) at 01fe9474 U-Boot relocated to 01fd0000 NAND:Probing at 0xff000000 32 MB ### main_loop entered: bootdelay=5 ### main_loop: bootcmd="<UNDEFINED>" => As you can see, the address of the environment before relocation is 0xfffd9474. Shouldn't this be 0xFFFFA000? Is there anything else I need to do to force the location of the environment into the required place? It looks like the address of the environment is based on the location of the 'environment' variable in common/environment.c. Do I need to change the LD script to force this variable to a certain location? If so, can anyone help with what I need to do (I'm not familiar with LD scripts yet). Many thanks. Andy

3 7

[U-Boot-Users] Re: [PATCH] Cleanup cpu/arm920t using SoC
by Wolfgang Denk 24 Jan '05

24 Jan '05

In message <4120DD8B.8040709(a)imc-berlin.de> you wrote: > > * Patch by Steven Scholz, 16 Aug 2004: > - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)" > - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0 > - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/ > - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/ > into cpu/arm920t/$(SOC)/ Added, thanks. Please feel free to go on now with the next step of cleanup. And sorry it took so long. Viele Grüße, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de Anyone who isn't confused here doesn't really know what's going on.

6 18

[U-Boot-Users] [PATCH] ARM Integrator CP flash fix
by Shawn 12 Jan '05

12 Jan '05

Hi, Here is the patch fixing the flash support of ARM Integrator CP board. Now it supports 28F640J3C and 28F128J3C flash chips. Best regards, -Shawn.

3 2

RE: [U-Boot-Users] ARM VersatilePB - Fixed flash support
by Philippe Robin 12 Jan '05

12 Jan '05

Shawn, > One issue I've encoutered is flash write timeout of a big > chunk of data (> 128KB). Write always times out no matter how > big the value of CFG_FLASH_WRITE_TOUT is. The issue hasn't > been solved yet. Any hints are appreciated. I have tried with removing the test for timeout in the write_data() routine, just looping on the status: while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) ; This worked fine for large amounts of data so the timeout value is probably too low. Let me know if this is the same with your setting. Regards, Philippe

3 4

[U-Boot-Users] Stand alone app for changing MAC address in SMC91C111
by Robin Getz 12 Jan '05

12 Jan '05

I have created a stand alone application to change MAC addresses in the EEPROM attached to the SMC91C111, as well as the following commands: - P : Print the MAC address in the EEROM and MAC - D : Dump the LAN91C111 EEPROM contents - M : Dump the LAN91C111 MAC contents - C : Copies the MAC address from the EEPROM to the LAN91C111 - W : Write a register in the EEPROM or in the MAC It can be reviewed at our u-boot (based on 1.1.1) cvs for the Blackfin BF533 processor at: [sorry for the long url, but what can you do?] http://cvs.blackfin.uclinux.org/cgi-bin/cvsweb.cgi/u-boot_1.1.1/examples/?c… added: smc91111_eeprom.c README.smc91111_eeprom Based on people's feedback, I will submit as a patch to this list. One questions: 1) should READMEs for stand-alone applications stay in the examples dir, or go in the doc directory? -Robin

3 2

[U-Boot-Users] [patch] Updating for RPXlite_DW
by Sam Song 11 Jan '05

11 Jan '05

Hi list, I got the nudge from some folkes chatting with Wolfgang about RESET/AUTOBOOT and did this patch. All for updating RPXlite_DW board. I tried to remove board/RPXlite_dw/README to doc/ but failed. CHANGELOG: * Patch by Sam Song, 11 October 2004: - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board - Adjust CPU:BUS frequency rato 1:1 when core frequency less than 50MHz ===== Best regards, Sam _________________________________________________________ Do You Yahoo!? 150万曲MP3疯狂搜，带您闯入音乐殿堂 http://music.yisou.com/ 美女明星应有尽有，搜遍美图、艳图和酷图 http://image.yisou.com 1G就是1000兆，雅虎电邮自助扩容！ http://cn.rd.yahoo.com/mail_cn/tag/1g/*http://cn.mail.yahoo.com/event/mail_… ? RPXlite_DW_update.patch Index: board/RPXlite_dw/README =================================================================== RCS file: /cvsroot/u-boot/u-boot/board/RPXlite_dw/README,v retrieving revision 1.1 diff -p -u -r1.1 README --- board/RPXlite_dw/README 9 Jun 2004 21:04:49 -0000 1.1 +++ board/RPXlite_dw/README 11 Oct 2004 04:34:07 -0000 @@ -2,11 +2,11 @@ After following the step of Yoo. Jonghoon and Wolfgang Denk, I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW. -There are three differences between the Yoo-ported RPXlite and the RPXlite_DW. +There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW. -Board(in U-BOOT) version(in EmbeddedPlanet) CPU SDRAM FLASH +Board(in U-Boot) version(in EmbeddedPlanet) CPU SDRAM FLASH RPXlite RPXlite CW 850 16MB 4MB -RPXlite_DW RPXlite DW 823e 64MB 16MB +RPXlite_DW RPXlite DW(EP 823 H1 DW) 823e 64MB 16MB This fireware is specially coded for EmbeddedPlanet Co. Software Development Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel. @@ -17,6 +17,7 @@ It has the following three features: The default setting is 48MHz.To get a 64MHz u-boot,just add '64' in make command,like +make distclean make RPXlite_DW_64_config make all @@ -28,19 +29,21 @@ didn't use EEPROM for ENV is that Planet home.Because of the possibility of using two firewares on this board,I didn't 'disturb' EEPROM.To get NVRAM support,you may use the following build command: +make distclean make RPXlite_DW_NVRAM_config make all 3. LCD panel support -To support the Platform better,I added LCD panel(NL6448BC20-08) function.But bewear of -the fact that once you build this support and program it to FLASH,you should make sure -you put workable kernel and ramdisk at the right place in FLASH or through NFS. -Otherwise, you must erase this fireware manually via BDI2000 or ICE tools.So this -function is used for deployment and demo only.Pls look before you leap. +To support the Platform better,I added LCD panel(NL6448BC20-08) function. +For the convenience of debug, CONFIG_PERBOOT was supported. So you just +perss ENTER if you want to get a serial console in boot downcounting. +Then you can switch to LCD and serial console freely just typing +'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled. To get a LCD support u-boot,you can do the following: +make distclean make RPXlite_DW_LCD_config make all @@ -68,7 +71,7 @@ make RPXlite_DW_64_LCD_config The boot process by "make RPXlite_DW_config" could be: -U-Boot 1.1.1 (Jun 8 2004 - 11:16:30) +U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache Board: RPXlite_DW @@ -84,6 +87,68 @@ u-boot> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +A word on the U-Boot enviroment variable setting and usage : + +In the beginning, you could just need very simple defult environment variable setting, +like[include/configs/RPXlite.h] : + +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "bootm" + +This is enough for kernel NFS test. But as debug process goes on, you would expect +to save some time on environment variable setting and u-boot/kernel updating. +So the default environment variable setting would become more complicated. Just like +the one I did in include/configs/RPXlite_DW.h. + +Two u-boot commands, ku and uu, should be careful to use. They were designed to update +kernel and u-boot image file respectively. You must tftp your image to default address +'100000' and then use them correctly. Yeah, you can create your own command to do this +job. :-) The example u-boot image updating process could be : + +u-boot>t 100000 RPXlite_DW_LCD.bin +Using SCC ETHERNET device +TFTP from server 172.16.115.6; our IP address is 172.16.115.7 +Filename 'RPXlite_DW_LCD.bin'. +Load address: 0x100000 +Loading: ############################# +done +Bytes transferred = 144700 (2353c hex) +u-boot>run uu +Un-Protect Flash Sectors 0-4 in Bank # 1 +Erase Flash Sectors 0-4 in Bank # 1 +.... done +Copy to Flash... done +ff000000: 27051956 552d426f 6f742031 2e312e32 '..VU-Boot 1.1.2 +ff000010: 20284175 67203239 20323030 34202d20 (Aug 29 2004 - +ff000020: 31353a32 303a3238 29000000 00000000 15:20:28)....... +ff000030: 00000000 00000000 00000000 00000000 ................ +ff000040: 00000000 00000000 00000000 00000000 ................ +ff000050: 00000000 00000000 00000000 00000000 ................ +ff000060: 00000000 00000000 00000000 00000000 ................ +ff000070: 00000000 00000000 00000000 00000000 ................ +ff000080: 00000000 00000000 00000000 00000000 ................ +ff000090: 00000000 00000000 00000000 00000000 ................ +ff0000a0: 00000000 00000000 00000000 00000000 ................ +ff0000b0: 00000000 00000000 00000000 00000000 ................ +ff0000c0: 00000000 00000000 00000000 00000000 ................ +ff0000d0: 00000000 00000000 00000000 00000000 ................ +ff0000e0: 00000000 00000000 00000000 00000000 ................ +ff0000f0: 00000000 00000000 00000000 00000000 ................ +u-boot updating finished +u-boot> + +Also for environment updating, 'run eu' could let you erase OLD default environment variable +and then use the working u-boot environment setting. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Finally, if you want to keep the serial port to possible debug on spot for deployment, you +just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string +defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot. + I'd like to extend my heartfelt gratitute to kind people for helping me work it out. I would particually thank Wolfgang Denk for his nice help. @@ -93,4 +158,4 @@ Sam Song, samsongshu(a)yahoo.com.cn Institute of Electrical Machinery and Controls Shanghai University -June 8,2004 +Oct. 11, 2004 Index: include/configs/RPXlite_DW.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/configs/RPXlite_DW.h,v retrieving revision 1.3 diff -p -u -r1.3 RPXlite_DW.h --- include/configs/RPXlite_DW.h 9 Oct 2004 22:45:00 -0000 1.3 +++ include/configs/RPXlite_DW.h 11 Oct 2004 04:34:18 -0000 @@ -45,6 +45,7 @@ */ /* #define DEBUG 1 */ +/* #ifdef DEPLOYMENT 1 */ #undef CONFIG_MPC860 #define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ @@ -59,19 +60,31 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ -#ifdef CONFIG_LCD -#define CONFIG_BOOTDELAY 12 /* autoboot after 12 seconds */ +#ifdef DEBUG +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ + +#ifdef DEPLOYMENT +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n" +#define CONFIG_AUTOBOOT_STOP_STR "st" +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_RESET_TO_RETRY 1 +#define CONFIG_BOOT_RETRY_MIN 1 +#endif #endif +/* pre-boot commands */ +#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" + #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "nfsargs=setenv bootargs console=ttyS0,9600 root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ramargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ - "root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ + "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \ "addip=setenv bootargs $(bootargs) " \ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ ":$(hostname):$(netdev):off panic=1\0" \ @@ -82,9 +95,25 @@ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ "gatewayip=172.16.115.254\0" \ "netmask=255.255.255.0\0" \ +<<<<<<< RPXlite_DW.h + "kernel_addr=ff040000\0" \ + "ramdisk_addr=ff200000\0" \ + "ku=era $(kernel_addr) ff1fffff;cp.b 100000 $(kernel_addr) " \ + "$(filesize);md $(kernel_addr);" \ + "echo kernel updating finished\0" \ + "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \ + "$(filesize);md ff000000;" \ + "echo u-boot updating finished\0" \ + "eu=protect off 1:6;era 1:6;reset\0" \ + "lcd=setenv stdout lcd;setenv stdin lcd\0" \ + "ser=setenv stdout serial;setenv stdin serial\0" \ + "verify=no" + +======= "kernel_addr=ff080000\0" \ "ramdisk_addr=ff200000\0" \ "" +>>>>>>> 1.3 #define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -178,8 +207,13 @@ #define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ #endif +<<<<<<< RPXlite_DW.h +#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) + +======= #define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) +>>>>>>> 1.3 /*----------------------------------------------------------------------- * Cache Configuration */ @@ -254,10 +288,16 @@ /* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */ #if defined(RPXlite_64MHz) #define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */ +<<<<<<< RPXlite_DW.h +#else +#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ +#endif +======= #else #define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ #endif +>>>>>>> 1.3 /*----------------------------------------------------------------------- * PCMCIA stuff *-----------------------------------------------------------------------

2 2

[U-Boot-Users] ARM VersatilePB - Fixed flash support
by Philippe Robin 10 Jan '05

10 Jan '05

Greetings, I have attached a patch fixing flash support with Versatile Boards: CHANGELOG Entry: * Patch by Philippe Robin, 28 Sept 2004: - Fix Flash support for Versatile. Regards, Philippe

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[U-Boot-Users] [Patch] Support for AMD db1550 board
by Leif Lindholm 10 Jan '05

10 Jan '05

Hi This patch adds support for the AMD db1550 board to u-boot. It is implemented as a flavor of the au1x00 family. Since I have not tested the pcmcia/ide stuff, this board has CONFIG_BOOTCOMMAND and CONFIG_COMMANDS ifdef:d to different values than the rest of the boards in the family. Also, the memory setup differs a bit from earlier boards, due to this board being equipped with DDR SDRAM. This has lead to quite a large memsetup.S (heavily ifdef:d). It also includes some code taken from AMD:s version of YAMON for this board (with their permission), for enabling cache and doing some preloads before reconfiguring the flash controller to correct values. This precaution may be a good idea on the other boards as well, but since I have not tested it on them, this part is ifdef:d CONFIG_DBAU1550. I have included the "new" version of mkconfig, which now accepts a "$6" specifying endianess. This software is only tested in little endian mode. This patch also contains some minor changes allowing for setting CPU clock frequency in only one place (instead of three) and calculating the correct divisor for the uart based on this. regards / Leif

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[U-Boot-Users] PATCH: add multiple serial support to ppc4xx
by Travis Sawyer 10 Jan '05

10 Jan '05

Greetings: This patch allows the use of both uart0 & uart1 on ppc4xx based systems. Patch was tested on the IBM PPC440GX reference platform (Ocotea) CHANGELOG * Patch by Travis Sawyer, 15 Sep 2004: Add CONFIG_SERIAL_MULTI support for ppc4xx, update README.serial_multi

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[U-Boot-Users] [patch] Wind River sbc405 support
by Dan Poirot 10 Jan '05

10 Jan '05

Howdy, I am pleased to submit this gzipped patch which adds support for the Wind River sbc405 board. The patch was created against the current CVS code set using the command: diff -purN u-boot u-boot_sbc405 > sbc405.patch CHANGELOG Entry : * Patch by Daniel Poirot, 10 Oct 2004: Add support for Wind River sbc405 board. All comments and feedback welcome.

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RE: [U-Boot-Users] u-boot compile problem
by Rainer Brestan (VI/SEA) 10 Jan '05

10 Jan '05

>Hi all, >I've downloaded the latest u-boot-1.1.1 and I'm trying to compile, >but I get this error at the end... any idea? >Toolchain: cross-3.2 (from arm linux) >regards > > > >arm-linux-gcc -g -Os -fno-strict-aliasing -fno-common -ffixed-r8 >-mshort-load-bytes -msoft-float -D__KERNEL__ -DTEXT_BASE=0x33F80000 >-I/root/audiotel/u-boot-1.1.1nand/include -fno-builtin -ffreestanding >-nostdinc -isystem >/usr/local/arm/current/bin/../lib/gcc-lib/arm-linux/3.2/include -pipe >-DCONFIG_ARM -D__ARM__ -mapcs-32 -march=armv4 -Wall -Wstrict-prototypes >-g -Os -fno-strict-aliasing -fno-common -ffixed-r8 >-mshort-load-bytes -msoft-float -D__KERNEL__ -DTEXT_BASE=0x33F80000 >-I/root/audiotel/u-boot-1.1.1nand/include -fno-builtin -ffreestanding >-nostdinc -isystem >/usr/local/arm/current/bin/../lib/gcc-lib/arm-linux/3.2/include -pipe >-DCONFIG_ARM -D__ARM__ -mapcs-32 -march=armv4 -I.. -Bstatic -T >/root/audiotel/u-boot-1.1.1nand/board/smdk2410/u-boot.lds -Ttext >0x33F80000 hello_world.c -o hello_world >/usr/local/arm/current/bin/../lib/gcc-lib/arm-linux/3.2/../../../../arm-linux/bin/ld: >cannot find -lfloat >collect2: ld returned 1 exit status >make[1]: *** [hello_world] Error 1 >make[1]: Leaving directory `/root/audiotel/u-boot-1.1.1nand/examples' >make: *** [examples] Error 2 >[root@tecne184 u-boot-1.1.1nand]# > You run into the same problem i had. It is not a problem with the toolchain, it is due to the fact how the makefile in examples is written. When you first run make without arm-linux-gcc in the path make does a lot, but it created only empty .depend files (because of compiler not found). Afterwards you include arm-linux-gcc in the path and run make again. Everything is running then except the examples directory. Make does not compile hello_world.c, instead it uses a builtin implicit rule to make hello_world (there is no dependency from OBJS and the explicit dependency for hello_world.o is missing, because of empty .depend). When you run make -r (no builtin implicit rules) it works. Work around: make clobber (deletes your wrong .depend) mkconfig ... adding arm-linux-gcc to your path make Hint to Wolfgang: If you add OBJS to the all rule in Makefile for examples, it will work in any case. all: .depend $(LIB) $(OBJS) $(SREC) $(BIN) Rainer

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[U-Boot-Users] New Resend : [patch][cvs] A fix in main.c
by Sam Song 10 Jan '05

10 Jan '05

Hello Thomas, I misused CONFIG_MENUKEY in my test program and found an error but not quite sure. Pls check it. BTW, CONFIG_MENUKEY and CONFIG_MENUCOMMAND is only used in the AmigaOneG3SE board, which you maintaine. I didn't see their info in README. Could you pls explain the usage or even better send a patch in README? Thanks a lot. Sorry, Thomas. I had sent you the 'same' mail two times. I didn't do it on purpose. First patch was broken by mail warper, which couldn't apply. Second was a misoperation. This one could be the correct one, I hope. Sam * Patch by Sam Song, 10 October 2004: - Fix a parameter of run_command in main.c Index: common/main.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/common/main.c,v retrieving revision 1.20 diff -p -u -r1.20 main.c --- common/main.c 23 Apr 2004 20:32:06 -0000 1.20 +++ common/main.c 10 Oct 2004 00:51:18 -0000 @@ -432,7 +432,7 @@ void main_loop (void) s = getenv("menucmd"); if (s) { # ifndef CFG_HUSH_PARSER - run_command (s, bd, 0); + run_command (s, 0); # else parse_string_outer(s, FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP); _________________________________________________________ Do You Yahoo!? 150万曲MP3疯狂搜，带您闯入音乐殿堂 http://music.yisou.com/ 美女明星应有尽有，搜遍美图、艳图和酷图 http://image.yisou.com 1G就是1000兆，雅虎电邮自助扩容！ http://cn.rd.yahoo.com/mail_cn/tag/1g/*http://cn.mail.yahoo.com/event/mail_…

2 1

[U-Boot-Users] [PATCH] NE2000 support
by Christian Pell 09 Jan '05

09 Jan '05

Hi, here is the CHANGELOG entry (more information in the README included in the patch): * Patch by Christian Pellegrin, 24 September 2004: Added support for NE2000 compatible (DP8390, DP83902) NICs. I provide a tarball with new files (just unpack in the U-Boot top directory) and the diff that touches just drivers/Makefile. Any comments welcome! -- Christian Pellegrin <chri(a)ascensit.com>, <c.pellegrin(a)eurotech.it>, <chri(a)infis.univ.ts.it>, <c.pellegrin(a)exadron.com>

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[U-Boot-Users] [U-Boot-Users][PATCH] to add COBRA5272-board-support
by Florian Schlote 09 Jan '05

09 Jan '05

Hi Wolfgang, Please find attached a patch (gzip) that adds (SenTec-)COBRA5272-board-support. The diff is done against the 1.1.1 version. Thanks to Josef Baumgartner for a his good work creating the coldfire support. --- CHANGELOG * Patch by Florian Schlote Added support for SenTec-COBRA5272-board (Coldfire) --- Best regards & thanks for integration, Florian --- mailto: FMWWS(a)gmx.de

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[U-Boot-Users] [PATCH] mpc824x: set PCI latency timer to a sane value.
by gleb＠nbase.co.il 09 Jan '05

09 Jan '05

It is 0 after reset. -- Gleb.

2 1

[U-Boot-Users] [PATCH] Fpga bitstream load support
by Kurt Stremerch 09 Jan '05

09 Jan '05

Hi all. This patch, against current cvs, adds the option loadb to the fpga command. The option allows users to configure a fpga directly with a bitstream stored in memory. Actually, the configuration is still done by fpga_load(), except the necessary bitswapping is applied on the configuration data before calling it. For now, only Xilinx bitstreams are supported. In FPGA_DEBUG mode, the loadb option can print bitstream project details like the design name, part number, date/time and the length of bitstream. Regards Kurt CHANGELOG: * Patch by Kurt Stremerch, 03 September 2004: Add bitstream configuration option for fpga command (Xilinx only).

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[U-Boot-Users] [PATCH] Spartan2E family support
by Kurt Stremerch 09 Jan '05

09 Jan '05

Hi all. This small patch, against current cvs, adds Xilinx Spartan2E support. Only the bitstream size differs from the Spartan2 family but the configuration method stays the same. Regards Kurt CHANGELOG: * Patch by Kurt Stremerch, 03 September 2004: Add Xilinx Spartan2E family fpga support

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[U-Boot-Users] [PATCH]: Support for EP8260 H2 (300MHz)
by Jeff Angielski 09 Jan '05

09 Jan '05

I was going through my records and noticed that I neglected to send in the updated patch for this hardware. The problem with the original patch I submitted was that the SYPCR[BMT] was not being set to 0x6 (48 clocks) as specified in the latest revision of the user manual. Without studying the design in detail, I am not sure why this is the case. However, if the BMT is not set to 0x6, FCC3 will generate TX buffer underrun errors for larger packets when used in Linux. In any event, here is the patch that adds support for this latest H2 version of the EP8260 board from Embedded Planet. CHANGELOG * Patch by Jeff Angielski, 02 Sep 2004 - Added support for H2 revision of the EP8260 board. Fixed the formatting for some of the EP8260 related source files. Jeff Angielski

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[U-Boot-Users] [PATCH] MPC85XX ADS/CDS Fix environment saving
by Jon Loeliger 09 Jan '05

09 Jan '05

Wolfgang, Here is a patch to correct the sizes of the monitor used by the CFI driver to mark sectors for read-only status. With this patch, we can once again save the environment on the MPC85xx ADS and CDS releases. Thanks, jdl * Patch by Jon Loeliger, 02-Sep-2004: Reset monitor size back to 256 so environment can be written to flash on MPC85xx ADS and CDS releases. Index: include/configs/MPC8540ADS.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/configs/MPC8540ADS.h,v retrieving revision 1.1.1.1.4.15 retrieving revision 1.1.1.1.4.16 diff -u -r1.1.1.1.4.15 -r1.1.1.1.4.16 --- include/configs/MPC8540ADS.h 2004/08/18 16:08:50 1.1.1.1.4.15 +++ include/configs/MPC8540ADS.h 2004/08/30 18:48:44 1.1.1.1.4.16 @@ -264,7 +264,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ Index: include/configs/MPC8541CDS.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/configs/Attic/MPC8541CDS.h,v retrieving revision 1.1.2.1 retrieving revision 1.1.2.2 diff -u -r1.1.2.1 -r1.1.2.2 --- include/configs/MPC8541CDS.h 2004/08/20 17:20:17 1.1.2.1 +++ include/configs/MPC8541CDS.h 2004/08/30 18:43:54 1.1.2.2 @@ -254,7 +254,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ Index: include/configs/MPC8555CDS.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/configs/Attic/MPC8555CDS.h,v retrieving revision 1.1.4.22 retrieving revision 1.1.4.23 diff -u -r1.1.4.22 -r1.1.4.23 --- include/configs/MPC8555CDS.h 2004/08/20 17:20:17 1.1.4.22 +++ include/configs/MPC8555CDS.h 2004/08/30 18:43:54 1.1.4.23 @@ -254,7 +254,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ Index: include/configs/MPC8560ADS.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/configs/MPC8560ADS.h,v retrieving revision 1.1.1.1.4.16 retrieving revision 1.1.1.1.4.17 diff -u -r1.1.1.1.4.16 -r1.1.1.1.4.17 --- include/configs/MPC8560ADS.h 2004/08/18 16:08:50 1.1.1.1.4.16 +++ include/configs/MPC8560ADS.h 2004/08/30 18:48:44 1.1.1.1.4.17 @@ -267,7 +267,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */

2 1

[U-Boot-Users] .bss section problem
by Paolo Broggini 09 Jan '05

09 Jan '05

Hi there, I'm working on the port of U-Boot to a new custom board based on the i.MX1 (ARM920T). I noticed that in the start.S the code in which the .bss will be cleared, loops until _bss_start != _bss_end i.e. clear_bss: ldr r0, _bss_start /* find start of bss segment */ add r0, r0, #4 /* start at first byte of bss */ ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l So, when _bss_end is not forced to be .ALIGNED(4) like the _bss_start is, the code may loops till it crashs :-( This is what actually happened in my case. Now to fix the problem on my port I changed my u-boot.lds as: . = ALIGN(4); __bss_start = .; .bss : { *(.bss) } _end = ALIGN(4); and to be consistent I replaced the 'bne clbss_1' with 'ble clbss_1' instruction. I was wondering if I'm missing something on the linker directives or indeed it is small bug. Thanks for your suggestions, -Paolo Broggini

2 1

[U-Boot-Users] Ping issue
by Vidya S 07 Dec '04

07 Dec '04

Hi, I am using smc91111.c driver of u-boot. all my network functionalities are working well. i am able to ping an other ip address and i get a message that the host is alive or not. Only problem is, when someone pings the target ip (my network card ip), it says destination not reachable. Is this really a problem? if so, pls help me solving it. regards vidya

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[U-Boot-Users] [patch][cvs] A fix in main.c
by Sam Song 01 Dec '04

01 Dec '04

Hello Thomas, I misused CONFIG_MENUKEY in my test program and found an error but not quite sure. Pls check it. BTW, CONFIG_MENUKEY and CONFIG_MENUCOMMAND is only used in the AmigaOneG3SE board, which you maintaine. I didn't see their info in README. Could you pls explain the usage or even better send a patch in README? Thanks a lot. * Patch by Sam Song, 10 October 2004: - Fix a parameter of run_command in main.c Index: common/main.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/common/main.c,v retrieving revision 1.20 diff -p -u -r1.20 main.c --- common/main.c 23 Apr 2004 20:32:06 -0000 1.20 +++ common/main.c 10 Oct 2004 00:51:18 -0000 @@ -432,7 +432,7 @@ void main_loop (void) s = getenv("menucmd"); if (s) { # ifndef CFG_HUSH_PARSER - run_command (s, bd, 0); + run_command (s, 0); # else parse_string_outer(s, FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP); ===== Best regards, Sam _________________________________________________________ Do You Yahoo!? 150万曲MP3疯狂搜，带您闯入音乐殿堂 http://music.yisou.com/ 美女明星应有尽有，搜遍美图、艳图和酷图 http://image.yisou.com 1G就是1000兆，雅虎电邮自助扩容！ http://cn.rd.yahoo.com/mail_cn/tag/1g/*http://cn.mail.yahoo.com/event/mail_…

2 2

RE: [U-Boot-Users] CFI driver
by York Sun 29 Nov '04

29 Nov '04

Here is the patch. Regards, York --- u-boot-pq3-base/drivers/cfi_flash.c 2004-08-06 13:08:19.000000000 -0500 +++ u-boot-pq3-for-release/drivers/cfi_flash.c 2004-10-27 16:02:34.028749216 -0500 @@ -10,6 +10,11 @@ * Ed Okerson * Modified to work with little-endian systems. * + * Copyright (C) 2004 + * York Sun + * Modified to support 8-bit port and 32-bit chip, not verified + * Modified to support polling DQ7 and DQ6 for AMD flash + * * See file CREDITS for list of people who contributed to this * project. * @@ -33,16 +38,29 @@ * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay) * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud) * 01/27/2004 - Little endian support Ed Okerson + * 10/26/2004 - Revised to support polling DQ7 and DQ6 for AMD flash + * and to support 8-bit port width on 8-bit chip + * and 32/64-bit port width on 32-bit chip (not verified) by York Sun + * According to AMD technical support: It is a good practice + * to the use exact where data is being written to when using + * "DQ6" method, even though in theory you don't have to. * * Tested Architectures * Port Width Chip Width # of banks Flash Chip Board * 32 16 1 28F128J3 seranoa/eagle * 64 16 1 28F128J3 seranoa/falcon + * 16 16 2 AM29LV641DH MPC8555CDS rev 1.0 + * 16 16 2 AM29LV641MH MPC8555CDS rev 1.0 * */ /* The DEBUG define must be before common to enable debugging */ -/* #define DEBUG */ +/* #define DEBUG */ + +#define POLLING_AMD_DQ6 +#ifndef POLLING_AMD_DQ6 +#define POLLING_AMD_DQ7 /* To use polling DQ7 instead of DQ6 for AMD algorithm */ +#endif #include <common.h> #include <asm/processor.h> @@ -105,6 +123,10 @@ #define AMD_CMD_UNLOCK_START 0xAA #define AMD_CMD_UNLOCK_ACK 0x55 +#define AMD_DQ7 0x80 +#define AMD_DQ5 0x20 +#define AMD_STATUS_TIMEOUT 0x20 + #define AMD_STATUS_TOGGLE 0x40 #define AMD_STATUS_ERROR 0x20 #define AMD_ADDR_ERASE_START 0x555 @@ -174,14 +196,14 @@ static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); -static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); -static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); -static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static int flash_isequal (flash_info_t * info, cfiptr_t cptr, uchar cmd); +static int flash_isset (flash_info_t * info, cfiptr_t cptr, uchar cmd); +static int flash_toggle (flash_info_t * info, cfiptr_t cptr, uchar cmd); static int flash_detect_cfi (flash_info_t * info); static ulong flash_get_size (ulong base, int banknum); static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); -static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, - ulong tout, char *prompt); +static int Data_Polling_Check(flash_info_t * info, cfiptr_t cptr, cfiword_t cword); +static int flash_full_status_check (flash_info_t * info, cfiptr_t cptr, cfiword_t cword, ulong tout, char *prompt); #ifdef CFG_FLASH_USE_BUFFER_WRITE static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len); #endif @@ -189,9 +211,21 @@ /*---------------------------------------------------------------------- - * create an address based on the offset and the port width */ +static const uint offset_multiply[9][5]={ /* chip width = 0 (dummy), 1 (8-bit), 2 (16-bit), 3 (dummy), 4(32-bit) */ + {0,0,0,0,0}, /* dummy */ + {0,2,0,0,0}, /* port width = 1 (8-bit) */ + {0,4,2,0,0}, /* port width = 2 (16-bit) */ + {0,0,0,0,0}, /* dummy */ + {0,8,4,0,4}, /* port width = 4 (32-bit) */ + {0,0,0,0,0}, /* 5, dummy */ + {0,0,0,0,0}, /* 6, dummy */ + {0,0,0,0,0}, /* 7, dummy */ + {0,16,8,0,8}, /* port width = 8 (64-bit) */ + }; + inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset) { - return ((uchar *) (info->start[sect] + (offset * info->portwidth))); + return ((uchar *) (info->start[sect] + (offset * offset_multiply[info->portwidth][info->chipwidth]))); } #ifdef DEBUG @@ -347,8 +381,12 @@ { int rcode = 0; int prot; + cfiword_t cword; + cfiptr_t cptr; flash_sect_t sect; + cword.c = 0xff; + if (info->flash_id != FLASH_MAN_CFI) { puts ("Can't erase unknown flash type - aborted\n"); return 1; @@ -393,11 +431,11 @@ info->vendor); break; } - - if (flash_full_status_check - (info, sect, info->erase_blk_tout, "erase")) { + cptr.cp = flash_make_addr(info,sect,0); + if (flash_full_status_check(info,cptr,cword, info->erase_blk_tout,"erase") ) { rcode = 1; - } else + } + else putc ('.'); } } @@ -416,8 +454,43 @@ return; } - printf ("CFI conformant FLASH (%d x %d)", + printf ("CFI compatible FLASH (%d port width with %d chip width)\n", (info->portwidth << 3), (info->chipwidth << 3)); + printf ("Command set is "); + switch (info->vendor) { + case CFI_CMDSET_INTEL_EXTENDED: + printf ("Intel/Sharp extended\n"); + break; + case CFI_CMDSET_AMD_STANDARD: + printf ("AMD/Fujitsu standard. "); +#ifdef POLLING_AMD_DQ7 + printf ("Driver is polling DQ7 for status checking.\n"); +#else + printf ("Driver is polling DQ6 for status checking.\n"); +#endif + break; + case CFI_CMDSET_INTEL_STANDARD: + printf ("Intel/Sharp standard\n"); + break; + case CFI_CMDSET_AMD_EXTENDED: + printf ("AMD/Fujitsu extended\n"); +#ifdef POLLING_AMD_DQ7 + printf ("Driver is polling DQ7 for status checking.\n"); +#else + printf ("Driver is polling DQ6 for status checking.\n"); +#endif + break; + case CFI_CMDSET_MITSU_STANDARD: + printf ("Mitsubishi standard\n"); + break; + case CFI_CMDSET_MITSU_EXTENDED: + printf ("Mitsubishi extendend\n"); + break; + default: + printf ("Not defined\n"); + break; + } + printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", @@ -482,6 +555,9 @@ int aln; cfiword_t cword; int i, rc; + ulong temp,count; + + count = cnt; #ifdef CFG_FLASH_USE_BUFFER_WRITE int buffered_size; @@ -522,6 +598,8 @@ cnt -= i; } #else + temp = 0; + printf("\n"); while (cnt >= info->portwidth) { cword.l = 0; for (i = 0; i < info->portwidth; i++) { @@ -531,6 +609,10 @@ return rc; wp += info->portwidth; cnt -= info->portwidth; + if (((count-cnt)>>10)>temp) { + temp=(count-cnt)>>10; + printf("\r%d KB",temp); + } } #endif /* CFG_FLASH_USE_BUFFER_WRITE */ if (cnt == 0) { @@ -568,7 +650,7 @@ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); if ((retcode = - flash_full_status_check (info, sector, info->erase_blk_tout, + flash_full_status_check (info, sector, 0,0,info->erase_blk_tout, prot ? "protect" : "unprotect")) == 0) { info->protect[sector] = prot; @@ -621,18 +703,22 @@ * flash_is_busy - check to see if the flash is busy * This routine checks the status of the chip and returns true if the chip is busy */ -static int flash_is_busy (flash_info_t * info, flash_sect_t sect) +static int flash_is_busy (flash_info_t * info, cfiptr_t cptr, cfiword_t cword) { int retval; switch (info->vendor) { case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: - retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); + retval = !flash_isset (info, cptr, FLASH_STATUS_DONE); break; case CFI_CMDSET_AMD_STANDARD: case CFI_CMDSET_AMD_EXTENDED: - retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); +#ifdef POLLING_AMD_DQ7 + retval = Data_Polling_Check (info, cptr, cword); /* data polling for D7 */ +#else + retval = flash_toggle (info, cptr, AMD_STATUS_TOGGLE); +#endif break; default: retval = 0; @@ -641,24 +727,109 @@ return retval; } + +/* ---------------------------------------------------------------------- + * Polling DQ5 for AMD flash + * Edited by York Sun (yorksun(a)freescale.com) + */ +static int flash_time_out (flash_info_t * info, cfiptr_t cptr, cfiword_t cword) +{ + int retval; + + switch (info->vendor) { + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + retval = flash_isset (info, cptr, AMD_STATUS_TIMEOUT); + break; + default: + retval = 0; + } + debug ("flash_time_out: %d\n", retval); + return retval; +} + +/* ---------------------------------------------------------------------- + * Polling DQ7 for AMD flash + * Edited by York Sun (yorksun(a)freescale.com) + */ +static int Data_Polling_Check(flash_info_t * info, cfiptr_t cptr, cfiword_t cword) +{ + uchar read_data=0,polling_data=0; + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + polling_data= cword.c; + break; + case FLASH_CFI_16BIT: + polling_data=(uchar) (cword.w & 0xff); + break; + case FLASH_CFI_32BIT: + polling_data=(uchar) (cword.l & 0xff); + break; + case FLASH_CFI_64BIT: + polling_data=(uchar) (cword.ll & 0xff); + break; + default: + printf("Error in function %s\n",__FUNCTION__); + } + do { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + read_data = cptr.cp[0]; + break; + case FLASH_CFI_16BIT: + read_data = (uchar) (cptr.wp[0] & 0xff); + break; + case FLASH_CFI_32BIT: + read_data = (uchar) (cptr.lp[0] & 0xff); + break; + case FLASH_CFI_64BIT: + read_data = (uchar) (cptr.llp[0] & 0xff); + break; + } + if ((read_data & AMD_DQ7) == (polling_data & AMD_DQ7)) + break; + } while ((read_data & AMD_DQ5) != (uchar) AMD_DQ5); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + read_data = cptr.cp[0]; + break; + case FLASH_CFI_16BIT: + read_data = (uchar) (cptr.wp[0] & 0xff); + break; + case FLASH_CFI_32BIT: + read_data = (uchar) (cptr.lp[0] & 0xff); + break; + case FLASH_CFI_64BIT: + read_data = (uchar) (cptr.llp[0] & 0xff); + break; + } + if ((read_data & AMD_DQ7) != (polling_data & AMD_DQ7)) + return ERR_TIMOUT; + else + return ERR_OK; +} + /*---------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. * This routine does not set the flash to read-array mode. + * get_timer does not always work. Polling DQ5 can get the time out info for AMD flash. */ -static int flash_status_check (flash_info_t * info, flash_sect_t sector, - ulong tout, char *prompt) +static int flash_status_check (flash_info_t * info, cfiptr_t cptr, cfiword_t cword, ulong tout, char *prompt) { - ulong start; + ulong start,now; /* Wait for command completion */ - start = get_timer (0); - while (flash_is_busy (info, sector)) { - if (get_timer (start) > info->erase_blk_tout * CFG_HZ) { - printf ("Flash %s timeout at address %lx data %lx\n", - prompt, info->start[sector], - flash_read_long (info, sector, 0)); - flash_write_cmd (info, sector, 0, info->cmd_reset); - return ERR_TIMOUT; + start = get_timer (0); + while (flash_is_busy (info, cptr,cword)) { + if ((flash_time_out(info,cptr,cword)) || \ + ((now=get_timer (start)) > info->erase_blk_tout * CFG_HZ)) { + if (flash_is_busy (info, cptr,cword)) { + printf ("Flash %s timeout at address %lx data %lx\n",\ + prompt, (ulong)cptr.cp,cword.l); + flash_write_cmd (info, 0, 0, info->cmd_reset); + return ERR_TIMOUT; + } } } return ERR_OK; @@ -668,36 +839,34 @@ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. * This routine sets the flash to read-array mode. */ -static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, - ulong tout, char *prompt) +static int flash_full_status_check (flash_info_t * info, cfiptr_t cptr, cfiword_t cword, ulong tout, char *prompt) { int retcode; - retcode = flash_status_check (info, sector, tout, prompt); + retcode = flash_status_check (info, cptr, cword, tout, prompt); switch (info->vendor) { case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: if ((retcode != ERR_OK) - && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { + && !flash_isequal (info, cptr, FLASH_STATUS_DONE)) { retcode = ERR_INVAL; - printf ("Flash %s error at address %lx\n", prompt, - info->start[sector]); - if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { + printf ("Flash %s error at address %lx\n", prompt,(ulong)cptr.cp); + if (flash_isset (info, cptr, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { puts ("Command Sequence Error.\n"); - } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) { + } else if (flash_isset (info, cptr, FLASH_STATUS_ECLBS)) { puts ("Block Erase Error.\n"); retcode = ERR_NOT_ERASED; - } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) { + } else if (flash_isset (info, cptr, FLASH_STATUS_PSLBS)) { puts ("Locking Error\n"); } - if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { + if (flash_isset (info, cptr, FLASH_STATUS_DPS)) { puts ("Block locked.\n"); retcode = ERR_PROTECTED; } - if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) + if (flash_isset (info, cptr, FLASH_STATUS_VPENS)) puts ("Vpp Low Error.\n"); } - flash_write_cmd (info, sector, 0, FLASH_CMD_RESET); + flash_write_cmd (info, 0,0, FLASH_CMD_RESET); break; default: break; @@ -762,9 +931,16 @@ uint stmpi; #endif uchar *cp = (uchar *) cmdbuf; - - for (i = 0; i < info->portwidth; i++) - *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd; + if (info->chipwidth < FLASH_CFI_BY32) { + for (i = 0; i < info->portwidth; i++) + *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd; + } + else { + ushort *ccp= (ushort *) cmdbuf; + ushort cmd_16= cmd + cmd * 256; + for (i = 0; i< info->portwidth; i=i+2) + *ccp++= ((i + 2) % info->chipwidth) ? '\0' :cmd_16; + } #if defined(__LITTLE_ENDIAN) switch (info->portwidth) { case FLASH_CFI_8BIT: @@ -797,20 +973,18 @@ flash_make_cmd (info, cmd, &cword); switch (info->portwidth) { case FLASH_CFI_8BIT: - debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd, - cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + debug ("fwc issues cmd %x to addr %p with %x,\nassuming flash port width 8bit, chip width %d bit\n",\ + cmd, addr.cp, cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); *addr.cp = cword.c; break; case FLASH_CFI_16BIT: - debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp, - cmd, cword.w, - info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + debug ("fwc issues cmd %x to addr %p with %4.4x,\nassuming flash port width 16bit, chip width %d bit\n",\ + cmd, addr.wp, cword.w, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); *addr.wp = cword.w; break; case FLASH_CFI_32BIT: - debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp, - cmd, cword.l, - info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + debug ("fwc issues cmd %x to addr %p with %8.8lx,\nassuming flash port width 32bit, chip width %d bit\n",\ + cmd, addr.lp, cword.l, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); *addr.lp = cword.l; break; case FLASH_CFI_64BIT: @@ -820,9 +994,8 @@ print_longlong (str, cword.ll); - debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", - addr.llp, cmd, str, - info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + debug ("fwrite issues cmd %x to addr %p with %s,\nassuming flash port width 64 bit, chip width %d bit\n",\ + cmd, addr.llp, str, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); } #endif *addr.llp = cword.ll; @@ -838,27 +1011,25 @@ /*---------------------------------------------------------------------- - */ -static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +static int flash_isequal (flash_info_t * info, cfiptr_t cptr, uchar cmd) { - cfiptr_t cptr; cfiword_t cword; int retval; - cptr.cp = flash_make_addr (info, sect, offset); flash_make_cmd (info, cmd, &cword); - debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp); + debug ("expecting net value is %x(%c) at addr %p,\n", cmd, cmd, cptr.cp); switch (info->portwidth) { case FLASH_CFI_8BIT: - debug ("is= %x %x\n", cptr.cp[0], cword.c); + debug ("expected read value %x, actual read %x\n", cword.c,cptr.cp[0]); retval = (cptr.cp[0] == cword.c); break; case FLASH_CFI_16BIT: - debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w); + debug ("expected read value %4.4x, actual read %4.4x\n", cword.w,cptr.wp[0]); retval = (cptr.wp[0] == cword.w); break; case FLASH_CFI_32BIT: - debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l); + debug ("expected read value %8.8lx, actual read %8.8lx\n", cword.l,cptr.lp[0]); retval = (cptr.lp[0] == cword.l); break; case FLASH_CFI_64BIT: @@ -869,7 +1040,7 @@ print_longlong (str1, cptr.llp[0]); print_longlong (str2, cword.ll); - debug ("is= %s %s\n", str1, str2); + debug ("expected read vaule is %s, actual read %s\n", str2, str1); } #endif retval = (cptr.llp[0] == cword.ll); @@ -883,13 +1054,11 @@ /*---------------------------------------------------------------------- - */ -static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +static int flash_isset (flash_info_t * info, cfiptr_t cptr, uchar cmd) { - cfiptr_t cptr; cfiword_t cword; int retval; - cptr.cp = flash_make_addr (info, sect, offset); flash_make_cmd (info, cmd, &cword); switch (info->portwidth) { case FLASH_CFI_8BIT: @@ -913,13 +1082,11 @@ /*---------------------------------------------------------------------- - */ -static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +static int flash_toggle (flash_info_t * info, cfiptr_t cptr, uchar cmd) { - cfiptr_t cptr; cfiword_t cword; int retval; - cptr.cp = flash_make_addr (info, sect, offset); flash_make_cmd (info, cmd, &cword); switch (info->portwidth) { case FLASH_CFI_8BIT: @@ -949,6 +1116,7 @@ */ static int flash_detect_cfi (flash_info_t * info) { + cfiptr_t cptr1,cptr2,cptr3; debug ("flash detect cfi\n"); for (info->portwidth = FLASH_CFI_8BIT; @@ -956,11 +1124,14 @@ for (info->chipwidth = FLASH_CFI_BY8; info->chipwidth <= info->portwidth; info->chipwidth <<= 1) { + cptr1.cp = flash_make_addr(info,0,FLASH_OFFSET_CFI_RESP); + cptr2.cp = flash_make_addr(info,0,FLASH_OFFSET_CFI_RESP + 1); + cptr3.cp = flash_make_addr(info,0,FLASH_OFFSET_CFI_RESP + 2); flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { + if (flash_isequal (info, cptr1,'Q') + && flash_isequal (info, cptr2, 'R') + && flash_isequal (info, cptr3, 'Y')) { info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE); debug ("device interface is %d\n", info->interface); @@ -992,6 +1163,7 @@ uchar num_erase_regions; int erase_region_size; int erase_region_count; + cfiptr_t cptr; info->start[0] = base; @@ -1044,10 +1216,9 @@ for (j = 0; j < erase_region_count; j++) { info->start[sect_cnt] = sector; sector += (erase_region_size * size_ratio); + cptr.cp = flash_make_addr(info,sect_cnt,FLASH_OFFSET_PROTECT); info->protect[sect_cnt] = - flash_isset (info, sect_cnt, - FLASH_OFFSET_PROTECT, - FLASH_STATUS_PROTECT); + flash_isset (info, cptr,FLASH_STATUS_PROTECT); sect_cnt++; } } @@ -1081,7 +1252,7 @@ cfiptr_t ctladdr; cfiptr_t cptr; - int flag; + int flag,retcode; ctladdr.cp = flash_make_addr (info, 0, 0); cptr.cp = (uchar *) dest; @@ -1142,7 +1313,8 @@ if (flag) enable_interrupts (); - return flash_full_status_check (info, 0, info->write_tout, "write"); + retcode = flash_full_status_check (info, cptr, cword, info->write_tout, "write"); + return flag; } #ifdef CFG_FLASH_USE_BUFFER_WRITE @@ -1181,7 +1353,7 @@ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); if ((retcode = - flash_status_check (info, sector, info->buffer_write_tout, + flash_status_check (info, sector, 0,0,info->buffer_write_tout, "write to buffer")) == ERR_OK) { /* reduce the number of loops by the width of the port */ switch (info->portwidth) { @@ -1224,7 +1396,7 @@ flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); retcode = - flash_full_status_check (info, sector, + flash_full_status_check (info, sector,0,0, info->buffer_write_tout, "buffer write"); }

4 4

[U-Boot-Users] Re: Problem building U-boot for RpxLite with Mpc823e
by Sam Song 28 Nov '04

28 Nov '04

Ccool <ccool(a)ninjatech.biz> wrote: > I was talking about Readme file : > "doc/README.RPXlite" file. I thought that > the section 1 might be obsolete. With the > documentation of my RPXlite, I > have'nt found any VisionClick flash programmer. A little hint: Pls make sure your board configuration. There are two type of RPXlite. One is CW,another DW. If it's CW,then RPXlite is what's your want.Or pls refer to RPXlite_DW board in u-boot cvs.There is another README in board/RPXlite_dw/ directory.I guess your target could be DW board because RPXlite CW was a old version board of EP. As for how to debug or program U-Boot with a flash programmer,just as Wolfgang said,read DULG. > I also tried the u-boot.srec, just in case the > S-record image would run=20 > better, but it did'nt. I guess that's why I'm > looking for someone who coul= > d=20 > give me a few hints about how to run u-boot. =20 There are some detailed points for a newbie to run u-boot.A good way is to list your process in details and consecution and some of us would see what's the wrong in that and give you a timely help. Good Luck! Sam _________________________________________________________ Do You Yahoo!? 150万曲MP3疯狂搜，带您闯入音乐殿堂 http://music.yisou.com/ 美女明星应有尽有，搜遍美图、艳图和酷图 http://image.yisou.com 1G就是1000兆，雅虎电邮自助扩容！ http://cn.rd.yahoo.com/mail_cn/tag/1g/*http://cn.mail.yahoo.com/event/mail_…

4 7

[U-Boot-Users] PATCH: Introducing CONFIG_BOARD_PRE_RESET
by Steven Scholz 23 Nov '04

23 Nov '04

Hi there, as mentioned on list before some boards/cpus might need some extra code to be executed _before_ rebooting. E.g. the i.MX hangs when doing "reset" while the LCD controller is still enabled. That is why I'd like to introduce CONFIG_BOARD_PRE_RESET and board_pre_reset(). The attached does exactly that. But only for cpu/arm920t. If wished I'll add the appropriate code to all cpu/$(CPU)/cpu.c files. * Patch by Steven Scholz, 25 Oct 2004: - Introducing CONFIG_BOARD_PRE_RESET and board_pre_reset() to allow code to be executed before actually rebooting -- Steven Scholz Index: board/mx1fs2/mx1fs2.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/board/mx1fs2/mx1fs2.c,v retrieving revision 1.2 diff -p -u -r1.2 mx1fs2.c --- board/mx1fs2/mx1fs2.c 10 Oct 2004 18:41:10 -0000 1.2 +++ board/mx1fs2/mx1fs2.c 25 Oct 2004 13:32:14 -0000 @@ -123,3 +123,14 @@ show_boot_progress(int status) #endif return; } + +#ifdef CONFIG_BOARD_PRE_RESET +void board_pre_reset(void) +{ + /* we must disable the LCD controller before reboot + * otherwise the processor might hang */ + DR(3) &= ~0x00001000; + LCDC_RMCR &= ~RMCR_LCDC_EN; +} +#endif + Index: cpu/arm920t/cpu.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/cpu.c,v retrieving revision 1.3 diff -p -u -r1.3 cpu.c --- cpu/arm920t/cpu.c 8 Feb 2004 19:38:43 -0000 1.3 +++ cpu/arm920t/cpu.c 25 Oct 2004 13:32:14 -0000 @@ -127,6 +127,9 @@ int do_reset (cmd_tbl_t *cmdtp, int flag { extern void reset_cpu (ulong addr); disable_interrupts (); +#ifdef CONFIG_BOARD_PRE_RESET + board_pre_reset(); +#endif reset_cpu (0); /*NOTREACHED*/ Index: include/common.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/common.h,v retrieving revision 1.46 diff -p -u -r1.46 common.h --- include/common.h 10 Oct 2004 18:41:14 -0000 1.46 +++ include/common.h 25 Oct 2004 13:32:15 -0000 @@ -318,6 +318,7 @@ int board_late_init (void); int board_postclk_init (void); /* after clocks/timebase, before env/serial */ int board_early_init_r (void); void board_poweroff (void); +void board_pre_reset (void); #if defined(CFG_DRAM_TEST) int testdram(void); Index: include/configs/mx1fs2.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/configs/mx1fs2.h,v retrieving revision 1.1 diff -p -u -r1.1 mx1fs2.h --- include/configs/mx1fs2.h 1 Aug 2004 22:48:22 -0000 1.1 +++ include/configs/mx1fs2.h 25 Oct 2004 13:32:15 -0000 @@ -114,6 +114,7 @@ #define AUTOREFRESH_CMD 0xa10a8300 #define CONFIG_INIT_CRITICAL +#define CONFIG_BOARD_PRE_RESET 1 #define BUS32BIT_VERSION /*

3 12

[U-Boot-Users] Bug in cpu/arm920t/imx/speed.c
by Steven Scholz 23 Nov '04

23 Nov '04

Hi there, there are two bugs in cpu/arm920t/imx/speed.c preventing us from determine the correct speed of the processor. CHANGELOG: * Patch by Steven Scholz, 22 Oct 2004: - Fix masking bug in cpu/arm920t/imx/speed.c -- Steven Scholz imc Measurement & Control Index: u-boot.SoC/cpu/arm920t/imx/speed.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/cpu/arm920t/imx/speed.c,v retrieving revision 1.1 diff -u -r1.1 speed.c --- u-boot.SoC/cpu/arm920t/imx/speed.c 9 Oct 2004 22:21:30 -0000 1.1 +++ u-boot.SoC/cpu/arm920t/imx/speed.c 22 Oct 2004 06:59:53 -0000 @@ -41,9 +41,9 @@ { /* FIXME: We assume System_SEL = 0 here */ u32 spctl0 = SPCTL0; + u32 mfn = (spctl0 >> 0) & 0x3ff; u32 mfi = (spctl0 >> 10) & 0xf; - u32 mfn = spctl0 & 0x3f; - u32 mfd = (spctl0 >> 16) & 0x3f; + u32 mfd = (spctl0 >> 16) & 0x3ff; u32 pd = (spctl0 >> 26) & 0xf; mfi = mfi<=5 ? 5 : mfi; @@ -55,9 +55,9 @@ { /* FIXME: We assume System_SEL = 0 here */ u32 mpctl0 = MPCTL0; + u32 mfn = (mpctl0 >> 0) & 0x3ff; u32 mfi = (mpctl0 >> 10) & 0xf; - u32 mfn = mpctl0 & 0x3f; - u32 mfd = (mpctl0 >> 16) & 0x3f; + u32 mfd = (mpctl0 >> 16) & 0x3ff; u32 pd = (mpctl0 >> 26) & 0xf; mfi = mfi<=5 ? 5 : mfi; @@ -74,7 +74,6 @@ ulong get_HCLK(void) { u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; - printf("bclkdiv: %d\n", bclkdiv); return get_systemPLLCLK() / bclkdiv; }

1 1

[U-Boot-Users] u-boot initialize PCI in ixdp425 platform ?
by Annamalai Prakash 04 Nov '04

04 Nov '04

Hi all , I m using u-boot 1.1.1 bootloader on my ixdp425. Everything is working fine.. i have connected miniPCI card in my board. I want know whether u-boot initialize PCI or not ?. coz in include/asm/arch/ixdp425.h, i seen the following lines. #if 0 #ifndef __ASSEMBLY__ extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data); extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data); extern void ixp425_pci_init(void *); #endif #endif My kernel doesnt identify that card also. #define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ The above line refers the PCI speed ?. Please clear my doubts ?.. Thanks Prakash

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[U-Boot-Users] Another DHCP/BOOTP problem? (Was: "Re: U-Boot DHCP request does n ot time out." and "[PATCH] fix dhcp command retry")
by Larsson Roger 02 Nov '04

02 Nov '04

(resent - I can't find it on archieve) Hi, I see a similar problem to the one described in "Re: U-Boot DHCP request does not time out." with U-Boot 1.1.1.1 But I have not seen any patch from Pantelis. The only related message is "[PATCH] fix dhcp command retry" from Roger Blofeld Does that patch fix the problem? In my case I think the counter restarts at 1 but the reboot BOOTP does not work. If I interrupt (CTRL-C) and issue a 'reset' the BOOTP broad cast after reset works. How to reproduce: * Power on -> BOOTP boot into Linux * In Linux issue 'reboot' command * Warm booted U-BOOT runs into this problem. - - - * U-BOOT CTRL-C and 'reset' -> BOOTP boot into Linux /RogerL >From: Pantelis Antoniou <panto@in...> > Re: U-Boot DHCP request does not time out. > >2004-08-30 23:49 Wolfgang Denk wrote: >> In message <31ADFA827355984B9E2A161514595B561C33A9@lp...> you wrote: >> >>>OMAP1510 Innovator # dhcp >>>Using MAC Address 00:0B:36:00:03:FB >>>BOOTP broadcast 1 >>>BOOTP broadcast 2 >>>BOOTP broadcast 3 >>>BOOTP broadcast 4 >>>BOOTP broadcast 5 >>> >>>Retry count exceeded; starting again >>>BOOTP broadcast 6 >>>... >>>Retry count exceeded; starting again >>>BOOTP broadcast 13 >>>... >> >> >> I see. Same here. Something is really broken. >> >> Best regards, >> >> Wolfgang Denk >> > > I"ve had the same problems. > > Please bear it till I send a patch that fixes that > and a number of other issues in DHCP. > > Next week perhaps since I"m swamped right now. > > Regards > > Pantelis ########################################### This message has been scanned by F-Secure Anti-Virus for Microsoft Exchange. For more information, connect to http://www.F-Secure.com/

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[U-Boot-Users] Hello world application running problem
by Jhavk 01 Nov '04

01 Nov '04

> I have read README.standalone. My target board is > smdk2440(Arm 9). > > So i transfer hello_world using tftp to address > 0x0c100000 and then call "go 0x0c100000 hello world" > > But after that the application seems to get stuck > and > nothing happens. Eventually i have to reset the > board. > > I have some doubts: > 1. Which file should i send. I think it should be > hello_world and not the srec or bin format. I ran > file > command on all 3 and found that hello_world is the > one meant for ARM. > > 2.Is the load and start address correct? May be its > different for ARM9? > > If all these are correct then what may be the > problem? > > > > > > > __________________________________ > Do you Yahoo!? > Take Yahoo! Mail with you! Get it on your mobile > phone. > http://mobile.yahoo.com/maildemo > __________________________________ Do you Yahoo!? Yahoo! Mail Address AutoComplete - You start. We finish. http://promotions.yahoo.com/new_mail

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[U-Boot-Users] hello world application
by Jhavk 31 Oct '04

31 Oct '04

I want to make gzipped hello_world application and later execute it using bootm command. I figured that mkimage is the utility for making compressed STANDALONE image. But it needs an option mkimage -d <datafile> Now what is this datafile? Is it hello_world or hello_world.bin or hello_world.srec I tried all 3, but they give different sizes of gzipped image. So i am confused. My target architecture is ARM. Thanks. __________________________________ Do you Yahoo!? Yahoo! Mail Address AutoComplete - You start. We finish. http://promotions.yahoo.com/new_mail

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[U-Boot-Users] Loading U-Boot SREC file
by Devraj Mukherjee 31 Oct '04

31 Oct '04

Hi everyone, Thanks to everyone who responded to my email. I managed to get a version of UBoot compiled for our target board and have ended up with an SREC file. The boot loader that already exists on the board allows me to load the SREC file via TFTP, and I have succeeded doing that. I am still unsure if we should go ahead burn the image and restart the board to see UBoot come up. If there is anyone out there using a LH7A400 based board then please let me know if I should look out for anything else. Any other suggestions are very welcome. Regards, Devraj -- ---------------------------------------------------------------------- Devraj Mukherjee, Eternity Technologies Pty. Ltd. Australia Host: Debian (Sarge) 3.1 Kernel 2.4.27-1-686 / GCC version 3.3.5 Target: LPD7A400 (ARM9) LogicPD eval. board / ARM GCC 3.3 GlibC 2.3.2 ----------------------------------------------------------------------

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[U-Boot-Users] Re: [ARMboot-users] Asking the concept for a newbie
by Wolfgang Denk 31 Oct '04

31 Oct '04

In message <4183729E.40196727(a)ms10.hinet.net> you wrote: > > I'm a newbie in this field, and deal with an ARM946E based borad. Note that ARMBoot is a dead project; deveoplment continues in the environment of the U-Boot project; followup set to the u-boot-users mailing list. > In my guess, there should have armboot, bzImage, & romfs in the flash. No. bzImage does not work. You will have to use the "mkimage" tool to build a special U-Boot / ARMBoot image. > How are they arranged by address in the flash memory? U-Boot must be locatewd such that it gets started when the CPU comes out of reset. On ARM this usually means that you will have to put it in flash such that it starts at physical address 0x0000. For the other images you can chose which addresses you want - it makes sense to align the images with the sectors of your flash memory, though. > Thanks for any information You are welcome. Best regards, Wolfgang Denk -- See us @ Embedded/Electronica Munich, Nov 09 - 12, Hall A.6 Booth 513 Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Lady Nancy Astor: "Winston, if you were my husband, I'd put poison in your coffee." Winston Churchill: "Nancy, if you were my wife, I'd drink it."

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[U-Boot-Users] Re: emulate u-boot in gdb
by Detlev Zundel 30 Oct '04

30 Oct '04

Hi Luc, > I am looking into SkyEye and busy in creating an extension for > potentially ipaq (cheap finished hardware to play with for embedded > software/ui development). > > How can I debug a boot loader such as u-boot in a emulator/simulator > environment ? Good question. I have only thought for a short while about this question, but I think in such an environment, you need only small pieces of U-Boot. Of course you don't have real hardware to setup in a debugger (so I guess, but I have never used one) things like setting up a memory controller etc. will probably not work without emulating all of the hardware of a "real system" - and I guess this is simply not possible to have emulators for all hardware components. So what you would need for such an environment would be U-Boot stripped from all the hardware inits which is probably a major surgery on the sources. Try asking on the U-Boot mailing list (I cc'ed the list) as there are _very probably_ more competent people in this field. > Is it possible to debug u-boot in a arm-linux-gdb environment ? If I > assign this to memory 0x000000 and put 'set $pc =0' should that work > ? ... it didn't when I tried It is of course possible to debug U-Boot on ARM systems - we did ports for some ARM based boards - but again putting U-Boot at address 0 is a much bigger question. What board config did you use? What address does this image think it runs from? And what address was U-Boot linked for? You have to load the U-Boot image there - but again I think the U-Boot hardware inits will cause you grief. > I searched the web but could not find any good result. Can give me > some direction ? I hope I did ;) Cheers Detlev -- ;; Self-replicator in ELisp ((lambda (l) (prin1-to-string (list l (list (quote quote) l)))) (quote (lambda (l) (prin1-to-string (list l (list (quote quote) l))))))

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[U-Boot-Users] Re: u-boot error message
by Detlev Zundel 30 Oct '04

30 Oct '04

Hi Bruce, > Hello Detlev Zundel , > > > I used u-boot-1.1.1 to boot linux.My target board is ALTERA DK1C20 and cpu > is nios.I used tools/mkimage to encapsulate a linux kernel image with > header information.But it display some error messages,it like that: First off - I am not the best person to answer these questions, as I have never used a NIOS system. So please try to get help on the mailing list that I cc'ed my last reply to. Someone there should be able to have better answers to your questions. One more thing though - from your description I am not sure what version of U-Boot you are using and whether you were able _at all_ to boot Linux on your system. The error messages below strongly leave me to not believe this. > Index: tools/mkimage.c > > =================================================================== > > RCS file: /cvsroot/u-boot/u-boot/tools/mkimage.c,v > > retrieving revision 1.13 > > diff -p -u -r1.13 mkimage.c > > --- tools/mkimage.c 10 Jul 2004 22:36:01 -0000 1.13 > > +++ tools/mkimage.c 29 Oct 2004 00:01:12 -0000 > > @@ -86,6 +86,8 @@ table_entry_t arch_name[] = { > > { IH_CPU_MICROBLAZE, "microblaze", "MicroBlaze", }, > > { IH_CPU_MIPS, "mips", "MIPS", }, > > { IH_CPU_MIPS64, "mips64", "MIPS 64 Bit", }, > > + { IH_CPU_NIOS, "nios", "NIOS", }, > > { IH_CPU_PPC, "ppc", "PowerPC", }, > > { IH_CPU_S390, "s390", "IBM S390", }, > > { IH_CPU_SH, "sh", "SuperH", }, Why did you remove the other line from my patch? Obviously this is the patch I suggested and the second line was in there because I have seen that there is still another CPU type not implemented yet in mkimage so one should try to fix this in one go. It does _not make sense_ to throw out such things after the work it has taken to put them in. > When I boot linux image to my target board, it have error messages. > > Like that: > > > > DK1C20 > imi 200000 > > > > ## Checking Image at 00200000 ... > > Image Name: linux kernel > > Image Type: Unknown Architecture Linux Kernel Image (uncompressed) > > Data Size: 1015552 Bytes = 991.8 kB > > Load Address: 01010000 > > Entry Point: 01010000 > > Verifying Checksum ... OK > As you know from studying cmd_bootm.c the imi command _does not_ check the compression type. The image type shows uncompressed so mkimage should have put a 0 in the compression type field. > DK1C20 > bootm 200000 > > ## Booting image at 00200000 ... > > Image Name: linux kernel > > Image Type: Unknown Architecture Linux Kernel Image (uncompressed) > > Data Size: 1015552 Bytes = 991.8 kB > > Load Address: 01010000 > > Entry Point: 01010000 > > Verifying Checksum ... OK > > Unimplemented compression type 39 > > DK1C20 > Yep, there are compression type 0, 1 and 2 but nothing else. According to what I wrote above the compression field is boguos. Of course you noticed reading the source for mkimage that it should have put a 0 in it and now theres a 39 in there. It looks like the image is corrupt for whatever reason - try using the debugger and a hexdump program to find out at what stage this goes wrong. And of course use U-Boot from CVS and _not_ U-Boot 1.1.1 Cheers Detlev PS: Mail f'up-to set _again_ to u-boot-users(a)lists.sourceforge.net. You know of course from the netiquette, that it is considered rude behaviour to ignore such hints repeatedly, don't you? -- (define Y (lambda (f) ((lambda (g) (f (lambda (x) ((g g) x)))) (lambda (g) (f (lambda (x) ((g g) x)))))))

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[U-Boot-Users] McAfee GroupShield Alert
by groupshield＠eucorp.westell.com 30 Oct '04

30 Oct '04

McAfee GroupShield Alert McAfee GroupShield discovered a problem with the following email. See your system administrator for further information. Date/Time sent: 30 Oct 2004 05:19:27 Subject line: U-Boot-Users digest, Vol 1 #1065 - 2 msgs From: u-boot-users-admin(a)lists.sourceforge.net To: u-boot-users(a)lists.sourceforge.net Action taken: Replaced Virus found: W32/Bagle!eml.gen Quarantined item: Filename: Ticket number: 11fc-4183-164f-0002 Copyright © 1993-2003, Networks Associates Technology, Inc. All Rights Reserved. http://www.mcafeesecurity.com <http://www.mcafeesecurity.com/>

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[U-Boot-Users] Delivery Status Notification (Failure)
by postmaster＠doubleclick.net 30 Oct '04

30 Oct '04

This is an automatically generated Delivery Status Notification. Delivery to the following recipients failed. 179-1(a)flonetwork.com

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