July 2003 - U-Boot

[U-Boot-Users] Re: JFFS2: CRC Problem with Kernel Image
by Martin, Vitali 25 Jul '03

25 Jul '03

> So what address are you loading to 1000 10000 or 100000 Sorry that I wasn't attentive im my last email. The memory address is always 0x100000. And data written by "tftpboot" and "fsload" to 0x100000 is not the same. There are differences from address 0x00101000, so I get Linux CRC Error running "iminfo" or "bootm". tftp = 00101000: dfc958e0 5f66d603 e27f2fe3 0027f536 fsload = 00101000: dfc9c970 de53a432 188d2417 af469b2b

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[U-Boot-Users] MPC8xxADS PLPRCR buglet
by Nye Liu 25 Jul '03

25 Jul '03

I have found a problem with the way the MPC8xxADS support deals with PLPRCR; it seems to be off by a factor of 2 in various places. If you see strange results when playing with FACT in MPC8xxADS.h, don't be suprised. Currently, from what i can tell, the CPU is running 2x as fast as what the boot prints out to the console, i.e. a FACT of 5 will print 50MHz, but the cpu is actually running at 100MHz. I will post futher patches and information after I figure out what went wrong. -- Nye Liu nliu(a)mrv.com (818) 772-6235x248 "Who would be stupid enough to quote a fictitious character?" -- Don Quixote

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Re: [U-Boot-Users] Patch: Support for Motorola PQ2FADS-ZU board
by Rick Bronson 24 Jul '03

24 Jul '03

Hi Yuli, I have a PQ2FADS-ZU board with a 8270 and am having trouble getting the ethernet working. I was wondering if you were able to get yours functional. When I do: tftp 0x0 host/memtest.bin it shows: => tftp 0x0 host/memtest.bin TFTP from server 10.186.20.95; our IP address is 10.186.20.99 Filename 'host/memtest.bin'. Load address: 0x0 Loading: T T T T ... Everytime the T occurs the collision light comes on on my 10 Mbit-only hub. I commented out the 1st line of: miiphy_write(0, 16, 0x610); miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); because bit 0x400 on register 16 on the Davicom 9161 part doesn't exist but it had no effect. One idea I have is that the speed (baud) is wrong but I couldn't find anywhere to set it in the docs. Any ideas/help are greatly appreciated. Rick Bronson

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RE: [U-Boot-Users] ECC code used in cmd_nand.c
by Woodruff, Richard 24 Jul '03

24 Jul '03

.. Shouldn't the noecc check be doing a if(start != round_down(start,0x200)) and a check for less than size 0x200? This should ensure that the address is at the proper boundary....does your board have sram/dram at 0. rkw > -----Original Message----- > From: Woodruff, Richard > Sent: Wednesday, July 23, 2003 5:59 PM > To: 'dge(a)sixnetio.com' > Cc: u-boot-users(a)lists.sourceforge.net > Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c > > > I'm thinking part of the problem I was having was my command > is bring up a > bug: > nand write 10008000 0 200 > > This will result in nand_rw calling nand_write_ecc with > an eccbuf = NULL, as the size and alignment check does not > work for the first block (noecc = (start!=start... ). > Nand_rw passes this to nand_write_ecc which passes it onto > nand_write page. Which then acts like its valid and starts > trying to read and write to address 0. As I have ROM there > what ends up going into the oob is my rom's first instruction. > > I've feeling a bit slow at the moment, and am wondering if > the rounding to see if we are starting on an aligned address > is even correct. > > As far as R/B goes, I have two types of systems, one has it > and the other doesn't. I've inserted code which seems to > allow things to work without a R/B connected...mainly using > the status read to wait till not busy followed by a read to > check for success or failure. The only real pain with out > having a RB and doing this all with GPIOs is my ARM does not > have anything which allows the equivalent of a ppc "sync" > instruction, so dependencies on the memory controller's > scheduling creep up. > > Regards/Thanks, > > Richard W. > > > > > -----Original Message----- > > From: Dave Ellis [mailto:dge@sixnetio.com] > > Sent: Wednesday, July 23, 2003 1:38 PM > > To: Woodruff, Richard > > Cc: u-boot-users(a)lists.sourceforge.net > > Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c > > > > > > Richard Woodruff wrote: > > > Can anyone verify that the write using "nand write aaaa > offf ssss" > > > should work with ECC enabled? I'm finding that if I > disable the ECC > > > generation I can write uImages and compare them and get what I > > > expect and boot from them. > > > > It has been working fine for me using the SXNI855T > > configuration. I built this morning's CVS version and it also > > seems OK. > > > > > If I enable ECC generation, on read it complains that > they are all > > > wrong (but there is no errors on the write which I think > it should > > > give if the written ecc does not match the calculated one). If I > > > disregard the ecc warnings and then "cmp" the data starting which > > > was loaded, the first 16k are indeed the same (16k is my block > > > size), however, there is some differences at the end of the first > > > block. Again, if I disable ECC no such problem. > > > > If you write if with ECC, but read it back without ECC is the > > data still corrupted? The data may be OK until the bad ECC > > data is used to 'correct' it. > > > > > ...If I do a read.oob of the first block, it appears that the > > > data_buf[0] is written to the first position of the oob, > instead of > > > the expected data. > > > > Are you sure NanD_WaitReady() is working? If it isn't, you > > could start to read the oob data before it is ready, and > > would see some old data from the start of the buffer. > > > > Dave > > > > Dave Ellis > > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > SIXNET - "Leading the Industrial Ethernet Revolution" > > 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA > > Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 > > Email me at: dge(a)sixnetio.com > > Detailed product info: www.sixnetio.com > > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > > > > > > ------------------------------------------------------- > This SF.Net email sponsored by: Free pre-built ASP.NET sites > including Data Reports, E-commerce, Portals, and Forums are > available now. Download today and enter to win an XBOX or > Visual Studio .NET. > http://aspnet.click-url.com/go/psa00100003ave/direct;at.aspnet _072303_01/01 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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RE: [U-Boot-Users] RE: Nand OOB layout, u-boot and the kernel sou rces do not agree.. ??
by Woodruff, Richard 24 Jul '03

24 Jul '03

The u-boot from CVS 4.4 has CONFIG_MTD_NAND_ECC_JFFS commented out by default. This results in NAND_NOOB_ECCPOS5 being defined for ECC. The header file sets defines this as position 5....right below the badblock pos is set position 5. An ECC value will be written to the bad block spot when calculated...turn on JFFS2 and this problem goes away...however, something is fishy in the bad_block and position 5 resolution code for some reason. The codes addressing doesn't look like whats in the kernel tree. At some point I'll submit a patch, but if someone else does it first that's just fine. Richard W. > -----Original Message----- > From: Dave Ellis [mailto:dge@sixnetio.com] > Sent: Thursday, July 24, 2003 2:00 PM > To: Woodruff, Richard > Cc: u-boot-users(a)lists.sourceforge.net > Subject: RE: [U-Boot-Users] RE: Nand OOB layout, u-boot and > the kernel sources do not agree.. ?? > > > Richard Woodruff wrote: > > Sent: Thursday, July 24, 2003 1:57 PM > > > -----Original Message----- > > > From: Woodruff, Richard > > > Sent: Thursday, July 24, 2003 12:45 PM > > > While trying to resolve what the OOB data layout should be I > > > see that the kernel headers as of 8-10-2002 have changed such > > > that both the NAND_JFFS2 and NAND_NOOB use position 5 for bad > > > block data. The u-boot headers do not reflect this > > > change...doesn't this mean u-boot will be incompatible with > > > more recent kernels? Should u-boot's headers be updated here? > > Position 5 is where the chip makers mark bad sectors, so we > do not get a choice. The NAND_NOOB values in U-BOOT are wrong > and should be changed to match the new ones in the Linux > kernel. I think the original cmd_nand.c was based on a very > old version of MTD. > > > ... Having more up to date definitions would seem better....as > > raw nand doesn't seem to be well supported except with jffs2 & > > possibly yaffs I don't suppose the NAND_NOOB is such a concern. > > I don't know what software (if any) uses NAND_NOOB, but I > think the definitions still should be fixed (or removed). In > my patch to cmd_nand.c I hard coded the bad block position at > 5, so they can't be used as they are. > > Dave > > Dave Ellis > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > SIXNET - "Leading the Industrial Ethernet Revolution" > 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA > Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 > Email me at: dge(a)sixnetio.com > Detailed product info: www.sixnetio.com > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > >

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[U-Boot-Users] RE: Nand OOB layout, u-boot and the kernel sources do not agree.. ??
by Woodruff, Richard 24 Jul '03

24 Jul '03

Looking about infradead.org tells that the OOB area can be reconfigured via ioctl. I suppose that this is something which would be needed prior to mount. Having more up to date definitions would seem better....as raw nand doesn't seem to be well supported except with jffs2 & possibly yaffs I don't suppose the NAND_NOOB is such a concern. Richard W. -----Original Message----- From: Woodruff, Richard Sent: Thursday, July 24, 2003 12:45 PM To: u-boot-users(a)lists.sourceforge.net Subject: Nand OOB layout, u-boot and the kernel sources do not agree..?? Hello, While trying to resolve what the OOB data layout should be I see that the kernel headers as of 8-10-2002 have changed such that both the NAND_JFFS2 and NAND_NOOB use position 5 for bad block data. The u-boot headers do not reflect this change...doesn't this mean u-boot will be incompatible with more recent kernels? Should u-boot's headers be updated here? Regards, Richard W.

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[U-Boot-Users] Nand OOB layout, u-boot and the kernel sources do not agree..??
by Woodruff, Richard 24 Jul '03

24 Jul '03

Hello, While trying to resolve what the OOB data layout should be I see that the kernel headers as of 8-10-2002 have changed such that both the NAND_JFFS2 and NAND_NOOB use position 5 for bad block data. The u-boot headers do not reflect this change...doesn't this mean u-boot will be incompatible with more recent kernels? Should u-boot's headers be updated here? Regards, Richard W.

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[U-Boot-Users] More on serial terminal and u-boot
by Brian S. Park 24 Jul '03

24 Jul '03

Hi all, I've been trouble shooting the problem of u-Boot not coming up when serial terminal is not connected. It turned out that when software CONFIG_SERIAL_SOFTWARE_FIFO is defined, putc will wait till terminal is ready to receive the data. From u-boot/cpu/ppc4xx/serial.c, line 676 void serial_buffered_putc (const char c) { /* Wait for CTS */ #if defined(CONFIG_HW_WATCHDOG) while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) WATCHDOG_RESET (); #else while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); #endif serial_putc (c); } Is the while loop necessary? printf's are ok because it uses serial_buffered_puts which eventually calls serial_putc with out waiting for CTS. Thank you Brian =============================================================== Brian S. Park brian(a)corelis.com (562) 926-6727 x143 --------------------------------------------------------------- Everything we do helps our customers get to market FASTER with HIGHER quality and LOWER cost ===============================================================

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[U-Boot-Users] Nios Port
by Scott McNutt 24 Jul '03

24 Jul '03

Is anyone working on a Nios port? If yes, please let me know how I can help. Otherwise, I started a Nios port myself and I welcome anyone interested in contributing. Regards, --Scott

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[U-Boot-Users] [PATCH] jffs2 indirect access.
by Kenneth Johansson 24 Jul '03

24 Jul '03

This is a patch that alters the jffs2 code to work on flash devices that is not directly memory mapped without the need to copy the whole flash to RAM. It is not ready for inclusion and I do not think I will push it as it was quite a bit slower than I expected. It also needs a little more cleanup. A callback function is added to struct part_info that works like memcpy and is the thing actually reading the flash. The offset member is gone and the jffs2 code always uses 0 as the start address for the filesystem. It is up to the callback function to remap that into something useful. This code however uses less memory than copying the flash to ram but it is slower. jffs2_scan_empty() could use some speedup but even in situations when that one is not taking mush time this is slower by a factor of 2-3. It's only faster if you happens to have ridiculously slow flash. I'm going on vacation and is not going to work more on this so if someone wants this added to u-boot you have to fix a proper patch yourself. -- Kenneth Johansson Ericsson AB Tel: +46 8 719 70 20 Tellusborgsvägen 90 Fax: +46 8 719 29 45 126 25 Stockholm ken(a)switchboard.ericsson.se

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[U-Boot-Users] Re: JFFS2: CRC Problem with Kernel Image
by Martin, Vitali 24 Jul '03

24 Jul '03

> How did the pImage file get to /dev/mtdblock1 in the first place? bash-2.05# eraseall /dev/mtd1 bash-2.05# mount -t jffs2 /dev/mtdblock1 /mnt/ bash-2.05# cp /pImage /mnt/ > We had a problem a while back where using scp to copy an image ... I'm using "cp" from the linux console, so I think there is no interrupt problem. Because I can copy pImage to JFFS2 filesystem and my image is still OK. I checked the memory with "md 100000" in U-Boot and there seems to be not the same data on the memory address 0x100 when I using "tftp 1000 pImage" and "fsload 10000 pImage". From address 0x101000 the data im the RAM memory is different??? ->tftp 10000 pImage TFTP from server 172.22.20.193; our IP address is 172.22.10.33 Filename 'pImage'. Load address: 0x10000 Loading: T ###################T #TX timeout done Bytes transferred = 520149 (7efd5 hex) ->md 100000 200000 00100000: 27051956 52c9c624 3f1d4bb5 0007ef95 '..VR..$?.K..... 00100010: 00000000 00000000 5171b599 05070201 ........Qq...... 00100020: 4c696e75 782d322e 342e3400 00000000 Linux-2.4.4..... ... 00101000: dfc958e0 5f66d603 e27f2fe3 0027f536 ..X._f..../..'.6 00101010: c055f99e f5e16e85 bd761595 a9ce7bd2 .U....n..v....{. ->fsload 100000 pImage ### JFFS2 loading 'pImage' to 0x100000 ### JFFS2 load complete: 520149 bytes loaded to 0x100000 ->md 100000 200000 00100000: 27051956 52c9c624 3f1d4bb5 0007ef95 '..VR..$?.K..... 00100010: 00000000 00000000 5171b599 05070201 ........Qq...... 00100020: 4c696e75 782d322e 342e3400 00000000 Linux-2.4.4..... ... 00101000: dfc9c970 de53a432 188d2417 af469b2b ...p.S.2..$..F.+ 00101010: 7dd3d9cf e1df4c64 65acdb75 83efc98b }.....Lde..u....

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[U-Boot-Users] Serial terminal & u-Boot
by Brian S. Park 24 Jul '03

24 Jul '03

Hi all, I'm using u-Boot 0.4.0 with our custom board based on IBM walnut. I noticed that if I do not have the HyperTerminal running, the boot process never proceeds. If I power up the target with out HyperTerminal running, it never comes up. As soon as start HyperTerminal, I see print out for Kernel download and the board boots up. It looks as though it was waiting for the serial communication before it starts downloading the kernel over the ethernet. Is this normal behavior? Is there a way to make it boot up regardless of whether a serial terminal is connected or not? Thank you Brian =============================================================== Brian S. Park brian(a)corelis.com (562) 926-6727 x143 --------------------------------------------------------------- Everything we do helps our customers get to market FASTER with HIGHER quality and LOWER cost ===============================================================

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[U-Boot-Users] cmd_nand.c :: check_block, wrong bad block pos ?
by Woodruff, Richard 24 Jul '03

24 Jul '03

Hello, Well I just got nand and ECC to work on my little endian ARM board. By using the following corrected round nand_rw zero deferences were stopped: noecc = (start != ROUND_DOWN(start, 0x200)) || (len < 0x200) ; And, I'm not quite sure what why, perhaps endianess, the read_oob in check block was returning byte 6 from the oob instead of 5. By changing it to ask for (badpos + 1) it started returning the correct byte. I'll need to check into this one a bit more. Does anyone know why badpos by itself is not enough? After I test a little I can post a patch back for others to test against. Regards, Richard W. -----Original Message----- From: Woodruff, Richard Sent: Wednesday, July 23, 2003 6:23 PM To: 'dge(a)sixnetio.com' Cc: u-boot-users(a)lists.sourceforge.net Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c .. Shouldn't the noecc check be doing a if(start != round_down(start,0x200)) and a check for less than size 0x200? This should ensure that the address is at the proper boundary....does your board have sram/dram at 0. rkw > -----Original Message----- > From: Woodruff, Richard > Sent: Wednesday, July 23, 2003 5:59 PM > To: 'dge(a)sixnetio.com' > Cc: u-boot-users(a)lists.sourceforge.net > Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c > > > I'm thinking part of the problem I was having was my command > is bring up a > bug: > nand write 10008000 0 200 > > This will result in nand_rw calling nand_write_ecc with > an eccbuf = NULL, as the size and alignment check does not > work for the first block (noecc = (start!=start... ). > Nand_rw passes this to nand_write_ecc which passes it onto > nand_write page. Which then acts like its valid and starts > trying to read and write to address 0. As I have ROM there > what ends up going into the oob is my rom's first instruction. > > I've feeling a bit slow at the moment, and am wondering if > the rounding to see if we are starting on an aligned address > is even correct. > > As far as R/B goes, I have two types of systems, one has it > and the other doesn't. I've inserted code which seems to > allow things to work without a R/B connected...mainly using > the status read to wait till not busy followed by a read to > check for success or failure. The only real pain with out > having a RB and doing this all with GPIOs is my ARM does not > have anything which allows the equivalent of a ppc "sync" > instruction, so dependencies on the memory controller's > scheduling creep up. > > Regards/Thanks, > > Richard W. > > > > > -----Original Message----- > > From: Dave Ellis [mailto:dge@sixnetio.com] > > Sent: Wednesday, July 23, 2003 1:38 PM > > To: Woodruff, Richard > > Cc: u-boot-users(a)lists.sourceforge.net > > Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c > > > > > > Richard Woodruff wrote: > > > Can anyone verify that the write using "nand write aaaa > offf ssss" > > > should work with ECC enabled? I'm finding that if I > disable the ECC > > > generation I can write uImages and compare them and get what I > > > expect and boot from them. > > > > It has been working fine for me using the SXNI855T > > configuration. I built this morning's CVS version and it also > > seems OK. > > > > > If I enable ECC generation, on read it complains that > they are all > > > wrong (but there is no errors on the write which I think > it should > > > give if the written ecc does not match the calculated one). If I > > > disregard the ecc warnings and then "cmp" the data starting which > > > was loaded, the first 16k are indeed the same (16k is my block > > > size), however, there is some differences at the end of the first > > > block. Again, if I disable ECC no such problem. > > > > If you write if with ECC, but read it back without ECC is the > > data still corrupted? The data may be OK until the bad ECC > > data is used to 'correct' it. > > > > > ...If I do a read.oob of the first block, it appears that the > > > data_buf[0] is written to the first position of the oob, > instead of > > > the expected data. > > > > Are you sure NanD_WaitReady() is working? If it isn't, you > > could start to read the oob data before it is ready, and > > would see some old data from the start of the buffer. > > > > Dave > > > > Dave Ellis > > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > SIXNET - "Leading the Industrial Ethernet Revolution" > > 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA > > Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 > > Email me at: dge(a)sixnetio.com > > Detailed product info: www.sixnetio.com > > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > > > > > > ------------------------------------------------------- > This SF.Net email sponsored by: Free pre-built ASP.NET sites > including Data Reports, E-commerce, Portals, and Forums are > available now. Download today and enter to win an XBOX or > Visual Studio .NET. > http://aspnet.click-url.com/go/psa00100003ave/direct;at.aspnet _072303_01/01 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users ------------------------------------------------------- This SF.Net email sponsored by: Free pre-built ASP.NET sites including Data Reports, E-commerce, Portals, and Forums are available now. Download today and enter to win an XBOX or Visual Studio .NET. http://aspnet.click-url.com/go/psa00100003ave/direct;at.aspnet_072303_01/01 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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RE: [U-Boot-Users] ECC code used in cmd_nand.c
by Woodruff, Richard 24 Jul '03

24 Jul '03

I'm thinking part of the problem I was having was my command is bring up a bug: nand write 10008000 0 200 This will result in nand_rw calling nand_write_ecc with an eccbuf = NULL, as the size and alignment check does not work for the first block (noecc = (start!=start... ). Nand_rw passes this to nand_write_ecc which passes it onto nand_write page. Which then acts like its valid and starts trying to read and write to address 0. As I have ROM there what ends up going into the oob is my rom's first instruction. I've feeling a bit slow at the moment, and am wondering if the rounding to see if we are starting on an aligned address is even correct. As far as R/B goes, I have two types of systems, one has it and the other doesn't. I've inserted code which seems to allow things to work without a R/B connected...mainly using the status read to wait till not busy followed by a read to check for success or failure. The only real pain with out having a RB and doing this all with GPIOs is my ARM does not have anything which allows the equivalent of a ppc "sync" instruction, so dependencies on the memory controller's scheduling creep up. Regards/Thanks, Richard W. > -----Original Message----- > From: Dave Ellis [mailto:dge@sixnetio.com] > Sent: Wednesday, July 23, 2003 1:38 PM > To: Woodruff, Richard > Cc: u-boot-users(a)lists.sourceforge.net > Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c > > > Richard Woodruff wrote: > > Can anyone verify that the write using "nand write aaaa offf > > ssss" should work with ECC enabled? I'm finding that if I > > disable the ECC generation I can write uImages and compare > > them and get what I expect and boot from them. > > It has been working fine for me using the SXNI855T > configuration. I built this morning's CVS version and it also > seems OK. > > > If I enable ECC generation, on read it complains that they > > are all wrong (but there is no errors on the write which I > > think it should give if the written ecc does not match the > > calculated one). If I disregard the ecc warnings and then > > "cmp" the data starting which was loaded, the first 16k are > > indeed the same (16k is my block size), however, there is > > some differences at the end of the first block. Again, if I > > disable ECC no such problem. > > If you write if with ECC, but read it back without ECC is the > data still corrupted? The data may be OK until the bad ECC > data is used to 'correct' it. > > > ...If I do a read.oob of the first block, it appears that the > > data_buf[0] is written to the first position of the oob, > > instead of the expected data. > > Are you sure NanD_WaitReady() is working? If it isn't, you > could start to read the oob data before it is ready, and > would see some old data from the start of the buffer. > > Dave > > Dave Ellis > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > SIXNET - "Leading the Industrial Ethernet Revolution" > 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA > Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 > Email me at: dge(a)sixnetio.com > Detailed product info: www.sixnetio.com > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > >

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[U-Boot-Users] ECC code used in cmd_nand.c
by Woodruff, Richard 23 Jul '03

23 Jul '03

Hello, Can anyone verify that the write using "nand write aaaa offf ssss" should work with ECC enabled? I'm finding that if I disable the ECC generation I can write uImages and compare them and get what I expect and boot from them. If I enable ECC generation, on read it complains that they are all wrong (but there is no errors on the write which I think it should give if the written ecc does not match the calculated one). If I disregard the ecc warnings and then "cmp" the data starting which was loaded, the first 16k are indeed the same (16k is my block size), however, there is some differences at the end of the first block. Again, if I disable ECC no such problem. ...If I do a read.oob of the first block, it appears that the data_buf[0] is written to the first position of the oob, instead of the expected data. Regards/Thanks for any info, Richard W.

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[U-Boot-Users] RE: u-boot on Memec P4/7-FG456 (w/ virtex II pro)?
by Shamile Khan 23 Jul '03

23 Jul '03

Hi Frank, We are trying to port u-boot to Memec P4/7-FG456 as well. What did you have to do to get the serial port working. Also did you get it to work with uart lite that ships with EDK or the full uart that has to be purchased separately. Thanks, Shamile

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[U-Boot-Users] Re: JFFS2: CRC Problem with Kernel Image
by Martin, Vitali 22 Jul '03

22 Jul '03

> Which version of U-Boot is this? 0.4.1 > Are you sure the image is still OK? My target mounts root filesystem over NFS. So running on my host system "mkimage -l /mnt/pImage" works: Target: bash-2.05# mount -t jffs2 /dev/mtdblock1 /mnt/ bash-2.05# cd /mnt/ bash-2.05# ll total 514 -rw-r--r-- 1 root root 525815 Jul 22 13:31 pImage bash-2.05# cp pImage /pImage Host: vm@pc241:/nfs/eldk/ppc_8xx> mkimage -l pImage Image Name: Linux-2.4.4 Created: Tue Jul 22 15:28:19 2003 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 525751 Bytes = 513.43 kB = 0.50 MB Load Address: 0x00000000 Entry Point: 0x00000000 With the same image "tftpboot" works fine. ->tftp 100000 pImage TFTP from server 172.22.20.193; our IP address is 172.22.10.33 Filename 'pImage'. Load address: 0x100000 Loading: T ################################## done Bytes transferred = 525815 (805f7 hex) ->imi ## Checking Image at 00100000 ... Image Name: Linux-2.4.4 Created: 2003-07-22 13:28:19 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 525751 Bytes = 513.4 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK -> So I am sure that my image file is OK, I suppose something goes wrong in "fsload", when pImage will copied to memory.

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RE: [U-Boot-Users] MPC8260/66: SDRAM init
by Rune Torgersen 22 Jul '03

22 Jul '03

Hi The reason this works on the MPC826xADS boards is that this is only necessary to do when the 60x bus is in 60x mode. When the bus is in "Single PowerQUICC II bus mode" (BCR register bit 0 (EBM) = 0), the value driven on the bus when writing to ramaddr after the mode set command, comes from the PSDMR register. All the 826xADS boards defaults to single 8260 mode bus. (no external cache and multiplexers) > -----Original Message----- > From: Holger Speck [mailto:hospe@gmx.de] > Sent: Tuesday, July 22, 2003 03:46 > To: u-boot-users(a)lists.sourceforge.net > Subject: [U-Boot-Users] MPC8260/66: SDRAM init > > > Hello, > > I had some problems with the initialisation of SDRAM (64MB) > on 60x bus. Below the code I changed according to MPC8260 UM/D: > > memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */ > /* see 11.4.9 SDRAM MODE-SET Command Timming MPC8260 UM/D > 05/2003, REV 1 */ > /* send mode (CAS latency as in PSDMR and burst length for > 16- or 64-bit > ports) to SDRAM > */ > ramaddr = (uchar *) (CFG_SDRAM_BASE | (((cas_latency << 4) | > 0x2) << 3)); *ramaddr = c; > > The original code does not set "ramaddr" to the mode value. I > tested this new code on special board derived from the > MPC8260ADS. I'm a litte bit astonished that the original code > works on the MPC8260ADS. > > Grettings, > Holger > > > > > ------------------------------------------------------- > This SF.net email is sponsored by: VM Ware > With VMware you can run multiple operating systems on a > single machine. WITHOUT REBOOTING! Mix Linux / Windows / > Novell virtual machines at the same time. Free trial click > here: http://www.vmware.com/wl/offer/345/0 > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users >

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AW: [U-Boot-Users] tftp server for Windows
by Martin, Vitali 22 Jul '03

22 Jul '03

I succefully used "SolarWinds.Net TFTP Server".

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[U-Boot-Users] JFFS2: CRC Problem with Kernel Image
by Martin, Vitali 22 Jul '03

22 Jul '03

Hi all, I have an PowerPC board running U-Boot and Linux. So I created an JFFS2 filesystem on one of my static MTD partitions an put the Kernel Image into. bash-2.05# eraseall /dev/mtd1 Erased 4096 Kibyte @ 0 -- 100% complete. bash-2.05# mount -t jffs2 /dev/mtdblock1 /mnt/ bash-2.05# cp /pImage /mnt/ bash-2.05# cd /mnt/ bash-2.05# ls -l total 527 -rw-r--r-- 1 root root 539419 Jul 22 11:36 pImage bash-2.05# cd .. bash-2.05# umount /mnt/ Then I reboot my board and U-Boot starts. I copy the Kernel Image to the memory with "fsload". But running "iminfo" or "bootm" I get a CRC Error. Some ideas what's wrong? (Thank you for any help.) ->ls Scanning JFFS2 FS: . done. -rw-r--r-- 539419 Tue Jul 22 15:42:25 2003 pImage ->fsload 100000 pImage ### JFFS2 loading 'pImage' to 0x100000 ### JFFS2 load complete: 539419 bytes loaded to 0x100000 ->iminfo 100000 ## Checking Image at 00100000 ... Image Name: Linux-2.4.4 Created: 2003-07-21 14:53:03 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 539355 Bytes = 526.7 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... Bad Data CRC ->

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Re: [U-Boot-Users] Debugging u-boot with BDI2000
by Wolfgang Denk 22 Jul '03

22 Jul '03

Dear Jürgen, in message <200307211005.32005.jbeisert(a)eurodsn.de> you wrote: > > My code does some modifications in chipset registers. One of it seems the bad > one and the cpu hangs when executing it. While I can't trace it, I have now > disabled the modifications step by step and find the bad one (OPBA0_CR). > > Does anybody knows something about the registers OPBA0_CR and OPBA0_PR > (OPB Arbiter control and priority)? After reset it's contents shows illegal > bit values (if I try to interpret the value after reset based on my 405GP > manual). And which CPU model is on your board? Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de "Most people would like to be delivered from temptation but would like it to keep in touch." - Robert Orben

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[U-Boot-Users] MPC8260/66: SDRAM init
by Holger Speck 22 Jul '03

22 Jul '03

Hello, I had some problems with the initialisation of SDRAM (64MB) on 60x bus. Below the code I changed according to MPC8260 UM/D: memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */ /* see 11.4.9 SDRAM MODE-SET Command Timming MPC8260 UM/D 05/2003, REV 1 */ /* send mode (CAS latency as in PSDMR and burst length for 16- or 64-bit ports) to SDRAM */ ramaddr = (uchar *) (CFG_SDRAM_BASE | (((cas_latency << 4) | 0x2) << 3)); *ramaddr = c; The original code does not set "ramaddr" to the mode value. I tested this new code on special board derived from the MPC8260ADS. I'm a litte bit astonished that the original code works on the MPC8260ADS. Grettings, Holger

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RE: [U-Boot-Users] tftp server for Windows
by Scott McNutt 21 Jul '03

21 Jul '03

Rune, I have been using TFTPD32 without any problems in a Windows 2000 environment: http://tftpd32.jounin.net Regards, --Scott > -----Original Message----- > From: Rune Raknerud [SMTP:rune.raknerud@cargoscan.com] > Sent: Monday, July 21, 2003 4:44 AM > To: U-Boot (E-mail) > Cc: Wolgang Denk (E-mail) > Subject: [U-Boot-Users] tftp server for Windows > > Hi > > I need to setup a tftp server on a Windows machine, and I tried to use > tftpsrv that is provided by Abatron. This works fine with my BDI2000, > but not with my custom MPC8245 board running u-boot. Both the BDI2000 > and the MPC8245 board work fine when connected to a tftp server on a > RedHat 7.3 machine. > > I use the following command for starting tftpsrv: tftpsrv w p > dc:\tftpboot\ > > The following is a screen capture of the console output from the MPC8245 > board. 172.23.151.225 is a PC running RedHat 7.3 and 172.23.151.232 is > a PC running Windows 2000 Prof and tftpserv from Abatron. I have enabled > debug output from u-boot. > > =>setenv serverip 172.23.151.225 > =>tftp 100000 8245.cfg > ARP broadcast 1 > Receive from protocol 0x806 > Got ARP > Got ARP REPLY, set server/gtwy eth addr > Got good ARP - start TFTP > > Server ethernet address 00:01:02:99:91:26 > TFTP from server 172.23.151.225; our IP address is 172.23.151.236 > Filename '8245.cfg'. > Load address: 0x100000 > Loading: *Receive from protocol 0x800 > Got IP > len=544, v=45 > #Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > #Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=347, v=45 > > done > Bytes transferred = 7483 (1d3b hex) > => reset > > U-Boot 0.2.0 (Jul 18 2003 - 09:10:38) > > CPU: MPC8245 Revision 1.2 at 299.999 MHz: 16 kB I-Cache 16 kB D-Cache > Board: Cargoscan CS0045 CPU/RF PowerPC MPC8245 > I2C: ready > DRAM: 64 MB > Altera 1k10 ,,,,,,,,,,,,,,,,,,, > Altera 1k50 > ........................................................................ > ......................... > FPGA: ready on 1 atempt. > FLASH: 8 MB > In: serial > Out: serial > Err: serial > Net: i82559#0, i82559#1 > IDE: Bus 0: OK > Device 0: Model: SanDisk SDCFB-64 Firm: vde 1.10 Ser#: 20312131908 > Type: Removable Hard Disk > Capacity: 61.2 MB = 0.0 GB (125440 x 512) > => printenv baudrate=38400 > serial#=AO031245612346 > filesize=9fdf1 > sereverip=172.23.151.231 > serverip=172.23.151.232 > ipaddr=172.23.151.236 > bootargs=console=ttyS0,38400 root=/dev/nfs rw > nfsroot=/home/filesystems/mvl30 > ip=172.23.151.233:172.23.151.232:172.23.151.40:255.255.255.0:io:eth0 > ide0=0xfe0001f0,0xfe0003f6,19 > stdin=serial > stdout=serial > stderr=serial > > Environment size: 342/131068 bytes > => tftp 100000 8245.cfg > ARP broadcast 1 > Receive from protocol 0x806 > Got ARP > Got ARP REPLY, set server/gtwy eth addr > Got good ARP - start TFTP > > Server ethernet address 00:08:74:3b:61:58 > TFTP from server 172.23.151.232; our IP address is 172.23.151.236 > Filename '8245.cfg'. > Load address: 0x100000 > Loading: *Receive from protocol 0x800 > Got IP > len=56, v=45 > Receive from protocol 0x800 > Got IP > len=128, v=45 > T Receive from protocol 0x800 > Got IP > len=56, v=45 > Receive from protocol 0x806 > Got ARP > T Receive from protocol 0x800 > Got IP > len=56, v=45 > Receive from protocol 0x8137 > Receive from protocol 0x806 > Got ARP > > Abort > => > > From the u-boot output, it looks like the packet lengths is to short. > > Have any of you got the Abatron tftpsrv to work with u-boot. If yes, how > did you do it? If no, do you know of any other tftp servers that run > under Windows and work with u-boot? > > Best regards > Rune Raknerud > Cargoscan AS > > > ------------------------------------------------------- > This SF.net email is sponsored by: VM Ware > With VMware you can run multiple operating systems on a single machine. > WITHOUT REBOOTING! Mix Linux / Windows / Novell virtual machines at the > same time. Free trial click here: http://www.vmware.com/wl/offer/345/0 > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] tftp server for Windows
by Rune Raknerud 21 Jul '03

21 Jul '03

Hi I need to setup a tftp server on a Windows machine, and I tried to use tftpsrv that is provided by Abatron. This works fine with my BDI2000, but not with my custom MPC8245 board running u-boot. Both the BDI2000 and the MPC8245 board work fine when connected to a tftp server on a RedHat 7.3 machine. I use the following command for starting tftpsrv: tftpsrv w p dc:\tftpboot\ The following is a screen capture of the console output from the MPC8245 board. 172.23.151.225 is a PC running RedHat 7.3 and 172.23.151.232 is a PC running Windows 2000 Prof and tftpserv from Abatron. I have enabled debug output from u-boot. =>setenv serverip 172.23.151.225 =>tftp 100000 8245.cfg ARP broadcast 1 Receive from protocol 0x806 Got ARP Got ARP REPLY, set server/gtwy eth addr Got good ARP - start TFTP Server ethernet address 00:01:02:99:91:26 TFTP from server 172.23.151.225; our IP address is 172.23.151.236 Filename '8245.cfg'. Load address: 0x100000 Loading: *Receive from protocol 0x800 Got IP len=544, v=45 #Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 #Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=347, v=45 done Bytes transferred = 7483 (1d3b hex) => reset U-Boot 0.2.0 (Jul 18 2003 - 09:10:38) CPU: MPC8245 Revision 1.2 at 299.999 MHz: 16 kB I-Cache 16 kB D-Cache Board: Cargoscan CS0045 CPU/RF PowerPC MPC8245 I2C: ready DRAM: 64 MB Altera 1k10 ,,,,,,,,,,,,,,,,,,, Altera 1k50 ........................................................................ ......................... FPGA: ready on 1 atempt. FLASH: 8 MB In: serial Out: serial Err: serial Net: i82559#0, i82559#1 IDE: Bus 0: OK Device 0: Model: SanDisk SDCFB-64 Firm: vde 1.10 Ser#: 20312131908 Type: Removable Hard Disk Capacity: 61.2 MB = 0.0 GB (125440 x 512) => printenv baudrate=38400 serial#=AO031245612346 filesize=9fdf1 sereverip=172.23.151.231 serverip=172.23.151.232 ipaddr=172.23.151.236 bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=/home/filesystems/mvl30 ip=172.23.151.233:172.23.151.232:172.23.151.40:255.255.255.0:io:eth0 ide0=0xfe0001f0,0xfe0003f6,19 stdin=serial stdout=serial stderr=serial Environment size: 342/131068 bytes => tftp 100000 8245.cfg ARP broadcast 1 Receive from protocol 0x806 Got ARP Got ARP REPLY, set server/gtwy eth addr Got good ARP - start TFTP Server ethernet address 00:08:74:3b:61:58 TFTP from server 172.23.151.232; our IP address is 172.23.151.236 Filename '8245.cfg'. Load address: 0x100000 Loading: *Receive from protocol 0x800 Got IP len=56, v=45 Receive from protocol 0x800 Got IP len=128, v=45 T Receive from protocol 0x800 Got IP len=56, v=45 Receive from protocol 0x806 Got ARP T Receive from protocol 0x800 Got IP len=56, v=45 Receive from protocol 0x8137 Receive from protocol 0x806 Got ARP Abort => >From the u-boot output, it looks like the packet lengths is to short. Have any of you got the Abatron tftpsrv to work with u-boot. If yes, how did you do it? If no, do you know of any other tftp servers that run under Windows and work with u-boot? Best regards Rune Raknerud Cargoscan AS

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[U-Boot-Users] [PATCH] fixed tftp error message output
by Andreas Oberritter 20 Jul '03

20 Jul '03

This patch fixes tftp error message output, i.e. does not print the last two bytes which contain garbage (at least for my setup, I hope this is not a tftp server issue). Changelog: Patch by Andreas Oberritter, 19 July 03 - fixed tftp error message output

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[U-Boot-Users] [PATCH] Flash IDs for STM M28W320CB
by Andreas Oberritter 19 Jul '03

19 Jul '03

A trivial patch for include/flash.h Changelog: Patch by Andreas Oberritter, 19 July 03: - Add IDs for STM M28W320CB 32MBit flash type

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[U-Boot-Users] [PATCH] fixed reset command on mpc8xx
by Andreas Oberritter 19 Jul '03

19 Jul '03

This patch does reset on 8xx like the linux kernel does it. Works without crashing u-boot unlike the previous version. Tested on mpc823. Changelog: Patch by Andreas Oberritter, 19 July 03 - fixed reset command on mpc8xx

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[U-Boot-Users] Debugging u-boot with BDI2000
by Juergen Beisert 18 Jul '03

18 Jul '03

Hello Wolfgang, >>I'm trying to debug my u-boot with BDI. It's a 405GP based system. >> In the telnet sessoin I can insert "reset run" and u-boot starts. When I >> enter "reset halt" and then "go" it won't do anything. I have tried with >> ddd > >What do you mean with "it won't do anything"? Who won't do anything? >The BDI2000? The CPU? What makes you think the CPU does not do >anything? At first I thought the 405GP cpu does not start. On my card is a LED display, so I can output some numbers very early in the startup process. With "reset halt", "go" the display never change its contents, with "reset run" it does. >Are you sure your BDI2000 config file is OK for your board? Good question. What should happen, to be shure? I have debugged a running Linux kernel with this configuration. So I think(!) the major settings are ok. > How did you configure "RESET type" and "STARTUP mode"? Is your > "START address" ok? RESET is not set, defaults to "SYSTEM" STARTUP is set to RESET START is set to 0x0000'0000 (readed from a default file) With "reset halt", "info" I see the CPU waiting at address 0xFFFF'FFFC, after one single step ("ti") it waits at address 0xFFFF'C0100. Seems ok. >> When I step the mtmsr instruction ddd shows address 0x700, and the esr >> register has 0x8800'0000 (illegal instruction occured?????). >> Same when I place a breakpoint behind the mtmsr instruction und use "cont" >> instead of "stepi". > >You are aware that you cannot single step through certain >instructions, aren't you? If the mtmsr instruction is not "single step able", it should run, if I place a breakpoint behind this instruction (for example later in the C routines) and use "go" to run up the breakpoint. Or not? >> What is the difference between "reset run" and "reset halt", "go"? >"reset run" and "reset halt" change the startup mode to "run" and >"halt", respectively. "go" sets the PC and starts the target system. >Ummm.. is there any specific part where the BDI2000 manual is unclear >about this? Perhaps my english is very bad. Question was: Why the cpu is running normal with "reset run", and did not run, when I enter "reset halt", enter a breakpoint and than "go" (it never reaches the breakpoint). -- JB

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Re: [U-Boot-Users] autoboot in U-boot
by Wolfgang Denk 18 Jul '03

18 Jul '03

Hello, in message <1058522316.1188.104.camel(a)localhost.localdomain> you wrote: > > > What do you get when you run the "printenv" command? > this is what i get when i issue printenv > > :>printenv > 0A" > $` > $A > .aB@ > stdgut=seri`l > stdin=serial > stdout=serial > stderr=serial > > Environment size: 71/262140 bytes As you can see, the environment contains only garbage. So it is not a big surprise that autoboot does not work as U-Boot cannot find a valid definition of the "bootdelay" environment variable. My suspicion that your environment is misconfigured seems to be correct. > > Why do you reserve 512 kB for U-Boot? U-Boot is needs much less > > memory! > > > err .. i dunno why.. did i reserve that much? hmm where do i configure > this. I hav just upgrade from ppcboot actually... and i am very new at > this boot loader stuff. All this is set in the board's config file. The relevant config variables are documented in the README file. > > Where are your environment variables stored? In flash? Embedded with > > the U-Boot image or separate? > > > environment variables?? i m really sorry, i m not sure what you are > talkin about. Is it board.c? Everything , the u-boot, kernel and ramdisk > is in flash. I am talking about variables and configuration parameters that U-Boot stores in the "environment". The envrionment can be stored in flash, I2C or SPI EEPROM, NVRAM, etc. Your environment is obviously misconfigured, which is the reason for your problems. > Thanks for your time in helping me out. I am sorry but I am new at this. > Well everyone has to start learning from somewhere. Maybe you find it useful to have a look at http://www.denx.de/re/DPLG.html Although this does not answer your immediate questions, it might help you to understand the concept of environment variables and what they can be used for. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de All your people must learn before you can reach for the stars. -- Kirk, "The Gamesters of Triskelion", stardate 3259.2

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[U-Boot-Users] autoboot in U-boot
by Sung 18 Jul '03

18 Jul '03

hi there, Can someone help me on this autoboot? I successfully configured the u-boot-0.4.0 for mpc857 custom board but somehow the bootcommand and boot arg would not run, it just skip the autoboot and goes to prompt. so help!!! this is part of the configuration .................................................................... #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled*/ #else #define CONFIG_BOOTDELAY 3 /* autoboot after 3 sec */ #endif #define CONFIG_BOOTCOMMAND "bootm 02800000 02880000" #define CONFIG_BOOTARGS "root=/dev/ram rw" #undef CONFIG_WATCHDOG /* watchdog disabled*/ #define CONFIG_SCC2_ENET 1 /* use SCC2 ethernet */ #undef CONFIG_FEC_ENET /* disable FEC ethernet */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> /* * Miscellaneous configurable options */ #undef CFG_LONGHELP /* undef to save memory*/ #define CFG_PROMPT ":>" /* Monitor CommandPrompt */ .................................................................. and this is the output displayed:- ...................................................................... U-Boot 0.4.0 (Jul 18 2003 - 10:17:35) CPU: unknown MPC850 (0x07000003) at 48 MHz: 4 kB I-Cache 4 kB D-Cache FEC pret *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** SDRAM: 16 MB Top of RAM usable for U-Boot at: 01000000 Reserving 512k for U-Boot at: 00f80000 Reserving 256k for malloc() at: 00f40000 Reserving 60 Bytes for Board Info at: 00f3ffc4 Reserving 52 Bytes for Global Data at: 00f3ff90 Stack Pointer at: 00f3ff78 New Stack Pointer is: 00f3ff78 Now running in RAM - U-Boot at: 00f80000 FLASH: 8 MB In: serial Out: serial Err: serial U-Boot relocated to 00f80000 Net: SCC ETHERNET :> :> ................................................................... So i don't understand... where did the autoboot go?? the u-boot is store in flash 0x2b00000 the kernel is store in flash 0x2800000 and the ramdisk is in flash 0x2880000 hmm.... thanks guys regards, Mike G.

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[U-Boot-Users] [PATCH] Fix OMAP1510 serial divisor settings.
by Woodruff, Richard 18 Jul '03

18 Jul '03

Here is a patch applied against u-boot-0.4.3 which enables changing the OMAP1510 baud rate. I had forgot to clear the 6.5 divisor in cases where 115200 was not the target rate. The register is write only so this is only way short of keeping a shadow register around for it...and its not worth it. Regards, Richard W.

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[U-Boot-Users] Patch: Support for Motorola PQ2FADS-ZU board
by Yuli Barcohen 17 Jul '03

17 Jul '03

Hi, The attached patch adds support for new Motorola PQ2FADS-ZU evaluation board which replaced MPC8260ADS and MPC8266ADS. Since it shares some 90% of code with MPC8260ADS, it's supported as an MPC8260ADS subtype and not completely new board to avoid unnecessary cloning. -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ======================================================================== Index: README =================================================================== RCS file: /home/CVS/u-boot/u-boot/README,v retrieving revision 1.1.1.4 diff -p -u -r1.1.1.4 README --- README 16 Jul 2003 11:23:40 -0000 1.1.1.4 +++ README 16 Jul 2003 13:12:52 -0000 @@ -197,7 +197,7 @@ Directory Hierarchy: - board/lwmon Files specific to LWMON boards - board/mbx8xx Files specific to MBX boards - board/mpc8260ads - Files specific to MMPC8260ADS boards + Files specific to MPC8260ADS and PQ2FADS-ZU boards - board/mpl/ Files specific to boards manufactured by MPL - board/mpl/common Common files for MPL boards - board/mpl/pip405 Files specific to PIP405 boards @@ -383,6 +383,14 @@ The following options need to be configu the lcd display every second with a "rotator" |\-/|\-/ +- Board flavour: (if CONFIG_MPC8260ADS is defined) + CONFIG_ADSTYPE + + Possible values are: + CFG_8260ADS - original MPC8260ADS + CFG_8266ADS - MPC8266ADS (untested) + CFG_PQ2FADS - PQ2FADS-ZU + - MPC824X Family Member (if CONFIG_MPC824X is defined) Define exactly one of CONFIG_MPC8240, CONFIG_MPC8245 @@ -1687,9 +1695,9 @@ Low Level (hardware related) configurati - CFG_DEFAULT_IMMR: Default address of the IMMR after system reset. - Needed on some 8260 systems (MPC8260ADS and RPXsuper) - to be able to adjust the position of the IMMR - register after a reset. + Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU, + and RPXsuper) to be able to adjust the position of + the IMMR register after a reset. - Floppy Disk Support: CFG_FDC_DRIVE_NUMBER @@ -1862,7 +1870,7 @@ configurations; the following names are GENIETV_config TQM823L_config PIP405_config GEN860T_config EBONY_config FPS860L_config ELPT860_config cmi_mpc5xx_config NETVIA_config - at91rm9200dk_config omap1510inn_config + at91rm9200dk_config omap1510inn_config MPC8260ADS_config Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for Index: board/mpc8260ads/mpc8260ads.c =================================================================== RCS file: /home/CVS/u-boot/u-boot/board/mpc8260ads/mpc8260ads.c,v retrieving revision 1.1.1.4 retrieving revision 1.7 diff -p -u -r1.1.1.4 -r1.7 --- board/mpc8260ads/mpc8260ads.c 16 Jul 2003 11:23:42 -0000 1.1.1.4 +++ board/mpc8260ads/mpc8260ads.c 16 Jul 2003 12:24:41 -0000 1.7 @@ -198,11 +198,19 @@ void reset_phy (void) vu_long *bcsr = (vu_long *)CFG_BCSR; /* reset the FEC port */ - bcsr[1] &= ~FETH_RST; + bcsr[1] &= ~FETH1_RST; udelay(2); - bcsr[1] |= FETH_RST; + bcsr[1] |= FETH1_RST; udelay(1000); #ifdef CONFIG_MII +#if CONFIG_ADSTYPE == CFG_PQ2FADS + /* + * Do not bypass Rx/Tx (de)scrambler (fix configuration error) + * Enable autonegotiation. + */ + miiphy_write(0, 16, 0x610); + miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#else /* * Ethernet PHY is configured (by means of configuration pins) * to work at 10Mb/s only. We reconfigure it using MII @@ -212,6 +220,7 @@ void reset_phy (void) miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */ miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */ miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ #endif /* CONFIG_MII */ } @@ -219,7 +228,7 @@ int board_pre_init (void) { vu_long *bcsr = (vu_long *)CFG_BCSR; - bcsr[1] = ~FETHIEN & ~RS232EN_1; + bcsr[1] = ~FETHIEN1 & ~RS232EN_1; return 0; } @@ -231,12 +240,10 @@ long int initdram (int board_type) volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar *ramaddr, c = 0xff; - - /* Initialisation is for 16MB DIMM the board is shipped with */ - long int msize = 16; - uint or = 0xFF000CA0; - uint psdmr = CFG_PSDMR; - uint psrt = CFG_PSRT; + long int msize; + uint or; + uint psdmr; + uint psrt; int i; @@ -246,22 +253,29 @@ long int initdram (int board_type) immap->im_siu_conf.sc_tescr1 = 0x00004000; memctl->memc_mptpr = CFG_MPTPR; - /* init local sdram, bank 4 */ - memctl->memc_lsrt = 0x00000010; +#ifdef CFG_LSDRAM_BASE + /* Init local bus SDRAM */ + memctl->memc_lsrt = CFG_LSRT; +#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */ + memctl->memc_or3 = 0xFF803280; + memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861; +#else /* CS4 */ memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = 0x04001861; - memctl->memc_lsdmr = 0x2886A522; + memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + memctl->memc_lsdmr = CFG_LSDMR | 0x28000000; ramaddr = (uchar *) CFG_LSDRAM_BASE; *ramaddr = c; - memctl->memc_lsdmr = 0x0886A522; + memctl->memc_lsdmr = CFG_LSDMR | 0x08000000; for (i = 0; i < 8; i++) { *ramaddr = c; } - memctl->memc_lsdmr = 0x1886A522; + memctl->memc_lsdmr = CFG_LSDMR | 0x18000000; *ramaddr = c; - memctl->memc_lsdmr = 0x4086A522; + memctl->memc_lsdmr = CFG_LSDMR | 0x40000000; +#endif /* CFG_LSDRAM_BASE */ - /* init sdram dimm */ + /* Init 60x bus SDRAM */ #ifdef CONFIG_SPD_EEPROM { spd_eeprom_t spd; @@ -398,6 +412,16 @@ long int initdram (int board_type) printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt); #endif /* SPD_DEBUG */ } +#else /* !CONFIG_SPD_EEPROM */ +#if CONFIG_ADSTYPE == CFG_PQ2FADS + msize = 32; + or = 0xFE002EC0; +#else + msize = 16; + or = 0xFF000CA0; +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + psdmr = CFG_PSDMR; + psrt = CFG_PSRT; #endif /* CONFIG_SPD_EEPROM */ memctl->memc_psrt = psrt; memctl->memc_or2 = or; @@ -415,12 +439,20 @@ long int initdram (int board_type) *ramaddr = c; #endif - /* return total ram size of DIMM */ + /* return total 60x bus SDRAM size */ return (msize * 1024 * 1024); } int checkboard (void) { +#if CONFIG_ADSTYPE == CFG_8260ADS puts ("Board: Motorola MPC8260ADS\n"); +#elif CONFIG_ADSTYPE == CFG_8266ADS + puts ("Board: Motorola MPC8266ADS\n"); +#elif CONFIG_ADSTYPE == CFG_PQ2FADS + puts ("Board: Motorola PQ2FADS-ZU\n"); +#else + puts ("Board: unknown\n"); +#endif return 0; } Index: include/configs/MPC8260ADS.h =================================================================== RCS file: /home/CVS/u-boot/u-boot/include/configs/MPC8260ADS.h,v retrieving revision 1.1.1.4 retrieving revision 1.9 diff -p -u -r1.1.1.4 -r1.9 --- include/configs/MPC8260ADS.h 16 Jul 2003 11:23:52 -0000 1.1.1.4 +++ include/configs/MPC8260ADS.h 14 Jul 2003 17:15:25 -0000 1.9 @@ -9,7 +9,8 @@ * * (C) Copyright 2003 Arabella Software Ltd. * Yuli Barcohen <yuli(a)arabellasw.com> - * Added support for SDRAM DIMMs SPD EEPROM, MII. + * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2. + * Ported to PQ2FADS-ZU board. * * See file CREDITS for list of people who contributed to this * project. @@ -41,6 +42,15 @@ #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */ +/* ADS flavours */ +#define CFG_8260ADS 1 /* MPC8260ADS */ +#define CFG_8266ADS 2 /* MPC8266ADS */ +#define CFG_PQ2FADS 3 /* PQ2FADS-ZU */ + +#ifndef CONFIG_ADSTYPE +#define CONFIG_ADSTYPE CFG_8260ADS +#endif /* CONFIG_ADSTYPE */ + #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ /* allow serial and ethaddr to be overwritten */ @@ -116,7 +126,9 @@ #endif /* CONFIG_ETHER_ON_FCC */ -/* other options */ +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#undef CONFIG_SPD_EEPROM /* On PQ2FADS-ZU, SDRAM is soldered */ +#else #define CONFIG_HARD_I2C 1 /* To enable I2C support */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -124,18 +136,23 @@ #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) #define CONFIG_SPD_ADDR 0x50 #endif +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ #ifndef CONFIG_SDRAM_PBI #define CONFIG_SDRAM_PBI 1 /* By default, use page-based interleaving */ #endif #ifndef CONFIG_8260_CLKIN +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#define CONFIG_8260_CLKIN 100000000 /* in Hz */ +#else #define CONFIG_8260_CLKIN 66666666 /* in Hz */ #endif +#endif + #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_BEDBUG | \ +#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ CFG_CMD_BMP | \ CFG_CMD_BSP | \ CFG_CMD_DATE | \ @@ -143,11 +160,11 @@ CFG_CMD_DTT | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ + CFG_CMD_FAT | \ CFG_CMD_FDC | \ CFG_CMD_FDOS | \ CFG_CMD_HWFLOW | \ CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ CFG_CMD_KGDB | \ CFG_CMD_MMC | \ CFG_CMD_NAND | \ @@ -155,8 +172,18 @@ CFG_CMD_PCMCIA | \ CFG_CMD_SCSI | \ CFG_CMD_SPI | \ - CFG_CMD_VFD | \ - CFG_CMD_USB ) ) + CFG_CMD_USB | \ + CFG_CMD_VFD + +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_EXCLUDE ) ) +#else +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_EXCLUDE ) ) +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -200,7 +227,6 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CFG_FLASH_BASE 0xff800000 -#define FLASH_BASE 0xff800000 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ #define CFG_FLASH_SIZE 8 @@ -219,14 +245,16 @@ #define CFG_DEFAULT_IMMR 0x0F010000 #define CFG_IMMR 0xF0000000 -#define CFG_BCSR 0x04500000 +#define CFG_BCSR 0xF4500000 #define CFG_SDRAM_BASE 0x00000000 -#define CFG_LSDRAM_BASE 0x04000000 +#define CFG_LSDRAM_BASE 0xD0000000 #define RS232EN_1 0x02000002 #define RS232EN_2 0x01000001 -#define FETHIEN 0x08000008 -#define FETH_RST 0x04000004 +#define FETHIEN1 0x08000008 +#define FETH1_RST 0x04000004 +#define FETHIEN2 0x01000000 +#define FETH2_RST 0x08000000 #define CFG_INIT_RAM_ADDR CFG_IMMR #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ @@ -288,19 +316,30 @@ #define CFG_SYPCR 0xFFFFFFC3 #define CFG_BCR 0x100C0000 #define CFG_SIUMCR 0x0A200000 -#define CFG_SCCR 0x00000000 -#define CFG_BR0_PRELIM 0xFF801801 -#define CFG_OR0_PRELIM 0xFF800836 -#define CFG_BR1_PRELIM 0x04501801 +#define CFG_SCCR SCCR_DFBRG01 +#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801 +#define CFG_OR0_PRELIM 0xFF800876 +#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 #define CFG_OR1_PRELIM 0xFFFF8010 -#define CFG_RMR 0 +#define CFG_RMR RMR_CSRE #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) #define CFG_RCCR 0 + +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#define CFG_PSDMR 0x824B36A3 +#define CFG_PSRT 0x13 +#define CFG_LSDMR 0x828737A3 +#define CFG_LSRT 0x13 +#define CFG_MPTPR 0x2800 +#else #define CFG_PSDMR 0x016EB452 -#define CFG_MPTPR 0x00001900 -#define CFG_PSRT 0x00000021 +#define CFG_PSRT 0x21 +#define CFG_LSDMR 0x0086A522 +#define CFG_LSRT 0x21 +#define CFG_MPTPR 0x1900 +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ #define CFG_RESET_ADDRESS 0x04400000 N: Yuli Barcohen E: <yuli(a)arabellasw.com> D: Support for Motorola PQ2FADS-ZU board

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[U-Boot-Users] probably bug in ds1621.c
by Palkin Andrey 17 Jul '03

17 Jul '03

In dtt/ds1621.c file: 1. int dtt_write(int sensor, int reg, int val) { int dlen; uchar data[2]; /* * Calculate sensor address and register. * */ sensor = DTT_I2C_DEV_CODE + (sensor & sensor); I think it should be: int dtt_write(int sensor, int reg, int val) { int dlen; uchar data[2]; /* * Calculate sensor address and register. * */ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); 2. else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) { dlen = 0; data[0] = (char)0; data[1] = (char)0; } I think it should be: else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) { dlen = 1; data[0] = (char)0; data[1] = (char)0; } differently MPC8260 I2C controller go in down -- Palkin Andrey

3 3

[U-Boot-Users] I2C POST test known problems?
by Robin Gilks 17 Jul '03

17 Jul '03

Greetings Is anyone aware of any problems with the I2C POST test - I've enabled it and it looks like it locks up the CPM with the busy flag in the command register remaining set all the time. Does anyone know if this is (well) tested code or should I just ignore it and write my own... -- Robin Gilks Senior Design Engineer Phone: (+64)(3) 357 1569 Tait Electronics Fax : (+64)(3) 359 4632 PO Box 1645 Christchurch Email : robin.gilks(a)tait.co.nz New Zealand

3 7

[U-Boot-Users] Swapping in IDE driver
by Marc Singer 16 Jul '03

16 Jul '03

I'm working to get the IDE driver working with an ARM cpu. I'd like to reconcile the three places where swapping does or ought to occur. 1) On PPC, the IDENTITY block is byte swapped as it is read. 2) The identity strings within the IDENTITY block are not byte-swapped. 3) The LBA count is always word-swapped. On an ARM, the combination that works is to swap the identity strings *only*. Enabling the PPC byte swapping will fix the strings, but it garbles the LBA count. It is possible that the reason this is so different on my target is that IDE controller IO is 16 bits wide. So, I'm looking for someone who is familiar with the current IDE driver so that I know the right way to integrate my changes. Cheers.

1 0

[U-Boot-Users] Patch: Correct flash and JFFS2 support for MPC8260ADS
by Yuli Barcohen 14 Jul '03

14 Jul '03

Hi, Original flash support for MPC8260ADS board was cloned from code written for 2x16bit flash configuration while this board uses 4x8bit flash SIMMs. Also, JFFS2 flash file system was not supported on this board. Attached patch fixes some flash support bugs and adds JFFS2 support. This code works unchanged on new Motorola evaluation board, PQ2FADS-ZU. It should work on MPC8266ADS too but I haven't got a board for test. -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ======================================================================== diff -purN CVS/README Arabella/README --- CVS/README 2003-07-13 18:20:25.000000000 +0300 +++ Arabella/README 2003-07-13 18:49:57.000000000 +0300 @@ -1481,6 +1481,16 @@ Configuration Settings: - CFG_FLASH_WRITE_TOUT: Timeout for Flash write operations (in ms) +- CFG_FLASH_LOCK_TOUT + Timeout for Flash set sector lock bit operation (in ms) + +- CFG_FLASH_UNLOCK_TOUT + Timeout for Flash clear lock bits operation (in ms) + +- CFG_FLASH_PROTECTION + If defined, hardware flash sectors protection is used + instead of U-Boot software protection. + - CFG_DIRECT_FLASH_TFTP: Enable TFTP transfers directly to flash memory; diff -purN CVS/board/mpc8260ads/flash.c Arabella/board/mpc8260ads/flash.c --- CVS/board/mpc8260ads/flash.c 2003-07-13 18:16:58.000000000 +0300 +++ Arabella/board/mpc8260ads/flash.c 2003-07-13 17:27:25.000000000 +0300 @@ -7,6 +7,11 @@ * I started with board/ip860/flash.c and made changes I found in * the MTD project by David Schleef. * + * (C) Copyright 2003 Arabella Software Ltd. + * Yuli Barcohen <yuli(a)arabellasw.com> + * Re-written to support multi-bank flash SIMMs. + * Added support for real protection and JFFS2. + * * See file CREDITS for list of people who contributed to this * project. * @@ -28,73 +33,118 @@ #include <common.h> +/* Intel-compatible flash ID */ +#define INTEL_COMPAT 0x89898989 +#define INTEL_ALT 0xB0B0B0B0 + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x10101010 +#define INTEL_ERASE 0x20202020 +#define INTEL_CLEAR 0x50505050 +#define INTEL_LOCKBIT 0x60606060 +#define INTEL_PROTECT 0x01010101 +#define INTEL_STATUS 0x70707070 +#define INTEL_READID 0x90909090 +#define INTEL_CONFIRM 0xD0D0D0D0 +#define INTEL_RESET 0xFFFFFFFF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x80808080 +#define INTEL_OK 0x80808080 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- + * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.) + * Up to 32MB of flash supported (up to 4 banks.) + * BCSR is used for flash presence detect (page 4-65 of the User's Manual) + * + * The following code can not run from flash! */ - unsigned long flash_init (void) { -#ifndef CONFIG_MPC8260ADS - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; -#endif - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ -#ifndef CONFIG_MPC8260ADS - bcsr->bd_ctrl |= BD_CTRL_FLWE; -#endif - - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* set the default sector offset */ + ulong size = 0, sect_start, sect_size, bank_size; + ushort sect_count; + int i, j, nbanks; + vu_long *addr = (vu_long *)CFG_FLASH_BASE; + vu_long *bcsr = (vu_long *)CFG_BCSR; + + switch (bcsr[2] & 0xF) { + case 0: + nbanks = 4; + break; + case 1: + nbanks = 2; + break; + case 2: + nbanks = 1; + break; + default: /* Unsupported configurations */ + nbanks = CFG_MAX_FLASH_BANKS; } - /* Static FLASH Bank configuration here - FIXME XXX */ - - size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]); + if (nbanks > CFG_MAX_FLASH_BANKS) + nbanks = CFG_MAX_FLASH_BANKS; - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size<<20); + for (i = 0; i < nbanks; i++) { + *addr = INTEL_READID; /* Read Intelligent Identifier */ + if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) { + switch (addr[1]) { + case SHARP_ID_28F016SCL: + case SHARP_ID_28F016SCZ: + flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; + sect_count = 32; + sect_size = 0x40000; + break; + default: + flash_info[i].flash_id = FLASH_UNKNOWN; + } + } + else + flash_info[i].flash_id = FLASH_UNKNOWN; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n", + addr[0], addr[1], (ulong)addr); + size = 0; + *addr = INTEL_RESET; /* Reset bank to Read Array mode */ + break; + } + flash_info[i].sector_count = sect_count; + flash_info[i].size = bank_size = sect_size * sect_count; + size += bank_size; + sect_start = (ulong)addr; + for (j = 0; j < sect_count; j++) { + addr = (vu_long *)sect_start; + flash_info[i].start[j] = sect_start; + flash_info[i].protect[j] = (addr[2] == 0x01010101); + sect_start += sect_size; + } + *addr = INTEL_RESET; /* Reset bank to Read Array mode */ + addr = (vu_long *)sect_start; + } + + if (size == 0) { /* Unknown flash, fill with hard-coded values */ + sect_start = CFG_FLASH_BASE; + sect_count = CFG_MAX_FLASH_SECT; + sect_size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS; + flash_info[i].sector_count = sect_count; + for (j = 0; j < sect_count; j++) { + flash_info[i].start[j] = sect_start; + flash_info[i].protect[j] = 0; + sect_start += sect_size; + } + } + size = CFG_FLASH_SIZE; } -#ifndef CONFIG_MPC8260ADS - /* Remap FLASH according to real size */ - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br1 & ~(BR_BA_MSK)); -#endif - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; + else + for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].size = 0; + flash_info[i].sector_count = 0; + } #if CFG_MONITOR_BASE >= CFG_FLASH_BASE /* monitor protection ON by default */ @@ -161,102 +211,6 @@ void flash_print_info (flash_info_t *in /*----------------------------------------------------------------------- */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - - value = addr[0] & 0x00FF00FF; - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - sector_offset = 0x20000; - break; /* => 2x4 MB */ - - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - info->size = 0x00800000; - sector_offset = 0x40000; - break; /* => 4x2 MB */ - - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - - *addr = 0xFFFFFF; /* reset bank to read array mode */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; @@ -292,12 +246,6 @@ int flash_erase (flash_info_t *info, int printf ("\n"); } - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ @@ -308,36 +256,26 @@ int flash_erase (flash_info_t *info, int /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - /* Reset Array */ - *addr = 0xffffffff; /* Clear Status Register */ - *addr = 0x50505050; + *addr = INTEL_CLEAR; /* Single Block Erase Command */ - *addr = 0x20202020; + *addr = INTEL_ERASE; /* Confirm */ - *addr = 0xD0D0D0D0; + *addr = INTEL_CONFIRM; if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; + *addr = INTEL_CONFIRM; } /* re-enable interrupts if necessary */ if (flag) enable_interrupts(); - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x80808080) != 0x80808080) { - if(*addr & 0x20202020){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ + *addr = INTEL_RESET; /* reset bank */ return 1; } /* show that we're waiting */ @@ -347,8 +285,15 @@ int flash_erase (flash_info_t *info, int } } + if (*addr != INTEL_OK) { + printf("Block erase failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + *addr = INTEL_RESET; /* reset bank */ + return 1; + } + /* reset to read mode */ - *addr = 0xFFFFFFFF; + *addr = INTEL_RESET; } } @@ -357,6 +302,58 @@ int flash_erase (flash_info_t *info, int } /*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + ulong start; + int rc = 0; + int flag; + vu_long *addr = (vu_long *)dest; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + + *addr = INTEL_CLEAR; /* Clear status register */ + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = INTEL_PROGRAM; + + /* Write Data */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + printf("Write timed out\n"); + rc = 1; + break; + } + } + if (*addr != INTEL_OK) { + printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr); + rc = 1; + } + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} + +/*----------------------------------------------------------------------- * Copy memory to flash, returns: * 0 - OK * 1 - write timeout @@ -370,6 +367,8 @@ int write_buff (flash_info_t *info, ucha wp = (addr & ~3); /* get lower word aligned address */ + *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */ + /* * handle unaligned start bytes */ @@ -424,85 +423,125 @@ int write_buff (flash_info_t *info, ucha data = (data << 8) | (*(uchar *)cp); } - return (write_word(info, wp, data)); + rc = write_word(info, wp, data); + + return rc; } /*----------------------------------------------------------------------- - * Write a word to Flash, returns: + * Set/Clear sector's lock bit, returns: * 0 - OK - * 1 - write timeout - * 2 - Flash not erased + * 1 - Error (timeout, voltage problems, etc.) */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +int flash_real_protect(flash_info_t *info, long sector, int prot) { - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; + ulong start; + int i; + int rc = 0; + vu_long *addr = (vu_long *)(info->start[sector]); + int flag = disable_interrupts(); + + *addr = INTEL_CLEAR; /* Clear status register */ + if (prot) { /* Set sector lock bit */ + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + } + else { /* Clear sector lock bit */ + *addr = INTEL_LOCKBIT; /* All sectors lock bits */ + *addr = INTEL_CONFIRM; /* clear */ + } + + start = get_timer(0); + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + printf("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); + if (*addr != INTEL_OK) { + printf("Flash lock bit operation failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + rc = 1; } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - /* Write Command */ - *addr = 0x10101010; + if (!rc) + info->protect[sector] = prot; - /* Write Data */ - *addr = data; + /* + * Clear lock bit command clears all sectors lock bits, so + * we have to restore lock bits of protected sectors. + */ + if (!prot) + for (i = 0; i < info->sector_count; i++) + if (info->protect[i]) { + addr = (vu_long *)(info->start[i]); + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + udelay(CFG_FLASH_LOCK_TOUT * 1000); + } - /* re-enable interrupts if necessary */ if (flag) enable_interrupts(); - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - while (((csr = *addr) & 0x80808080) != 0x80808080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; + *addr = INTEL_RESET; /* Reset to read array mode */ - return (flag); + return rc; } /*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout + * Support for flash file system (JFFS2) + * + * We use custom partition info function because we have to fit the + * file system image between first sector (containing hard reset + * configuration word) and the sector containing U-Boot image. Standard + * partition info function does not allow for last sector specification + * and assumes that the file system occupies flash bank up to and + * including bank's last sector. */ +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART) -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; +#ifndef CFG_JFFS2_FIRST_SECTOR +#define CFG_JFFS2_FIRST_SECTOR 0 +#endif +#ifndef CFG_JFFS2_FIRST_BANK +#define CFG_JFFS2_FIRST_BANK 0 +#endif +#ifndef CFG_JFFS2_NUM_BANKS +#define CFG_JFFS2_NUM_BANKS 1 +#endif +#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1) - /* Reset Array */ - *addr = 0xffffffff; - /* Clear Status Register */ - *addr = 0x50505050; +#include <jffs2/jffs2.h> - *addr = 0x60606060; - *addr = 0xd0d0d0d0; +static struct part_info partition; - start = get_timer (0); - while(*addr != 0x80808080){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; +struct part_info *jffs2_part_info(int part_num) +{ + int i; + + if (part_num == 0) { + if (partition.usr_priv == 0) { + partition.offset = + (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR]; + for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++) + partition.size += flash_info[i].size; + partition.size -= + flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] - + flash_info[CFG_JFFS2_FIRST_BANK].start[0]; +#ifdef CFG_JFFS2_LAST_SECTOR + i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1; + partition.size -= + flash_info[CFG_JFFS2_LAST_BANK].start[i] - + flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR]; +#endif + + partition.usr_priv = (void *)1; } + return &partition; } return 0; } + +#endif /* JFFS2 */

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[U-Boot-Users] Patch: New PowerQUICC II processors support
by Yuli Barcohen 14 Jul '03

14 Jul '03

Latest additions to PowerQUICC II family (8270/8275/8280) have got different PVR values and different clock generation scheme. This patch adds support for these processors. -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ======================================================================== diff -purN CVS/cpu/mpc8260/commproc.c Arabella/cpu/mpc8260/commproc.c --- CVS/cpu/mpc8260/commproc.c 2003-07-13 20:49:08.000000000 +0300 +++ Arabella/cpu/mpc8260/commproc.c 2003-07-13 20:59:49.000000000 +0300 @@ -111,9 +111,9 @@ m8260_cpm_hostalloc(uint size, uint alig * to port numbers). Documentation uses 1-based numbering. */ #define BRG_INT_CLK gd->brg_clk -#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16) +#define BRG_UART_CLK (BRG_INT_CLK / 16) -/* This function is used by UARTS, or anything else that uses a 16x +/* This function is used by UARTs, or anything else that uses a 16x * oversampled clock. */ void @@ -123,9 +123,10 @@ m8260_cpm_setbrg(uint brg, uint rate) volatile immap_t *immr = (immap_t *)CFG_IMMR; volatile uint *bp; + uint cd = BRG_UART_CLK / rate; - /* This is good enough to get SMCs running..... - */ + if ((BRG_UART_CLK % rate) < (rate / 2)) + cd--; if (brg < 4) { bp = (uint *)&immr->im_brgc1; } @@ -134,7 +135,7 @@ m8260_cpm_setbrg(uint brg, uint rate) brg -= 4; } bp += brg; - *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; + *bp = (cd << 1) | CPM_BRG_EN; } /* This function is used to set high speed synchronous baud rate diff -purN CVS/cpu/mpc8260/cpu.c Arabella/cpu/mpc8260/cpu.c --- CVS/cpu/mpc8260/cpu.c 2003-07-13 20:26:46.000000000 +0300 +++ Arabella/cpu/mpc8260/cpu.c 2003-07-13 20:37:50.000000000 +0300 @@ -22,7 +22,7 @@ */ /* - * CPU specific code for the MPC8255 / MPC8260 CPUs + * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x * * written or collected and sometimes rewritten by * Magnus Damm <damm(a)bitsmart.com> @@ -35,6 +35,9 @@ * * added 8260 masks by * Marius Groeger <mag(a)sysgo.de> + * + * added HiP7 (8270/8275/8280) processors support by + * Yuli Barcohen <yuli(a)arabellasw.com> */ #include <common.h> @@ -56,15 +59,27 @@ int checkcpu (void) puts ("CPU: "); - if (((pvr >> 16) & 0xff) != 0x81) + switch (pvr) { + case PVR_8260: + case PVR_8260_HIP3: + strcpy (buf, "HiP3"); + break; + case PVR_8260_HIP4: + strcpy (buf, "HiP4"); + break; + case PVR_8260_HIP7: + strcpy (buf, "HiP7"); + break; + default: return -1; /* whoops! not an MPC8260 */ + } rev = pvr & 0xff; immr = immap->im_memctl.memc_immr; if ((immr & IMMR_ISB_MSK) != CFG_IMMR) return -1; /* whoops! someone moved the IMMR */ - printf (CPU_ID_STR " (Rev %02x, Mask ", rev); + printf (CPU_ID_STR " (%s Rev %02x, Mask ", buf, rev); /* * the bottom 16 bits of the immr are the Part Number and Mask Number @@ -104,6 +119,12 @@ int checkcpu (void) case 0x0062: printf ("B.1 4K25A"); break; + case 0x0A00: + printf ("0.0 0K49M"); + break; + case 0x0A01: + printf ("0.1 1K49M"); + break; default: printf ("unknown [immr=0x%04x,k=0x%04x]", m, k); break; diff -purN CVS/cpu/mpc8260/speed.c Arabella/cpu/mpc8260/speed.c --- CVS/cpu/mpc8260/speed.c 2003-07-13 20:51:15.000000000 +0300 +++ Arabella/cpu/mpc8260/speed.c 2003-07-13 17:27:30.000000000 +0300 @@ -120,15 +120,19 @@ int get_clocks (void) scmr = immap->im_clkrst.car_scmr; corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; - busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; - cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; - plldf = (scmr & SCMR_PLLDF) ? 1 : 0; - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; - cp = &corecnf_tab[corecnf]; - gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); + busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; + cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; + if (get_pvr () == PVR_8260_HIP7) { /* HiP7 */ + pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT; + gd->vco_out = clkin * (pllmf + 1); + } else { /* HiP3, HiP4 */ + pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; + plldf = (scmr & SCMR_PLLDF) ? 1 : 0; + gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); + } #if 0 if (gd->vco_out / (busdf + 1) != clkin) { /* aaarrrggghhh!!! */ diff -purN CVS/include/asm-ppc/processor.h Arabella/include/asm-ppc/processor.h --- CVS/include/asm-ppc/processor.h 2003-07-13 20:27:48.000000000 +0300 +++ Arabella/include/asm-ppc/processor.h 2003-07-13 20:32:30.000000000 +0300 @@ -524,8 +524,15 @@ #define PVR_860 PVR_821 #define PVR_7400 0x000C0000 #define PVR_8240 0x00810100 -#define PVR_8260 PVR_8240 +/* + * PowerQUICC II family processors report different PVR values depending + * on silicon process (HiP3, HiP4, HiP7, etc.) + */ +#define PVR_8260 PVR_8240 +#define PVR_8260_HIP3 0x00810101 +#define PVR_8260_HIP4 0x80811014 +#define PVR_8260_HIP7 0x80822011 /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single

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[U-Boot-Users] Re: Cannot compile u-boot under Mandrake 9.1
by Yun-Fong Loh 13 Jul '03

13 Jul '03

John, > gcc -Wall -pedantic -O -I/opt/powerpc/include -o ^^^ this is your problem > astest astest.o error.o -L/opt/powerpc/lib -lbfd > -liberty > /usr//bin/ld: cannot find -lbfd > collect2: ld returned 1 exit status > make[2]: *** [astest] Error 1 Try defining CROSS_COMPILE environment variable with the prefix of your cross compilation tools, e.g.: make CROSS_COMPILE=powerpc-linux- Yun

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[U-Boot-Users] Cannot compile u-boot under Mandrake 9.1
by john duc 13 Jul '03

13 Jul '03

Hi, I tried to compile u-boot-0.4.0 on Mandrake 9.1, but not successful. Could someone help me fix this problem. Here what I did: make distclean make MPC8260ADS_config make all The error is: gcc -Wall -pedantic -O -I/opt/powerpc/include -o astest astest.o error.o -L/opt/powerpc/lib -lbfd -liberty /usr//bin/ld: cannot find -lbfd collect2: ld returned 1 exit status make[2]: *** [astest] Error 1 Some libraries probably missing? Thanks, john __________________________________ Do you Yahoo!? SBC Yahoo! DSL - Now only $29.95 per month! http://sbc.yahoo.com

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[U-Boot-Users] H/W breakpoint
by Dhanuka, Anupam 11 Jul '03

11 Jul '03

Hi there I have made a few changes to u-boot to suit my target requirements. I am trying to debug the code using Abatron BDI h/w debugger. I am unable to stop the target through h/w breakpoints (the target doesn't stop at the address that I provide). Does u-boot disable h/w debugging support (by clearing the Debug Enable bit in some register)? My target is PPC440GP on the EBONY reference board. Thanks Anupam This message (including any attachments) may contain confidential information intended for a specific individual and purpose. If you are not the intended recipient, delete this message. If you are not the intended recipient, disclosing, copying, distributing, or taking any action based on this message is strictly prohibited.

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[U-Boot-Users] printf
by Rune Torgersen 11 Jul '03

11 Jul '03

Hi Does anybody know how to get printf (for 82xx CPU) to priont floting point numbers? I have tried %f %e and %g but all it prints on the console is f e and g... I am using a workaround for now, by printing the number as two integers... float_num = some_float_operation; i = (int)float_num; r = ((int)float_num - i) * 100; printf("%d.%d", i, r); But this is kind of bothersome for the long run. I need this to print out the measured voltages in the system. (done by a supervisor circuit). And yes... The 8266 CPU (actually all the 82xx) has a working FPU unit. Rune Torgersen System Developer Innovative Systems LLC 1000 Innovative Drive Mitchell, SD 57301 Ph: 605-995-6120 www.innovsys.com

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RE: [U-Boot-Users] Probelm with 8266ADS board.
by Rune Torgersen 11 Jul '03

11 Jul '03

This is of course a problem with the SDRAM. Check that CONFIG_PBI is set to 0 (set in top of mpc8266ads.c) This stets the controller in Bank Based interleave. I have seen this excact problem when running Page Based access to the standard 16MB devices. Page Based is supposed to be faster, and is necessary to use more than 128MB per chip select. > -----Original Message----- > From: *L/E<a [mailto:houcheng@turbonetworks.com.tw] > Sent: Thursday, July 10, 2003 21:56 > To: U-Boot Users (E-mail) > Subject: [U-Boot-Users] Probelm with 8266ADS board. > > > Hi All: > I am using MPC8266ADS-PCI board, my board seems crash at > "relocate_code:" and reboot again and again. So I can see the > boot messages repeatly printed on my console. Any good ideas > ? Thanks a lot. > > >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> MESSAGES DRUING BOOTING, REPEATED > U-Boot 0.4.0 (Jul 10 2003 - 17:37:18) > > MPC8260 Reset Status: Check Stop, External Soft, External Hard > > MPC8260 Clock Configuration > - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core > Freq 100-300 > - dfbrg 0, corecnf 0x0a, busdf 5, cpmdf 1, plldf 0, pllmf 2 > - vco_out 396000000, scc_clk 99000000, brg_clk 99000000 > - cpu_clk 264000000, cpm_clk 198000000, bus_clk 66000000 > > CPU: MPC8260 (Rev 14, Mask A.0(A) 2K25A) at 264 MHz > Board: Motorola MPC8266ADS > I2C: ready > DRAM: SDRAM configuration read from SPD > Size per side = 16MB > Organization: 1 sides, 2 banks, 9 Columns, 11 Rows, > Data width = 64 bits > Refresh rate = 33, CAS latency = 3 > Total size: 16 MB > Top of RAM usable for U-Boot at: 01000000 > haha > Reserving 190k for U-Boot at: 00fd0000 > Reserving 384k for malloc() at: 00f70000 > Reserving 76 Bytes for Board Info at: 00f6ffb4 > Reserving 68 Bytes for Global Data at: 00f6ff70 > Stack Pointer at: 00f6ff58 > New Stack Pointer is: 00f6ff58 > before memcpy 16187248, -268419200, 68 > after memcpy > > U-Boot 0.4.0 (Jul 10 2003 - 17:37:18) > > MPC8260 Reset Status: Check Stop, External Soft, External Hard > > MPC8260 Clock Configuration > - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core > Freq 100-300 > - dfbrg 0, corecnf 0x0a, busdf 5, cpmdf 1, plldf 0, pllmf 2 > - vco_out 396000000, scc_clk 99000000, brg_clk 99000000 > - cpu_clk 264000000, cpm_clk 198000000, bus_clk 66000000 > > > > > > > ------------------------------------------------------- > This SF.Net email sponsored by: Parasoft > Error proof Web apps, automate testing & more. > Download & eval WebKing and get a free book. > www.parasoft.com/bulletproofapps1 > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users >

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[U-Boot-Users] Probelm with 8266ADS board.
by �L�E�� 11 Jul '03

11 Jul '03

Hi All: I am using MPC8266ADS-PCI board, my board seems crash at "relocate_code:" and reboot again and again. So I can see the boot messages repeatly printed on my console. Any good ideas ? Thanks a lot. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> MESSAGES DRUING BOOTING, REPEATED U-Boot 0.4.0 (Jul 10 2003 - 17:37:18) MPC8260 Reset Status: Check Stop, External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core Freq 100-300 - dfbrg 0, corecnf 0x0a, busdf 5, cpmdf 1, plldf 0, pllmf 2 - vco_out 396000000, scc_clk 99000000, brg_clk 99000000 - cpu_clk 264000000, cpm_clk 198000000, bus_clk 66000000 CPU: MPC8260 (Rev 14, Mask A.0(A) 2K25A) at 264 MHz Board: Motorola MPC8266ADS I2C: ready DRAM: SDRAM configuration read from SPD Size per side = 16MB Organization: 1 sides, 2 banks, 9 Columns, 11 Rows, Data width = 64 bits Refresh rate = 33, CAS latency = 3 Total size: 16 MB Top of RAM usable for U-Boot at: 01000000 haha Reserving 190k for U-Boot at: 00fd0000 Reserving 384k for malloc() at: 00f70000 Reserving 76 Bytes for Board Info at: 00f6ffb4 Reserving 68 Bytes for Global Data at: 00f6ff70 Stack Pointer at: 00f6ff58 New Stack Pointer is: 00f6ff58 before memcpy 16187248, -268419200, 68 after memcpy U-Boot 0.4.0 (Jul 10 2003 - 17:37:18) MPC8260 Reset Status: Check Stop, External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core Freq 100-300 - dfbrg 0, corecnf 0x0a, busdf 5, cpmdf 1, plldf 0, pllmf 2 - vco_out 396000000, scc_clk 99000000, brg_clk 99000000 - cpu_clk 264000000, cpm_clk 198000000, bus_clk 66000000

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[U-Boot-Users] BDI error
by Rune Torgersen 10 Jul '03

10 Jul '03

Hi Have anybody seen this BDI error and have an idea why it happens? The board is based on a 8266. (FLASH is programed with HRCW (0x08b23645) starting at address 0xff800000) - TARGET: waiting for target Vcc - TARGET: processing power-up delay - TARGET: processing user reset request - BDI asserts HRESET - Reset JTAG controller passed - Bypass check: 0x55 => 0xAA - Bypass check: 0x55 => 0xAA - JTAG exists check passed - Target PVR is 0x80911014 - COP status is 0x01 - Check running state passed - BDI scans COP freeze command - BDI removes HRESET - COP status is 0x05 - Check stopped state passed - Check LSRL length passed - BDI sets breakpoint at 0xFFF00100 - BDI resumes program execution - COP status is 0xF1 - Waiting for target stop failed - TARGET: Break at boot vector failed, freeze forced - TARGET: Target PVR is 0x80911014 - TARGET: resetting target passed - TARGET: processing target startup .... - TARGET: processing target startup passed Rune Torgersen System Developer Innovative Systems LLC 1000 Innovative Drive Mitchell, SD 57301 Ph: 605-995-6120 www.innovsys.com

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[U-Boot-Users] mpc8260 eth_loopback_test()
by Maynard Cabiente 10 Jul '03

10 Jul '03

Hello, I am currently using u-boot version 0.4.0 for the MPC8260ADS board. I am trying to use the additional code in cpu/mpc8260/ether_fcc.c to do the ethernet loopback test. I already added the configuration for the MPC8260ADS to connect FCC's tx and rx clocks with the following code: #elif defined(CONFIG_MPC8260ADS) /* * Attention: this is board-specific (only using FCC2) * - FCC2 Rx-CLK is CLK13 * - FCC2 Tx-CLK is CLK14 */ /* 28.9 - (3): connect FCC's tx and rx clocks */ immr->im_cpmux.cmx_uar = 0; immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14; #else #error "eth_loopback_test not supported on your board" #endif Well, I compiled it and run the test itself by creating a command for it (just like ping or mtest) for my own testing and not through "post". Here's the questions. Does the eth_loopback_test() in cpu/mpc8260/ether_fcc.c needs to have a loopback cable connected to the ethernet port [crossing pin 1 (TX+) and pin 3 (RX+) together and cross pin 2 (TX-) and pin 6 (RX-) together]? Or is it supposed to be run connected directly to the network? I tried both ways and couldn't tell which one is correct or if I need to modify something else in the code to make it work properly. Both have Receive errors in it. (Are we supposed to get RX errors?) Any help is appreciated. Thanks.

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Re: [U-Boot-Users] U-boot on EP8260 Board
by Wolfgang Denk 10 Jul '03

10 Jul '03

In message <20030710152137.56D1143076(a)denx.de> you wrote: > Thanks for the tip. > Now I am using uImage file to boot MV Kernel from U-boot on Embedded Planet > EP8260 board. But it seems to be stuck after uncompressing: I think now it's time to read the Q&A section of http://www.denx.de/re/DPLG.html Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de Living on Earth may be expensive, but it includes an annual free trip around the Sun.

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Re: [U-Boot-Users] U-boot on EP8260 Board
by mss59＠att.net 10 Jul '03

10 Jul '03

Thanks for the tip. Now I am using uImage file to boot MV Kernel from U-boot on Embedded Planet EP8260 board. But it seems to be stuck after uncompressing: =>tftp 0x400000 uImage.ep8260 ARP broadcast 1 TFTP from server 10.0.0.1; our IP address is 10.0.0.2 Filename 'uImage.ep8260'. Load address: 0x400000 Loading: ################################################################# ############################################################### done Bytes transferred = 655335 (9ffe7 hex) => imi ## Checking Image at 00400000 ... Image Name: MV Linux Kernel Image for EP8260 Created: 2003-07-10 13:09:51 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 655271 Bytes = 639.9 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK => bootm 0x400000 ## Booting image at 00400000 ... Image Name: MV Linux Kernel Image for EP8260 Created: 2003-07-10 13:09:51 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 655271 Bytes = 639.9 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK Nothing happens after this. I tried to enable the Pipeline in the boot which results in some extra characters after "Uncompressing Kernel Image ... OK". I used following to make uImage.ep8260 file ../u-boot-0.3.0/tools/mkimage -A ppc -O linux -T kernel -C gzip -a 0 -e 0 - n "MV Linux Kernel Image for EP8260" - d /prj3/kernel/arch/ppc/boot/images/vmlinux.gz /tftpboot/uImage.ep8260 Thanks MSS// > In message <E19aLYj-0004yx-00(a)sc8-sf-list1.sourceforge.net> you wrote: > > I am using u-boot to boot an EP8260 board. However once I load/tftp Kernel ELF > > file to 0x400000 and try to run the kernel from 0x410000, it crashes... > > I used the same ELF file with Embedded planet's boot loader and it works fine. > > Any pointers.... > > Read the README. U-Boot does not use ELF files to boot Linux. > > > Wolfgang Denk > > -- > Software Engineering: Embedded and Realtime Systems, Embedded Linux > Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de > The human race is faced with a cruel choice: work or daytime tele- > vision.

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RE: [U-Boot-Users] Serial Port Configuration on MPC8xx
by Christophe.LINDHEIMER＠fr.thalesgroup.com 10 Jul '03

10 Jul '03

> > > > In fact when I change the baudrate of SMC1 in UBoot, I see > that the same > > baudrate remains used in the linux console ( am I getting > mad ?? :-)) ) > > This is just lucky coincidence if you happen to use the same serial > port for cosole in U-Boot and Linux. Normally, you will have to pass > the required information to the Linux kernel as a boot argument, like > "console=ttyS2,115200" > I am thinking that in the Bd_info there is a parameter indicating the baudrate of the serial lline. This value must be used by Linux to set up the console at the right baudrate even without using the console boot argument... > > So I thought that the IO Connfiguration & The BRG settings > was done only by > > UBoot. > > No, the philosophy is that each part of the software, each driver, is > responsible to initialize the hardware it accesses. So the LInux UART > driver will initialize the serial port(s) itself. > > > BTW, depending on the hardware the IO pins ( and the IO > Config ) are not the > > same and nothing in the linux config allow to choose > that... So it should > > There are some de-facto standard configurations, which are supported > by the Linux driver. > > > mean that the Linux Uart Driver should be patched depending on your > > hardware. > > Indeed. If your hardware guys decided to build some different confi- > guration, this may require to add some #ifdef's to the Linux kernel > code. If you have a look at the UART drivers in our kernel treee you > will see what I mean :-( Ok . I gonna see if I had to change something in the UART driver. Thanks. Chris

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RE: [U-Boot-Users] Serial Port Configuration on MPC8xx
by Christophe.LINDHEIMER＠fr.thalesgroup.com 10 Jul '03

10 Jul '03

Hi > > > Is there something clean to do under Uboot to make it > configure SMC2 ? > > Why should U-Boot initialize a port it does not use? > > > Where should this init done ? > > This should be done, and actually it _is_ done, in the Linux UART > driver. No help from U-Boot needed here. > > > Ummm... what exactly is the problem? > Hum I think that I don't understand something. In fact when I change the baudrate of SMC1 in UBoot, I see that the same baudrate remains used in the linux console ( am I getting mad ?? :-)) ) So I thought that the IO Connfiguration & The BRG settings was done only by UBoot. BTW, depending on the hardware the IO pins ( and the IO Config ) are not the same and nothing in the linux config allow to choose that... So it should mean that the Linux Uart Driver should be patched depending on your hardware. Chris

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[U-Boot-Users] Serial Port Configuration on MPC8xx
by Christophe.LINDHEIMER＠fr.thalesgroup.com 10 Jul '03

10 Jul '03

Hi. I use smc1 for the output of Uboot. So I set #define CONFIG_8xx_CONS_SMC1. In linux config I set SMC1 as my console output. I would like to use SMC2 in linux also. So I added use SMC2 as UART in linux conf. For the SMC1 it works fine as Uboot makes the config of the BRG and IO when CONFIG_8xx_CONS_SMC1 is set. But for SMC2 no config is done by Uboot and I can't set CONFIG_8xx_CONS_SMC2 & CONFIG_8xx_CONS_SMC1. Is there something clean to do under Uboot to make it configure SMC2 ? Where should this init done ? Thanks Regards Chris

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