July 2003 - U-Boot

[U-Boot-Users] loading linux in FADS860T board through u-boot-1.0.0
by RamanaYV 17 Mar '04

17 Mar '04

I was trying to load linux-2.4.4 in FADS860T board using u-boot-1.0.0. I have settted environment variables like ipaddr,serverip,ethaddr,bootargs bootfile and saved the environment. Then,i typed tftpboot to download image from server. Then,i typed bootm to start the booting process. System is stucked by showing "Uncompressing Kernel Image ... OK" sequence of these events r given below.can u please suggest, what i need to do to come out from this. Thank you. U-Boot 1.0.0 (Mar 17 2004 - 14:06:16) CPU: XPC86xxxZPnnD4 at 40 MHz: 4 kB I-Cache 4 kB D-Cache FEC present Board: FADS with db MPC821, MPC860 / MPC860SAR / MPC860T rev PILOT DRAM: (4 MB SDRAM) 4M 60ns DRAM: 8 MB FLASH: 2 MB In: serial Out: serial Err: serial Net: FEC ETHERNET =>printenv stdin=serial stdout=serial stderr=serial Environment size: 41/16380 bytes =>setenv ipaddr 192.168.1.115 =>setenv serverip 192.168.1.87 =>setenv ip 192.168.1.115 =>setenv ethaddr 00:30:bf:01:02:d0 =>setenv bootargs "root=/dev/nfs rw nfsroot=192.168.1.87:/opt/eldk/ppc8xx ip=192 .168.1.115:192.168.1.87:192.168.1.115:255.255.255.0:ppc::off" =>setenv bootfile "pImage_fads_fec" =>saveenv Saving Environment to Flash... Un-Protected 1 sectors Erasing Flash... . done Erased 1 sectors Writing to Flash... done Protected 1 sectors =>printenv stdin=serial stdout=serial stderr=serial ipaddr=192.168.1.115 serverip=192.168.1.87 ip=192.168.1.115 ethaddr=00:30:bf:01:02:d0 bootargs="root=/dev/nfs rw nfsroot=192.168.1.87:/opt/eldk/ppc8xx ip=192.168 1.11 5:192.168.1.87:192.168.1.115:255.255.255.0:ppc::off" bootfile="pImage_fads_fec" Environment size: 287/16380 bytes =>tftpboot TFTP from server 192.168.1.87; our IP address is 192.168.1.115 Filename 'pImage_fads_fec'. Load address: 0x100000 Loading: T invalid RARP header #####################################################TX timeout ############ ####################### done Bytes transferred = 448321 (6d741 hex) =>bootm ## Booting image at 00100000 . Image Name: Linux-2.4.4 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 448257 Bytes = 437.8 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK

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[U-Boot-Users] FADS860T board
by RamanaYV 17 Mar '04

17 Mar '04

I was trying to load linux-2.4.4 in FADS860T board using u-boot-1.0.0. i am getting the followin symptom, can anyone suggest to come out from this problem.. U-Boot 1.0.0 (Mar 17 2004 - 14:06:16) CPU: XPC86xxxZPnnD4 at 40 MHz: 4 kB I-Cache 4 kB D-Cache FEC present Board: FADS with db MPC821, MPC860 / MPC860SAR / MPC860T rev PILOT DRAM: (4 MB SDRAM) 4M 60ns DRAM: 8 MB FLASH: 2 MB In: serial Out: serial Err: serial Net: FEC ETHERNET =>printenv stdin=serial stdout=serial stderr=serial Environment size: 41/16380 bytes =>setenv ipaddr 192.168.1.115 =>setenv serverip 192.168.1.87 =>setenv ip 192.168.1.115 =>setenv ethaddr 00:30:bf:01:02:d0 =>setenv bootargs "root=/dev/nfs rw nfsroot=192.168.1.87:/opt/eldk/ppc8xx ip=192 .168.1.115:192.168.1.87:192.168.1.115:255.255.255.0:ppc::off" =>setenv bootfile "pImage_fads_fec" =>saveenv Saving Environment to Flash... Un-Protected 1 sectors Erasing Flash... . done Erased 1 sectors Writing to Flash... done Protected 1 sectors =>printenv stdin=serial stdout=serial stderr=serial ipaddr=192.168.1.115 serverip=192.168.1.87 ip=192.168.1.115 ethaddr=00:30:bf:01:02:d0 bootargs="root=/dev/nfs rw nfsroot=192.168.1.87:/opt/eldk/ppc8xx ip=192.168.1.11 5:192.168.1.87:192.168.1.115:255.255.255.0:ppc::off" bootfile="pImage_fads_fec" Environment size: 287/16380 bytes =>tftpboot TFTP from server 192.168.1.87; our IP address is 192.168.1.115 Filename 'pImage_fads_fec'. Load address: 0x100000 Loading: T invalid RARP header #####################################################TX timeout ############ ####################### done Bytes transferred = 448321 (6d741 hex) =>bootm ## Booting image at 00100000 ... Image Name: Linux-2.4.4 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 448257 Bytes = 437.8 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK Thanks to all.

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[U-Boot-Users] [PATCH] support for Intel IXP
by Kyle Harris 10 Oct '03

10 Oct '03

Wolfgang, Please find attached a patch for Intel CPU IXP425 and eval board IXDP425. This is applied against 0.4.0 (I tried several times to pull from CVS but failed, and finally gave up). Note: This patch does NOT include support for the PCI bridge :( Regards, Kyle.

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[U-Boot-Users] (no subject)
by C Doyle 27 Sep '03

27 Sep '03

Hello all, Ive been trying to compile u-boot0.4 for the mpc8266ads board. I am using the hardhat ppc-cross compiler and am coming across problems with the compilation. First of all make fails at a bootp error which can be fixed by placing parenthesis around the #define. It next fails in the examples folder where I think it is trying the hello_world.bin & others and this can be fixed by doing a chmod on each of the examples it fails on. Just wondering if anyone is coming across the same problems and if any official fixes are available for this? After I change these the project compiles ok. Cheers _________________________________________________________________ MSN 8 with e-mail virus protection service: 2 months FREE* http://join.msn.com/?page=features/virus

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[U-Boot-Users] u-boot on Memec P4/7-FG456 (w/ virtex II pro)?
by jds 12 Sep '03

12 Sep '03

hi, has anyone done any u-boot porting work for the Memec Virtex-II Pro P4/7-FG456 evaluation board? as you can see from the link below this is a development board which has the Virtex-II Pro (w/ single 405GP core) along with SDRAM, NV stroage via compact flash, and so forth. http://www.memec.com/cgi-bin/bvutf8/memec/scripts/local/manuDetailArticle.j… we are considering using this board as an R&D platfrom for an upcoming project. thanks! -- Perfection is reached, not when there is no longer anything to add, but when there is no longer anything to take away. - Antoine de Saint-Exupery

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[U-Boot-Users] Linux kernel crash in the early_init function
by llandre 28 Aug '03

28 Aug '03

I have a problem with U-Boot on the 405EP eval. board. Everything works fine until the kernel takes control and the system hangs: ------------------------------------------------------------------------------------ U-Boot 0.2.0 (May 6 2003 - 12:04:15) CPU: IBM PowerPC 405EP Rev. A at 266.666 MHz (PLB=133, OPB=66, EBC=66 MHz) PCI async ext clock used (sync mode not supported), internal PCI arbd 16 kB I-Cache 16 kB D-Cache Board: ### No HW ID - assuming WALNUT405 I2C: ready DRAM: 128 MB Top of RAM usable for U-Boot at: 08000000 Reserving 192k for U-Boot at: 07fd0000 Reserving 132k for malloc() at: 07faf000 Reserving 112 Bytes for Board Info at: 07faef90 Reserving 44 Bytes for Global Data at: 07faef64 Stack Pointer at: 07faef48 New Stack Pointer is: 07faef48 Now running in RAM - U-Boot at: 07fd0000 FLASH: 512 kB [board.c, 767] Calling env_relocate ... env_relocate[203] offset = 0x8050000 env_relocate[221] malloced ENV at 07faf008 In: serial Out: serial Err: serial KGDB: kgdb ready ready U-Boot relocated to 07fd0000 [board.c, 913] Calling interrupt_init ... ### main_loop entered: bootdelay=3 ### main_loop: bootcmd="tftpboot 0x400000 vmlinux.PPCBoot" Hit any key to stop autoboot: 0 ENET Speed is 10 Mbps - HALF duplex connection TX_BUFF 0 @ 0x07fb0228 RX_BUFF 0 @ 0x07ff3fc0 RX_BUFF 1 @ 0x07ff45c0 RX_BUFF 2 @ 0x07ff4bc0 RX_BUFF 3 @ 0x07ff51c0 Install interrupt for vector 9 ==> 07fd49c0 Install interrupt for vector 10 ==> 07fd49c0 Install interrupt for vector 11 ==> 07fd49c0 Install interrupt for vector 12 ==> 07fd49c0 Install interrupt for vector 13 ==> 07fd49c0 Install interrupt for vector 14 ==> 07fd49c0 Install interrupt for vector 15 ==> 07fd49c0 ARP broadcast 1 Got good ARP - start TFTP TFTP from server 192.168.10.6; our IP address is 192.168.10.203 Filename 'vmlinux.PPCBoot'. Load address: 0x400000 Loading: ################################################################# ######################################### done Bytes transferred = 539758 (83c6e hex) Automatic boot of image at addr 0x00400000 ... ## Booting image at 00400000 ... Image Name: Linux-2.4.21-pre5 Created: 2003-05-06 11:42:31 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 539694 Bytes = 527 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK ## Current stack ends at 0x07FAE5B8 => set upper limit to 0x00800000 ## cmdline at 0x007FFC00 ... 0x007FFC16 bd address = 0x07FAEF90 memstart = 0x00000000 memsize = 0x08000000 flashstart = 0xFFF80000 flashsize = 0x00080000 flashoffset = 0x00030000 sramstart = 0x00000000 sramsize = 0x00000000 bootflags = 0x6BBA3A55 procfreq = 266.666 MHz plb_busfreq = 133.333 MHz pci_busfreq = 33.333 MHz ethaddr = 00:50:C2:1E:AF:FE IP addr = 192.168.10.203 baudrate = 115200 bps No initrd ## Transferring control to Linux (at address 00000000) ... ------------------------------------------------------------------------------------ I found that the function memset_io, invoked by early_init, corrupts the memory region where the function identify_cpu is located. This is the disassembled produced by objdump: c0006774 <identify_cpu>: c0006774: 3d 03 c0 12 addis r8,r3,-16366 c0006778: 39 08 e1 40 addi r8,r8,-7872 c000677c: 7c ff 42 a6 mfpvr r7 c0006780: 80 a8 00 00 lwz r5,0(r8) c0006784: 7c a5 38 38 and r5,r5,r7 c0006788: 80 c8 00 04 lwz r6,4(r8) c000678c: 7c 06 28 40 cmplw r6,r5 c0006790: 41 82 00 0c beq- c000679c <identify_cpu+0x28> c0006794: 39 08 00 20 addi r8,r8,32 c0006798: 4b ff ff e8 b c0006780 <identify_cpu+0xc> c000679c: 3c c3 c0 14 addis r6,r3,-16364 c00067a0: 38 c6 f0 bc addi r6,r6,-3908 c00067a4: 54 84 10 3a rlwinm r4,r4,2,0,29 c00067a8: 7d 03 40 50 subf r8,r3,r8 c00067ac: 7d 04 31 2e stwx r8,r4,r6 c00067b0: 4e 80 00 20 blr This is what I see in memory before executing the memset_io: PPC405EP>go - TARGET: target has entered debug mode PPC405EP>md 0xc0006774 8 c0006774 : 0x3d03c012 1023655954 =... c0006778 : 0x3908e140 956883264 9..@ c000677c : 0x7cff42a6 2097103526 |.B. c0006780 : 0x80a80000 -2136473600 .... c0006784 : 0x7ca53838 2091202616 |.88 c0006788 : 0x80c80004 -2134376444 .... c000678c : 0x7c062840 2080778304 |.(@ c0006790 : 0x4182000c 1099038732 A... PPC405EP>go - TARGET: target has entered debug mode This is what I see in memory after executing the memset_io: PPC405EP>md 0xc0006774 8 c0006774 : 0xff03ffff - 16515073 .... c0006778 : 0xff08ffff - 16187393 .... c000677c : 0xff08ffff - 16187393 .... c0006780 : 0x80a80000 -2136473600 .... c0006784 : 0x7ca53838 2091202616 |.88 c0006788 : 0x80c80004 -2134376444 .... c000678c : 0x3c060840 1007028288 <..@ c0006790 : 0x7c062840 2080778304 |.(@ PPC405EP> Anybody have already seen something like that? Is it possible that this has to do with an erroneous cache initialization? Many thanks in advance. llandre

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[U-Boot-Users] DiscoveryII (Marvell MV64360) support?
by wombat＠ottawa.com 18 Aug '03

18 Aug '03

Hi folks, I was just curious what the status of (Marvell MV64360). I've looked around, and grabbed the latest 'u-boot' cvs snapshot and don't see any DISCOII support. I do see DISCOI (marvell 64260) support in include/galileo/*. Does anyone have plans to add that support to 'u-boot'? Doing some looking around, the only thing I could find was that Artesyn seems to have a cPCI PPC board with both DISCOII & 'ppcboot' (on their webpage, they probably haven't updated the webpage and they mean u-boot). http://www.artesyncp.com/products/Katana750i.html Any information would be greatly appreciated. thanks, Craig.

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[U-Boot-Users] Function pointers after relocation
by Robin Gilks 03 Aug '03

03 Aug '03

Greetings When u-boot has relocated from Flash to RAM, it is correct that function pointers (eg. getenv()) still point to the Flash code rather than the RAM copy? Would this be corrected by changing the link address, in which case where do I find it (the link address that is) - in the .lds file? board = mpc866ads (fads alike) cpu = mpc866 (mpc860 alike) all changes based on ads860+fads merge!! -- Robin Gilks Senior Design Engineer Phone: (+64)(3) 357 1569 Tait Electronics Fax : (+64)(3) 359 4632 PO Box 1645 Christchurch Email : robin.gilks(a)tait.co.nz New Zealand

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[U-Boot-Users] Compiling U-boot using ELDK on Mandrake9.1
by C Doyle 31 Jul '03

31 Jul '03

Hello, I am a student trying to get u-boot0.4.0 up and running on an MPC8266ADS board using ELDK as a cross compiler. I managed to get the ELDK installed what seems to be problem free. I am trying to cross compile u-boot0.4.0 for the MPC8266ADS development board. I have a Host PC running Mandrake 9.1 which I notice is about the only distribution that eldk has not been tested with. Has anyone managed to get u-boot0.4.0 compiled on Mandrake or can anyone tell me what the problem is in the astest.o symbol at the end of the Makefile output below? There seems to be some problem with the /opt/eldk/ppc_82xx/usr/lib/libbfd.so. Previously I have used a hardhat cross-compiler and noticed that it was using /libbfd.a as opposed to /libbfd.so. Do I need to export the symbols from libbfd.so? Any help would be greatly appreciated... Thanks, Ciaran Doyle I have made the following changes to the root dir Makefile: HOSTARCH := ppc ifndef CROSS_COMPILE ifeq ($(HOSTARCH),ppc) CROSS_COMPILE = /opt/eldk/usr/bin/ppc_82xx- else ifeq ($(ARCH),ppc) CROSS_COMPILE = ppc_8xx- endif And in the ./tools/gdb/Makefile I have updated the path as follows: astest: astest.o error.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ -L$(BFD_ROOT_DIR)/lib -L /opt/eldk/ppc_82xx/usr/lib -lbfd -liberty I run the configuration script for u-boot0.4.0 [root@MPC8266 u-boot-0.4.0]# make MPC8266ADS_config rm -f include/config.h include/config.mk Configuring for MPC8266ADS board... -Followed by a make all (sorry for including all of the make output - just in case theres any clues in it): [root@MPC8266 u-boot-0.4.0]# make all make[1]: Entering directory `/u-boot-0.4.0/tools' ln -s ../common/environment.c environment.c ln -s ../lib_generic/crc32.c crc32.c gcc -M -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC environment.c img2srec.c mkimage.c crc32.c envcrc.c gen_eth_addr.c bmp_logo.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/tools' make[1]: Entering directory `/u-boot-0.4.0/tools' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/tools' make[1]: Entering directory `/u-boot-0.4.0/lib_generic' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes crc32.c ctype.c display_options.c ldiv.c string.c vsprintf.c zlib.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/lib_generic' make[1]: Entering directory `/u-boot-0.4.0/lib_generic' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/lib_generic' make[1]: Entering directory `/u-boot-0.4.0/lib_ppc' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes ppcstring.S ticks.S board.c bat_rw.c cache.c extable.c kgdb.c time.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/lib_ppc' make[1]: Entering directory `/u-boot-0.4.0/lib_ppc' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/lib_ppc' make[1]: Entering directory `/u-boot-0.4.0/cpu/mpc8260' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes start.S kgdb.S traps.c serial_smc.c serial_scc.c cpu.c cpu_init.c speed.c interrupts.c ether_scc.c ether_fcc.c i2c.c commproc.c bedbug_603e.c pci.c spi.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/cpu/mpc8260' make[1]: Entering directory `/u-boot-0.4.0/cpu/mpc8260' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/cpu/mpc8260' make[1]: Entering directory `/u-boot-0.4.0/board/mpc8266ads' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board mpc8266ads.c flash.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/board/mpc8266ads' make[1]: Entering directory `/u-boot-0.4.0/board/mpc8266ads' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/board/mpc8266ads' make[1]: Entering directory `/u-boot-0.4.0/common' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes main.c altera.c bedbug.c cmd_autoscript.c cmd_bedbug.c cmd_bmp.c cmd_boot.c cmd_bootm.c cmd_cache.c cmd_console.c cmd_date.c cmd_dcr.c cmd_diag.c cmd_doc.c cmd_nand.c cmd_dtt.c cmd_eeprom.c cmd_elf.c cmd_fat.c cmd_fdc.c cmd_fdos.c cmd_flash.c cmd_fpga.c cmd_i2c.c cmd_ide.c cmd_immap.c cmd_jffs2.c cmd_log.c cmd_mem.c cmd_mii.c cmd_misc.c cmd_mmc.c cmd_net.c cmd_nvedit.c env_common.c env_flash.c env_eeprom.c env_nvram.c env_nowhere.c cmd_pci.c cmd_pcmcia.c cmd_portio.c cmd_reginfo.c cmd_scsi.c cmd_vfd.c cmd_usb.c command.c console.c devices.c dlmalloc.c docecc.c environment.c flash.c fpga.c hush.c kgdb.c lists.c miiphybb.c miiphyutil.c s_record.c soft_i2c.c soft_spi.c cmd_spi.c spartan2.c usb.c usb_kbd.c usb_storage.c virtex2.c xilinx.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/common' make[1]: Entering directory `/u-boot-0.4.0/common' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/common' make[1]: Entering directory `/u-boot-0.4.0/disk' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes part.c part_mac.c part_dos.c part_iso.c part_amiga.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/disk' make[1]: Entering directory `/u-boot-0.4.0/disk' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/disk' make[1]: Entering directory `/u-boot-0.4.0/fs' make[2]: Entering directory `/u-boot-0.4.0/fs/jffs2' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes jffs2_1pass.c compr_rtime.c compr_rubin.c compr_zlib.c mini_inflate.c > .depend make[2]: Leaving directory `/u-boot-0.4.0/fs/jffs2' make[2]: Entering directory `/u-boot-0.4.0/fs/jffs2' make[2]: `.depend' is up to date. make[2]: Leaving directory `/u-boot-0.4.0/fs/jffs2' make[2]: Entering directory `/u-boot-0.4.0/fs/fdos' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes fat.c vfat.c dev.c fdos.c fs.c subdir.c > .depend make[2]: Leaving directory `/u-boot-0.4.0/fs/fdos' make[2]: Entering directory `/u-boot-0.4.0/fs/fdos' make[2]: `.depend' is up to date. make[2]: Leaving directory `/u-boot-0.4.0/fs/fdos' make[2]: Entering directory `/u-boot-0.4.0/fs/fat' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I../..//include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I../..//board -Wall -Wstrict-prototypes fat.c file.c > .depend make[2]: Leaving directory `/u-boot-0.4.0/fs/fat' make[2]: Entering directory `/u-boot-0.4.0/fs/fat' make[2]: `.depend' is up to date. make[2]: Leaving directory `/u-boot-0.4.0/fs/fat' make[1]: Leaving directory `/u-boot-0.4.0/fs' make[1]: Entering directory `/u-boot-0.4.0/net' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes net.c tftp.c bootp.c rarp.c eth.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/net' make[1]: Entering directory `/u-boot-0.4.0/net' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/net' make[1]: Entering directory `/u-boot-0.4.0/rtc' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes date.c ds12887.c ds1302.c ds1306.c ds1307.c ds1337.c ds1556.c ds164x.c ds174x.c m41t11.c m48t35ax.c mc146818.c mk48t59.c mpc8xx.c pcf8563.c s3c24x0_rtc.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/rtc' make[1]: Entering directory `/u-boot-0.4.0/rtc' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/rtc' make[1]: Entering directory `/u-boot-0.4.0/dtt' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes lm75.c ds1621.c adm1021.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/dtt' make[1]: Entering directory `/u-boot-0.4.0/dtt' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/dtt' make[1]: Entering directory `/u-boot-0.4.0/drivers' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes 3c589.c 5701rls.c ali512x.c bcm570x.c bcm570x_autoneg.c cfb_console.c cs8900.c ct69000.c dataflash.c dc2114x.c e1000.c eepro100.c i8042.c i82365.c inca-ip_sw.c lan91c96.c natsemi.c ns16550.c ns8382x.c ns87308.c pci.c pci_auto.c pci_indirect.c pcnet.c plb2800_eth.c s3c24x0_i2c.c sed13806.c serial.c serial_max3100.c smc91111.c smiLynxEM.c sym53c8xx.c ti_pci1410a.c tigon3.c w83c553f.c status_led.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/drivers' make[1]: Entering directory `/u-boot-0.4.0/drivers' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/drivers' make[1]: Entering directory `/u-boot-0.4.0/post' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes cache_8xx.S post.c tests.c cpu.c rtc.c watchdog.c memory.c i2c.c cache.c sysmon.c uart.c ether.c usb.c spr.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/post' make[1]: Entering directory `/u-boot-0.4.0/post' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/post' make[1]: Entering directory `/u-boot-0.4.0/post/cpu' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes asm.S cmp.c cmpi.c two.c twox.c three.c threex.c threei.c andi.c srawi.c rlwnm.c rlwinm.c rlwimi.c store.c load.c cr.c b.c multi.c string.c complex.c > .depend make[1]: Leaving directory `/u-boot-0.4.0/post/cpu' make[1]: Entering directory `/u-boot-0.4.0/post/cpu' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/post/cpu' make[1]: Entering directory `/u-boot-0.4.0/examples' /opt/eldk/usr/bin/ppc_82xx-gcc -M -g -Os -mrelocatable -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/include -fno-builtin -nostdinc -isystem /opt/eldk/usr/lib/gcc-lib/ppc-linux/2.95.4/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_8260 -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -mmultiple -DTEXT_BASE=0xfe000000 -I/u-boot-0.4.0/board -Wall -Wstrict-prototypes hello_world.c sched.c mem_to_mem_idma2intr.c syscall.S ppc_longjmp.S ppc_setjmp.S > .depend make[1]: Leaving directory `/u-boot-0.4.0/examples' make[1]: Entering directory `/u-boot-0.4.0/examples' make[1]: `.depend' is up to date. make[1]: Leaving directory `/u-boot-0.4.0/examples' make[1]: Entering directory `/u-boot-0.4.0/tools' gcc -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -c -o img2srec.o img2srec.c gcc -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -o img2srec img2srec.o strip img2srec gcc -g -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -c mkimage.c gcc -g -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -c crc32.c gcc -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -o mkimage mkimage.o crc32.o strip mkimage gcc -g -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -c envcrc.c gcc -g -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -c environment.c gcc -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -o envcrc envcrc.o crc32.o environment.o gcc -g -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -c gen_eth_addr.c gcc -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -o gen_eth_addr gen_eth_addr.o strip gen_eth_addr gcc -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -c -o bmp_logo.o bmp_logo.c gcc -Wall -pedantic -I../include -I.. -DTEXT_BASE=0xfe000000 -DUSE_HOSTCC -O -o bmp_logo bmp_logo.o strip bmp_logo ./bmp_logo logos/denx.bmp >/u-boot-0.4.0/include/bmp_logo.h make[2]: Entering directory `/u-boot-0.4.0/tools/gdb' gcc -M -I/opt/eldk/ppc_82xx/include -I../include gdbsend.c gdbcont.c astest.c error.c remote.c serial.c > .depend make[2]: Leaving directory `/u-boot-0.4.0/tools/gdb' make[2]: Entering directory `/u-boot-0.4.0/tools/gdb' gcc -Wall -pedantic -O -I/opt/eldk/ppc_82xx/include -I /opt/eldk/ppc_82xx/lib -c -o gdbsend.o gdbsend.c gcc -Wall -pedantic -O -I/opt/eldk/ppc_82xx/include -I /opt/eldk/ppc_82xx/lib -c -o error.o error.c gcc -Wall -pedantic -O -I/opt/eldk/ppc_82xx/include -I /opt/eldk/ppc_82xx/lib -c -o remote.o remote.c gcc -Wall -pedantic -O -I/opt/eldk/ppc_82xx/include -I /opt/eldk/ppc_82xx/lib -c -o serial.o serial.c gcc -Wall -pedantic -O -I/opt/eldk/ppc_82xx/include -I /opt/eldk/ppc_82xx/lib -o gdbsend gdbsend.o error.o remote.o serial.o gcc -Wall -pedantic -O -I/opt/eldk/ppc_82xx/include -I /opt/eldk/ppc_82xx/lib -c -o gdbcont.o gdbcont.c gcc -Wall -pedantic -O -I/opt/eldk/ppc_82xx/include -I /opt/eldk/ppc_82xx/lib -o gdbcont gdbcont.o error.o remote.o serial.o gcc -Wall -pedantic -O -I/opt/eldk/ppc_82xx/include -I /opt/eldk/ppc_82xx/lib -c -o astest.o astest.c gcc -Wall -pedantic -O -I/opt/eldk/ppc_82xx/include -I /opt/eldk/ppc_82xx/lib -o astest astest.o error.o -L/opt/eldk/ppc_82xx/lib -L /opt/eldk/ppc_82xx/usr/lib -lbfd -liberty /opt/eldk/ppc_82xx/usr/lib/libbfd.so: could not read symbols: Invalid operation collect2: ld returned 1 exit status make[2]: *** [astest] Error 1 make[2]: Leaving directory `/u-boot-0.4.0/tools/gdb' make[1]: *** [subdirs] Error 1 make[1]: Leaving directory `/u-boot-0.4.0/tools' make: *** [subdirs] Error 1 [root@MPC8266 u-boot-0.4.0]# _________________________________________________________________ Add photos to your e-mail with MSN 8. Get 2 months FREE*. http://join.msn.com/?page=features/featuredemail

2 1

[U-Boot-Users] Using MPC8xx SCC?
by Steven Scholz 31 Jul '03

31 Jul '03

Hi there, I have a display connected to SCC1 and want to display some boot message while the real console for U-Boot and Linux should be SMC1? What would be the best way to do so? Thanks a million, Steven

1 0

[U-Boot-Users] help in customizing uboot for inhouse board
by nikhil bhargav 31 Jul '03

31 Jul '03

hello friends, I am currently working on customization of uboot for inhouse mpc 860 based board. I have studied my board parameters and mpc 860 manuals and currently studying the source code of uboot. I am closely following the queries n solutions in this group. My problem is how to get started in modifying the code as per my board. Any pointers regarding this will help me to get the process kicked. bye, nikhil Nikhil Bhargav, Research Engineer, IMT - 2000 CDOT, Delhi India ___________________________________________________ Download the hottest & happening ringtones here! OR SMS: Top tone to 7333 Click here now: http://sms.rediff.com/cgi-bin/ringtone/ringhome.pl

2 1

[U-Boot-Users] [Q] mpc8245 PortX
by 배장식 31 Jul '03

31 Jul '03

i want to access extended rom area (0x70000000) in mpc8245 sandpoint board (ARTis Microsystems A-3000) i tried to reallocate BAT1(initial stack area ) 0x40000000 to 0x70000000 but board was hang... i wrote BAT1 reallocation function and call BAT1 reallocation function in board.c ( board_init_r () ) void move_bat1 (void) { mtspr (IBAT1L, (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)); mtspr (IBAT1U, (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)); mtspr (DBAT1L, (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)); mtspr (DBAT1U, (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)); __asm__ __volatile__("eieio"); __asm__ __volatile__("isync"); __asm__ __volatile__("sync"); } i think ram use stack at this function so 0x40000000 nerver accessed what's wrong... :-(( ^^ best regard~~

1 0

[U-Boot-Users] ep7312 address problem
by pure lau 31 Jul '03

31 Jul '03

Hi all: Now I am working on a EP7312 board with uboot and I have been blocked by a unknown problem for several week.Before descride the problem,let me intrduce my working flow. I compile u-boot under rh linux 7.3 with cross-compile tools download from arm.linux.org.uk. At the time I get u-boot.bin via cross-compile, I generate u-boot.asm by "arm-linux-objdump -d u-boot > u-boot.asm" Then program the u-boot.bin to flash(sst29vf040) with programmer. Switch the ep7312 board to external boot mode ,and begin boot. I use ICE and ADS 1.2 to trace how the board works.And I can trace that u-boot has init the ep7312 board and has relocated it self form flash(0x0) to sdram (0xc0f00000). The following is a piece of code in the sdram: (near the start of <start_armboot>) ------------------------------------------------ c0f00a50: [0xe92d40f0] stmfd r13!,{r4-r7,r14} c0f00a54: [0xe24dd088] sub r13,r13,#0x88 c0f00a58: [0xe28d8068] add r8,r13,#0x68 c0f00a5c: [0xe1a00008] mov r0,r8 c0f00a60: [0xe3a01000] mov r1,#0 c0f00a64: [0xe3a02020] mov r2,#0x20 c0f00a68: [0xeb002826] bl 0xc0f0ab08 ------------------------------------------------- please note the last line :(wrong,u-boot crashes here) ------------------------------------------------- c0f00a68: [0xeb002826] bl 0xc0f0ab08 ------------------------------------------------- In u-boot.asm and in flash ,this piece of code was: ------------------------------------------------- c0f00a50 <start_armboot>: c0f00a50: e92d40f0 stmdb sp!, {r4, r5, r6, r7, lr} c0f00a54: e24dd088 sub sp, sp, #136 ; 0x88 c0f00a58: e28d8068 add r8, sp, #104 ; 0x68 c0f00a5c: e1a00008 mov r0, r8 c0f00a60: e3a01000 mov r1, #0 ; 0x0 c0f00a64: e3a02020 mov r2, #32 ; 0x20 c0f00a68: eb002926 bl c0f0af08 <memset> ------------------------------------------------- where the last line was :(right,u-boot jump to <memset>) ------------------------------------------------- c0f00a68: eb002926 bl c0f0af08 <memset> ------------------------------------------------- we can compare the wrong and right line and find that the two BL address have a discrepancy of 0x400. (c0f0ab08 and c0f0af08).This makes u-boot to crash. I have been blocked here for several weeks.The content of u-boot.asm seems all right and in flash it does.But why after relocating to sdram the BL operating number subtracts 0x400? ------------------------------------------------------ the detailed info of my ep7312 board is as follows: cpu : EP7312 sdram: (4 bank * 1M * 16 bit) * 2 flash: 512k * 8 bit cs0 has been set to 8bit,slowest. ep7312.h and memsetup.S also attached. ------------------------------------------------------- Any one can help? Thanks in advance! Pure _________________________________________________________________ 与联机的朋友进行交流，请使用 MSN Messenger: http://messenger.msn.com/cn

1 0

[U-Boot-Users] ep7312 address problem
by pure lau 31 Jul '03

31 Jul '03

Hi all: Now I am working on a EP7312 board with uboot and I have been blocked by a unknown problem for several week.Before descride the problem,let me intrduce my working flow. I compile u-boot under rh linux 7.3 with cross-compile tools download from arm.linux.org.uk. At the time I get u-boot.bin via cross-compile, I generate u-boot.asm by "arm-linux-objdump -d u-boot > u-boot.asm" Then program the u-boot.bin to flash(sst29vf040) with programmer. Switch the ep7312 board to external boot mode ,and begin boot. I use ICE and ADS 1.2 to trace how the board works.And I can trace that u-boot has init the ep7312 board and has relocated it self form flash(0x0) to sdram (0xc0f00000). The following is a piece of code in the sdram: (near the start of <start_armboot>) ------------------------------------------------ c0f00a50: [0xe92d40f0] stmfd r13!,{r4-r7,r14} c0f00a54: [0xe24dd088] sub r13,r13,#0x88 c0f00a58: [0xe28d8068] add r8,r13,#0x68 c0f00a5c: [0xe1a00008] mov r0,r8 c0f00a60: [0xe3a01000] mov r1,#0 c0f00a64: [0xe3a02020] mov r2,#0x20 c0f00a68: [0xeb002826] bl 0xc0f0ab08 ------------------------------------------------- please note the last line :(wrong,u-boot crashes here) ------------------------------------------------- c0f00a68: [0xeb002826] bl 0xc0f0ab08 ------------------------------------------------- In u-boot.asm and in flash ,this piece of code was: ------------------------------------------------- c0f00a50 <start_armboot>: c0f00a50: e92d40f0 stmdb sp!, {r4, r5, r6, r7, lr} c0f00a54: e24dd088 sub sp, sp, #136 ; 0x88 c0f00a58: e28d8068 add r8, sp, #104 ; 0x68 c0f00a5c: e1a00008 mov r0, r8 c0f00a60: e3a01000 mov r1, #0 ; 0x0 c0f00a64: e3a02020 mov r2, #32 ; 0x20 c0f00a68: eb002926 bl c0f0af08 <memset> ------------------------------------------------- where the last line was :(right,u-boot jump to <memset>) ------------------------------------------------- c0f00a68: eb002926 bl c0f0af08 <memset> ------------------------------------------------- we can compare the wrong and right line and find that the two BL address have a discrepancy of 0x400. (c0f0ab08 and c0f0af08).This makes u-boot to crash. I have been blocked here for several weeks.The content of u-boot.asm seems all right and in flash it does.But why after relocating to sdram the BL operating number subtracts 0x400? ------------------------------------------------------ the detailed info of my ep7312 board is as follows: cpu : EP7312 sdram: (4 bank * 1M * 16 bit) * 2 flash: 512k * 8 bit cs0 has been set to 8bit,slowest. ep7312.h and memsetup.S also attached. ------------------------------------------------------- Any one can help? Thanks in advance! Pure _________________________________________________________________ 与联机的朋友进行交流，请使用 MSN Messenger: http://messenger.msn.com/cn

1 0

[U-Boot-Users] mpc8245 Portx BAT setting...
by 배장식 31 Jul '03

31 Jul '03

I have tried to configure PortX for use of memory space 0x7000_0000. I have modified MCCR4[EXTROM] to enable entened ROM. but i can't accessed address 0x70000000 ... i find something worng in include/config_Sandpint8245.h according to define BATs in config_Sandpint8245.h not allocate BATs for address 0x7000000 , so i try change BAT1 for extended rom i modify ppcboot code to blow list 1. 0x40000000 used by initial stack , until sdram init....(BAT1 allocation) 2. command/board.c : board_init_r () this function use stack...in ram so no more need 0x40000000 3. my added code to BAT1 realloction for 0x70000000.. void move_bat1 (void) { mtspr (IBAT1L, (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)); mtspr (IBAT1U, (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)); mtspr (DBAT1L, (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)); mtspr (DBAT1U, (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)); __asm__ __volatile__("eieio"); __asm__ __volatile__("isync"); __asm__ __volatile__("sync"); } 4. call move_bat1 at board_init_r ...... but...board not working.....

3 2

[U-Boot-Users] [Q]MPC8245 Extended Rom Setting
by 배장식 31 Jul '03

31 Jul '03

i want to access extended rom area (0x70000000) in mpc8245 sandpoint board (ARTis Microsystems A-3000) i tried to reallocate BAT1(initial stack area ) 0x40000000 to 0x70000000 but board was hang... i wrote BAT1 reallocation function and call BAT1 reallocation function in board.c ( board_init_r () ) void move_bat1 (void) { mtspr (IBAT1L, (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)); mtspr (IBAT1U, (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)); mtspr (DBAT1L, (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)); mtspr (DBAT1U, (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)); __asm__ __volatile__("eieio"); __asm__ __volatile__("isync"); __asm__ __volatile__("sync"); } i think ram use stack at this function so 0x40000000 nerver accessed what's wrong... :-(( ^^ best regard~~

1 0

RE: [U-Boot-Users] PATCH : Allow dhcp to get IP address from and keep other env data .
by Woodruff, Richard 30 Jul '03

30 Jul '03

Yes that's ok. I think most of those fields in dhcp are optional, as a client I think you can even send requests with them included as suggestions to the server. A while ago I had some similar issues with the kernel's built in dhcp code and had read though the RFC back then, but its been a while (my problem then was ATAGS were not being set properly thus overrides were not being processed correctly). The kernel does allow you to dhcp for an address and allows overrides with what ever the dhcp server sends back via boot/init parameters. I would think u-boot should do the same. The issue with u-boot would seem to be which and "when" environment variable parameters should override dhcp server reply information. I was taking the stance that if you have sent them in env then the code should use them even if they are NOT reasonable. Effort could be made to check and see if variables from the environment and reply are reasonable before setting them, but that seems like to much work at this level....and the desired functionality can be obtained and now has been sort of documented in discussion. Regards, Richard W. > -----Original Message----- > From: Wolfgang Denk [mailto:wd@denx.de] > Sent: Wednesday, July 30, 2003 10:35 AM > To: Woodruff, Richard > Cc: u-boot-users(a)lists.sourceforge.net > Subject: Re: [U-Boot-Users] PATCH : Allow dhcp to get IP > address from and keep other env data . > > > In message > <FD2AC9A020DDD51194710008C7089B200BEE2232(a)dlee17.itg.ti.com> > you wrote: > > > > Yes, this does work. I hadn't considered this sequence. In > some sense > > it's as much a workaround as a valid solution. The flexibility of > > having a shell like interpreter goes a long way. I will > likely stick > > with my code to keeps the steps down. > > I'm not sure what standard behaviour for DHCP requires - for > now, I think I will not change the code. Is this OK with you? > > > Best regards, > > Wolfgang Denk > > -- > Software Engineering: Embedded and Realtime Systems, Embedded Linux > Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: > wd(a)denx.de One of the advantages of being a captain is being > able to ask for ad- vice without necessarily having to take it. > -- Kirk, "Dagger of the Mind", stardate 2715.2 >

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RE: [U-Boot-Users] PATCH : Allow dhcp to get IP address from and keep other env data .
by Woodruff, Richard 30 Jul '03

30 Jul '03

Hi Wolfgang, Yes, this does work. I hadn't considered this sequence. In some sense it's as much a workaround as a valid solution. The flexibility of having a shell like interpreter goes a long way. I will likely stick with my code to keeps the steps down. Best Regards, Richard W. > -----Original Message----- > From: Wolfgang Denk [mailto:wd@denx.de] > > > > => setenv my_bootfile "/tftpboot/foo" > > => setenv my_tftpserver XXX.XXX.XXX.XXX > > => saveenv > > > > => setenv autoload no > > => dhcp > > => setenv serverip $(my_tftpserver) > > => tftp 200000 $(my_bootfile) > > Doesn't this work for you?

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RE: [U-Boot-Users] PATCH : Allow dhcp to get IP address from and keep other env data .
by Woodruff, Richard 30 Jul '03

30 Jul '03

Wolfgang, Seems to be some misunderstanding here. For the site I'm working at the global network is administrated by people in another location, and for some things in another city. All my "work" computers get their IP address via dhcp. If for convience sake I want to use my embedded target on the main network (its common for me to just NFS mount my development system for a built in root, or shared file system), all I can do easily is to use a static IP address which I either assign in a semi-unsafe way, or request one and wait. This works fine for just one person in small scale but when any number of people want to develop in a similar way things start to get messy. A dhcp server on my own machine with a lot of careful settings could be set up on my work station, however the networking administrators are very paranoid about running dhcp servers on the live network....and with some reason....hundreds of machines have been brought down in the past by people trying and mis-configuring. A second and more correct alternative, is to set up private networks off of workstations, unfortunately not all workstations are created equal in the number of interfaces they are shipped with, and even if they were its more effort to set up routing and the like to get it working properly. So, the shorter term and easier approach is to run a tftpserver on a workstation on the main network to deliver files, AND just use the main networks dhcp server for a valid IP address & netmask & gateway information. Now here is where u-boot comes in ... If I issue the dhcp command, the global dhcp server will NOT fill in bootfile name and the server name fields in optional fields. HOWEVER, the u-boot code _DOES_ write the NULLs back to the defaults (beneath the env names) making them unusable. ... the variable BootFile in memory always gets the first path argument stomped, and the server is zero'ed and not set. So, the patch I applied allows me to use the global dhcp server which I can ONLY ask address of, to give a valid address, and my environment variables allow resolution of my tftpserver and bootfile name. and all in one command. Hopefully this is clear, Regards, Richard W. -----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Wednesday, July 30, 2003 2:13 AM To: Woodruff, Richard Cc: u-boot-users(a)lists.sourceforge.net Subject: Re: [U-Boot-Users] PATCH : Allow dhcp to get IP address from and keep other env data . Dear Richard, in message <FD2AC9A020DDD51194710008C7089B200BEE2230(a)dlee17.itg.ti.com> you wrote: > > This small patch adds the conditional DHCP_IP_ADDR_ONLY . This allows > someone to use the dhcp command to load a file on a network where you DON'T > have access to the dhcp server, but would like to use it to have fast > downloads of development kernels or other files. I have to admit that I don't understand this sentence. How can you use "it" (the dhcp server?), when you don't have access to it? > Prior to this patch the the reply packet would trash your environment > settings for bootfile and serverip will not be used when issuing the dhcp Sorry, but I disagree. Those variables will be _set_, not trashed. And only if your DHCP server transmits this sort of ionformation. If you don't want it, don't send it, i. e. configure your DHCP server not to send it. > command. By adding the CFG_DHCP_CMD, along with DHCP_IP_ADDR_ONLY in your > board config file you can use your company network server to get your file. > The ip,gateway,netmask still are gotten from the dhcp reply. I can see no need for this. If I understand you correctly, you want to use DHCP to configure the network interface, yet download by TFTP from a different server. Did you thy something like this: => setenv my_bootfile "/tftpboot/foo" => setenv my_tftpserver XXX.XXX.XXX.XXX => saveenv => setenv autoload no => dhcp => setenv serverip $(my_tftpserver) => tftp 200000 $(my_bootfile) Or what exactly is your problem? Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de To program is to be.

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[U-Boot-Users] Relocation on MPC852T AdderII
by Raghu 30 Jul '03

30 Jul '03

Hi, Working on u-boot for AdderII ( MPC852T ) I am able to get SMC1 up ( CPU_CLK issue ). Now the code is copied into RAM and is executing from RAM. But it is not able to branch to func "board_init_r" I have confirmed using BDI2000 the the code for "board_init_r" is actually present at that RAM location. The branch is done in func "clear_bss" cpu/mpc8xx/start.S file. But the PC always jumps to "trap_init" function. I am using the "u-boot.lds" file from FADS board. I have attached the assembly listing and dump from BDI. Regards, Raghu. __________________________________ Do you Yahoo!? Yahoo! SiteBuilder - Free, easy-to-use web site design software http://sitebuilder.yahoo.com void board_init_r (gd_t *id, ulong dest_addr) { fe003924: 94 21 ff d8 stwu r1,-40(r1) fe003928: 7c 08 02 a6 mflr r0 fe00392c: 48 00 00 05 bl fe003930 <board_init_r+0xc> fe003930: bf 61 00 14 stmw r27,20(r1) fe003934: 7f c8 02 a6 mflr r30 fe003938: 90 01 00 2c stw r0,44(r1) fe00393c: 80 1e ff f0 lwz r0,-16(r30) DECLARE_GLOBAL_DATA_PTR; BDI>md 0x007bf924 007bf924 : 9421ffd8 7c0802a6 48000005 bf610014 .!..|...H....a.. 007bf934 : 7fc802a6 9001002c 801efff0 7c7d1b78 .......,....|}.x 007bf944 : 7fc0f214 80030004 807e8064 60000001 .........~.d`... 007bf954 : 7c9f2378 901d0004 837d0000 48005ab5 |.#x.....}..H.Z. 007bf964 : 811e8070 813e806c 80080000 817e8068 ...p.>.l.....~.h fe002380 <clear_bss>: fe002380: 80 6e 80 20 lwz r3,-32736(r14) fe002384: 80 8e 80 24 lwz r4,-32732(r14) fe002388: 7c 03 20 40 cmplw r3,r4 fe00238c: 41 82 00 18 beq- fe0023a4 <clear_bss+0x24> fe002390: 38 00 00 00 li r0,0 fe002394: 90 03 00 00 stw r0,0(r3) fe002398: 38 63 00 04 addi r3,r3,4 fe00239c: 7c 03 20 40 cmplw r3,r4 fe0023a0: 40 82 ff f4 bne+ fe002394 <clear_bss+0x14> fe0023a4: 7d 23 4b 78 mr r3,r9 fe0023a8: 7d 44 53 78 mr r4,r10 fe0023ac: 48 00 15 79 bl fe003924 <board_init_r> BDI>rd GPR00: 00000000 0075bf78 00000000 fe01a000 GPR04: 007d6000 007d6000 00000010 007d5ffc GPR08: fe019ffc 0075bf98 007bc000 fe018000 GPR12: 00000000 30100010 007dc000 027bc000 GPR16: 00191410 001000a0 10001084 02010000 GPR20: 22440800 00000001 10000080 80008462 GPR24: 0075bf98 007bc000 0075bfc4 00000000 GPR28: 0075bf78 fa202ec0 007dc0f0 00000001 CR : 28000002 MSR: 00001002 BDI> U-Boot 0.4.0 (Jul 30 2003 - 18:36:04) CPU: unknown MPC860 (0x08000003) at 48 MHz: 4 kB I-Cache 4 kB D-Cache FEC pres ent Board: AdderII DRAM: 8 MB Top of RAM usable for U-Boot at: 00800000 Reserving 272k for U-Boot at: 007bc000 Reserving 384k for malloc() at: 0075c000 Reserving 60 Bytes for Board Info at: 0075bfc4 Reserving 44 Bytes for Global Data at: 0075bf98 Stack Pointer at: 0075bf78 New Stack Pointer is: 0075bf78

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[U-Boot-Users] [mpc8245 Portx problem]
by 배장식 30 Jul '03

30 Jul '03

I have tried to configure PortX for use of memory space 0x7000_0000. I have modified MCCR4[EXTROM] to enable entened ROM. but i can't accessed address 0x70000000 ... i find something worng in include/config_Sandpint8245.h according to define BATs in config_Sandpint8245.h not allocate BATs for address 0x7000000 , so i try change BAT1 for extended rom i modify ppcboot code to blow list 1. 0x40000000 used by initial stack , until sdram init....(BAT1 allocation) 2. command/board.c : board_init_r () this function use stack...in ram so no more need 0x40000000 3. my added code to BAT1 realloction for 0x70000000.. void move_bat1 (void) { mtspr (IBAT1L, (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)); mtspr (IBAT1U, (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)); mtspr (DBAT1L, (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)); mtspr (DBAT1U, (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)); __asm__ __volatile__("eieio"); __asm__ __volatile__("isync"); __asm__ __volatile__("sync"); } 4. call move_bat1 at board_init_r ...... but...board not working.....

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[U-Boot-Users] PATCH : Allow dhcp to get IP address from and keep other env data .
by Woodruff, Richard 30 Jul '03

30 Jul '03

Hello, This small patch adds the conditional DHCP_IP_ADDR_ONLY . This allows someone to use the dhcp command to load a file on a network where you DON'T have access to the dhcp server, but would like to use it to have fast downloads of development kernels or other files. Prior to this patch the the reply packet would trash your environment settings for bootfile and serverip will not be used when issuing the dhcp command. By adding the CFG_DHCP_CMD, along with DHCP_IP_ADDR_ONLY in your board config file you can use your company network server to get your file. The ip,gateway,netmask still are gotten from the dhcp reply. Regards, Richard W.

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RE: [U-Boot-Users] heap location (PXA)
by Woodruff, Richard 29 Jul '03

29 Jul '03

Hello, The memory map for ARM is not as documented in the u-boot README (which is still fairly powerpc centric in several spots). I can't say that it has really bothered me one way or the other as what is there is functional. BOTH the stack and heap are currently located above the relocated text area (as is the board info structure). - armboot_real_end's value of deadcode is really only a place holder until the variable is initialized after relocation in cpu.c. Fixing the memory map to match would be nice from a consistency standpoint, but I'm not sure if there is any great functional gain from it. If there is I'd like to hear about it also, and then perhaps then would it be worth the effort to switch it. The main gain in the "overall" scheme which is used on PPC seems to be its selective relocation allowing for a very small dynamic memory footprint, not so much in its arrangement. Of coarse small is all relative to what you have, but these days it seems to be less a concern on 32bit systems. The map I use looks something like. --------------------------- 0x11f6df84 | | Heap for malloc |- Environment |- nand struct --------------------------- 0x11f3DF84, malloc_start | - abort stack 3 words | - u-boot globals (r8) | Stack | --------------------------- 0x11f1df84, _armboot_end | | Text | | |--------------------------- 0x11f00000, Regards, Richard W. -----Original Message----- From: Nemec, Bernhard [mailto:Bernhard.Nemec@jaeger-toennies.com] Sent: Monday, July 28, 2003 3:25 AM To: u-boot-users(a)lists.sourceforge.net Subject: [U-Boot-Users] heap location (PXA) Hi, I'm porting u-boot 0.4.0 to a custom PXA255 board similar to the CSB226, of which I used the configuration as a starting point. What I'm confused about ATM is _armboot_real_end, which is used for heap initialisation with mem_malloc_init() in lib_arm/board.c. 1 - _armboot_real_end has the value 0x0BADC0DE, which is not in RAM, but in FLASH range of the PXA. 2 - the heap is supposed to be located *below* u-boot, not above, since u-boot itself gets relocated to the upper end of RAM. Therefore I would propose to change mem_malloc_init (_armboot_real_end); to mem_malloc_init ( _armboot_start - CFG_MALLOC_LEN ); in start_armboot(). I'm interested in any thoughts on the subject. Thanks, Bernhard

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[U-Boot-Users] u-boot for MPC8266-PCI board
by Thomas Schäfer 29 Jul '03

29 Jul '03

Rune and Yuli, thank you for your replies. I tried out Rune's hints and found the board resetting continously after initialization of the SDRAM. I enabled the debug messages in the SDRAM initialization sequence and found the following memory controller settings: U-Boot 0.4.5 (Jul 28 2003 - 14:18:33) MPC8260 Reset Status: External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq 33-100, Core Freq 100-300 - dfbrg 0, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf 1 - vco_out 264000000, scc_clk 66000000, brg_clk 66000000 - cpu_clk 198000000, cpm_clk 132000000, bus_clk 66000000 CPU: MPC8260 (HiP4 Rev 14, Mask A.0(A) 2K25A) at 198 MHz Board: Motorola MPC8266ADS I2C: ready DRAM: memctl->memc_mptpr = 0x00001900 memctl->memc_psrt = 0x00000021 memctl->memc_br2 = 0x00000041 memctl->memc_or2 = 0xff001080 memctl->memc_psdmr = 0xeb6eb493 ramaddr = 0x00000008 memctl->memc_psdmr = 0xcb6eb493 memctl->memc_psdmr = 0xdb6eb493 memctl->memc_psdmr = 0xc36eb493 SDRAM configuration read from SPD Size per side = 16MB Organization: 1 sides, 2 banks, 9 Columns, 11 Rows, Data width = 64 bits Refresh rate = 33, CAS latency = 3 Total size: 16 MB In the u-boot-0.3.0 source tree I found that the memory controller was programmed with hard-set values. Trying these values I found that u-boot started to the prompt without problems. The settings are listed below: U-Boot 0.4.5 (Jul 28 2003 - 16:44:07) MPC8260 Reset Status: Software Watchdog, External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq 33-100, Core Freq 100-300 - dfbrg 0, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf 1 - vco_out 264000000, scc_clk 66000000, brg_clk 66000000 - cpu_clk 198000000, cpm_clk 132000000, bus_clk 66000000 CPU: MPC8260 (HiP4 Rev 14, Mask A.0(A) 2K25A) at 198 MHz Board: Motorola MPC8266ADS I2C: ready DRAM: memctl->memc_mptpr = 0x00001900 memctl->memc_psrt = 0x00000021 memctl->memc_br2 = 0x00000041 memctl->memc_or2 = 0xff001080 memctl->memc_psdmr = 0x296eb452 <=> 0xeb6eb493 ramaddr = 0x00000008 memctl->memc_psdmr = 0x096eb452 <=> 0xcb6eb493 memctl->memc_psdmr = 0x196eb452 <=> 0xdb6eb493 memctl->memc_psdmr = 0x416eb452 <=> 0xc36eb493 SDRAM configuration read from SPD Size per side = 16MB Organization: 1 sides, 2 banks, 9 Columns, 11 Rows, Data width = 64 bits Refresh rate = 33, CAS latency = 3 Total size: 16 MB FLASH: 8 MB *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: FCC2 ETHERNET Hit any key to stop autoboot => Playing with the parameters I found that the problem is located in the SDAM bits of the PSDMR register which have to be programmed for my board as shown in the second setting. Any ideas? I have another question according the CIP and BMS settings of the HRCW. They are both set to '1' which means that exceptions are vectored to 0x000n_nnnn and boot memory region is located at 0x0000_0000. I tried out to set those bits to '0', it didn't work. Why? Best regards, Thomas Schäfer ____________________________________ GIGA STREAM GmbH Konrad-Zuse-Str. 7 66115 Saarbrücken Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: tschaefer(a)giga-stream.de

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[U-Boot-Users] Using SMC1 UART on MPC852T ( AdderII board )
by Raghu 29 Jul '03

29 Jul '03

Hi All, I am trying to port u-boot on AdderII card( analogue-micro ) hosting MPC852T. Is this already done this before ?? I am trying to configure SMC1 port as a console to get boot up messages. I have defined #define CONFIG_8xx_CONS_SMC1 1 I have a assembly listing, I am using BDI to single step. It complets "serial_init" function and calls "display_options" func. This in turn calls .. printf() -> puts() -> serial_putc(). In the serial_putc func, it goes into an endless loop, here. while (tbdf->cbd_sc & BD_SC_READY) { WATCHDOG_RESET (); __asm__("eieio"); } The assembly listing is as, --------------------------------------------------- fe0145b8: 7c 00 06 ac eieio fe0145bc: a0 0a 00 00 lhz r0,0(r10) fe0145c0: 70 09 80 00 andi. r9,r0,32768 fe0145c4: 40 82 ff f4 bne+ fe0145b8 <serial_putc+0x68> ---------------------------------------------------- Any clues please ?? Warm Regards Raghu. __________________________________ Do you Yahoo!? Yahoo! SiteBuilder - Free, easy-to-use web site design software http://sitebuilder.yahoo.com

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Re: [U-Boot-Users] PATCH : Fixes and enhancements for NAND f
by Jerry Van Baren 28 Jul '03

28 Jul '03

At 03:38 PM 7/27/2003 -0400, wd(a)denx.de wrote: [snip previous discussion and question on code style formatting] >vi and indent (indent -kr -i8 -bad -bap -nbc -br -c33 -cd33 -ncdb -ce >-ci8 -cli0 -cp33 -d0 -di1 -nfc1 -nfca -i4 -ip0 -l75 -lp -pcs -npsl >-nsc -nsob -nss -ts4, to be precise). > > >Best regards, > >Wolfgang Denk Hi Wolfgang, Thanks for the recommendation for indent options. I ran man and looked up the options. I am confused on a couple of them... * Up front you use -i8 (indent 8), but about half way through the second line (as shown above) you have -i4. You also has -ci8 (continuation indent 8). Should that first -i8 be -i4, effectively moving the --i4? * You have -c33 and -cd33 (comment indentation options), but then specify -nfc1 (don't format comments in column 1) and -nfca (don't format any comments). There seems to be some redundancy here. I would assume -nfca covers everything. Thanks, gvb ********************************************************************** This e-mail and any files transmitted with it may be confidential and may be legally privileged or otherwise exempt from disclosure under applicable law. This e-mail and its files are intended solely for the individual or entity to whom they are addressed and their content is the property of Smiths Aerospace. If you are not the intended recipient, please do not read, copy, use or disclose this communication. If you have received this e-mail in error please notify the e-mail administrator at postmaster(a)smiths-aerospace.com and then delete this e-mail, its files and any copies. This footnote also confirms that this e-mail message has been scanned for the presence of known computer viruses. Smiths addresses are changing! The new addresses are of the form firstname.lastname(a)smiths-aerospace.com. Please update your address books! Please begin using the new form immediately. ***********************************************************************

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[U-Boot-Users] heap location (PXA)
by Nemec, Bernhard 28 Jul '03

28 Jul '03

Hi, I'm porting u-boot 0.4.0 to a custom PXA255 board similar to the CSB226, of which I used the configuration as a starting point. What I'm confused about ATM is _armboot_real_end, which is used for heap initialisation with mem_malloc_init() in lib_arm/board.c. 1 - _armboot_real_end has the value 0x0BADC0DE, which is not in RAM, but in FLASH range of the PXA. 2 - the heap is supposed to be located *below* u-boot, not above, since u-boot itself gets relocated to the upper end of RAM. Therefore I would propose to change mem_malloc_init (_armboot_real_end); to mem_malloc_init ( _armboot_start - CFG_MALLOC_LEN ); in start_armboot(). I'm interested in any thoughts on the subject. Thanks, Bernhard

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RE: [U-Boot-Users] Debug symbols for start.S
by Mark Doherty 28 Jul '03

28 Jul '03

Wolfgang, >This is probably a known problem. If you like, you can try out our >latest patches; you can find a test version of our cross GDB at >ftp://ftp.denx.de/pub/tmp/ppc-linux-gdb - don't forget to set the >CROSS_COMPILE environment variable as needed (= ppc_82xx- in your >case) as with all our ELDK tools. > > >Please let me know if it works for you... It does indeed solve the problem, many thanks for your assistance. Best wishes Mark.

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RE: [U-Boot-Users] Debug symbols for start.S
by Mark Doherty 28 Jul '03

28 Jul '03

Thanks Wolfgang, will do. Mark Doherty -----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: 26 July 2003 20:33 To: Mark Doherty Cc: 'u-boot-users(a)lists.sourceforge.net' Subject: Re: [U-Boot-Users] Debug symbols for start.S Dear Mark, in message <9901EE1E8F8BD3119109009027A1B5F596AE23@DIGINET2> you wrote: > > I have a problem which is causing me some headaches during my porting > exercise, I am currently porting u-boot from the ep8260 to our own hardware. > I am lucky enough to have not one but four Abatron probes however my problem > seems to lie with gdb. > > I have compiled the u-boot code straight out of the box so to speak, so I > haven't changed anything strange, however when I load gdb with the elf file > I find that gdb cannot find the start.S file, it prompts the following: This is probably a known problem. If you like, you can try out our latest patches; you can find a test version of our cross GDB at ftp://ftp.denx.de/pub/tmp/ppc-linux-gdb - don't forget to set the CROSS_COMPILE environment variable as needed (= ppc_82xx- in your case) as with all our ELDK tools. Please let me know if it works for you... Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de The night sky over the planet Krikkit is the least interesting sight in the entire Universe. - Douglas Adams _Life, the Universe, and Everything_

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[U-Boot-Users] MPC8xx FEC POST anyone?
by Robin Gilks 28 Jul '03

28 Jul '03

Greetings Has anyone done an FEC POST test for the MPC8xx series CPUs that have the 100M interface on them? The current Ethernet POST tests are based on the SCC rather than the FEC! -- Robin Gilks Senior Design Engineer Phone: (+64)(3) 357 1569 Tait Electronics Fax : (+64)(3) 359 4632 PO Box 1645 Christchurch Email : robin.gilks(a)tait.co.nz New Zealand

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RE: [U-Boot-Users] PATCH : Fixes and enhancements for NAND flash.
by Woodruff, Richard 27 Jul '03

27 Jul '03

Yes placement could be improved. However, it is done on a per block basis, not byte, so the overhead isn't that noticeable. Spinning a wheel every 16k should not be that bad. (Its currently spinning at the page size instead of the block, but that could be easily changed). Regards, Richard W. -----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Sunday, July 27, 2003 8:39 AM To: Woodruff, Richard Cc: u-boot-users(a)lists.sourceforge.net Subject: Re: [U-Boot-Users] PATCH : Fixes and enhancements for NAND flash. Dear Richard, in message <FD2AC9A020DDD51194710008C7089B200BEE2224(a)dlee17.itg.ti.com> you wrote: > > I do like the spinning wheel. Is there any standard way to add a progress > indicator into this or any code with significant delay? Any of the users of Use common sense. The only thing it does is making a part of the code which takes more time than you like eveln slower: I'm not talking about the few CPU cycles for the printf (putc() would have been much simpler), but especially about trashing the cache for "pretty" things that don't add value, and the time it takes to output this stuff on a slow serial line. > the code I've talked with like such a feature. It seems that same bit of > code has been replicated in a few places. Surly having a library call and > some ifdef's would be acceptable. No, not at this place. It's a different story when - for example - waiting for a flash sector be return to ready state when erasing it. Here you have to wait anyway, so feel free to implement this busy wait as you like it. > As far a code formatting, I'll see if I can't fix it up. I find myself > using several editors depending on the context of what I'm doing. I've not > mastered any of them... When I do the diff -purN for the patch, I generally > don't notice differences except in the areas I have changed something. What > code reformatter/filter do you use? Some of the more recent u-boot releases > have had a lot of style changes to the point I would suspect you ran > something over the code. vi and indent (indent -kr -i8 -bad -bap -nbc -br -c33 -cd33 -ncdb -ce -ci8 -cli0 -cp33 -d0 -di1 -nfc1 -nfca -i4 -ip0 -l75 -lp -pcs -npsl -nsc -nsob -nss -ts4, to be precise). Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de If something is different, it's either better or worse, and usually both. - Larry Wall

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RE: [U-Boot-Users] PATCH : Fixes and enhancements for NAND flash.
by Woodruff, Richard 27 Jul '03

27 Jul '03

Wolfgang, I do like the spinning wheel. Is there any standard way to add a progress indicator into this or any code with significant delay? Any of the users of the code I've talked with like such a feature. It seems that same bit of code has been replicated in a few places. Surly having a library call and some ifdef's would be acceptable. As far a code formatting, I'll see if I can't fix it up. I find myself using several editors depending on the context of what I'm doing. I've not mastered any of them... When I do the diff -purN for the patch, I generally don't notice differences except in the areas I have changed something. What code reformatter/filter do you use? Some of the more recent u-boot releases have had a lot of style changes to the point I would suspect you ran something over the code. Regards, Richard W. in message <FD2AC9A020DDD51194710008C7089B200BEE2218(a)dlee17.itg.ti.com> you wrote: > > The following path fixes a few bugs in cmd_nand.c : > - Fixed null dereference which could result in incorrect ECC values. > - Added support for devices with no Ready/Busy signal connected. > - Added OMAP1510 read/write protect handling. > - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock for > non-JFFS2. > - Switched default ECC to be JFFS2. Added so far. Will push to CVS soon. > - Added spinning wheel. Skipped / rejected. May I please ask you to adhere to the guidlines for coding style? Please do not add trailing white space, especially not to existing code. Please stick with 8 char indentation. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de The man on tops walks a lonely street; the "chain" of command is often a noose.

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[U-Boot-Users] Re: u-boot for MPC8266-PCI board
by Yuli Barcohen 27 Jul '03

27 Jul '03

Due to a problem in my mail system junk message may have been sent before this one. Just ignore it and excuse me, please. >>>>> Thomas Schaefer writes: Thomas> Hi all, Thomas> I'm trying to run u-boot on our MPC8266-PCI board. I'm using Thomas> the latest CVS tree 0.4.5 from sourceforge. I found Thomas> MPC8260ADS.h and MPC8266ADS.h in the configs Thomas> directory. Trying the MPC8266ADS configuration and starting Thomas> it ends with no console output at all. Trying the MPC8260ADS Thomas> configuration with CONFIG_ADSTYPE=CFG_8266ADS ends with a Thomas> bus fault after some console outputs (see below). What am I Thomas> doing wrong? CFG_8266ADS flavour of MPC8260ADS port was not tested (as mentioned in README) because I haven't got a board, but due to similarity in boards architecture you may be able to run it with minor changes. First of all, MPC8266-PCI hasn't got Local bus SDRAM so undefine CFG_LSDRAM_BASE in MPC8260ADS.h. After this the board may boot. Another problem is flash support. MPC8266-PCI uses different flash so you will have to clone flash support from other boards supporting AMD flashes. All other boards of MPC260ADS family use Sharp flashes which are supported. If the current code boots, you'll have no support for writing to flash. PCI bridge in target mode is not supported by current ports AFAIK. MPC8260ADS port does not support PCI at all. -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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[U-Boot-Users] Re:U-Boot-Users digest, Vol 1 #315 - 13 msgs
by Yuli Barcohen 27 Jul '03

27 Jul '03

>>>>> u-boot-users-request writes: Thomas> Send U-Boot-Users mailing list submissions to Thomas> u-boot-users(a)lists.sourceforge.net Thomas> To subscribe or unsubscribe via the World Wide Web, visit Thomas> Thomas> https://lists.sourceforge.net/lists/listinfo/u-boot-users Thomas> or, via email, send a message with subject or body 'help' to Thomas> u-boot-users-request(a)lists.sourceforge.net Thomas> You can reach the person managing the list at Thomas> u-boot-users-admin(a)lists.sourceforge.net Thomas> When replying, please edit your Subject line so it is more Thomas> specific than "Re: Contents of U-Boot-Users digest..." Thomas> Today's Topics: Thomas> 1. Re: Where do I need to call my set-enet-address function? Thomas> (Wolfgang Denk) Thomas> 2. Re: JFFS2: CRC Problem with Kernel Image (Martin, Vitali) Thomas> 3. u-boot for MPC8266-PCI board Thomas> (=?iso-8859-1?Q?Thomas_Sch=E4fer?=) Thomas> 4. RE: [PATCH] jffs2 indirect access. (Kenneth Johansson) Thomas> 5. Debug symbols for start.S (Mark Doherty) Thomas> 6. e1000 and ebony (Brian Padalino) Thomas> 7. Should CRC32 be changed to work against address 0 ? Thomas> (Woodruff, Richard) Thomas> 8. Re: Should CRC32 be changed to work against address 0 ? Thomas> (Wolfgang Denk) Thomas> 9. RE: Should CRC32 be changed to work against addres Thomas> s 0 ? (Woodruff, Richard) Thomas> 10. PATCH : omap/925t reset in start.S. (Woodruff, Richard) Thomas> 11. FADS (Ing.Gianfranco Morandi) Thomas> 12. RE: u-boot for MPC8266-PCI board (Rune Torgersen) Thomas> --__--__-- Thomas> Message: 1 To: Kodis Babu Janardhanan <kodisj(a)qualcomm.com> Thomas> Cc: u-boot-users(a)lists.sourceforge.net Subject: Re: Thomas> [U-Boot-Users] Where do I need to call my set-enet-address Thomas> function? From: Wolfgang Denk <wd(a)denx.de> Date: Fri, 25 Jul Thomas> 2003 09:12:01 +0200 Thomas> In message Thomas> <4.3.1.2.20030724173324.01755348(a)jittlov.qualcomm.com> you Thomas> wrote: >> >> I trying to get rid off hard-coded mac addresss and trying to set >> the mac address by reading from the eeprom. I commented the >> CONFIG_ETHADDR in the config file and called my function from the >> lib_ppc/board.c (init routine), it complains about ethaddr not >> set. Where is the appropriate place to call my function. Thomas> Use the existing framework? See the "Note for Redundant Thomas> Ethernet Interfaces" in the README. Thomas> If you add such a feature, please do it the same way as it's Thomas> been done for the other ethernet drivers that support this Thomas> feature. Thomas> Best regards, Thomas> Wolfgang Denk Thomas> -- Software Engineering: Embedded and Realtime Systems, Thomas> Embedded Linux Phone: (+49)-8142-4596-87 Fax: Thomas> (+49)-8142-4596-88 Email: wd(a)denx.de Some people march to Thomas> the beat of a different drummer. And some people tango! Thomas> --__--__-- Thomas> Message: 2 Subject: [U-Boot-Users] Re: JFFS2: CRC Problem Thomas> with Kernel Image Date: Fri, 25 Jul 2003 08:25:22 +0200 Thomas> From: "Martin, Vitali" <vmartin(a)init-ka.de> To: Thomas> <u-boot-users(a)lists.sourceforge.net> >> So what address are you loading to 1000 10000 or 100000 Thomas> Sorry that I wasn't attentive im my last email. The memory Thomas> address is always 0x100000. Thomas> And data written by "tftpboot" and "fsload" to 0x100000 is Thomas> not the same. = There are differences from address Thomas> 0x00101000, so I get Linux CRC Error = running "iminfo" or Thomas> "bootm". Thomas> tftp =3D 00101000: dfc958e0 5f66d603 e27f2fe3 0027f536 Thomas> fsload =3D 00101000: dfc9c970 de53a432 188d2417 af469b2b Thomas> =20 Thomas> --__--__-- Thomas> Message: 3 Reply-To: <tschaefer(a)giga-stream.de> From: Thomas> =?iso-8859-1?Q?Thomas_Sch=E4fer?= <tschaefer(a)giga-stream.de> Thomas> To: <u-boot-users(a)lists.sourceforge.net> Date: Fri, 25 Jul Thomas> 2003 11:36:32 +0200 Subject: [U-Boot-Users] u-boot for Thomas> MPC8266-PCI board Thomas> Hi all, Thomas> I'm trying to run u-boot on our MPC8266-PCI board. I'm using Thomas> the latest C= VS tree 0.4.5 from sourceforge. I found Thomas> MPC8260ADS.h and MPC8266ADS.h in the configs Thomas> directory. Trying the MPC8266ADS configuration and starting Thomas> it en= ds with no console output at all. Trying the Thomas> MPC8260ADS configuration with CONFIG_ADSTYPE=3DCFG_8266ADS Thomas> ends with a bus fault after some console out= puts (see Thomas> below). What am I doing wrong? Thomas> U-Boot 0.4.5 (Jul 25 2003 - 11:18:40) Thomas> MPC8260 Reset Status: External Soft, External Hard Thomas> MPC8260 Clock Configuration Thomas> - Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq 33-100, Core Thomas> Freq 100-30= Thomas> 0 Thomas> - dfbrg 1, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf 1 Thomas> - vco_out 266666664, scc_clk 66666666, brg_clk 16666666 Thomas> - cpu_clk 199999998, cpm_clk 133333332, bus_clk 66666666 Thomas> CPU: MPC8260 (HiP4 Rev 14, Mask A.0(A) 2K25A) at 199.999 MHz Thomas> Board: Motorola MPC8266ADS I2C: ready DRAM: 16 MB FLASH: Bus Thomas> Fault @ 0x00feac3c, fixup 0x00000000 Machine check in kernel Thomas> mode. Caused by (from msr): regs 00f71e10 Unknown values in Thomas> msr NIP: 00FEAC3C XER: 20000000 LR: 00FD6E94 REGS: 00f71e10 Thomas> TRAP: 0200 DAR: 00000000MSR: 00003000 E=AA: 0 PR: 0 FP: 1 Thomas> ME: 1 IR/DR: 00 Thomas> GPR00: 00500092 00F71F00 04280112 00000000 00FD6E88 Bus Thomas> Fault @ 0x00fe73d= 0, fixup 0x00000000 Machine check in Thomas> kernel mode. Caused by (from msr): regs 00f71af8 Unknown Thomas> values in msr NIP: 00FE73D0 XER: 00000000 LR: 00FE7360 REGS: Thomas> 00f71af8 TRAP: 0200 DAR: 00000000MSR: 00003000 EE: 0 PR: 0 Thomas> FP: 1 ME: 1 IR/DR: 00 Thomas> Any hints would be appreciated. Thomas> Best regards, Thomas> Thomas Sch=E4fer Thomas> ____________________________________ Thomas> GIGA STREAM GmbH Thomas> Konrad-Zuse-Str. 7 66115 Saarbr=FCcken Thomas> Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - Thomas> 100 E-mail: tschaefer(a)giga-stream.de Thomas> --__--__-- Thomas> Message: 4 Subject: RE: [U-Boot-Users] [PATCH] jffs2 Thomas> indirect access. From: Kenneth Johansson Thomas> <kenneth.johansson(a)etx.ericsson.se> To: "Woodruff, Richard" Thomas> <r-woodruff2(a)ti.com> Cc: Thomas> "u-boot-users(a)lists.sourceforge.net" Thomas> <u-boot-users(a)lists.sourceforge.net> Thomas> Date: 25 Jul 2003 14:18:59 +0200 Thomas> On Thu, 2003-07-24 at 16:20, Woodruff, Richard wrote: >> Hi, =20 I had considered doing something similar to support NAND. >> After reading though Dave's comments as attached below (speed, >> size, ...) and some othe= Thomas> r >> reading I decided from my perspective it wasn't worth it. For >> the most p= Thomas> art >> memory is abundant at the boot loader so copying a moderately >> sized kerne= Thomas> l >> partition doesn't seem that bad, especially given the speed cost. >> In my board I've added a ram entry flash device array and copy >> data there. Thomas> Yes when you have NAND flash an extra partition or two is Thomas> not going to cost you much. And when you are using NOR flash Thomas> you probably is going to have a lot more DRAM than flash Thomas> anyway. Thomas> I should mention that most of the work on this patch was Thomas> done by a summer intern named Michal Cendrowski I just Thomas> dotted the i's and crossed the t's well actually I freed the Thomas> mallocs and moved some things out of loops. Thomas> It should be possible to change the code in a why that makes Thomas> it a compile time option to use the callback function or Thomas> directly map the filesystem. I think that would be the only Thomas> acceptable change as the overhead otherwise is just to large Thomas> for situations when copying the whole thing is not a Thomas> problem. Thomas> hmm That should almost be possible now just changing the Thomas> jffs2copy macro. Thomas> --=20 Kenneth Johansson=09 Ericsson AB Tel: +46 8 719 70 20 Thomas> Tellusborgsv=E4gen 90 Fax: +46 8 719 29 45 126 25 Stockholm Thomas> ken(a)switchboard.ericsson.se Thomas> --__--__-- Thomas> Message: 5 From: Mark Doherty Thomas> <mdoherty(a)arca-technologies.com> To: Thomas> "'u-boot-users(a)lists.sourceforge.net'" Thomas> <u-boot-users(a)lists.sourceforge.net> Thomas> Date: Fri, 25 Jul 2003 15:12:05 +0100 Subject: Thomas> [U-Boot-Users] Debug symbols for start.S Thomas> Hi, Thomas> I have a problem which is causing me some headaches during Thomas> my porting exercise, I am currently porting u-boot from the Thomas> ep8260 to our own hardware. I am lucky enough to have not Thomas> one but four Abatron probes however my problem seems to lie Thomas> with gdb. Thomas> I have compiled the u-boot code straight out of the box so Thomas> to speak, so I haven't changed anything strange, however Thomas> when I load gdb with the elf file I find that gdb cannot Thomas> find the start.S file, it prompts the following: Thomas> $ ppc_82xx-gdb u-boot GNU gdb 5.2.1 Copyright 2002 Free Thomas> Software Foundation, Inc. GDB is free software, covered by Thomas> the GNU General Public License, and you are welcome to Thomas> change it and/or distribute copies of it under certain Thomas> conditions. Type "show copying" to see the conditions. Thomas> There is absolutely no warranty for GDB. Type "show Thomas> warranty" for details. This GDB was configured as Thomas> "--host=i686-pc-linux-gnu --target=powerpc-hardhat-linux"... Thomas> (gdb) target remote bdi:2001 Remote debugging using bdi:2001 Thomas> 0x00000100 in _start () (gdb) list 1 {standard input}: No Thomas> such file or directory. Thomas> in {standard input} Thomas> (gdb) list strc strcat strchr strcmp strcpy (gdb) list Thomas> strcmp 48 bne 1b 49 blr 50 51 .globl strcmp 52 strcmp: 53 Thomas> addi r5,r3,-1 54 addi r4,r4,-1 55 1: lbzu r3,1(r5) 56 cmpwi Thomas> 1,r3,0 57 lbzu r0,1(r4) (gdb) Thomas> The strange thing is that the ppcstring.S routines and Thomas> others seem fine, I was hoping someone else has seen the Thomas> same problem? Any help would be very much appreciated. Thomas> Thanks Thomas> Mark Doherty Thomas> --__--__-- Thomas> Message: 6 From: "Brian Padalino" <bpadalino(a)perigee.com> Thomas> To: <u-boot-users(a)lists.sourceforge.net> Date: Fri, 25 Jul Thomas> 2003 10:35:50 -0400 Subject: [U-Boot-Users] e1000 and ebony Thomas> I am trying to boot off the e1000 PCI-X (Pro 1000 MT) Thomas> ethernet card I have for my Ebony board. I added the Thomas> configuration lines #define CONFIG_ENV_OVERWRITE just so I Thomas> can change ethaddr's and I also have #define CONFIG_E1000 in Thomas> there as well. Thomas> Do I need any other configuration options? What should Thomas> U-Boot say if it finds the PCI card? How do I know which Thomas> ethaddr is bound to the e1000 (ethaddr, eth2addr, eth3addr, Thomas> etc)? Thomas> Any help is very much appreciated. Thomas> Thanks, Brian Thomas> --__--__-- Thomas> Message: 7 From: "Woodruff, Richard" <r-woodruff2(a)ti.com> Thomas> To: u-boot-users(a)lists.sourceforge.net Date: Fri, 25 Jul Thomas> 2003 10:37:59 -0500 Subject: [U-Boot-Users] Should CRC32 be Thomas> changed to work against address 0 ? Thomas> This message is in MIME format. Since your mail reader does Thomas> not understand this format, some or all of this message may Thomas> not be legible. Thomas> ------_=_NextPart_001_01C352C2.4CDFDA53 Content-Type: Thomas> text/plain Thomas> Hello, Thomas> CRC32 currently will return 0 if its sent buf address of Thomas> zero. Is this proper? My ROM is at zero, so running a Thomas> CRC32 over it might be a useful thing, however, CRC 32 Thomas> always returns 0 for a start address of zero. Is there some Thomas> reason this needs to be this way? It doesn't seem right to Thomas> me at first glance. Thomas> Regards, Thomas> Richard W. Thomas> ------_=_NextPart_001_01C352C2.4CDFDA53 Content-Type: Thomas> text/html Thomas> <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Thomas> Transitional//EN"> <HTML><HEAD> <META Thomas> HTTP-EQUIV="Content-Type" CONTENT="text/html; Thomas> charset=us-ascii"> <TITLE>Message</TITLE> Thomas> <META content="MSHTML 6.00.2800.1170" name=GENERATOR></HEAD> Thomas> <BODY> <DIV><FONT face=Arial size=2><SPAN Thomas> class=665493415-25072003>Hello,</SPAN></FONT></DIV> Thomas> <DIV><FONT face=Arial size=2><SPAN Thomas> class=665493415-25072003></SPAN></FONT> </DIV> Thomas> <DIV><FONT face=Arial size=2><SPAN Thomas> class=665493415-25072003>CRC32 currently will return 0 if Thomas> its sent buf address of zero.  Is this proper?  My Thomas> ROM is at zero, so running a CRC32 over it might be a useful Thomas> thing, however, CRC 32 always returns 0 for a start address Thomas> of zero.  Is there some reason this needs to be this Thomas> way?  It doesn't seem right to me at first Thomas> glance.</SPAN></FONT></DIV> <DIV><FONT face=Arial Thomas> size=2><SPAN Thomas> class=665493415-25072003></SPAN></FONT> </DIV> Thomas> <DIV><FONT face=Arial size=2><SPAN Thomas> class=665493415-25072003>Regards,</SPAN></FONT></DIV> Thomas> <DIV><FONT face=Arial size=2><SPAN Thomas> class=665493415-25072003></SPAN></FONT> </DIV> Thomas> <DIV><FONT face=Arial size=2><SPAN Thomas> class=665493415-25072003>Richard Thomas> W.</SPAN></FONT></DIV></BODY></HTML> Thomas> ------_=_NextPart_001_01C352C2.4CDFDA53-- Thomas> --__--__-- Thomas> Message: 8 To: "Woodruff, Richard" <r-woodruff2(a)ti.com> Cc: Thomas> u-boot-users(a)lists.sourceforge.net Subject: Re: Thomas> [U-Boot-Users] Should CRC32 be changed to work against Thomas> address 0 ? From: Wolfgang Denk <wd(a)denx.de> Date: Fri, 25 Thomas> Jul 2003 18:08:29 +0200 Thomas> Dear Richard, Thomas> in message Thomas> <FD2AC9A020DDD51194710008C7089B200BEE221C(a)dlee17.itg.ti.com> Thomas> you wrote: >> >> CRC32 currently will return 0 if its sent buf address of zero. >> Is this Thomas> Arghhh... >> proper? My ROM is at zero, so running a CRC32 over it might be a >> useful thing, however, CRC 32 always returns 0 for a start >> address of zero. Is there some reason this needs to be this way? >> It doesn't seem right to me at first glance. Thomas> The reason is that the CRC32 code was designed to be used Thomas> with user-land applications in a standard OS, where a NULL Thomas> buffer pointer is always an indication of some problem. Thomas> With U-Boot, this is just a bug. Thanks for pointing it out. Thomas> Fixed in my local tree. Will push it to CVS later today. Thomas> Best regards, Thomas> Wolfgang Denk Thomas> -- Software Engineering: Embedded and Realtime Systems, Thomas> Embedded Linux Phone: (+49)-8142-4596-87 Fax: Thomas> (+49)-8142-4596-88 Email: wd(a)denx.de ... Jesus cried with a Thomas> loud voice: Lazarus, come forth; the bug hath been found and Thomas> thy program runneth. And he that was dead came forth... -- Thomas> John 11:43-44 [version 2.0?] Thomas> --__--__-- Thomas> Message: 9 From: "Woodruff, Richard" <r-woodruff2(a)ti.com> Thomas> To: "'Wolfgang Denk'" <wd(a)denx.de> Cc: Thomas> u-boot-users(a)lists.sourceforge.net Subject: RE: Thomas> [U-Boot-Users] Should CRC32 be changed to work against Thomas> addres Thomas> s 0 ? Thomas> Date: Fri, 25 Jul 2003 11:21:35 -0500 Thomas> Pretty much as I guessed and I've changed mine. ... However, Thomas> from my point of view, as a user I'd rather take the Thomas> exception when trying to touch zero as opposed to a wrong Thomas> answer. I think that most mmu aware systems have disallowed Thomas> access to virtual address zero for some time. If the code Thomas> came from the embedded space than maybe. Thomas> Richard W. >> -----Original Message----- From: Wolfgang Denk >> [mailto:wd@denx.de] Sent: Friday, July 25, 2003 11:08 AM To: >> Woodruff, Richard Cc: u-boot-users(a)lists.sourceforge.net Subject: >> Re: [U-Boot-Users] Should CRC32 be changed to work against >> address 0 ? >> >> >> Dear Richard, >> >> in message >> <FD2AC9A020DDD51194710008C7089B200BEE221C(a)dlee17.itg.ti.com> you >> wrote: >> > >> > CRC32 currently will return 0 if its sent buf address of zero. >> > Is this >> >> Arghhh... >> >> > proper? My ROM is at zero, so running a CRC32 over it might be >> > a useful thing, however, CRC 32 always returns 0 for a start >> address of >> > zero. Is there some reason this needs to be this way? It >> > doesn't seem right to me at first glance. >> >> The reason is that the CRC32 code was designed to be used with >> user-land applications in a standard OS, where a NULL buffer >> pointer is always an indication of some problem. >> >> With U-Boot, this is just a bug. Thanks for pointing it out. >> >> Fixed in my local tree. Will push it to CVS later today. >> >> Best regards, >> >> Wolfgang Denk >> >> -- Software Engineering: Embedded and Realtime Systems, Embedded >> Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: >> wd(a)denx.de ... Jesus cried with a loud voice: Lazarus, come >> forth; the bug hath been found and thy program runneth. And he >> that was dead came forth... -- John 11:43-44 [version 2.0?] >> Thomas> --__--__-- Thomas> Message: 10 From: "Woodruff, Richard" <r-woodruff2(a)ti.com> Thomas> To: "'u-boot-users(a)lists.sourceforge.net'" Thomas> <u-boot-users(a)lists.sourceforge.net> Thomas> Date: Fri, 25 Jul 2003 12:07:30 -0500 Subject: Thomas> [U-Boot-Users] PATCH : omap/925t reset in start.S. Thomas> This message is in MIME format. Since your mail reader does Thomas> not understand this format, some or all of this message may Thomas> not be legible. Thomas> ------_=_NextPart_000_01C352CF.3B5E6218 Content-Type: Thomas> text/plain Thomas> Hello, Thomas> I've been finding that the reset method in the cpu/arm925 Thomas> tree is not reliable, depends on the image size and Thomas> alignment. This patch switches to another reset method as Thomas> defined in the TRM which seems to be much more reliable in Thomas> this environment. Thomas> Regards, Thomas> Richard W. Thomas> ------_=_NextPart_000_01C352CF.3B5E6218 Content-Type: Thomas> application/octet-stream; Thomas> name="reset.changelog" Thomas> Content-Transfer-Encoding: quoted-printable Thomas> Content-Disposition: attachment; Thomas> filename="reset.changelog" Thomas> Patch by Richard Woodruff, 25 July 03:=0A= Thomas> - Changed to use more reliable reset for OMAP/925T.=0A= Thomas> ------_=_NextPart_000_01C352CF.3B5E6218 Content-Type: Thomas> application/octet-stream; Thomas> name="reset.diff" Thomas> Content-Transfer-Encoding: quoted-printable Thomas> Content-Disposition: attachment; Thomas> filename="reset.diff" Thomas> diff -purN u-boot-0.4.4/cpu/arm925t/start.S = Thomas> u-boot-0.4.4-2/cpu/arm925t/start.S=0A= Thomas> --- u-boot-0.4.4/cpu/arm925t/start.S Wed Jul 16 16:53:03 Thomas> 2003=0A= Thomas> +++ u-boot-0.4.4-2/cpu/arm925t/start.S Fri Jul 25 11:38:19 Thomas> 2003=0A= Thomas> @@ -31,6 +31,7 @@=0A= Thomas> */=0A= Thomas> =0A= =0A= Thomas> +=0A= Thomas> #include <config.h>=0A= include <version.h>=0A= Thomas> =0A= Thomas> @@ -136,14 +137,14 @@ reset:=0A= Thomas> bic r0,r0,#0x1f=0A= orr r0,r0,#0xd3=0A= msr cpsr,r0=0A= Thomas> -=0A= Thomas> + =0A= Thomas> /*=0A= Thomas> * Set up 925T mode=0A= Thomas> */=0A= Thomas> mov r1, #0x81 /* Set ARM925T configuration. */=0A= mcr Thomas> p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration Thomas> register. = Thomas> */=0A= Thomas> =0A= Thomas> - /*=0A= Thomas> + /* =0A= Thomas> * turn off the watchdog, unlock/diable sequence=0A= Thomas> */=0A= Thomas> mov r1, #0xF5=0A= Thomas> @@ -161,9 +162,9 @@ reset:=0A= Thomas> ldr r0, =3DREG_IHL2_MIR=0A= str r1, [r0]=0A= Thomas> =0A= Thomas> - /*=0A= Thomas> + /* =0A= Thomas> * wait for dpll to lock=0A= Thomas> - */=0A= Thomas> + */ =0A= Thomas> ldr r0, =3DCK_DPLL1=0A= mov r1, #0x10=0A= strh r1, Thomas> [r0]=0A= Thomas> @@ -413,10 +414,9 @@ fiq:=0A= Thomas> .globl reset_cpu=0A= reset_cpu:=0A= Thomas> ldr r1, rstctl1 /* get clkm1 reset ctl */=0A= Thomas> - mov r3, #0x0=0A= Thomas> - strh r3, [r1] /* clear it */=0A= Thomas> - mov r3, #0x8=0A= Thomas> - strh r3, [r1] /* force dsp+arm reset */=0A= Thomas> + mov r3, #0x3 /* dsp_en + arm_rst =3D global reset */ =0A= Thomas> + strh r3, [r1] /* force reset */=0A= Thomas> + mov r0, r0=0A= Thomas> _loop_forever:=0A= Thomas> b _loop_forever=0A= Thomas> rstctl1:=0A= Thomas> ------_=_NextPart_000_01C352CF.3B5E6218-- Thomas> --__--__-- Thomas> Message: 11 Reply-To: "Ing.Gianfranco Morandi" Thomas> <gianfranco.morandi(a)euro-studio.it> From: "Ing.Gianfranco Thomas> Morandi" <gianfranco.morandi(a)euro-studio.it> To: Thomas> <u-boot-users(a)lists.sourceforge.net> Date: Fri, 25 Jul 2003 Thomas> 19:38:30 +0200 Organization: Eurostudio s.r.l. Subject: Thomas> [U-Boot-Users] FADS Thomas> Hi to all, Thomas> I'm currently porting the u-boot on the FADS860T board and I Thomas> have started the activity only few days ago. Thomas> I have used the FADS860t.h that comes with u-boot-0.3.0 by Thomas> changing only = the clock related defines. I have a problem Thomas> during the early initialization of the console; when the Thomas> board starts from power up the first part of the message is Thomas> corrupted as follow: Thomas> =E1=D9=C1=E1=E1iA=B9=B9=81=C1=B9=CD=B9=C1=81=81.=D1=81=D1=E5=B9=E1=C1=C1=81= Thomas> 5!=E9=E9 4 kB I-Cache 4 kB D-Cache FEC present Thomas> *** Warning: CPU Core has Silicon Bugs -- Check the Errata Thomas> *** Thomas> Board: FADS with db MPC821, MPC860 / MPC860SAR / MPC860T rev Thomas> ENG or PILOT ... ... Thomas> while if I reset the board without switch it off, the Thomas> message is correct. Thomas> CPU: XPC860xxZPnnB at 49.800 MHz: 4 kB I-Cache 4 kB D-Cache Thomas> FEC present Thomas> *** Warning: CPU Core has Silicon Bugs -- Check the Errata Thomas> *** Thomas> Board: FADS with db MPC821, MPC860 / MPC860SAR / MPC860T rev Thomas> ENG or PILOT ... ... Thomas> Does anybody have any idea if or where I missed some stuff ? Thomas> Any help would be appreciated Thomas> Gianfranco Thomas> --__--__-- Thomas> Message: 12 From: Rune Torgersen <runet(a)innovsys.com> To: Thomas> "'tschaefer(a)giga-stream.de'" <tschaefer(a)giga-stream.de>, Thomas> u-boot-users(a)lists.sourceforge.net Thomas> Subject: RE: [U-Boot-Users] u-boot for MPC8266-PCI board Thomas> Date: Fri, 25 Jul 2003 13:01:59 -0500 Thomas> First off. The MPC8260ADS config files will not run on a Thomas> MPC8266ADS. Most likely culprit here (Remember seeing the Thomas> same thing when dd ther initial port) is that it hangs when Thomas> trying to initialise the = (nonexisting) 4MB og SDRAM on the Thomas> local bus that the MPC8260 has, and the MPC8266 = doesn't. Thomas> The reason the config file for the MPC8266ADS don't give any Thomas> output is = most likely because it loads at adifferent Thomas> initial configuration address. = (See top of Thomas> include/configs/MPC8266ADS.h for details) Thomas> To get it to work the way it is; Write the whole image to Thomas> the start of = the FLASH (on a board with JP3 in 2-3 Thomas> position this is 0xFF800000). Then = set JP3 in the 1-2 Thomas> position. The flash start and boot at 0xFE000000. >> -----Original Message----- From: Thomas Sch=E4fer >> [mailto:tschaefer@giga-stream.de]=20 Sent: Friday, July 25, 2003 >> 04:37 To: u-boot-users(a)lists.sourceforge.net Subject: >> [U-Boot-Users] u-boot for MPC8266-PCI board =20 =20 Hi all, =20 >> I'm trying to run u-boot on our MPC8266-PCI board. I'm using=20 >> the latest CVS tree 0.4.5 from sourceforge. I found=20 >> MPC8260ADS.h and MPC8266ADS.h in the configs directory.=20 Trying >> the MPC8266ADS configuration and starting it ends with=20 no >> console output at all. Trying the MPC8260ADS configuration=20 >> with CONFIG_ADSTYPE=3DCFG_8266ADS ends with a bus fault after=20 >> some console outputs (see below). What am I doing wrong? =20 >> U-Boot 0.4.5 (Jul 25 2003 - 11:18:40) =20 MPC8260 Reset Status: >> External Soft, External Hard =20 MPC8260 Clock Configuration >> - Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq 33-100, Core=20 >> Freq 100-300 >> - dfbrg 1, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf 1 >> - vco_out 266666664, scc_clk 66666666, brg_clk 16666666 >> - cpu_clk 199999998, cpm_clk 133333332, bus_clk 66666666 >> =20 CPU: MPC8260 (HiP4 Rev 14, Mask A.0(A) 2K25A) at 199.999 MHz >> Board: Motorola MPC8266ADS I2C: ready DRAM: 16 MB FLASH: Bus >> Fault @ 0x00feac3c, fixup 0x00000000 Machine check in kernel >> mode. Caused by (from msr): regs 00f71e10 Unknown values in msr >> NIP: 00FEAC3C XER: 20000000 LR: 00FD6E94 REGS: 00f71e10 TRAP:=20 >> 0200 DAR: 00000000MSR: 00003000 E=AA: 0 PR: 0 FP: 1 ME: 1 IR/DR: >> 00 =20 GPR00: 00500092 00F71F00 04280112 00000000 00FD6E88 Bus >> Fault=20 @ 0x00fe73d0, fixup 0x00000000 Machine check in kernel >> mode.=20 Caused by (from msr): regs 00f71af8 Unknown values in >> msr NIP: 00FE73D0 XER: 00000000 LR: 00FE7360 REGS: 00f71af8 >> TRAP:=20 0200 DAR: 00000000MSR: 00003000 EE: 0 PR: 0 FP: 1 ME: 1 >> IR/DR: 00 =20 Any hints would be appreciated. =20 Best regards, >> =20 Thomas Sch=E4fer =20 ____________________________________ =20 >> GIGA STREAM GmbH =20 Konrad-Zuse-Str. 7 66115 Saarbr=FCcken =20 >> Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 >> E-mail: tschaefer(a)giga-stream.de =20 =20 =20 =20 >> ------------------------------------------------------- >> This SF.Net email sponsored by: Free pre-built ASP.NET sites=20 >> including Data Reports, E-commerce, Portals, and Forums are=20 >> available now. Download today and enter to win an XBOX or=20 >> Visual Studio .NET.=20 >> http://aspnet.click-url.com/go/psa00100003ave/direct;at.aspnet Thomas> _072303_01/01 Thomas> _______________________________________________ U-Boot-Users Thomas> mailing list U-Boot-Users(a)lists.sourceforge.net Thomas> https://lists.sourceforge.net/lists/listinfo/u-boot-users Thomas> --__--__-- Thomas> _______________________________________________ U-Boot-Users Thomas> mailing list U-Boot-Users(a)lists.sourceforge.net Thomas> https://lists.sourceforge.net/lists/listinfo/u-boot-users Thomas> End of U-Boot-Users Digest -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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[U-Boot-Users] Start of new ARM920T target
by Marc Singer 27 Jul '03

27 Jul '03

I'm sending an initial patch for the KEV7A400 dev board in order to get some feedback about the configuration extension I'm proposing. This is *not* complete. It ought not break any of the non-ARM9 builds though it may break one of the ARM9 ones. How it works: 1) The top-level script, ./mkconfigx, takes the configured include/config.h file and compiles a list of defines roughly of the (regex) form CONFIG_.* 2) These are transformed into CONFIG_.*=y 3) The written to ./configx.mk in a form that can be included in Makefiles. 4) The cpu/arm920t/Makefile includes this file. I believe this could be included in the ./config.mk file so that everyone benefits. 5) The cpu/arm920t/Makefile has been turned up-side down to make it more amenable to this form of configuration. The present form isn't as elegant as it should, and will, be. It's there to make the point of 'how' it might look. Notice that source files are declared instead of object files. 6) The board/kev7a400/u-boot.lds has an important change. Previously, the name of the start.o object file was hard coded. Instead, start.S has been moved to a named section, .start, and the linker script reflects this. The effect is the same as before, but the dependency is removed. The serial_lh7a400.c file could be moved to share a home with other serial drivers. With this sort of configuration methodology, the configuration file selects the desired driver with something like this: #define CONFIG_SERIAL_LH7A400 or #define CONFIG_SERIAL_NS16550 Why do I prefer this? Ifdefs tend to make code harder to read. A few are usually OK. As the code grows, it is desirable to separate the conditionally compiled code. Likewise, whole file ifdefs are not very clear. One can see the #ifdef at the top, and may not know if it matches the one at the bottom of a long source file. With this configuration method, needed files are explicitly built and linked when the appropriate configuration option is present. Cheers.

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[U-Boot-Users] [PATCH] MPC866ADS board
by Robin Gilks 27 Jul '03

27 Jul '03

Greetings Please find attached a _minimal_ patch to run on the new MPC866ADS prototype board from Motorola. This is based on stable release 0.4.0 It is minimal in that the objective was to get it to run and to boot Linux which it does very well. Known items not complete are: 1. Displaying the CPU type - this wasn't important to our objectives! 2. POST tests - watchdog and I2C fail. Interesting that the current config says that the ethernet loopback test is OK when the POST code only checks SCC1 but we're using FEC... hmmm. There may be an outstanding issue with clock rates. The baud rate changes (19200->9600) depending on whether the bdi200 is connected or not!! Based on the original FADS board and hence only requiring 1 minor tweak on a conditional in .../cpu/mpc8xx/start.S. MAKEALL has been tested - our uclibc/gcc3.3 comes up with a few warnings but I think they are specific to the compiler. I don't have time at present to repeat the tests & post a complete set of results!! Time to move on to our prototype hardware:-)) -- Robin Gilks Senior Design Engineer Phone: (+64)(3) 357 1569 Tait Electronics Fax : (+64)(3) 359 4632 PO Box 1645 Christchurch Email : robin.gilks(a)tait.co.nz New Zealand

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[U-Boot-Users] Patch: Lynx KDIs
by Scott McNutt 27 Jul '03

27 Jul '03

Adds support for LynuxWorks Kernel Downloadable Images (KDIs). Both LynxOS and BlueCat linux KDIs are supported. Currently supports only the MPC8260 (as I am unable to test on other CPUs/Targets). Tested using MPC8260ADS, BlueCat 3.0, and LynxOS 4.0. The type of KDI (e.g. LynxOS or BlueCat) is auto-detected. As such mkimage must specify os type "lynxos". See doc/README.lynxkdi for more details. Regards, --Scott <<lynxkdi.diff>>

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[U-Boot-Users] PATCH : omap/925t reset in start.S.
by Woodruff, Richard 27 Jul '03

27 Jul '03

Hello, I've been finding that the reset method in the cpu/arm925 tree is not reliable, depends on the image size and alignment. This patch switches to another reset method as defined in the TRM which seems to be much more reliable in this environment. Regards, Richard W.

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[U-Boot-Users] MPC86xx patch
by Nye Liu 27 Jul '03

27 Jul '03

Minor oversight in mpc8xx.h Index: include/mpc8xx.h =================================================================== RCS file: /home/cvs/u-boot-mrv/include/mpc8xx.h,v retrieving revision 1.1.1.3 diff -u -r1.1.1.3 mpc8xx.h --- include/mpc8xx.h 26 Jul 2003 01:44:08 -0000 1.1.1.3 +++ include/mpc8xx.h 26 Jul 2003 02:41:23 -0000 @@ -135,7 +135,7 @@ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 */ #ifdef CONFIG_MPC866_et_al -#define PLPRCR_MF_MSK 0xffff0000 /* Multiplication factor bits */ +#define PLPRCR_MF_MSK 0xffff001e /* Multiplication factor + PDF bits */ #define PLPRCR_MFN_MSK 0xf8000000 /* Multiplication factor numerator bits */ #define PLPRCR_MFN_SHIFT 0x0000001b /* Multiplication factor numerator shift*/ #define PLPRCR_MFD_MSK 0x03c00000 /* Multiplication factor denominator bits */ -- Nye Liu nliu(a)mrv.com (818) 772-6235x248 "Who would be stupid enough to quote a fictitious character?" -- Don Quixote

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[U-Boot-Users] PATCH : Fixes and enhancements for NAND flash.
by Woodruff, Richard 26 Jul '03

26 Jul '03

Hello, The following path fixes a few bugs in cmd_nand.c : - Fixed null dereference which could result in incorrect ECC values. - Added support for devices with no Ready/Busy signal connected. - Added OMAP1510 read/write protect handling. - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock for non-JFFS2. - Switched default ECC to be JFFS2. - Added spinning wheel. -------------------- Prior to this only ECC for JFFS2 would have worked, and that only if you had memory at zero which you didn't mind being corrupted. The other method would result in a corrupted bad block byte in the oob data. Regards, Richard W.

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[U-Boot-Users] Debug symbols for start.S
by Mark Doherty 26 Jul '03

26 Jul '03

Hi, I have a problem which is causing me some headaches during my porting exercise, I am currently porting u-boot from the ep8260 to our own hardware. I am lucky enough to have not one but four Abatron probes however my problem seems to lie with gdb. I have compiled the u-boot code straight out of the box so to speak, so I haven't changed anything strange, however when I load gdb with the elf file I find that gdb cannot find the start.S file, it prompts the following: $ ppc_82xx-gdb u-boot GNU gdb 5.2.1 Copyright 2002 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type "show copying" to see the conditions. There is absolutely no warranty for GDB. Type "show warranty" for details. This GDB was configured as "--host=i686-pc-linux-gnu --target=powerpc-hardhat-linux"... (gdb) target remote bdi:2001 Remote debugging using bdi:2001 0x00000100 in _start () (gdb) list 1 {standard input}: No such file or directory. in {standard input} (gdb) list strc strcat strchr strcmp strcpy (gdb) list strcmp 48 bne 1b 49 blr 50 51 .globl strcmp 52 strcmp: 53 addi r5,r3,-1 54 addi r4,r4,-1 55 1: lbzu r3,1(r5) 56 cmpwi 1,r3,0 57 lbzu r0,1(r4) (gdb) The strange thing is that the ppcstring.S routines and others seem fine, I was hoping someone else has seen the same problem? Any help would be very much appreciated. Thanks Mark Doherty

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RE: [U-Boot-Users] FADS
by Dave Ellis 25 Jul '03

25 Jul '03

> Ing.Gianfranco Morandi wrote: > I have a problem during the early initialization of the console; when the > board starts from power up the first part of the message is corrupted as > follow: > > áÙÁááiA¹¹Á¹Í¹Á.ÑÑå¹áÁÁ5!éé 4 kB I-Cache 4 kB D-Cache FEC present > *** Warning: CPU Core has Silicon Bugs -- Check the > Errata *** > Board: FADS with db MPC821, MPC860 / MPC860SAR / MPC860T rev > ENG or PILOT > ... > ... > > while if I reset the board without switch it off, the message > is correct. > > CPU: XPC860xxZPnnB at 49.800 MHz: 4 kB I-Cache 4 kB D-Cache > FEC present > *** Warning: CPU Core has Silicon Bugs -- Check the > Errata *** > Board: FADS with db MPC821, MPC860 / MPC860SAR / MPC860T rev > ENG or PILOT > ... > ... > > Does anybody have any idea if or where I missed some stuff ? The garbled output is because for the FADS the rs232 port is disabled at powerup until U-Boot enables it. It takes a little while for the charge pumps to develop enough voltage to send properly, so the first characters are garbled. When you reset the board the rs232 ports are left enabled, so the rs232 output works immediately. You can safely ignore it, or fix it by adding a delay (maybe 50 milliseconds?) after the rs232 port is enabled in cpu/mpc8xx/serial.c. Look for BCSR1_RS232EN_1. In my experience, what you should fix is this: > CPU: XPC860xxZPnnB at 49.800 MHz: 4 kB I-Cache 4 kB D-Cache > FEC present > *** Warning: CPU Core has Silicon Bugs -- Check the The MPC860T rev B silicon has serious problems. You should replace the CPU with a revision D processor. My experience with the FADS was pretty good once I did that, but other people have had lots of problems and really _hate_ it. Dave Dave Ellis ~~~~~~~~~~~~~~~~~~~~~~~~~~ SIXNET - "Leading the Industrial Ethernet Revolution" 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 Email me at: dge(a)sixnetio.com Detailed product info: www.sixnetio.com ~~~~~~~~~~~~~~~~~~~~~~~~~~

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[U-Boot-Users] FADS
by Ing.Gianfranco Morandi 25 Jul '03

25 Jul '03

Hi to all, I'm currently porting the u-boot on the FADS860T board and I have started the activity only few days ago. I have used the FADS860t.h that comes with u-boot-0.3.0 by changing only the clock related defines. I have a problem during the early initialization of the console; when the board starts from power up the first part of the message is corrupted as follow: áÙÁááiA¹¹Á¹Í¹Á.ÑÑå¹áÁÁ5!éé 4 kB I-Cache 4 kB D-Cache FEC present *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** Board: FADS with db MPC821, MPC860 / MPC860SAR / MPC860T rev ENG or PILOT ... ... while if I reset the board without switch it off, the message is correct. CPU: XPC860xxZPnnB at 49.800 MHz: 4 kB I-Cache 4 kB D-Cache FEC present *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** Board: FADS with db MPC821, MPC860 / MPC860SAR / MPC860T rev ENG or PILOT ... ... Does anybody have any idea if or where I missed some stuff ? Any help would be appreciated Gianfranco

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RE: [U-Boot-Users] u-boot for MPC8266-PCI board
by Rune Torgersen 25 Jul '03

25 Jul '03

First off. The MPC8260ADS config files will not run on a MPC8266ADS. Most likely culprit here (Remember seeing the same thing when dd ther initial port) is that it hangs when trying to initialise the (nonexisting) 4MB og SDRAM on the local bus that the MPC8260 has, and the MPC8266 doesn't. The reason the config file for the MPC8266ADS don't give any output is most likely because it loads at adifferent initial configuration address. (See top of include/configs/MPC8266ADS.h for details) To get it to work the way it is; Write the whole image to the start of the FLASH (on a board with JP3 in 2-3 position this is 0xFF800000). Then set JP3 in the 1-2 position. The flash start and boot at 0xFE000000. > -----Original Message----- > From: Thomas Schäfer [mailto:tschaefer@giga-stream.de] > Sent: Friday, July 25, 2003 04:37 > To: u-boot-users(a)lists.sourceforge.net > Subject: [U-Boot-Users] u-boot for MPC8266-PCI board > > > Hi all, > > I'm trying to run u-boot on our MPC8266-PCI board. I'm using > the latest CVS tree 0.4.5 from sourceforge. I found > MPC8260ADS.h and MPC8266ADS.h in the configs directory. > Trying the MPC8266ADS configuration and starting it ends with > no console output at all. Trying the MPC8260ADS configuration > with CONFIG_ADSTYPE=CFG_8266ADS ends with a bus fault after > some console outputs (see below). What am I doing wrong? > > U-Boot 0.4.5 (Jul 25 2003 - 11:18:40) > > MPC8260 Reset Status: External Soft, External Hard > > MPC8260 Clock Configuration > - Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq 33-100, Core > Freq 100-300 > - dfbrg 1, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf 1 > - vco_out 266666664, scc_clk 66666666, brg_clk 16666666 > - cpu_clk 199999998, cpm_clk 133333332, bus_clk 66666666 > > CPU: MPC8260 (HiP4 Rev 14, Mask A.0(A) 2K25A) at 199.999 MHz > Board: Motorola MPC8266ADS > I2C: ready > DRAM: 16 MB > FLASH: Bus Fault @ 0x00feac3c, fixup 0x00000000 > Machine check in kernel mode. > Caused by (from msr): regs 00f71e10 Unknown values in msr > NIP: 00FEAC3C XER: 20000000 LR: 00FD6E94 REGS: 00f71e10 TRAP: > 0200 DAR: > 00000000MSR: 00003000 Eª: 0 PR: 0 FP: 1 ME: 1 IR/DR: 00 > > GPR00: 00500092 00F71F00 04280112 00000000 00FD6E88 Bus Fault > @ 0x00fe73d0, fixup 0x00000000 Machine check in kernel mode. > Caused by (from msr): regs 00f71af8 Unknown values in msr > NIP: 00FE73D0 XER: 00000000 LR: 00FE7360 REGS: 00f71af8 TRAP: > 0200 DAR: > 00000000MSR: 00003000 EE: 0 PR: 0 FP: 1 ME: 1 IR/DR: 00 > > Any hints would be appreciated. > > Best regards, > > Thomas Schäfer > > ____________________________________ > > GIGA STREAM GmbH > > Konrad-Zuse-Str. 7 > 66115 Saarbrücken > > Tel.: + 49 (0)681 / 95916 - 203 > Fax: + 49 (0)681 / 95916 - 100 > E-mail: tschaefer(a)giga-stream.de > > > > > ------------------------------------------------------- > This SF.Net email sponsored by: Free pre-built ASP.NET sites > including Data Reports, E-commerce, Portals, and Forums are > available now. Download today and enter to win an XBOX or > Visual Studio .NET. > http://aspnet.click-url.com/go/psa00100003ave/direct;at.aspnet _072303_01/01 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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RE: [U-Boot-Users] Should CRC32 be changed to work against addres s 0 ?
by Woodruff, Richard 25 Jul '03

25 Jul '03

Pretty much as I guessed and I've changed mine. ... However, from my point of view, as a user I'd rather take the exception when trying to touch zero as opposed to a wrong answer. I think that most mmu aware systems have disallowed access to virtual address zero for some time. If the code came from the embedded space than maybe. Richard W. > -----Original Message----- > From: Wolfgang Denk [mailto:wd@denx.de] > Sent: Friday, July 25, 2003 11:08 AM > To: Woodruff, Richard > Cc: u-boot-users(a)lists.sourceforge.net > Subject: Re: [U-Boot-Users] Should CRC32 be changed to work > against address 0 ? > > > Dear Richard, > > in message > <FD2AC9A020DDD51194710008C7089B200BEE221C(a)dlee17.itg.ti.com> > you wrote: > > > > CRC32 currently will return 0 if its sent buf address of zero. Is > > this > > Arghhh... > > > proper? My ROM is at zero, so running a CRC32 over it might be a > > useful thing, however, CRC 32 always returns 0 for a start > address of > > zero. Is there some reason this needs to be this way? It doesn't > > seem right to me at first glance. > > The reason is that the CRC32 code was designed to be > used with user-land applications in a standard OS, where a > NULL buffer pointer is always an indication of some problem. > > With U-Boot, this is just a bug. Thanks for pointing it out. > > Fixed in my local tree. Will push it to CVS later today. > > Best regards, > > Wolfgang Denk > > -- > Software Engineering: Embedded and Realtime Systems, Embedded Linux > Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: > wd(a)denx.de ... Jesus cried with a loud voice: Lazarus, come > forth; the bug hath been found and thy program runneth. > And he that was dead came > forth... -- John 11:43-44 [version 2.0?] >

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[U-Boot-Users] Should CRC32 be changed to work against address 0 ?
by Woodruff, Richard 25 Jul '03

25 Jul '03

Hello, CRC32 currently will return 0 if its sent buf address of zero. Is this proper? My ROM is at zero, so running a CRC32 over it might be a useful thing, however, CRC 32 always returns 0 for a start address of zero. Is there some reason this needs to be this way? It doesn't seem right to me at first glance. Regards, Richard W.

2 1

[U-Boot-Users] e1000 and ebony
by Brian Padalino 25 Jul '03

25 Jul '03

I am trying to boot off the e1000 PCI-X (Pro 1000 MT) ethernet card I have for my Ebony board. I added the configuration lines #define CONFIG_ENV_OVERWRITE just so I can change ethaddr's and I also have #define CONFIG_E1000 in there as well. Do I need any other configuration options? What should U-Boot say if it finds the PCI card? How do I know which ethaddr is bound to the e1000 (ethaddr, eth2addr, eth3addr, etc)? Any help is very much appreciated. Thanks, Brian

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RE: [U-Boot-Users] [PATCH] jffs2 indirect access.
by Woodruff, Richard 25 Jul '03

25 Jul '03

Hi, I had considered doing something similar to support NAND. After reading though Dave's comments as attached below (speed, size, ...) and some other reading I decided from my perspective it wasn't worth it. For the most part memory is abundant at the boot loader so copying a moderately sized kernel partition doesn't seem that bad, especially given the speed cost. In my board I've added a ram entry flash device array and copy data there. Regards, Richard W. ---------------------------------------------------------------------------- -- Richard Woodruff [mailto:r-woodruff2@ti.com] wrote: > Has anyone used adapted/used any of the u-boot JFFS2 code to be NAND aware? > A very quick look at the JFFS2 code (called by fsload, fsinfo, ..) > seems to > indicate to me that reading of raw data is done via a straight memcpy > (direct dereference, assuming linear flash). I'm wondering if making > it work might be as simple as conditionalizing that code to call the > nand_mtd read.j equivalents....unfortunately few things are ever just > simple... I have it working, but in a simpler way. I have a 2 MiB boot partition at the start of the nand flash (with just the kernel image and maybe a backup kernel). I read the whole partition to RAM and let JFFS2 read it from there. nand read.j 400000 0 200000; fsload 200000 image; bootm 200000 The only tricky part is that the configuration options for JFFS2 only work with memory in NOR flash, so I used CFG_JFFS_CUSTOM_PART and implemented jffs2_part_info() so it points to RAM. Someday it would be good (IMHO) to accept CFG_JFFS2_BASE and CFG_JFFS2_SIZE as an alternative (even for NOR flash) to the sector/bank scheme (CFG_JFFS2_FIRST_SECTOR, etc.). Copying the NAND to RAM means each sector is only read from NAND once, which is good since both reading the NAND and doing the ECC calculations can be slow. > The ideal case is to just allow the kernel to be part of the > filesytem, though I suppose it might not be strictly necessary and a > raw partition which ignores bad blocks might be enough....at the > moment I'm wondering how > one safely draw the lines of how big a partition would need to be at > the "physical" level to guarantee that your kernel will always fit, > assuming some of the blocks go bad over time. If you use a separate boot partition very few blocks should wear out, since they won't be written very often. The safest way to update the kernel is to load the new kernel without deleting the old one, so if you allow twice the largest possible size of your kernel plus 15 or 20 erase blocks for JFFS2 overhead and bad blocks, you should be OK. But NAND is cheap and kernels grow, so I would allocate more if possible. With the kernel in a larger partition with lots of files booting is slow, since both reading the flash and sorting all of the file fragments take a lot of time. Dave Dave Ellis ~~~~~~~~~~~~~~~~~~~~~~~~~~ SIXNET - "Leading the Industrial Ethernet Revolution" 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 Email me at: dge(a)sixnetio.com Detailed product info: www.sixnetio.com ~~~~~~~~~~~~~~~~~~~~~~~~~~ > -----Original Message----- > From: Kenneth Johansson [mailto:kenneth.johansson@etx.ericsson.se] > Sent: Thursday, July 24, 2003 7:35 AM > To: u-boot-users(a)lists.sourceforge.net > Subject: [U-Boot-Users] [PATCH] jffs2 indirect access. > > > This is a patch that alters the jffs2 code to work on flash > devices that is not directly memory mapped without the need > to copy the whole flash to RAM. > > It is not ready for inclusion and I do not think I will push > it as it was quite a bit slower than I expected. It also > needs a little more cleanup. > > A callback function is added to struct part_info that works > like memcpy and is the thing actually reading the flash. The > offset member is gone and the jffs2 code always uses 0 as the > start address for the filesystem. It is up to the callback > function to remap that into something useful. > > This code however uses less memory than copying the flash to > ram but it is slower. jffs2_scan_empty() could use some > speedup but even in situations when that one is not taking > mush time this is slower by a factor of 2-3. It's only faster > if you happens to have ridiculously slow flash. > > I'm going on vacation and is not going to work more on this > so if someone wants this added to u-boot you have to fix a > proper patch yourself. > > > -- > Kenneth Johansson > Ericsson AB Tel: +46 8 719 70 20 > Tellusborgsvägen 90 Fax: +46 8 719 29 45 > 126 25 Stockholm ken(a)switchboard.ericsson.se >

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[U-Boot-Users] u-boot for MPC8266-PCI board
by Thomas Schäfer 25 Jul '03

25 Jul '03

Hi all, I'm trying to run u-boot on our MPC8266-PCI board. I'm using the latest CVS tree 0.4.5 from sourceforge. I found MPC8260ADS.h and MPC8266ADS.h in the configs directory. Trying the MPC8266ADS configuration and starting it ends with no console output at all. Trying the MPC8260ADS configuration with CONFIG_ADSTYPE=CFG_8266ADS ends with a bus fault after some console outputs (see below). What am I doing wrong? U-Boot 0.4.5 (Jul 25 2003 - 11:18:40) MPC8260 Reset Status: External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq 33-100, Core Freq 100-300 - dfbrg 1, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf 1 - vco_out 266666664, scc_clk 66666666, brg_clk 16666666 - cpu_clk 199999998, cpm_clk 133333332, bus_clk 66666666 CPU: MPC8260 (HiP4 Rev 14, Mask A.0(A) 2K25A) at 199.999 MHz Board: Motorola MPC8266ADS I2C: ready DRAM: 16 MB FLASH: Bus Fault @ 0x00feac3c, fixup 0x00000000 Machine check in kernel mode. Caused by (from msr): regs 00f71e10 Unknown values in msr NIP: 00FEAC3C XER: 20000000 LR: 00FD6E94 REGS: 00f71e10 TRAP: 0200 DAR: 00000000MSR: 00003000 Eª: 0 PR: 0 FP: 1 ME: 1 IR/DR: 00 GPR00: 00500092 00F71F00 04280112 00000000 00FD6E88 Bus Fault @ 0x00fe73d0, fixup 0x00000000 Machine check in kernel mode. Caused by (from msr): regs 00f71af8 Unknown values in msr NIP: 00FE73D0 XER: 00000000 LR: 00FE7360 REGS: 00f71af8 TRAP: 0200 DAR: 00000000MSR: 00003000 EE: 0 PR: 0 FP: 1 ME: 1 IR/DR: 00 Any hints would be appreciated. Best regards, Thomas Schäfer ____________________________________ GIGA STREAM GmbH Konrad-Zuse-Str. 7 66115 Saarbrücken Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: tschaefer(a)giga-stream.de

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[U-Boot-Users] Where do I need to call my set-enet-address function?
by Kodis Babu Janardhanan 25 Jul '03

25 Jul '03

Hi, I trying to get rid off hard-coded mac addresss and trying to set the mac address by reading from the eeprom. I commented the CONFIG_ETHADDR in the config file and called my function from the lib_ppc/board.c (init routine), it complains about ethaddr not set. Where is the appropriate place to call my function. Thanks Kodis

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[U-Boot-Users] Re: JFFS2: CRC Problem with Kernel Image
by Martin, Vitali 25 Jul '03

25 Jul '03

> So what address are you loading to 1000 10000 or 100000 Sorry that I wasn't attentive im my last email. The memory address is always 0x100000. And data written by "tftpboot" and "fsload" to 0x100000 is not the same. There are differences from address 0x00101000, so I get Linux CRC Error running "iminfo" or "bootm". tftp = 00101000: dfc958e0 5f66d603 e27f2fe3 0027f536 fsload = 00101000: dfc9c970 de53a432 188d2417 af469b2b

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[U-Boot-Users] MPC8xxADS PLPRCR buglet
by Nye Liu 25 Jul '03

25 Jul '03

I have found a problem with the way the MPC8xxADS support deals with PLPRCR; it seems to be off by a factor of 2 in various places. If you see strange results when playing with FACT in MPC8xxADS.h, don't be suprised. Currently, from what i can tell, the CPU is running 2x as fast as what the boot prints out to the console, i.e. a FACT of 5 will print 50MHz, but the cpu is actually running at 100MHz. I will post futher patches and information after I figure out what went wrong. -- Nye Liu nliu(a)mrv.com (818) 772-6235x248 "Who would be stupid enough to quote a fictitious character?" -- Don Quixote

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Re: [U-Boot-Users] Patch: Support for Motorola PQ2FADS-ZU board
by Rick Bronson 24 Jul '03

24 Jul '03

Hi Yuli, I have a PQ2FADS-ZU board with a 8270 and am having trouble getting the ethernet working. I was wondering if you were able to get yours functional. When I do: tftp 0x0 host/memtest.bin it shows: => tftp 0x0 host/memtest.bin TFTP from server 10.186.20.95; our IP address is 10.186.20.99 Filename 'host/memtest.bin'. Load address: 0x0 Loading: T T T T ... Everytime the T occurs the collision light comes on on my 10 Mbit-only hub. I commented out the 1st line of: miiphy_write(0, 16, 0x610); miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); because bit 0x400 on register 16 on the Davicom 9161 part doesn't exist but it had no effect. One idea I have is that the speed (baud) is wrong but I couldn't find anywhere to set it in the docs. Any ideas/help are greatly appreciated. Rick Bronson

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RE: [U-Boot-Users] ECC code used in cmd_nand.c
by Woodruff, Richard 24 Jul '03

24 Jul '03

.. Shouldn't the noecc check be doing a if(start != round_down(start,0x200)) and a check for less than size 0x200? This should ensure that the address is at the proper boundary....does your board have sram/dram at 0. rkw > -----Original Message----- > From: Woodruff, Richard > Sent: Wednesday, July 23, 2003 5:59 PM > To: 'dge(a)sixnetio.com' > Cc: u-boot-users(a)lists.sourceforge.net > Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c > > > I'm thinking part of the problem I was having was my command > is bring up a > bug: > nand write 10008000 0 200 > > This will result in nand_rw calling nand_write_ecc with > an eccbuf = NULL, as the size and alignment check does not > work for the first block (noecc = (start!=start... ). > Nand_rw passes this to nand_write_ecc which passes it onto > nand_write page. Which then acts like its valid and starts > trying to read and write to address 0. As I have ROM there > what ends up going into the oob is my rom's first instruction. > > I've feeling a bit slow at the moment, and am wondering if > the rounding to see if we are starting on an aligned address > is even correct. > > As far as R/B goes, I have two types of systems, one has it > and the other doesn't. I've inserted code which seems to > allow things to work without a R/B connected...mainly using > the status read to wait till not busy followed by a read to > check for success or failure. The only real pain with out > having a RB and doing this all with GPIOs is my ARM does not > have anything which allows the equivalent of a ppc "sync" > instruction, so dependencies on the memory controller's > scheduling creep up. > > Regards/Thanks, > > Richard W. > > > > > -----Original Message----- > > From: Dave Ellis [mailto:dge@sixnetio.com] > > Sent: Wednesday, July 23, 2003 1:38 PM > > To: Woodruff, Richard > > Cc: u-boot-users(a)lists.sourceforge.net > > Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c > > > > > > Richard Woodruff wrote: > > > Can anyone verify that the write using "nand write aaaa > offf ssss" > > > should work with ECC enabled? I'm finding that if I > disable the ECC > > > generation I can write uImages and compare them and get what I > > > expect and boot from them. > > > > It has been working fine for me using the SXNI855T > > configuration. I built this morning's CVS version and it also > > seems OK. > > > > > If I enable ECC generation, on read it complains that > they are all > > > wrong (but there is no errors on the write which I think > it should > > > give if the written ecc does not match the calculated one). If I > > > disregard the ecc warnings and then "cmp" the data starting which > > > was loaded, the first 16k are indeed the same (16k is my block > > > size), however, there is some differences at the end of the first > > > block. Again, if I disable ECC no such problem. > > > > If you write if with ECC, but read it back without ECC is the > > data still corrupted? The data may be OK until the bad ECC > > data is used to 'correct' it. > > > > > ...If I do a read.oob of the first block, it appears that the > > > data_buf[0] is written to the first position of the oob, > instead of > > > the expected data. > > > > Are you sure NanD_WaitReady() is working? If it isn't, you > > could start to read the oob data before it is ready, and > > would see some old data from the start of the buffer. > > > > Dave > > > > Dave Ellis > > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > SIXNET - "Leading the Industrial Ethernet Revolution" > > 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA > > Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 > > Email me at: dge(a)sixnetio.com > > Detailed product info: www.sixnetio.com > > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > > > > > > ------------------------------------------------------- > This SF.Net email sponsored by: Free pre-built ASP.NET sites > including Data Reports, E-commerce, Portals, and Forums are > available now. Download today and enter to win an XBOX or > Visual Studio .NET. > http://aspnet.click-url.com/go/psa00100003ave/direct;at.aspnet _072303_01/01 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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RE: [U-Boot-Users] RE: Nand OOB layout, u-boot and the kernel sou rces do not agree.. ??
by Woodruff, Richard 24 Jul '03

24 Jul '03

The u-boot from CVS 4.4 has CONFIG_MTD_NAND_ECC_JFFS commented out by default. This results in NAND_NOOB_ECCPOS5 being defined for ECC. The header file sets defines this as position 5....right below the badblock pos is set position 5. An ECC value will be written to the bad block spot when calculated...turn on JFFS2 and this problem goes away...however, something is fishy in the bad_block and position 5 resolution code for some reason. The codes addressing doesn't look like whats in the kernel tree. At some point I'll submit a patch, but if someone else does it first that's just fine. Richard W. > -----Original Message----- > From: Dave Ellis [mailto:dge@sixnetio.com] > Sent: Thursday, July 24, 2003 2:00 PM > To: Woodruff, Richard > Cc: u-boot-users(a)lists.sourceforge.net > Subject: RE: [U-Boot-Users] RE: Nand OOB layout, u-boot and > the kernel sources do not agree.. ?? > > > Richard Woodruff wrote: > > Sent: Thursday, July 24, 2003 1:57 PM > > > -----Original Message----- > > > From: Woodruff, Richard > > > Sent: Thursday, July 24, 2003 12:45 PM > > > While trying to resolve what the OOB data layout should be I > > > see that the kernel headers as of 8-10-2002 have changed such > > > that both the NAND_JFFS2 and NAND_NOOB use position 5 for bad > > > block data. The u-boot headers do not reflect this > > > change...doesn't this mean u-boot will be incompatible with > > > more recent kernels? Should u-boot's headers be updated here? > > Position 5 is where the chip makers mark bad sectors, so we > do not get a choice. The NAND_NOOB values in U-BOOT are wrong > and should be changed to match the new ones in the Linux > kernel. I think the original cmd_nand.c was based on a very > old version of MTD. > > > ... Having more up to date definitions would seem better....as > > raw nand doesn't seem to be well supported except with jffs2 & > > possibly yaffs I don't suppose the NAND_NOOB is such a concern. > > I don't know what software (if any) uses NAND_NOOB, but I > think the definitions still should be fixed (or removed). In > my patch to cmd_nand.c I hard coded the bad block position at > 5, so they can't be used as they are. > > Dave > > Dave Ellis > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > SIXNET - "Leading the Industrial Ethernet Revolution" > 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA > Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 > Email me at: dge(a)sixnetio.com > Detailed product info: www.sixnetio.com > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > >

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[U-Boot-Users] RE: Nand OOB layout, u-boot and the kernel sources do not agree.. ??
by Woodruff, Richard 24 Jul '03

24 Jul '03

Looking about infradead.org tells that the OOB area can be reconfigured via ioctl. I suppose that this is something which would be needed prior to mount. Having more up to date definitions would seem better....as raw nand doesn't seem to be well supported except with jffs2 & possibly yaffs I don't suppose the NAND_NOOB is such a concern. Richard W. -----Original Message----- From: Woodruff, Richard Sent: Thursday, July 24, 2003 12:45 PM To: u-boot-users(a)lists.sourceforge.net Subject: Nand OOB layout, u-boot and the kernel sources do not agree..?? Hello, While trying to resolve what the OOB data layout should be I see that the kernel headers as of 8-10-2002 have changed such that both the NAND_JFFS2 and NAND_NOOB use position 5 for bad block data. The u-boot headers do not reflect this change...doesn't this mean u-boot will be incompatible with more recent kernels? Should u-boot's headers be updated here? Regards, Richard W.

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[U-Boot-Users] Nand OOB layout, u-boot and the kernel sources do not agree..??
by Woodruff, Richard 24 Jul '03

24 Jul '03

Hello, While trying to resolve what the OOB data layout should be I see that the kernel headers as of 8-10-2002 have changed such that both the NAND_JFFS2 and NAND_NOOB use position 5 for bad block data. The u-boot headers do not reflect this change...doesn't this mean u-boot will be incompatible with more recent kernels? Should u-boot's headers be updated here? Regards, Richard W.

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[U-Boot-Users] More on serial terminal and u-boot
by Brian S. Park 24 Jul '03

24 Jul '03

Hi all, I've been trouble shooting the problem of u-Boot not coming up when serial terminal is not connected. It turned out that when software CONFIG_SERIAL_SOFTWARE_FIFO is defined, putc will wait till terminal is ready to receive the data. From u-boot/cpu/ppc4xx/serial.c, line 676 void serial_buffered_putc (const char c) { /* Wait for CTS */ #if defined(CONFIG_HW_WATCHDOG) while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) WATCHDOG_RESET (); #else while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); #endif serial_putc (c); } Is the while loop necessary? printf's are ok because it uses serial_buffered_puts which eventually calls serial_putc with out waiting for CTS. Thank you Brian =============================================================== Brian S. Park brian(a)corelis.com (562) 926-6727 x143 --------------------------------------------------------------- Everything we do helps our customers get to market FASTER with HIGHER quality and LOWER cost ===============================================================

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[U-Boot-Users] Nios Port
by Scott McNutt 24 Jul '03

24 Jul '03

Is anyone working on a Nios port? If yes, please let me know how I can help. Otherwise, I started a Nios port myself and I welcome anyone interested in contributing. Regards, --Scott

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[U-Boot-Users] [PATCH] jffs2 indirect access.
by Kenneth Johansson 24 Jul '03

24 Jul '03

This is a patch that alters the jffs2 code to work on flash devices that is not directly memory mapped without the need to copy the whole flash to RAM. It is not ready for inclusion and I do not think I will push it as it was quite a bit slower than I expected. It also needs a little more cleanup. A callback function is added to struct part_info that works like memcpy and is the thing actually reading the flash. The offset member is gone and the jffs2 code always uses 0 as the start address for the filesystem. It is up to the callback function to remap that into something useful. This code however uses less memory than copying the flash to ram but it is slower. jffs2_scan_empty() could use some speedup but even in situations when that one is not taking mush time this is slower by a factor of 2-3. It's only faster if you happens to have ridiculously slow flash. I'm going on vacation and is not going to work more on this so if someone wants this added to u-boot you have to fix a proper patch yourself. -- Kenneth Johansson Ericsson AB Tel: +46 8 719 70 20 Tellusborgsvägen 90 Fax: +46 8 719 29 45 126 25 Stockholm ken(a)switchboard.ericsson.se

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[U-Boot-Users] Re: JFFS2: CRC Problem with Kernel Image
by Martin, Vitali 24 Jul '03

24 Jul '03

> How did the pImage file get to /dev/mtdblock1 in the first place? bash-2.05# eraseall /dev/mtd1 bash-2.05# mount -t jffs2 /dev/mtdblock1 /mnt/ bash-2.05# cp /pImage /mnt/ > We had a problem a while back where using scp to copy an image ... I'm using "cp" from the linux console, so I think there is no interrupt problem. Because I can copy pImage to JFFS2 filesystem and my image is still OK. I checked the memory with "md 100000" in U-Boot and there seems to be not the same data on the memory address 0x100 when I using "tftp 1000 pImage" and "fsload 10000 pImage". From address 0x101000 the data im the RAM memory is different??? ->tftp 10000 pImage TFTP from server 172.22.20.193; our IP address is 172.22.10.33 Filename 'pImage'. Load address: 0x10000 Loading: T ###################T #TX timeout done Bytes transferred = 520149 (7efd5 hex) ->md 100000 200000 00100000: 27051956 52c9c624 3f1d4bb5 0007ef95 '..VR..$?.K..... 00100010: 00000000 00000000 5171b599 05070201 ........Qq...... 00100020: 4c696e75 782d322e 342e3400 00000000 Linux-2.4.4..... ... 00101000: dfc958e0 5f66d603 e27f2fe3 0027f536 ..X._f..../..'.6 00101010: c055f99e f5e16e85 bd761595 a9ce7bd2 .U....n..v....{. ->fsload 100000 pImage ### JFFS2 loading 'pImage' to 0x100000 ### JFFS2 load complete: 520149 bytes loaded to 0x100000 ->md 100000 200000 00100000: 27051956 52c9c624 3f1d4bb5 0007ef95 '..VR..$?.K..... 00100010: 00000000 00000000 5171b599 05070201 ........Qq...... 00100020: 4c696e75 782d322e 342e3400 00000000 Linux-2.4.4..... ... 00101000: dfc9c970 de53a432 188d2417 af469b2b ...p.S.2..$..F.+ 00101010: 7dd3d9cf e1df4c64 65acdb75 83efc98b }.....Lde..u....

2 1

[U-Boot-Users] Serial terminal & u-Boot
by Brian S. Park 24 Jul '03

24 Jul '03

Hi all, I'm using u-Boot 0.4.0 with our custom board based on IBM walnut. I noticed that if I do not have the HyperTerminal running, the boot process never proceeds. If I power up the target with out HyperTerminal running, it never comes up. As soon as start HyperTerminal, I see print out for Kernel download and the board boots up. It looks as though it was waiting for the serial communication before it starts downloading the kernel over the ethernet. Is this normal behavior? Is there a way to make it boot up regardless of whether a serial terminal is connected or not? Thank you Brian =============================================================== Brian S. Park brian(a)corelis.com (562) 926-6727 x143 --------------------------------------------------------------- Everything we do helps our customers get to market FASTER with HIGHER quality and LOWER cost ===============================================================

3 5

[U-Boot-Users] cmd_nand.c :: check_block, wrong bad block pos ?
by Woodruff, Richard 24 Jul '03

24 Jul '03

Hello, Well I just got nand and ECC to work on my little endian ARM board. By using the following corrected round nand_rw zero deferences were stopped: noecc = (start != ROUND_DOWN(start, 0x200)) || (len < 0x200) ; And, I'm not quite sure what why, perhaps endianess, the read_oob in check block was returning byte 6 from the oob instead of 5. By changing it to ask for (badpos + 1) it started returning the correct byte. I'll need to check into this one a bit more. Does anyone know why badpos by itself is not enough? After I test a little I can post a patch back for others to test against. Regards, Richard W. -----Original Message----- From: Woodruff, Richard Sent: Wednesday, July 23, 2003 6:23 PM To: 'dge(a)sixnetio.com' Cc: u-boot-users(a)lists.sourceforge.net Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c .. Shouldn't the noecc check be doing a if(start != round_down(start,0x200)) and a check for less than size 0x200? This should ensure that the address is at the proper boundary....does your board have sram/dram at 0. rkw > -----Original Message----- > From: Woodruff, Richard > Sent: Wednesday, July 23, 2003 5:59 PM > To: 'dge(a)sixnetio.com' > Cc: u-boot-users(a)lists.sourceforge.net > Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c > > > I'm thinking part of the problem I was having was my command > is bring up a > bug: > nand write 10008000 0 200 > > This will result in nand_rw calling nand_write_ecc with > an eccbuf = NULL, as the size and alignment check does not > work for the first block (noecc = (start!=start... ). > Nand_rw passes this to nand_write_ecc which passes it onto > nand_write page. Which then acts like its valid and starts > trying to read and write to address 0. As I have ROM there > what ends up going into the oob is my rom's first instruction. > > I've feeling a bit slow at the moment, and am wondering if > the rounding to see if we are starting on an aligned address > is even correct. > > As far as R/B goes, I have two types of systems, one has it > and the other doesn't. I've inserted code which seems to > allow things to work without a R/B connected...mainly using > the status read to wait till not busy followed by a read to > check for success or failure. The only real pain with out > having a RB and doing this all with GPIOs is my ARM does not > have anything which allows the equivalent of a ppc "sync" > instruction, so dependencies on the memory controller's > scheduling creep up. > > Regards/Thanks, > > Richard W. > > > > > -----Original Message----- > > From: Dave Ellis [mailto:dge@sixnetio.com] > > Sent: Wednesday, July 23, 2003 1:38 PM > > To: Woodruff, Richard > > Cc: u-boot-users(a)lists.sourceforge.net > > Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c > > > > > > Richard Woodruff wrote: > > > Can anyone verify that the write using "nand write aaaa > offf ssss" > > > should work with ECC enabled? I'm finding that if I > disable the ECC > > > generation I can write uImages and compare them and get what I > > > expect and boot from them. > > > > It has been working fine for me using the SXNI855T > > configuration. I built this morning's CVS version and it also > > seems OK. > > > > > If I enable ECC generation, on read it complains that > they are all > > > wrong (but there is no errors on the write which I think > it should > > > give if the written ecc does not match the calculated one). If I > > > disregard the ecc warnings and then "cmp" the data starting which > > > was loaded, the first 16k are indeed the same (16k is my block > > > size), however, there is some differences at the end of the first > > > block. Again, if I disable ECC no such problem. > > > > If you write if with ECC, but read it back without ECC is the > > data still corrupted? The data may be OK until the bad ECC > > data is used to 'correct' it. > > > > > ...If I do a read.oob of the first block, it appears that the > > > data_buf[0] is written to the first position of the oob, > instead of > > > the expected data. > > > > Are you sure NanD_WaitReady() is working? If it isn't, you > > could start to read the oob data before it is ready, and > > would see some old data from the start of the buffer. > > > > Dave > > > > Dave Ellis > > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > SIXNET - "Leading the Industrial Ethernet Revolution" > > 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA > > Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 > > Email me at: dge(a)sixnetio.com > > Detailed product info: www.sixnetio.com > > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > > > > > > ------------------------------------------------------- > This SF.Net email sponsored by: Free pre-built ASP.NET sites > including Data Reports, E-commerce, Portals, and Forums are > available now. Download today and enter to win an XBOX or > Visual Studio .NET. > http://aspnet.click-url.com/go/psa00100003ave/direct;at.aspnet _072303_01/01 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users ------------------------------------------------------- This SF.Net email sponsored by: Free pre-built ASP.NET sites including Data Reports, E-commerce, Portals, and Forums are available now. Download today and enter to win an XBOX or Visual Studio .NET. http://aspnet.click-url.com/go/psa00100003ave/direct;at.aspnet_072303_01/01 _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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RE: [U-Boot-Users] ECC code used in cmd_nand.c
by Woodruff, Richard 24 Jul '03

24 Jul '03

I'm thinking part of the problem I was having was my command is bring up a bug: nand write 10008000 0 200 This will result in nand_rw calling nand_write_ecc with an eccbuf = NULL, as the size and alignment check does not work for the first block (noecc = (start!=start... ). Nand_rw passes this to nand_write_ecc which passes it onto nand_write page. Which then acts like its valid and starts trying to read and write to address 0. As I have ROM there what ends up going into the oob is my rom's first instruction. I've feeling a bit slow at the moment, and am wondering if the rounding to see if we are starting on an aligned address is even correct. As far as R/B goes, I have two types of systems, one has it and the other doesn't. I've inserted code which seems to allow things to work without a R/B connected...mainly using the status read to wait till not busy followed by a read to check for success or failure. The only real pain with out having a RB and doing this all with GPIOs is my ARM does not have anything which allows the equivalent of a ppc "sync" instruction, so dependencies on the memory controller's scheduling creep up. Regards/Thanks, Richard W. > -----Original Message----- > From: Dave Ellis [mailto:dge@sixnetio.com] > Sent: Wednesday, July 23, 2003 1:38 PM > To: Woodruff, Richard > Cc: u-boot-users(a)lists.sourceforge.net > Subject: RE: [U-Boot-Users] ECC code used in cmd_nand.c > > > Richard Woodruff wrote: > > Can anyone verify that the write using "nand write aaaa offf > > ssss" should work with ECC enabled? I'm finding that if I > > disable the ECC generation I can write uImages and compare > > them and get what I expect and boot from them. > > It has been working fine for me using the SXNI855T > configuration. I built this morning's CVS version and it also > seems OK. > > > If I enable ECC generation, on read it complains that they > > are all wrong (but there is no errors on the write which I > > think it should give if the written ecc does not match the > > calculated one). If I disregard the ecc warnings and then > > "cmp" the data starting which was loaded, the first 16k are > > indeed the same (16k is my block size), however, there is > > some differences at the end of the first block. Again, if I > > disable ECC no such problem. > > If you write if with ECC, but read it back without ECC is the > data still corrupted? The data may be OK until the bad ECC > data is used to 'correct' it. > > > ...If I do a read.oob of the first block, it appears that the > > data_buf[0] is written to the first position of the oob, > > instead of the expected data. > > Are you sure NanD_WaitReady() is working? If it isn't, you > could start to read the oob data before it is ready, and > would see some old data from the start of the buffer. > > Dave > > Dave Ellis > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > SIXNET - "Leading the Industrial Ethernet Revolution" > 331 Ushers Road, P.O. Box 767, Clifton Park, NY 12065 USA > Tel +1 (518) 877-5173 Fax +1 (518) 877-8346 > Email me at: dge(a)sixnetio.com > Detailed product info: www.sixnetio.com > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > >

1 0

[U-Boot-Users] ECC code used in cmd_nand.c
by Woodruff, Richard 23 Jul '03

23 Jul '03

Hello, Can anyone verify that the write using "nand write aaaa offf ssss" should work with ECC enabled? I'm finding that if I disable the ECC generation I can write uImages and compare them and get what I expect and boot from them. If I enable ECC generation, on read it complains that they are all wrong (but there is no errors on the write which I think it should give if the written ecc does not match the calculated one). If I disregard the ecc warnings and then "cmp" the data starting which was loaded, the first 16k are indeed the same (16k is my block size), however, there is some differences at the end of the first block. Again, if I disable ECC no such problem. ...If I do a read.oob of the first block, it appears that the data_buf[0] is written to the first position of the oob, instead of the expected data. Regards/Thanks for any info, Richard W.

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[U-Boot-Users] RE: u-boot on Memec P4/7-FG456 (w/ virtex II pro)?
by Shamile Khan 23 Jul '03

23 Jul '03

Hi Frank, We are trying to port u-boot to Memec P4/7-FG456 as well. What did you have to do to get the serial port working. Also did you get it to work with uart lite that ships with EDK or the full uart that has to be purchased separately. Thanks, Shamile

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[U-Boot-Users] Re: JFFS2: CRC Problem with Kernel Image
by Martin, Vitali 22 Jul '03

22 Jul '03

> Which version of U-Boot is this? 0.4.1 > Are you sure the image is still OK? My target mounts root filesystem over NFS. So running on my host system "mkimage -l /mnt/pImage" works: Target: bash-2.05# mount -t jffs2 /dev/mtdblock1 /mnt/ bash-2.05# cd /mnt/ bash-2.05# ll total 514 -rw-r--r-- 1 root root 525815 Jul 22 13:31 pImage bash-2.05# cp pImage /pImage Host: vm@pc241:/nfs/eldk/ppc_8xx> mkimage -l pImage Image Name: Linux-2.4.4 Created: Tue Jul 22 15:28:19 2003 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 525751 Bytes = 513.43 kB = 0.50 MB Load Address: 0x00000000 Entry Point: 0x00000000 With the same image "tftpboot" works fine. ->tftp 100000 pImage TFTP from server 172.22.20.193; our IP address is 172.22.10.33 Filename 'pImage'. Load address: 0x100000 Loading: T ################################## done Bytes transferred = 525815 (805f7 hex) ->imi ## Checking Image at 00100000 ... Image Name: Linux-2.4.4 Created: 2003-07-22 13:28:19 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 525751 Bytes = 513.4 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK -> So I am sure that my image file is OK, I suppose something goes wrong in "fsload", when pImage will copied to memory.

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RE: [U-Boot-Users] MPC8260/66: SDRAM init
by Rune Torgersen 22 Jul '03

22 Jul '03

Hi The reason this works on the MPC826xADS boards is that this is only necessary to do when the 60x bus is in 60x mode. When the bus is in "Single PowerQUICC II bus mode" (BCR register bit 0 (EBM) = 0), the value driven on the bus when writing to ramaddr after the mode set command, comes from the PSDMR register. All the 826xADS boards defaults to single 8260 mode bus. (no external cache and multiplexers) > -----Original Message----- > From: Holger Speck [mailto:hospe@gmx.de] > Sent: Tuesday, July 22, 2003 03:46 > To: u-boot-users(a)lists.sourceforge.net > Subject: [U-Boot-Users] MPC8260/66: SDRAM init > > > Hello, > > I had some problems with the initialisation of SDRAM (64MB) > on 60x bus. Below the code I changed according to MPC8260 UM/D: > > memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */ > /* see 11.4.9 SDRAM MODE-SET Command Timming MPC8260 UM/D > 05/2003, REV 1 */ > /* send mode (CAS latency as in PSDMR and burst length for > 16- or 64-bit > ports) to SDRAM > */ > ramaddr = (uchar *) (CFG_SDRAM_BASE | (((cas_latency << 4) | > 0x2) << 3)); *ramaddr = c; > > The original code does not set "ramaddr" to the mode value. I > tested this new code on special board derived from the > MPC8260ADS. I'm a litte bit astonished that the original code > works on the MPC8260ADS. > > Grettings, > Holger > > > > > ------------------------------------------------------- > This SF.net email is sponsored by: VM Ware > With VMware you can run multiple operating systems on a > single machine. WITHOUT REBOOTING! Mix Linux / Windows / > Novell virtual machines at the same time. Free trial click > here: http://www.vmware.com/wl/offer/345/0 > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users >

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AW: [U-Boot-Users] tftp server for Windows
by Martin, Vitali 22 Jul '03

22 Jul '03

I succefully used "SolarWinds.Net TFTP Server".

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[U-Boot-Users] JFFS2: CRC Problem with Kernel Image
by Martin, Vitali 22 Jul '03

22 Jul '03

Hi all, I have an PowerPC board running U-Boot and Linux. So I created an JFFS2 filesystem on one of my static MTD partitions an put the Kernel Image into. bash-2.05# eraseall /dev/mtd1 Erased 4096 Kibyte @ 0 -- 100% complete. bash-2.05# mount -t jffs2 /dev/mtdblock1 /mnt/ bash-2.05# cp /pImage /mnt/ bash-2.05# cd /mnt/ bash-2.05# ls -l total 527 -rw-r--r-- 1 root root 539419 Jul 22 11:36 pImage bash-2.05# cd .. bash-2.05# umount /mnt/ Then I reboot my board and U-Boot starts. I copy the Kernel Image to the memory with "fsload". But running "iminfo" or "bootm" I get a CRC Error. Some ideas what's wrong? (Thank you for any help.) ->ls Scanning JFFS2 FS: . done. -rw-r--r-- 539419 Tue Jul 22 15:42:25 2003 pImage ->fsload 100000 pImage ### JFFS2 loading 'pImage' to 0x100000 ### JFFS2 load complete: 539419 bytes loaded to 0x100000 ->iminfo 100000 ## Checking Image at 00100000 ... Image Name: Linux-2.4.4 Created: 2003-07-21 14:53:03 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 539355 Bytes = 526.7 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... Bad Data CRC ->

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Re: [U-Boot-Users] Debugging u-boot with BDI2000
by Wolfgang Denk 22 Jul '03

22 Jul '03

Dear Jürgen, in message <200307211005.32005.jbeisert(a)eurodsn.de> you wrote: > > My code does some modifications in chipset registers. One of it seems the bad > one and the cpu hangs when executing it. While I can't trace it, I have now > disabled the modifications step by step and find the bad one (OPBA0_CR). > > Does anybody knows something about the registers OPBA0_CR and OPBA0_PR > (OPB Arbiter control and priority)? After reset it's contents shows illegal > bit values (if I try to interpret the value after reset based on my 405GP > manual). And which CPU model is on your board? Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de "Most people would like to be delivered from temptation but would like it to keep in touch." - Robert Orben

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[U-Boot-Users] MPC8260/66: SDRAM init
by Holger Speck 22 Jul '03

22 Jul '03

Hello, I had some problems with the initialisation of SDRAM (64MB) on 60x bus. Below the code I changed according to MPC8260 UM/D: memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */ /* see 11.4.9 SDRAM MODE-SET Command Timming MPC8260 UM/D 05/2003, REV 1 */ /* send mode (CAS latency as in PSDMR and burst length for 16- or 64-bit ports) to SDRAM */ ramaddr = (uchar *) (CFG_SDRAM_BASE | (((cas_latency << 4) | 0x2) << 3)); *ramaddr = c; The original code does not set "ramaddr" to the mode value. I tested this new code on special board derived from the MPC8260ADS. I'm a litte bit astonished that the original code works on the MPC8260ADS. Grettings, Holger

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RE: [U-Boot-Users] tftp server for Windows
by Scott McNutt 21 Jul '03

21 Jul '03

Rune, I have been using TFTPD32 without any problems in a Windows 2000 environment: http://tftpd32.jounin.net Regards, --Scott > -----Original Message----- > From: Rune Raknerud [SMTP:rune.raknerud@cargoscan.com] > Sent: Monday, July 21, 2003 4:44 AM > To: U-Boot (E-mail) > Cc: Wolgang Denk (E-mail) > Subject: [U-Boot-Users] tftp server for Windows > > Hi > > I need to setup a tftp server on a Windows machine, and I tried to use > tftpsrv that is provided by Abatron. This works fine with my BDI2000, > but not with my custom MPC8245 board running u-boot. Both the BDI2000 > and the MPC8245 board work fine when connected to a tftp server on a > RedHat 7.3 machine. > > I use the following command for starting tftpsrv: tftpsrv w p > dc:\tftpboot\ > > The following is a screen capture of the console output from the MPC8245 > board. 172.23.151.225 is a PC running RedHat 7.3 and 172.23.151.232 is > a PC running Windows 2000 Prof and tftpserv from Abatron. I have enabled > debug output from u-boot. > > =>setenv serverip 172.23.151.225 > =>tftp 100000 8245.cfg > ARP broadcast 1 > Receive from protocol 0x806 > Got ARP > Got ARP REPLY, set server/gtwy eth addr > Got good ARP - start TFTP > > Server ethernet address 00:01:02:99:91:26 > TFTP from server 172.23.151.225; our IP address is 172.23.151.236 > Filename '8245.cfg'. > Load address: 0x100000 > Loading: *Receive from protocol 0x800 > Got IP > len=544, v=45 > #Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > #Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=544, v=45 > Receive from protocol 0x800 > Got IP > len=347, v=45 > > done > Bytes transferred = 7483 (1d3b hex) > => reset > > U-Boot 0.2.0 (Jul 18 2003 - 09:10:38) > > CPU: MPC8245 Revision 1.2 at 299.999 MHz: 16 kB I-Cache 16 kB D-Cache > Board: Cargoscan CS0045 CPU/RF PowerPC MPC8245 > I2C: ready > DRAM: 64 MB > Altera 1k10 ,,,,,,,,,,,,,,,,,,, > Altera 1k50 > ........................................................................ > ......................... > FPGA: ready on 1 atempt. > FLASH: 8 MB > In: serial > Out: serial > Err: serial > Net: i82559#0, i82559#1 > IDE: Bus 0: OK > Device 0: Model: SanDisk SDCFB-64 Firm: vde 1.10 Ser#: 20312131908 > Type: Removable Hard Disk > Capacity: 61.2 MB = 0.0 GB (125440 x 512) > => printenv baudrate=38400 > serial#=AO031245612346 > filesize=9fdf1 > sereverip=172.23.151.231 > serverip=172.23.151.232 > ipaddr=172.23.151.236 > bootargs=console=ttyS0,38400 root=/dev/nfs rw > nfsroot=/home/filesystems/mvl30 > ip=172.23.151.233:172.23.151.232:172.23.151.40:255.255.255.0:io:eth0 > ide0=0xfe0001f0,0xfe0003f6,19 > stdin=serial > stdout=serial > stderr=serial > > Environment size: 342/131068 bytes > => tftp 100000 8245.cfg > ARP broadcast 1 > Receive from protocol 0x806 > Got ARP > Got ARP REPLY, set server/gtwy eth addr > Got good ARP - start TFTP > > Server ethernet address 00:08:74:3b:61:58 > TFTP from server 172.23.151.232; our IP address is 172.23.151.236 > Filename '8245.cfg'. > Load address: 0x100000 > Loading: *Receive from protocol 0x800 > Got IP > len=56, v=45 > Receive from protocol 0x800 > Got IP > len=128, v=45 > T Receive from protocol 0x800 > Got IP > len=56, v=45 > Receive from protocol 0x806 > Got ARP > T Receive from protocol 0x800 > Got IP > len=56, v=45 > Receive from protocol 0x8137 > Receive from protocol 0x806 > Got ARP > > Abort > => > > From the u-boot output, it looks like the packet lengths is to short. > > Have any of you got the Abatron tftpsrv to work with u-boot. If yes, how > did you do it? If no, do you know of any other tftp servers that run > under Windows and work with u-boot? > > Best regards > Rune Raknerud > Cargoscan AS > > > ------------------------------------------------------- > This SF.net email is sponsored by: VM Ware > With VMware you can run multiple operating systems on a single machine. > WITHOUT REBOOTING! Mix Linux / Windows / Novell virtual machines at the > same time. Free trial click here: http://www.vmware.com/wl/offer/345/0 > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] tftp server for Windows
by Rune Raknerud 21 Jul '03

21 Jul '03

Hi I need to setup a tftp server on a Windows machine, and I tried to use tftpsrv that is provided by Abatron. This works fine with my BDI2000, but not with my custom MPC8245 board running u-boot. Both the BDI2000 and the MPC8245 board work fine when connected to a tftp server on a RedHat 7.3 machine. I use the following command for starting tftpsrv: tftpsrv w p dc:\tftpboot\ The following is a screen capture of the console output from the MPC8245 board. 172.23.151.225 is a PC running RedHat 7.3 and 172.23.151.232 is a PC running Windows 2000 Prof and tftpserv from Abatron. I have enabled debug output from u-boot. =>setenv serverip 172.23.151.225 =>tftp 100000 8245.cfg ARP broadcast 1 Receive from protocol 0x806 Got ARP Got ARP REPLY, set server/gtwy eth addr Got good ARP - start TFTP Server ethernet address 00:01:02:99:91:26 TFTP from server 172.23.151.225; our IP address is 172.23.151.236 Filename '8245.cfg'. Load address: 0x100000 Loading: *Receive from protocol 0x800 Got IP len=544, v=45 #Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 #Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=544, v=45 Receive from protocol 0x800 Got IP len=347, v=45 done Bytes transferred = 7483 (1d3b hex) => reset U-Boot 0.2.0 (Jul 18 2003 - 09:10:38) CPU: MPC8245 Revision 1.2 at 299.999 MHz: 16 kB I-Cache 16 kB D-Cache Board: Cargoscan CS0045 CPU/RF PowerPC MPC8245 I2C: ready DRAM: 64 MB Altera 1k10 ,,,,,,,,,,,,,,,,,,, Altera 1k50 ........................................................................ ......................... FPGA: ready on 1 atempt. FLASH: 8 MB In: serial Out: serial Err: serial Net: i82559#0, i82559#1 IDE: Bus 0: OK Device 0: Model: SanDisk SDCFB-64 Firm: vde 1.10 Ser#: 20312131908 Type: Removable Hard Disk Capacity: 61.2 MB = 0.0 GB (125440 x 512) => printenv baudrate=38400 serial#=AO031245612346 filesize=9fdf1 sereverip=172.23.151.231 serverip=172.23.151.232 ipaddr=172.23.151.236 bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=/home/filesystems/mvl30 ip=172.23.151.233:172.23.151.232:172.23.151.40:255.255.255.0:io:eth0 ide0=0xfe0001f0,0xfe0003f6,19 stdin=serial stdout=serial stderr=serial Environment size: 342/131068 bytes => tftp 100000 8245.cfg ARP broadcast 1 Receive from protocol 0x806 Got ARP Got ARP REPLY, set server/gtwy eth addr Got good ARP - start TFTP Server ethernet address 00:08:74:3b:61:58 TFTP from server 172.23.151.232; our IP address is 172.23.151.236 Filename '8245.cfg'. Load address: 0x100000 Loading: *Receive from protocol 0x800 Got IP len=56, v=45 Receive from protocol 0x800 Got IP len=128, v=45 T Receive from protocol 0x800 Got IP len=56, v=45 Receive from protocol 0x806 Got ARP T Receive from protocol 0x800 Got IP len=56, v=45 Receive from protocol 0x8137 Receive from protocol 0x806 Got ARP Abort => >From the u-boot output, it looks like the packet lengths is to short. Have any of you got the Abatron tftpsrv to work with u-boot. If yes, how did you do it? If no, do you know of any other tftp servers that run under Windows and work with u-boot? Best regards Rune Raknerud Cargoscan AS

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[U-Boot-Users] [PATCH] fixed tftp error message output
by Andreas Oberritter 20 Jul '03

20 Jul '03

This patch fixes tftp error message output, i.e. does not print the last two bytes which contain garbage (at least for my setup, I hope this is not a tftp server issue). Changelog: Patch by Andreas Oberritter, 19 July 03 - fixed tftp error message output

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[U-Boot-Users] [PATCH] Flash IDs for STM M28W320CB
by Andreas Oberritter 19 Jul '03

19 Jul '03

A trivial patch for include/flash.h Changelog: Patch by Andreas Oberritter, 19 July 03: - Add IDs for STM M28W320CB 32MBit flash type

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[U-Boot-Users] [PATCH] fixed reset command on mpc8xx
by Andreas Oberritter 19 Jul '03

19 Jul '03

This patch does reset on 8xx like the linux kernel does it. Works without crashing u-boot unlike the previous version. Tested on mpc823. Changelog: Patch by Andreas Oberritter, 19 July 03 - fixed reset command on mpc8xx

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[U-Boot-Users] Debugging u-boot with BDI2000
by Juergen Beisert 18 Jul '03

18 Jul '03

Hello Wolfgang, >>I'm trying to debug my u-boot with BDI. It's a 405GP based system. >> In the telnet sessoin I can insert "reset run" and u-boot starts. When I >> enter "reset halt" and then "go" it won't do anything. I have tried with >> ddd > >What do you mean with "it won't do anything"? Who won't do anything? >The BDI2000? The CPU? What makes you think the CPU does not do >anything? At first I thought the 405GP cpu does not start. On my card is a LED display, so I can output some numbers very early in the startup process. With "reset halt", "go" the display never change its contents, with "reset run" it does. >Are you sure your BDI2000 config file is OK for your board? Good question. What should happen, to be shure? I have debugged a running Linux kernel with this configuration. So I think(!) the major settings are ok. > How did you configure "RESET type" and "STARTUP mode"? Is your > "START address" ok? RESET is not set, defaults to "SYSTEM" STARTUP is set to RESET START is set to 0x0000'0000 (readed from a default file) With "reset halt", "info" I see the CPU waiting at address 0xFFFF'FFFC, after one single step ("ti") it waits at address 0xFFFF'C0100. Seems ok. >> When I step the mtmsr instruction ddd shows address 0x700, and the esr >> register has 0x8800'0000 (illegal instruction occured?????). >> Same when I place a breakpoint behind the mtmsr instruction und use "cont" >> instead of "stepi". > >You are aware that you cannot single step through certain >instructions, aren't you? If the mtmsr instruction is not "single step able", it should run, if I place a breakpoint behind this instruction (for example later in the C routines) and use "go" to run up the breakpoint. Or not? >> What is the difference between "reset run" and "reset halt", "go"? >"reset run" and "reset halt" change the startup mode to "run" and >"halt", respectively. "go" sets the PC and starts the target system. >Ummm.. is there any specific part where the BDI2000 manual is unclear >about this? Perhaps my english is very bad. Question was: Why the cpu is running normal with "reset run", and did not run, when I enter "reset halt", enter a breakpoint and than "go" (it never reaches the breakpoint). -- JB

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Re: [U-Boot-Users] autoboot in U-boot
by Wolfgang Denk 18 Jul '03

18 Jul '03

Hello, in message <1058522316.1188.104.camel(a)localhost.localdomain> you wrote: > > > What do you get when you run the "printenv" command? > this is what i get when i issue printenv > > :>printenv > 0A" > $` > $A > .aB@ > stdgut=seri`l > stdin=serial > stdout=serial > stderr=serial > > Environment size: 71/262140 bytes As you can see, the environment contains only garbage. So it is not a big surprise that autoboot does not work as U-Boot cannot find a valid definition of the "bootdelay" environment variable. My suspicion that your environment is misconfigured seems to be correct. > > Why do you reserve 512 kB for U-Boot? U-Boot is needs much less > > memory! > > > err .. i dunno why.. did i reserve that much? hmm where do i configure > this. I hav just upgrade from ppcboot actually... and i am very new at > this boot loader stuff. All this is set in the board's config file. The relevant config variables are documented in the README file. > > Where are your environment variables stored? In flash? Embedded with > > the U-Boot image or separate? > > > environment variables?? i m really sorry, i m not sure what you are > talkin about. Is it board.c? Everything , the u-boot, kernel and ramdisk > is in flash. I am talking about variables and configuration parameters that U-Boot stores in the "environment". The envrionment can be stored in flash, I2C or SPI EEPROM, NVRAM, etc. Your environment is obviously misconfigured, which is the reason for your problems. > Thanks for your time in helping me out. I am sorry but I am new at this. > Well everyone has to start learning from somewhere. Maybe you find it useful to have a look at http://www.denx.de/re/DPLG.html Although this does not answer your immediate questions, it might help you to understand the concept of environment variables and what they can be used for. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de All your people must learn before you can reach for the stars. -- Kirk, "The Gamesters of Triskelion", stardate 3259.2

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[U-Boot-Users] autoboot in U-boot
by Sung 18 Jul '03

18 Jul '03

hi there, Can someone help me on this autoboot? I successfully configured the u-boot-0.4.0 for mpc857 custom board but somehow the bootcommand and boot arg would not run, it just skip the autoboot and goes to prompt. so help!!! this is part of the configuration .................................................................... #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled*/ #else #define CONFIG_BOOTDELAY 3 /* autoboot after 3 sec */ #endif #define CONFIG_BOOTCOMMAND "bootm 02800000 02880000" #define CONFIG_BOOTARGS "root=/dev/ram rw" #undef CONFIG_WATCHDOG /* watchdog disabled*/ #define CONFIG_SCC2_ENET 1 /* use SCC2 ethernet */ #undef CONFIG_FEC_ENET /* disable FEC ethernet */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> /* * Miscellaneous configurable options */ #undef CFG_LONGHELP /* undef to save memory*/ #define CFG_PROMPT ":>" /* Monitor CommandPrompt */ .................................................................. and this is the output displayed:- ...................................................................... U-Boot 0.4.0 (Jul 18 2003 - 10:17:35) CPU: unknown MPC850 (0x07000003) at 48 MHz: 4 kB I-Cache 4 kB D-Cache FEC pret *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** SDRAM: 16 MB Top of RAM usable for U-Boot at: 01000000 Reserving 512k for U-Boot at: 00f80000 Reserving 256k for malloc() at: 00f40000 Reserving 60 Bytes for Board Info at: 00f3ffc4 Reserving 52 Bytes for Global Data at: 00f3ff90 Stack Pointer at: 00f3ff78 New Stack Pointer is: 00f3ff78 Now running in RAM - U-Boot at: 00f80000 FLASH: 8 MB In: serial Out: serial Err: serial U-Boot relocated to 00f80000 Net: SCC ETHERNET :> :> ................................................................... So i don't understand... where did the autoboot go?? the u-boot is store in flash 0x2b00000 the kernel is store in flash 0x2800000 and the ramdisk is in flash 0x2880000 hmm.... thanks guys regards, Mike G.

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[U-Boot-Users] [PATCH] Fix OMAP1510 serial divisor settings.
by Woodruff, Richard 18 Jul '03

18 Jul '03

Here is a patch applied against u-boot-0.4.3 which enables changing the OMAP1510 baud rate. I had forgot to clear the 6.5 divisor in cases where 115200 was not the target rate. The register is write only so this is only way short of keeping a shadow register around for it...and its not worth it. Regards, Richard W.

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[U-Boot-Users] Patch: Support for Motorola PQ2FADS-ZU board
by Yuli Barcohen 17 Jul '03

17 Jul '03

Hi, The attached patch adds support for new Motorola PQ2FADS-ZU evaluation board which replaced MPC8260ADS and MPC8266ADS. Since it shares some 90% of code with MPC8260ADS, it's supported as an MPC8260ADS subtype and not completely new board to avoid unnecessary cloning. -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ======================================================================== Index: README =================================================================== RCS file: /home/CVS/u-boot/u-boot/README,v retrieving revision 1.1.1.4 diff -p -u -r1.1.1.4 README --- README 16 Jul 2003 11:23:40 -0000 1.1.1.4 +++ README 16 Jul 2003 13:12:52 -0000 @@ -197,7 +197,7 @@ Directory Hierarchy: - board/lwmon Files specific to LWMON boards - board/mbx8xx Files specific to MBX boards - board/mpc8260ads - Files specific to MMPC8260ADS boards + Files specific to MPC8260ADS and PQ2FADS-ZU boards - board/mpl/ Files specific to boards manufactured by MPL - board/mpl/common Common files for MPL boards - board/mpl/pip405 Files specific to PIP405 boards @@ -383,6 +383,14 @@ The following options need to be configu the lcd display every second with a "rotator" |\-/|\-/ +- Board flavour: (if CONFIG_MPC8260ADS is defined) + CONFIG_ADSTYPE + + Possible values are: + CFG_8260ADS - original MPC8260ADS + CFG_8266ADS - MPC8266ADS (untested) + CFG_PQ2FADS - PQ2FADS-ZU + - MPC824X Family Member (if CONFIG_MPC824X is defined) Define exactly one of CONFIG_MPC8240, CONFIG_MPC8245 @@ -1687,9 +1695,9 @@ Low Level (hardware related) configurati - CFG_DEFAULT_IMMR: Default address of the IMMR after system reset. - Needed on some 8260 systems (MPC8260ADS and RPXsuper) - to be able to adjust the position of the IMMR - register after a reset. + Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU, + and RPXsuper) to be able to adjust the position of + the IMMR register after a reset. - Floppy Disk Support: CFG_FDC_DRIVE_NUMBER @@ -1862,7 +1870,7 @@ configurations; the following names are GENIETV_config TQM823L_config PIP405_config GEN860T_config EBONY_config FPS860L_config ELPT860_config cmi_mpc5xx_config NETVIA_config - at91rm9200dk_config omap1510inn_config + at91rm9200dk_config omap1510inn_config MPC8260ADS_config Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for Index: board/mpc8260ads/mpc8260ads.c =================================================================== RCS file: /home/CVS/u-boot/u-boot/board/mpc8260ads/mpc8260ads.c,v retrieving revision 1.1.1.4 retrieving revision 1.7 diff -p -u -r1.1.1.4 -r1.7 --- board/mpc8260ads/mpc8260ads.c 16 Jul 2003 11:23:42 -0000 1.1.1.4 +++ board/mpc8260ads/mpc8260ads.c 16 Jul 2003 12:24:41 -0000 1.7 @@ -198,11 +198,19 @@ void reset_phy (void) vu_long *bcsr = (vu_long *)CFG_BCSR; /* reset the FEC port */ - bcsr[1] &= ~FETH_RST; + bcsr[1] &= ~FETH1_RST; udelay(2); - bcsr[1] |= FETH_RST; + bcsr[1] |= FETH1_RST; udelay(1000); #ifdef CONFIG_MII +#if CONFIG_ADSTYPE == CFG_PQ2FADS + /* + * Do not bypass Rx/Tx (de)scrambler (fix configuration error) + * Enable autonegotiation. + */ + miiphy_write(0, 16, 0x610); + miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#else /* * Ethernet PHY is configured (by means of configuration pins) * to work at 10Mb/s only. We reconfigure it using MII @@ -212,6 +220,7 @@ void reset_phy (void) miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */ miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */ miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ #endif /* CONFIG_MII */ } @@ -219,7 +228,7 @@ int board_pre_init (void) { vu_long *bcsr = (vu_long *)CFG_BCSR; - bcsr[1] = ~FETHIEN & ~RS232EN_1; + bcsr[1] = ~FETHIEN1 & ~RS232EN_1; return 0; } @@ -231,12 +240,10 @@ long int initdram (int board_type) volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar *ramaddr, c = 0xff; - - /* Initialisation is for 16MB DIMM the board is shipped with */ - long int msize = 16; - uint or = 0xFF000CA0; - uint psdmr = CFG_PSDMR; - uint psrt = CFG_PSRT; + long int msize; + uint or; + uint psdmr; + uint psrt; int i; @@ -246,22 +253,29 @@ long int initdram (int board_type) immap->im_siu_conf.sc_tescr1 = 0x00004000; memctl->memc_mptpr = CFG_MPTPR; - /* init local sdram, bank 4 */ - memctl->memc_lsrt = 0x00000010; +#ifdef CFG_LSDRAM_BASE + /* Init local bus SDRAM */ + memctl->memc_lsrt = CFG_LSRT; +#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */ + memctl->memc_or3 = 0xFF803280; + memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861; +#else /* CS4 */ memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = 0x04001861; - memctl->memc_lsdmr = 0x2886A522; + memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + memctl->memc_lsdmr = CFG_LSDMR | 0x28000000; ramaddr = (uchar *) CFG_LSDRAM_BASE; *ramaddr = c; - memctl->memc_lsdmr = 0x0886A522; + memctl->memc_lsdmr = CFG_LSDMR | 0x08000000; for (i = 0; i < 8; i++) { *ramaddr = c; } - memctl->memc_lsdmr = 0x1886A522; + memctl->memc_lsdmr = CFG_LSDMR | 0x18000000; *ramaddr = c; - memctl->memc_lsdmr = 0x4086A522; + memctl->memc_lsdmr = CFG_LSDMR | 0x40000000; +#endif /* CFG_LSDRAM_BASE */ - /* init sdram dimm */ + /* Init 60x bus SDRAM */ #ifdef CONFIG_SPD_EEPROM { spd_eeprom_t spd; @@ -398,6 +412,16 @@ long int initdram (int board_type) printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt); #endif /* SPD_DEBUG */ } +#else /* !CONFIG_SPD_EEPROM */ +#if CONFIG_ADSTYPE == CFG_PQ2FADS + msize = 32; + or = 0xFE002EC0; +#else + msize = 16; + or = 0xFF000CA0; +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + psdmr = CFG_PSDMR; + psrt = CFG_PSRT; #endif /* CONFIG_SPD_EEPROM */ memctl->memc_psrt = psrt; memctl->memc_or2 = or; @@ -415,12 +439,20 @@ long int initdram (int board_type) *ramaddr = c; #endif - /* return total ram size of DIMM */ + /* return total 60x bus SDRAM size */ return (msize * 1024 * 1024); } int checkboard (void) { +#if CONFIG_ADSTYPE == CFG_8260ADS puts ("Board: Motorola MPC8260ADS\n"); +#elif CONFIG_ADSTYPE == CFG_8266ADS + puts ("Board: Motorola MPC8266ADS\n"); +#elif CONFIG_ADSTYPE == CFG_PQ2FADS + puts ("Board: Motorola PQ2FADS-ZU\n"); +#else + puts ("Board: unknown\n"); +#endif return 0; } Index: include/configs/MPC8260ADS.h =================================================================== RCS file: /home/CVS/u-boot/u-boot/include/configs/MPC8260ADS.h,v retrieving revision 1.1.1.4 retrieving revision 1.9 diff -p -u -r1.1.1.4 -r1.9 --- include/configs/MPC8260ADS.h 16 Jul 2003 11:23:52 -0000 1.1.1.4 +++ include/configs/MPC8260ADS.h 14 Jul 2003 17:15:25 -0000 1.9 @@ -9,7 +9,8 @@ * * (C) Copyright 2003 Arabella Software Ltd. * Yuli Barcohen <yuli(a)arabellasw.com> - * Added support for SDRAM DIMMs SPD EEPROM, MII. + * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2. + * Ported to PQ2FADS-ZU board. * * See file CREDITS for list of people who contributed to this * project. @@ -41,6 +42,15 @@ #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */ +/* ADS flavours */ +#define CFG_8260ADS 1 /* MPC8260ADS */ +#define CFG_8266ADS 2 /* MPC8266ADS */ +#define CFG_PQ2FADS 3 /* PQ2FADS-ZU */ + +#ifndef CONFIG_ADSTYPE +#define CONFIG_ADSTYPE CFG_8260ADS +#endif /* CONFIG_ADSTYPE */ + #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ /* allow serial and ethaddr to be overwritten */ @@ -116,7 +126,9 @@ #endif /* CONFIG_ETHER_ON_FCC */ -/* other options */ +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#undef CONFIG_SPD_EEPROM /* On PQ2FADS-ZU, SDRAM is soldered */ +#else #define CONFIG_HARD_I2C 1 /* To enable I2C support */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -124,18 +136,23 @@ #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) #define CONFIG_SPD_ADDR 0x50 #endif +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ #ifndef CONFIG_SDRAM_PBI #define CONFIG_SDRAM_PBI 1 /* By default, use page-based interleaving */ #endif #ifndef CONFIG_8260_CLKIN +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#define CONFIG_8260_CLKIN 100000000 /* in Hz */ +#else #define CONFIG_8260_CLKIN 66666666 /* in Hz */ #endif +#endif + #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_BEDBUG | \ +#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ CFG_CMD_BMP | \ CFG_CMD_BSP | \ CFG_CMD_DATE | \ @@ -143,11 +160,11 @@ CFG_CMD_DTT | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ + CFG_CMD_FAT | \ CFG_CMD_FDC | \ CFG_CMD_FDOS | \ CFG_CMD_HWFLOW | \ CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ CFG_CMD_KGDB | \ CFG_CMD_MMC | \ CFG_CMD_NAND | \ @@ -155,8 +172,18 @@ CFG_CMD_PCMCIA | \ CFG_CMD_SCSI | \ CFG_CMD_SPI | \ - CFG_CMD_VFD | \ - CFG_CMD_USB ) ) + CFG_CMD_USB | \ + CFG_CMD_VFD + +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_EXCLUDE ) ) +#else +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_EXCLUDE ) ) +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -200,7 +227,6 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CFG_FLASH_BASE 0xff800000 -#define FLASH_BASE 0xff800000 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ #define CFG_FLASH_SIZE 8 @@ -219,14 +245,16 @@ #define CFG_DEFAULT_IMMR 0x0F010000 #define CFG_IMMR 0xF0000000 -#define CFG_BCSR 0x04500000 +#define CFG_BCSR 0xF4500000 #define CFG_SDRAM_BASE 0x00000000 -#define CFG_LSDRAM_BASE 0x04000000 +#define CFG_LSDRAM_BASE 0xD0000000 #define RS232EN_1 0x02000002 #define RS232EN_2 0x01000001 -#define FETHIEN 0x08000008 -#define FETH_RST 0x04000004 +#define FETHIEN1 0x08000008 +#define FETH1_RST 0x04000004 +#define FETHIEN2 0x01000000 +#define FETH2_RST 0x08000000 #define CFG_INIT_RAM_ADDR CFG_IMMR #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ @@ -288,19 +316,30 @@ #define CFG_SYPCR 0xFFFFFFC3 #define CFG_BCR 0x100C0000 #define CFG_SIUMCR 0x0A200000 -#define CFG_SCCR 0x00000000 -#define CFG_BR0_PRELIM 0xFF801801 -#define CFG_OR0_PRELIM 0xFF800836 -#define CFG_BR1_PRELIM 0x04501801 +#define CFG_SCCR SCCR_DFBRG01 +#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801 +#define CFG_OR0_PRELIM 0xFF800876 +#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 #define CFG_OR1_PRELIM 0xFFFF8010 -#define CFG_RMR 0 +#define CFG_RMR RMR_CSRE #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) #define CFG_RCCR 0 + +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#define CFG_PSDMR 0x824B36A3 +#define CFG_PSRT 0x13 +#define CFG_LSDMR 0x828737A3 +#define CFG_LSRT 0x13 +#define CFG_MPTPR 0x2800 +#else #define CFG_PSDMR 0x016EB452 -#define CFG_MPTPR 0x00001900 -#define CFG_PSRT 0x00000021 +#define CFG_PSRT 0x21 +#define CFG_LSDMR 0x0086A522 +#define CFG_LSRT 0x21 +#define CFG_MPTPR 0x1900 +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ #define CFG_RESET_ADDRESS 0x04400000 N: Yuli Barcohen E: <yuli(a)arabellasw.com> D: Support for Motorola PQ2FADS-ZU board

2 1

[U-Boot-Users] probably bug in ds1621.c
by Palkin Andrey 17 Jul '03

17 Jul '03

In dtt/ds1621.c file: 1. int dtt_write(int sensor, int reg, int val) { int dlen; uchar data[2]; /* * Calculate sensor address and register. * */ sensor = DTT_I2C_DEV_CODE + (sensor & sensor); I think it should be: int dtt_write(int sensor, int reg, int val) { int dlen; uchar data[2]; /* * Calculate sensor address and register. * */ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); 2. else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) { dlen = 0; data[0] = (char)0; data[1] = (char)0; } I think it should be: else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) { dlen = 1; data[0] = (char)0; data[1] = (char)0; } differently MPC8260 I2C controller go in down -- Palkin Andrey

3 3

[U-Boot-Users] I2C POST test known problems?
by Robin Gilks 17 Jul '03

17 Jul '03

Greetings Is anyone aware of any problems with the I2C POST test - I've enabled it and it looks like it locks up the CPM with the busy flag in the command register remaining set all the time. Does anyone know if this is (well) tested code or should I just ignore it and write my own... -- Robin Gilks Senior Design Engineer Phone: (+64)(3) 357 1569 Tait Electronics Fax : (+64)(3) 359 4632 PO Box 1645 Christchurch Email : robin.gilks(a)tait.co.nz New Zealand

3 7

[U-Boot-Users] Swapping in IDE driver
by Marc Singer 16 Jul '03

16 Jul '03

I'm working to get the IDE driver working with an ARM cpu. I'd like to reconcile the three places where swapping does or ought to occur. 1) On PPC, the IDENTITY block is byte swapped as it is read. 2) The identity strings within the IDENTITY block are not byte-swapped. 3) The LBA count is always word-swapped. On an ARM, the combination that works is to swap the identity strings *only*. Enabling the PPC byte swapping will fix the strings, but it garbles the LBA count. It is possible that the reason this is so different on my target is that IDE controller IO is 16 bits wide. So, I'm looking for someone who is familiar with the current IDE driver so that I know the right way to integrate my changes. Cheers.

1 0

[U-Boot-Users] Patch: Correct flash and JFFS2 support for MPC8260ADS
by Yuli Barcohen 14 Jul '03

14 Jul '03

Hi, Original flash support for MPC8260ADS board was cloned from code written for 2x16bit flash configuration while this board uses 4x8bit flash SIMMs. Also, JFFS2 flash file system was not supported on this board. Attached patch fixes some flash support bugs and adds JFFS2 support. This code works unchanged on new Motorola evaluation board, PQ2FADS-ZU. It should work on MPC8266ADS too but I haven't got a board for test. -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ======================================================================== diff -purN CVS/README Arabella/README --- CVS/README 2003-07-13 18:20:25.000000000 +0300 +++ Arabella/README 2003-07-13 18:49:57.000000000 +0300 @@ -1481,6 +1481,16 @@ Configuration Settings: - CFG_FLASH_WRITE_TOUT: Timeout for Flash write operations (in ms) +- CFG_FLASH_LOCK_TOUT + Timeout for Flash set sector lock bit operation (in ms) + +- CFG_FLASH_UNLOCK_TOUT + Timeout for Flash clear lock bits operation (in ms) + +- CFG_FLASH_PROTECTION + If defined, hardware flash sectors protection is used + instead of U-Boot software protection. + - CFG_DIRECT_FLASH_TFTP: Enable TFTP transfers directly to flash memory; diff -purN CVS/board/mpc8260ads/flash.c Arabella/board/mpc8260ads/flash.c --- CVS/board/mpc8260ads/flash.c 2003-07-13 18:16:58.000000000 +0300 +++ Arabella/board/mpc8260ads/flash.c 2003-07-13 17:27:25.000000000 +0300 @@ -7,6 +7,11 @@ * I started with board/ip860/flash.c and made changes I found in * the MTD project by David Schleef. * + * (C) Copyright 2003 Arabella Software Ltd. + * Yuli Barcohen <yuli(a)arabellasw.com> + * Re-written to support multi-bank flash SIMMs. + * Added support for real protection and JFFS2. + * * See file CREDITS for list of people who contributed to this * project. * @@ -28,73 +33,118 @@ #include <common.h> +/* Intel-compatible flash ID */ +#define INTEL_COMPAT 0x89898989 +#define INTEL_ALT 0xB0B0B0B0 + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x10101010 +#define INTEL_ERASE 0x20202020 +#define INTEL_CLEAR 0x50505050 +#define INTEL_LOCKBIT 0x60606060 +#define INTEL_PROTECT 0x01010101 +#define INTEL_STATUS 0x70707070 +#define INTEL_READID 0x90909090 +#define INTEL_CONFIRM 0xD0D0D0D0 +#define INTEL_RESET 0xFFFFFFFF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x80808080 +#define INTEL_OK 0x80808080 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- + * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.) + * Up to 32MB of flash supported (up to 4 banks.) + * BCSR is used for flash presence detect (page 4-65 of the User's Manual) + * + * The following code can not run from flash! */ - unsigned long flash_init (void) { -#ifndef CONFIG_MPC8260ADS - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; -#endif - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ -#ifndef CONFIG_MPC8260ADS - bcsr->bd_ctrl |= BD_CTRL_FLWE; -#endif - - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* set the default sector offset */ + ulong size = 0, sect_start, sect_size, bank_size; + ushort sect_count; + int i, j, nbanks; + vu_long *addr = (vu_long *)CFG_FLASH_BASE; + vu_long *bcsr = (vu_long *)CFG_BCSR; + + switch (bcsr[2] & 0xF) { + case 0: + nbanks = 4; + break; + case 1: + nbanks = 2; + break; + case 2: + nbanks = 1; + break; + default: /* Unsupported configurations */ + nbanks = CFG_MAX_FLASH_BANKS; } - /* Static FLASH Bank configuration here - FIXME XXX */ - - size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]); + if (nbanks > CFG_MAX_FLASH_BANKS) + nbanks = CFG_MAX_FLASH_BANKS; - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size<<20); + for (i = 0; i < nbanks; i++) { + *addr = INTEL_READID; /* Read Intelligent Identifier */ + if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) { + switch (addr[1]) { + case SHARP_ID_28F016SCL: + case SHARP_ID_28F016SCZ: + flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; + sect_count = 32; + sect_size = 0x40000; + break; + default: + flash_info[i].flash_id = FLASH_UNKNOWN; + } + } + else + flash_info[i].flash_id = FLASH_UNKNOWN; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n", + addr[0], addr[1], (ulong)addr); + size = 0; + *addr = INTEL_RESET; /* Reset bank to Read Array mode */ + break; + } + flash_info[i].sector_count = sect_count; + flash_info[i].size = bank_size = sect_size * sect_count; + size += bank_size; + sect_start = (ulong)addr; + for (j = 0; j < sect_count; j++) { + addr = (vu_long *)sect_start; + flash_info[i].start[j] = sect_start; + flash_info[i].protect[j] = (addr[2] == 0x01010101); + sect_start += sect_size; + } + *addr = INTEL_RESET; /* Reset bank to Read Array mode */ + addr = (vu_long *)sect_start; + } + + if (size == 0) { /* Unknown flash, fill with hard-coded values */ + sect_start = CFG_FLASH_BASE; + sect_count = CFG_MAX_FLASH_SECT; + sect_size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS; + flash_info[i].sector_count = sect_count; + for (j = 0; j < sect_count; j++) { + flash_info[i].start[j] = sect_start; + flash_info[i].protect[j] = 0; + sect_start += sect_size; + } + } + size = CFG_FLASH_SIZE; } -#ifndef CONFIG_MPC8260ADS - /* Remap FLASH according to real size */ - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br1 & ~(BR_BA_MSK)); -#endif - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; + else + for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].size = 0; + flash_info[i].sector_count = 0; + } #if CFG_MONITOR_BASE >= CFG_FLASH_BASE /* monitor protection ON by default */ @@ -161,102 +211,6 @@ void flash_print_info (flash_info_t *in /*----------------------------------------------------------------------- */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - - value = addr[0] & 0x00FF00FF; - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - sector_offset = 0x20000; - break; /* => 2x4 MB */ - - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - info->size = 0x00800000; - sector_offset = 0x40000; - break; /* => 4x2 MB */ - - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - - *addr = 0xFFFFFF; /* reset bank to read array mode */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; @@ -292,12 +246,6 @@ int flash_erase (flash_info_t *info, int printf ("\n"); } - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ @@ -308,36 +256,26 @@ int flash_erase (flash_info_t *info, int /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - /* Reset Array */ - *addr = 0xffffffff; /* Clear Status Register */ - *addr = 0x50505050; + *addr = INTEL_CLEAR; /* Single Block Erase Command */ - *addr = 0x20202020; + *addr = INTEL_ERASE; /* Confirm */ - *addr = 0xD0D0D0D0; + *addr = INTEL_CONFIRM; if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; + *addr = INTEL_CONFIRM; } /* re-enable interrupts if necessary */ if (flag) enable_interrupts(); - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x80808080) != 0x80808080) { - if(*addr & 0x20202020){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ + *addr = INTEL_RESET; /* reset bank */ return 1; } /* show that we're waiting */ @@ -347,8 +285,15 @@ int flash_erase (flash_info_t *info, int } } + if (*addr != INTEL_OK) { + printf("Block erase failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + *addr = INTEL_RESET; /* reset bank */ + return 1; + } + /* reset to read mode */ - *addr = 0xFFFFFFFF; + *addr = INTEL_RESET; } } @@ -357,6 +302,58 @@ int flash_erase (flash_info_t *info, int } /*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + ulong start; + int rc = 0; + int flag; + vu_long *addr = (vu_long *)dest; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + + *addr = INTEL_CLEAR; /* Clear status register */ + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = INTEL_PROGRAM; + + /* Write Data */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + printf("Write timed out\n"); + rc = 1; + break; + } + } + if (*addr != INTEL_OK) { + printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr); + rc = 1; + } + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} + +/*----------------------------------------------------------------------- * Copy memory to flash, returns: * 0 - OK * 1 - write timeout @@ -370,6 +367,8 @@ int write_buff (flash_info_t *info, ucha wp = (addr & ~3); /* get lower word aligned address */ + *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */ + /* * handle unaligned start bytes */ @@ -424,85 +423,125 @@ int write_buff (flash_info_t *info, ucha data = (data << 8) | (*(uchar *)cp); } - return (write_word(info, wp, data)); + rc = write_word(info, wp, data); + + return rc; } /*----------------------------------------------------------------------- - * Write a word to Flash, returns: + * Set/Clear sector's lock bit, returns: * 0 - OK - * 1 - write timeout - * 2 - Flash not erased + * 1 - Error (timeout, voltage problems, etc.) */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +int flash_real_protect(flash_info_t *info, long sector, int prot) { - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; + ulong start; + int i; + int rc = 0; + vu_long *addr = (vu_long *)(info->start[sector]); + int flag = disable_interrupts(); + + *addr = INTEL_CLEAR; /* Clear status register */ + if (prot) { /* Set sector lock bit */ + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + } + else { /* Clear sector lock bit */ + *addr = INTEL_LOCKBIT; /* All sectors lock bits */ + *addr = INTEL_CONFIRM; /* clear */ + } + + start = get_timer(0); + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + printf("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); + if (*addr != INTEL_OK) { + printf("Flash lock bit operation failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + rc = 1; } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - /* Write Command */ - *addr = 0x10101010; + if (!rc) + info->protect[sector] = prot; - /* Write Data */ - *addr = data; + /* + * Clear lock bit command clears all sectors lock bits, so + * we have to restore lock bits of protected sectors. + */ + if (!prot) + for (i = 0; i < info->sector_count; i++) + if (info->protect[i]) { + addr = (vu_long *)(info->start[i]); + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + udelay(CFG_FLASH_LOCK_TOUT * 1000); + } - /* re-enable interrupts if necessary */ if (flag) enable_interrupts(); - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - while (((csr = *addr) & 0x80808080) != 0x80808080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; + *addr = INTEL_RESET; /* Reset to read array mode */ - return (flag); + return rc; } /*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout + * Support for flash file system (JFFS2) + * + * We use custom partition info function because we have to fit the + * file system image between first sector (containing hard reset + * configuration word) and the sector containing U-Boot image. Standard + * partition info function does not allow for last sector specification + * and assumes that the file system occupies flash bank up to and + * including bank's last sector. */ +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART) -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; +#ifndef CFG_JFFS2_FIRST_SECTOR +#define CFG_JFFS2_FIRST_SECTOR 0 +#endif +#ifndef CFG_JFFS2_FIRST_BANK +#define CFG_JFFS2_FIRST_BANK 0 +#endif +#ifndef CFG_JFFS2_NUM_BANKS +#define CFG_JFFS2_NUM_BANKS 1 +#endif +#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1) - /* Reset Array */ - *addr = 0xffffffff; - /* Clear Status Register */ - *addr = 0x50505050; +#include <jffs2/jffs2.h> - *addr = 0x60606060; - *addr = 0xd0d0d0d0; +static struct part_info partition; - start = get_timer (0); - while(*addr != 0x80808080){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; +struct part_info *jffs2_part_info(int part_num) +{ + int i; + + if (part_num == 0) { + if (partition.usr_priv == 0) { + partition.offset = + (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR]; + for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++) + partition.size += flash_info[i].size; + partition.size -= + flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] - + flash_info[CFG_JFFS2_FIRST_BANK].start[0]; +#ifdef CFG_JFFS2_LAST_SECTOR + i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1; + partition.size -= + flash_info[CFG_JFFS2_LAST_BANK].start[i] - + flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR]; +#endif + + partition.usr_priv = (void *)1; } + return &partition; } return 0; } + +#endif /* JFFS2 */

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[U-Boot-Users] Patch: New PowerQUICC II processors support
by Yuli Barcohen 14 Jul '03

14 Jul '03

Latest additions to PowerQUICC II family (8270/8275/8280) have got different PVR values and different clock generation scheme. This patch adds support for these processors. -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ======================================================================== diff -purN CVS/cpu/mpc8260/commproc.c Arabella/cpu/mpc8260/commproc.c --- CVS/cpu/mpc8260/commproc.c 2003-07-13 20:49:08.000000000 +0300 +++ Arabella/cpu/mpc8260/commproc.c 2003-07-13 20:59:49.000000000 +0300 @@ -111,9 +111,9 @@ m8260_cpm_hostalloc(uint size, uint alig * to port numbers). Documentation uses 1-based numbering. */ #define BRG_INT_CLK gd->brg_clk -#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16) +#define BRG_UART_CLK (BRG_INT_CLK / 16) -/* This function is used by UARTS, or anything else that uses a 16x +/* This function is used by UARTs, or anything else that uses a 16x * oversampled clock. */ void @@ -123,9 +123,10 @@ m8260_cpm_setbrg(uint brg, uint rate) volatile immap_t *immr = (immap_t *)CFG_IMMR; volatile uint *bp; + uint cd = BRG_UART_CLK / rate; - /* This is good enough to get SMCs running..... - */ + if ((BRG_UART_CLK % rate) < (rate / 2)) + cd--; if (brg < 4) { bp = (uint *)&immr->im_brgc1; } @@ -134,7 +135,7 @@ m8260_cpm_setbrg(uint brg, uint rate) brg -= 4; } bp += brg; - *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; + *bp = (cd << 1) | CPM_BRG_EN; } /* This function is used to set high speed synchronous baud rate diff -purN CVS/cpu/mpc8260/cpu.c Arabella/cpu/mpc8260/cpu.c --- CVS/cpu/mpc8260/cpu.c 2003-07-13 20:26:46.000000000 +0300 +++ Arabella/cpu/mpc8260/cpu.c 2003-07-13 20:37:50.000000000 +0300 @@ -22,7 +22,7 @@ */ /* - * CPU specific code for the MPC8255 / MPC8260 CPUs + * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x * * written or collected and sometimes rewritten by * Magnus Damm <damm(a)bitsmart.com> @@ -35,6 +35,9 @@ * * added 8260 masks by * Marius Groeger <mag(a)sysgo.de> + * + * added HiP7 (8270/8275/8280) processors support by + * Yuli Barcohen <yuli(a)arabellasw.com> */ #include <common.h> @@ -56,15 +59,27 @@ int checkcpu (void) puts ("CPU: "); - if (((pvr >> 16) & 0xff) != 0x81) + switch (pvr) { + case PVR_8260: + case PVR_8260_HIP3: + strcpy (buf, "HiP3"); + break; + case PVR_8260_HIP4: + strcpy (buf, "HiP4"); + break; + case PVR_8260_HIP7: + strcpy (buf, "HiP7"); + break; + default: return -1; /* whoops! not an MPC8260 */ + } rev = pvr & 0xff; immr = immap->im_memctl.memc_immr; if ((immr & IMMR_ISB_MSK) != CFG_IMMR) return -1; /* whoops! someone moved the IMMR */ - printf (CPU_ID_STR " (Rev %02x, Mask ", rev); + printf (CPU_ID_STR " (%s Rev %02x, Mask ", buf, rev); /* * the bottom 16 bits of the immr are the Part Number and Mask Number @@ -104,6 +119,12 @@ int checkcpu (void) case 0x0062: printf ("B.1 4K25A"); break; + case 0x0A00: + printf ("0.0 0K49M"); + break; + case 0x0A01: + printf ("0.1 1K49M"); + break; default: printf ("unknown [immr=0x%04x,k=0x%04x]", m, k); break; diff -purN CVS/cpu/mpc8260/speed.c Arabella/cpu/mpc8260/speed.c --- CVS/cpu/mpc8260/speed.c 2003-07-13 20:51:15.000000000 +0300 +++ Arabella/cpu/mpc8260/speed.c 2003-07-13 17:27:30.000000000 +0300 @@ -120,15 +120,19 @@ int get_clocks (void) scmr = immap->im_clkrst.car_scmr; corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; - busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; - cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; - plldf = (scmr & SCMR_PLLDF) ? 1 : 0; - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; - cp = &corecnf_tab[corecnf]; - gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); + busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; + cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; + if (get_pvr () == PVR_8260_HIP7) { /* HiP7 */ + pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT; + gd->vco_out = clkin * (pllmf + 1); + } else { /* HiP3, HiP4 */ + pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; + plldf = (scmr & SCMR_PLLDF) ? 1 : 0; + gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); + } #if 0 if (gd->vco_out / (busdf + 1) != clkin) { /* aaarrrggghhh!!! */ diff -purN CVS/include/asm-ppc/processor.h Arabella/include/asm-ppc/processor.h --- CVS/include/asm-ppc/processor.h 2003-07-13 20:27:48.000000000 +0300 +++ Arabella/include/asm-ppc/processor.h 2003-07-13 20:32:30.000000000 +0300 @@ -524,8 +524,15 @@ #define PVR_860 PVR_821 #define PVR_7400 0x000C0000 #define PVR_8240 0x00810100 -#define PVR_8260 PVR_8240 +/* + * PowerQUICC II family processors report different PVR values depending + * on silicon process (HiP3, HiP4, HiP7, etc.) + */ +#define PVR_8260 PVR_8240 +#define PVR_8260_HIP3 0x00810101 +#define PVR_8260_HIP4 0x80811014 +#define PVR_8260_HIP7 0x80822011 /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single

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[U-Boot-Users] Re: Cannot compile u-boot under Mandrake 9.1
by Yun-Fong Loh 13 Jul '03

13 Jul '03

John, > gcc -Wall -pedantic -O -I/opt/powerpc/include -o ^^^ this is your problem > astest astest.o error.o -L/opt/powerpc/lib -lbfd > -liberty > /usr//bin/ld: cannot find -lbfd > collect2: ld returned 1 exit status > make[2]: *** [astest] Error 1 Try defining CROSS_COMPILE environment variable with the prefix of your cross compilation tools, e.g.: make CROSS_COMPILE=powerpc-linux- Yun

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[U-Boot-Users] Cannot compile u-boot under Mandrake 9.1
by john duc 13 Jul '03

13 Jul '03

Hi, I tried to compile u-boot-0.4.0 on Mandrake 9.1, but not successful. Could someone help me fix this problem. Here what I did: make distclean make MPC8260ADS_config make all The error is: gcc -Wall -pedantic -O -I/opt/powerpc/include -o astest astest.o error.o -L/opt/powerpc/lib -lbfd -liberty /usr//bin/ld: cannot find -lbfd collect2: ld returned 1 exit status make[2]: *** [astest] Error 1 Some libraries probably missing? Thanks, john __________________________________ Do you Yahoo!? SBC Yahoo! DSL - Now only $29.95 per month! http://sbc.yahoo.com

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[U-Boot-Users] H/W breakpoint
by Dhanuka, Anupam 11 Jul '03

11 Jul '03

Hi there I have made a few changes to u-boot to suit my target requirements. I am trying to debug the code using Abatron BDI h/w debugger. I am unable to stop the target through h/w breakpoints (the target doesn't stop at the address that I provide). Does u-boot disable h/w debugging support (by clearing the Debug Enable bit in some register)? My target is PPC440GP on the EBONY reference board. Thanks Anupam This message (including any attachments) may contain confidential information intended for a specific individual and purpose. If you are not the intended recipient, delete this message. If you are not the intended recipient, disclosing, copying, distributing, or taking any action based on this message is strictly prohibited.

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[U-Boot-Users] printf
by Rune Torgersen 11 Jul '03

11 Jul '03

Hi Does anybody know how to get printf (for 82xx CPU) to priont floting point numbers? I have tried %f %e and %g but all it prints on the console is f e and g... I am using a workaround for now, by printing the number as two integers... float_num = some_float_operation; i = (int)float_num; r = ((int)float_num - i) * 100; printf("%d.%d", i, r); But this is kind of bothersome for the long run. I need this to print out the measured voltages in the system. (done by a supervisor circuit). And yes... The 8266 CPU (actually all the 82xx) has a working FPU unit. Rune Torgersen System Developer Innovative Systems LLC 1000 Innovative Drive Mitchell, SD 57301 Ph: 605-995-6120 www.innovsys.com

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RE: [U-Boot-Users] Probelm with 8266ADS board.
by Rune Torgersen 11 Jul '03

11 Jul '03

This is of course a problem with the SDRAM. Check that CONFIG_PBI is set to 0 (set in top of mpc8266ads.c) This stets the controller in Bank Based interleave. I have seen this excact problem when running Page Based access to the standard 16MB devices. Page Based is supposed to be faster, and is necessary to use more than 128MB per chip select. > -----Original Message----- > From: *L/E<a [mailto:houcheng@turbonetworks.com.tw] > Sent: Thursday, July 10, 2003 21:56 > To: U-Boot Users (E-mail) > Subject: [U-Boot-Users] Probelm with 8266ADS board. > > > Hi All: > I am using MPC8266ADS-PCI board, my board seems crash at > "relocate_code:" and reboot again and again. So I can see the > boot messages repeatly printed on my console. Any good ideas > ? Thanks a lot. > > >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> MESSAGES DRUING BOOTING, REPEATED > U-Boot 0.4.0 (Jul 10 2003 - 17:37:18) > > MPC8260 Reset Status: Check Stop, External Soft, External Hard > > MPC8260 Clock Configuration > - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core > Freq 100-300 > - dfbrg 0, corecnf 0x0a, busdf 5, cpmdf 1, plldf 0, pllmf 2 > - vco_out 396000000, scc_clk 99000000, brg_clk 99000000 > - cpu_clk 264000000, cpm_clk 198000000, bus_clk 66000000 > > CPU: MPC8260 (Rev 14, Mask A.0(A) 2K25A) at 264 MHz > Board: Motorola MPC8266ADS > I2C: ready > DRAM: SDRAM configuration read from SPD > Size per side = 16MB > Organization: 1 sides, 2 banks, 9 Columns, 11 Rows, > Data width = 64 bits > Refresh rate = 33, CAS latency = 3 > Total size: 16 MB > Top of RAM usable for U-Boot at: 01000000 > haha > Reserving 190k for U-Boot at: 00fd0000 > Reserving 384k for malloc() at: 00f70000 > Reserving 76 Bytes for Board Info at: 00f6ffb4 > Reserving 68 Bytes for Global Data at: 00f6ff70 > Stack Pointer at: 00f6ff58 > New Stack Pointer is: 00f6ff58 > before memcpy 16187248, -268419200, 68 > after memcpy > > U-Boot 0.4.0 (Jul 10 2003 - 17:37:18) > > MPC8260 Reset Status: Check Stop, External Soft, External Hard > > MPC8260 Clock Configuration > - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core > Freq 100-300 > - dfbrg 0, corecnf 0x0a, busdf 5, cpmdf 1, plldf 0, pllmf 2 > - vco_out 396000000, scc_clk 99000000, brg_clk 99000000 > - cpu_clk 264000000, cpm_clk 198000000, bus_clk 66000000 > > > > > > > ------------------------------------------------------- > This SF.Net email sponsored by: Parasoft > Error proof Web apps, automate testing & more. > Download & eval WebKing and get a free book. > www.parasoft.com/bulletproofapps1 > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users >

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[U-Boot-Users] Probelm with 8266ADS board.
by �L�E�� 11 Jul '03

11 Jul '03

Hi All: I am using MPC8266ADS-PCI board, my board seems crash at "relocate_code:" and reboot again and again. So I can see the boot messages repeatly printed on my console. Any good ideas ? Thanks a lot. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> MESSAGES DRUING BOOTING, REPEATED U-Boot 0.4.0 (Jul 10 2003 - 17:37:18) MPC8260 Reset Status: Check Stop, External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core Freq 100-300 - dfbrg 0, corecnf 0x0a, busdf 5, cpmdf 1, plldf 0, pllmf 2 - vco_out 396000000, scc_clk 99000000, brg_clk 99000000 - cpu_clk 264000000, cpm_clk 198000000, bus_clk 66000000 CPU: MPC8260 (Rev 14, Mask A.0(A) 2K25A) at 264 MHz Board: Motorola MPC8266ADS I2C: ready DRAM: SDRAM configuration read from SPD Size per side = 16MB Organization: 1 sides, 2 banks, 9 Columns, 11 Rows, Data width = 64 bits Refresh rate = 33, CAS latency = 3 Total size: 16 MB Top of RAM usable for U-Boot at: 01000000 haha Reserving 190k for U-Boot at: 00fd0000 Reserving 384k for malloc() at: 00f70000 Reserving 76 Bytes for Board Info at: 00f6ffb4 Reserving 68 Bytes for Global Data at: 00f6ff70 Stack Pointer at: 00f6ff58 New Stack Pointer is: 00f6ff58 before memcpy 16187248, -268419200, 68 after memcpy U-Boot 0.4.0 (Jul 10 2003 - 17:37:18) MPC8260 Reset Status: Check Stop, External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core Freq 100-300 - dfbrg 0, corecnf 0x0a, busdf 5, cpmdf 1, plldf 0, pllmf 2 - vco_out 396000000, scc_clk 99000000, brg_clk 99000000 - cpu_clk 264000000, cpm_clk 198000000, bus_clk 66000000

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[U-Boot-Users] BDI error
by Rune Torgersen 10 Jul '03

10 Jul '03

Hi Have anybody seen this BDI error and have an idea why it happens? The board is based on a 8266. (FLASH is programed with HRCW (0x08b23645) starting at address 0xff800000) - TARGET: waiting for target Vcc - TARGET: processing power-up delay - TARGET: processing user reset request - BDI asserts HRESET - Reset JTAG controller passed - Bypass check: 0x55 => 0xAA - Bypass check: 0x55 => 0xAA - JTAG exists check passed - Target PVR is 0x80911014 - COP status is 0x01 - Check running state passed - BDI scans COP freeze command - BDI removes HRESET - COP status is 0x05 - Check stopped state passed - Check LSRL length passed - BDI sets breakpoint at 0xFFF00100 - BDI resumes program execution - COP status is 0xF1 - Waiting for target stop failed - TARGET: Break at boot vector failed, freeze forced - TARGET: Target PVR is 0x80911014 - TARGET: resetting target passed - TARGET: processing target startup .... - TARGET: processing target startup passed Rune Torgersen System Developer Innovative Systems LLC 1000 Innovative Drive Mitchell, SD 57301 Ph: 605-995-6120 www.innovsys.com

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[U-Boot-Users] mpc8260 eth_loopback_test()
by Maynard Cabiente 10 Jul '03

10 Jul '03

Hello, I am currently using u-boot version 0.4.0 for the MPC8260ADS board. I am trying to use the additional code in cpu/mpc8260/ether_fcc.c to do the ethernet loopback test. I already added the configuration for the MPC8260ADS to connect FCC's tx and rx clocks with the following code: #elif defined(CONFIG_MPC8260ADS) /* * Attention: this is board-specific (only using FCC2) * - FCC2 Rx-CLK is CLK13 * - FCC2 Tx-CLK is CLK14 */ /* 28.9 - (3): connect FCC's tx and rx clocks */ immr->im_cpmux.cmx_uar = 0; immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14; #else #error "eth_loopback_test not supported on your board" #endif Well, I compiled it and run the test itself by creating a command for it (just like ping or mtest) for my own testing and not through "post". Here's the questions. Does the eth_loopback_test() in cpu/mpc8260/ether_fcc.c needs to have a loopback cable connected to the ethernet port [crossing pin 1 (TX+) and pin 3 (RX+) together and cross pin 2 (TX-) and pin 6 (RX-) together]? Or is it supposed to be run connected directly to the network? I tried both ways and couldn't tell which one is correct or if I need to modify something else in the code to make it work properly. Both have Receive errors in it. (Are we supposed to get RX errors?) Any help is appreciated. Thanks.

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Re: [U-Boot-Users] U-boot on EP8260 Board
by Wolfgang Denk 10 Jul '03

10 Jul '03

In message <20030710152137.56D1143076(a)denx.de> you wrote: > Thanks for the tip. > Now I am using uImage file to boot MV Kernel from U-boot on Embedded Planet > EP8260 board. But it seems to be stuck after uncompressing: I think now it's time to read the Q&A section of http://www.denx.de/re/DPLG.html Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de Living on Earth may be expensive, but it includes an annual free trip around the Sun.

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Re: [U-Boot-Users] U-boot on EP8260 Board
by mss59＠att.net 10 Jul '03

10 Jul '03

Thanks for the tip. Now I am using uImage file to boot MV Kernel from U-boot on Embedded Planet EP8260 board. But it seems to be stuck after uncompressing: =>tftp 0x400000 uImage.ep8260 ARP broadcast 1 TFTP from server 10.0.0.1; our IP address is 10.0.0.2 Filename 'uImage.ep8260'. Load address: 0x400000 Loading: ################################################################# ############################################################### done Bytes transferred = 655335 (9ffe7 hex) => imi ## Checking Image at 00400000 ... Image Name: MV Linux Kernel Image for EP8260 Created: 2003-07-10 13:09:51 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 655271 Bytes = 639.9 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK => bootm 0x400000 ## Booting image at 00400000 ... Image Name: MV Linux Kernel Image for EP8260 Created: 2003-07-10 13:09:51 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 655271 Bytes = 639.9 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK Nothing happens after this. I tried to enable the Pipeline in the boot which results in some extra characters after "Uncompressing Kernel Image ... OK". I used following to make uImage.ep8260 file ../u-boot-0.3.0/tools/mkimage -A ppc -O linux -T kernel -C gzip -a 0 -e 0 - n "MV Linux Kernel Image for EP8260" - d /prj3/kernel/arch/ppc/boot/images/vmlinux.gz /tftpboot/uImage.ep8260 Thanks MSS// > In message <E19aLYj-0004yx-00(a)sc8-sf-list1.sourceforge.net> you wrote: > > I am using u-boot to boot an EP8260 board. However once I load/tftp Kernel ELF > > file to 0x400000 and try to run the kernel from 0x410000, it crashes... > > I used the same ELF file with Embedded planet's boot loader and it works fine. > > Any pointers.... > > Read the README. U-Boot does not use ELF files to boot Linux. > > > Wolfgang Denk > > -- > Software Engineering: Embedded and Realtime Systems, Embedded Linux > Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de > The human race is faced with a cruel choice: work or daytime tele- > vision.

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RE: [U-Boot-Users] Serial Port Configuration on MPC8xx
by Christophe.LINDHEIMER＠fr.thalesgroup.com 10 Jul '03

10 Jul '03

> > > > In fact when I change the baudrate of SMC1 in UBoot, I see > that the same > > baudrate remains used in the linux console ( am I getting > mad ?? :-)) ) > > This is just lucky coincidence if you happen to use the same serial > port for cosole in U-Boot and Linux. Normally, you will have to pass > the required information to the Linux kernel as a boot argument, like > "console=ttyS2,115200" > I am thinking that in the Bd_info there is a parameter indicating the baudrate of the serial lline. This value must be used by Linux to set up the console at the right baudrate even without using the console boot argument... > > So I thought that the IO Connfiguration & The BRG settings > was done only by > > UBoot. > > No, the philosophy is that each part of the software, each driver, is > responsible to initialize the hardware it accesses. So the LInux UART > driver will initialize the serial port(s) itself. > > > BTW, depending on the hardware the IO pins ( and the IO > Config ) are not the > > same and nothing in the linux config allow to choose > that... So it should > > There are some de-facto standard configurations, which are supported > by the Linux driver. > > > mean that the Linux Uart Driver should be patched depending on your > > hardware. > > Indeed. If your hardware guys decided to build some different confi- > guration, this may require to add some #ifdef's to the Linux kernel > code. If you have a look at the UART drivers in our kernel treee you > will see what I mean :-( Ok . I gonna see if I had to change something in the UART driver. Thanks. Chris

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RE: [U-Boot-Users] Serial Port Configuration on MPC8xx
by Christophe.LINDHEIMER＠fr.thalesgroup.com 10 Jul '03

10 Jul '03

Hi > > > Is there something clean to do under Uboot to make it > configure SMC2 ? > > Why should U-Boot initialize a port it does not use? > > > Where should this init done ? > > This should be done, and actually it _is_ done, in the Linux UART > driver. No help from U-Boot needed here. > > > Ummm... what exactly is the problem? > Hum I think that I don't understand something. In fact when I change the baudrate of SMC1 in UBoot, I see that the same baudrate remains used in the linux console ( am I getting mad ?? :-)) ) So I thought that the IO Connfiguration & The BRG settings was done only by UBoot. BTW, depending on the hardware the IO pins ( and the IO Config ) are not the same and nothing in the linux config allow to choose that... So it should mean that the Linux Uart Driver should be patched depending on your hardware. Chris

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[U-Boot-Users] Serial Port Configuration on MPC8xx
by Christophe.LINDHEIMER＠fr.thalesgroup.com 10 Jul '03

10 Jul '03

Hi. I use smc1 for the output of Uboot. So I set #define CONFIG_8xx_CONS_SMC1. In linux config I set SMC1 as my console output. I would like to use SMC2 in linux also. So I added use SMC2 as UART in linux conf. For the SMC1 it works fine as Uboot makes the config of the BRG and IO when CONFIG_8xx_CONS_SMC1 is set. But for SMC2 no config is done by Uboot and I can't set CONFIG_8xx_CONS_SMC2 & CONFIG_8xx_CONS_SMC1. Is there something clean to do under Uboot to make it configure SMC2 ? Where should this init done ? Thanks Regards Chris

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