December 2002 - U-Boot

Re: [U-Boot-Users] PPC 405 _start code - Clarification
by Wolfgang Denk 14 Dec '02

14 Dec '02

Dear Jerry, in message <EGEGIJHKDKJGAJMGIDPNCEHJCCAA.jwalden(a)digitalatlantic.com> you wrote: > Thanks for the clarification! You are welcome. > I am used to the x86 world, and when I disassemble something, I > am used to seeing a one for one mapping from instruction to op-code. This is the same with PowerPC. But there may be several equivalent mnemonics to encode the same instruction. The green book ("The Programming Environments") says: "To simplify assembly language programming, a set of simplified mnemonics (referred to as extended mnemonics in the architecture specification) and symbols is provided ..." > It is obvious that I need to become more proficient in PPC assembly, > how could you tell that the instruction we "equivalent" - did you > use a tool, or is it that you are simply that familiar with the PPC > assembly code. In this case I didn't need a book; but you can actually look it up. For example your first statement: > addi r4,r0,0x0000 The green book lists for "addi": addi rD,rA,SIMM and the simplified mnemonics: li rD,value equivalent to addi rD,0,value la rD,disp(rA) equivalent to addi rD,rA,disp subi rD,rA,value equivalent to addi rD,rA,-value The listing you got from the disassembler: > fff80100: 38 80 00 00 li r4,0 obviously matches rule 1 (well, it's only obvious if you now about the special role or R0 in such cases :-). Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de Where people stand is not as important as which way they face. - Terry Pratchett & Stephen Briggs, _The Discworld Companion_

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[U-Boot-Users] PPC 405 _start code
by Jerry Walden 14 Dec '02

14 Dec '02

Greetings: I just build a version of u-boot for the PPC 405GP. If I disassemble the code that is generated I see the following: fff80100 <_start>: fff80100: 38 80 00 00 li r4,0 fff80104: 7c 99 eb a6 mtsgr r4 fff80108: 7c 9a eb a6 mtdcwr r4 fff8010c: 7c 94 f3 a6 mtesr r4 fff80110: 7c 9a f3 a6 mttcr r4 fff80114: 7c 81 03 a6 mtxer r4 fff80118: 7c 96 f3 a6 mtevpr r4 fff8011c: 38 80 10 00 li r4,4096 So to develop a deeper understanding of how all the pieces fit together I went to the start.S module under the cpu subdirecory. There I see the _start vector - however the code I see in start.S does not correspond to the code that I disassembled. What am I missing? Kindest Regards, Jerry

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[U-Boot-Users] Big ppcboot image
by "Callebaut, Benoît" 13 Dec '02

13 Dec '02

Hello, I am using ppcboot 2.0.0 and I placed the linux kernel in the ppcboot image ( included in an header file). Note that I use automatic boot (ie I don't use the main loop) The idea is that instead of loading the image from an esternal source (nfs,...) I use only bootm to boot the image directly from memory. THe problem is that the ppcboot image is now around 720 kBytes instead of 120 kBytes. And something goes wrong at the end of the board_init_f just before the realocation (realocate_code) or in it. PPCBoot give me the following message "PPCBoot size -292044 > reserved (786432)" Some tips on what is going wrong. ---------------------------------------------------------------------------- ------ Benoit Callebaut Software Development Engineer Barco | Control Rooms Noordlaan 5, 8520 Kuurne, Belgium Tel +32(0)56 36 84 28 Fax +32(0)56 36 86 05 mailto:benoit.callebaut@barco.com http://www.barcocontrolrooms.com

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[U-Boot-Users] Patch for multiple standalone images for bootm
by Rod Boyce 12 Dec '02

12 Dec '02

<<cmd_bootm.tar.gz>> All, Here is a patch to load multiple images from bootm command when the first image is a standalone image. There is a readme file inside the patch file. The patch is against the CVS version of U-Boot on 2002-12-11 Regards, Rod Boyce

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[U-Boot-Users] Setting SIUMCR FYI
by Jim Mesenbrink 12 Dec '02

12 Dec '02

We are using u-boot for our custom board based on the MPC8260. For this board the chip select 10 pin is configured as BCTL1. u-boot would hang after SIUMCR was set in cpu_init_f() in the file cpu/mpc8260/cpu_init.c. The problem is that out of reset OR0[BCTLD] defaults to 0 ("BCTLx is asserted upon access to the current memory bank" 10-18). My next access to FLASH hung the system. I moved the assignment of SIUMCR after the memory controller ORx/BRx registers are setup, where ORx[BCTLD] is set they way we need, and u-boot ran fine. As the title suggests this is a FYI. I hope it is helpful. -- Jim Mesenbrink FlightSafety International mesenb(a)vss.fsi.com Visual Simulation Systems Phone: 314-551-8422 5695 Campus Parkway FAX: 314-551-8444 St. Louis, MO 63042-2338

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[U-Boot-Users] Looking for ARM9E u-boot/linux platform - recommendations?
by Nye Liu 11 Dec '02

11 Dec '02

Greetings: I am working on an embedded linux ARM9E based project and i'm looking for a good eval board to get my feet wet... any suggestions? My primary concerns are (in order of importance): 1) MMU/cache/SDRAM support/stability (most important) 2) availability (preferably US mfg'r) 3) linux/u-boot stability 4) cost 5) performance (least important) PS: Hi Wolfgang! Moving to another project name will not get rid of me so easily, muahahaha ;) -- Nye Liu nliu(a)mrv.com "Who would be stupid enough to quote a fictitious character?" -- Don Quixote

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[U-Boot-Users] uncompressing two gziped images
by Rod Boyce 11 Dec '02

11 Dec '02

All, We are using U-Boot to start a new PPC platform. One of the things we need to do is to load hardware debug software and start it. U-Boot does this very well but we also need to load a data pack. This data pack is big for our flash but we can compress it. My question is how can I uncompress two stand alone images before starting one of them (the first one)? Before I start changing the code to do this for us I though I'd ask incase there is a way I have not been able to figure out yet. I have tried using mkimage and setting one to a Linux kernel image and the other one to a RAM disk but the RAM disk is not decompressed before being relocated. Regards, Rod Boyce

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[U-Boot-Users] 82559( eepro100.c) & interrupt handling
by "Callebaut, Benoît" 09 Dec '02

09 Dec '02

Hello, I am trying use the MAC/PHY 82559 (rev C I think) on an interrupt base manner. The interrupt line of the chip is connected directly to the PPC (INT0), so I use the EPIC in direct mode. When the IVPR0[P] is active low configured and IVPR[S] is level sensitive configured I receive continuously an interrupt which is normal (I think the IRQ line of the chip is configured active high) When it is another configuration I receive nothing. I think, it is a problem with the configuration of the chip since with Linux the chip send well interrupts (every ms) but with Linux, the problem is the EPIC config. Does someone have an idea to solve this or better documentation than the one of Intel ? ---------------------------------------------------------------------------- ------ Benoit Callebaut Software Development Engineer Barco | Control Rooms Noordlaan 5, 8520 Kuurne, Belgium Tel +32(0)56 36 84 28 Fax +32(0)56 36 86 05 mailto:benoit.callebaut@barco.com http://www.barcocontrolrooms.com

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[U-Boot-Users] Re: Boot Loader
by Marius Groeger 09 Dec '02

09 Dec '02

On Mon, 9 Dec 2002, Wolfgang Denk wrote: > > Until the U-Boot surfaces, would this be a good way to go, when faced > > with a custom board? > > No. You should not spend time on a project which has been > discontinued. Just download the latest (top of tree) version from the > U-Boot CVS server. Please note that not everyone can access SF's Anon-CVS because of their corporate firewalls. Are the nightly CVS snapshots available to everyone? Regards, Marius ----------------------------------------------------------------------------- Marius Groeger SYSGO Real-Time Solutions AG mgroeger(a)sysgo.de Software Engineering Embedded and Real-Time Software www.sysgo.de Voice: +49-6136-9948-0 Am Pfaffenstein 14 www.osek.de FAX: +49-6136-9948-10 55270 Klein-Winternheim, Germany www.elinos.com

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[U-Boot-Users] Patch: MPC8xx interrupt
by Pierre AUBERT 06 Dec '02

06 Dec '02

Dear Wolfgang, Currently, for the MPC8xx cpu, the irq_install_handler/irq_free_handler works only for the CPM interrupt. The attached patch allows to use irq_install_handler and irq_free_handler for external interrupts _and_ CPM interrupts. Best regards CHANGELOG: * Patch by Pierre Aubert , 28 Nov 2002 Add support for external interrupts on MPC8xx

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